diff --git a/clang/test/OpenMP/cancel_codegen.cpp b/clang/test/OpenMP/cancel_codegen.cpp --- a/clang/test/OpenMP/cancel_codegen.cpp +++ b/clang/test/OpenMP/cancel_codegen.cpp @@ -7,21 +7,21 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t.1 %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-enable-irbuilder -std=c++11 -include-pch %t.1 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t.2 %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -std=c++11 -include-pch %t.2 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -std=c++11 -include-pch %t.2 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t.3 %s -// RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t.3 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t.3 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t.4 %s -// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -std=c++11 -include-pch %t.4 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -std=c++11 -include-pch %t.4 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp-simd -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t.5 %s -// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t.5 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t.5 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2568,66 +2568,615 @@ // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_LB_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_UB_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_ST_3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_IL_4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_IV_5:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 // CHECK5-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 // CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK5-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8*, i8** [[TMP4]], i64 0 -// CHECK5-NEXT: [[TMP5:%.*]] = load i8*, i8** [[ARRAYIDX2]], align 8 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, i8* [[TMP5]], i64 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[ARRAYIDX3]], align 1 -// CHECK5-NEXT: [[CONV4:%.*]] = sext i8 [[TMP6]] to i32 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[TMP3]] -// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK5-NEXT: store i8 [[CONV5]], i8* [[ARRAYIDX3]], align 1 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i8*** [[ARGV_ADDR]], i32* [[ARGC_ADDR]]) +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0 +// CHECK5-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 0 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: switch i32 [[TMP7]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ +// CHECK5-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] +// CHECK5-NEXT: ] +// CHECK5: .omp.sections.case: +// CHECK5-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) +// CHECK5-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK5-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK5: .cancel.exit: +// CHECK5-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK5: .cancel.continue: +// CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK5: .omp.sections.exit: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) +// CHECK5-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK5: cancel.cont: +// CHECK5-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP0]]) +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_1]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_3]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_4]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_4]], i32* [[DOTOMP_SECTIONS_LB_1]], i32* [[DOTOMP_SECTIONS_UB_2]], i32* [[DOTOMP_SECTIONS_ST_3]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP11]], 1 +// CHECK5-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 1 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_SECTIONS_UB_2]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_SECTIONS_IV_5]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND6:%.*]] +// CHECK5: omp.inner.for.cond6: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY8:%.*]], label [[OMP_INNER_FOR_END18:%.*]] +// CHECK5: omp.inner.for.body8: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 +// CHECK5-NEXT: switch i32 [[TMP17]], label [[DOTOMP_SECTIONS_EXIT15:%.*]] [ +// CHECK5-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE9:%.*]] +// CHECK5-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE12:%.*]] +// CHECK5-NEXT: ] +// CHECK5: .omp.sections.case9: +// CHECK5-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) +// CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK5-NEXT: br i1 [[TMP19]], label [[DOTCANCEL_EXIT10:%.*]], label [[DOTCANCEL_CONTINUE11:%.*]] +// CHECK5: .cancel.exit10: +// CHECK5-NEXT: br label [[CANCEL_EXIT19:%.*]] +// CHECK5: cancel.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) +// CHECK5-NEXT: br label [[CANCEL_CONT]] +// CHECK5: .cancel.continue11: +// CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT15]] +// CHECK5: .omp.sections.case12: +// CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) +// CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK5-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT13:%.*]], label [[DOTCANCEL_CONTINUE14:%.*]] +// CHECK5: .cancel.exit13: +// CHECK5-NEXT: br label [[CANCEL_EXIT19]] +// CHECK5: .cancel.continue14: +// CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT15]] +// CHECK5: .omp.sections.exit15: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]] +// CHECK5: omp.inner.for.inc16: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 +// CHECK5-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK5-NEXT: store i32 [[INC17]], i32* [[DOTOMP_SECTIONS_IV_5]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND6]] +// CHECK5: omp.inner.for.end18: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) +// CHECK5-NEXT: br label [[CANCEL_CONT20:%.*]] +// CHECK5: cancel.cont20: +// CHECK5-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB22:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB22]], i32* [[DOTCAPTURE_EXPR_21]], align 4 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP23:%.*]] = icmp slt i32 0, [[TMP25]] +// CHECK5-NEXT: br i1 [[CMP23]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK5-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK5-NEXT: [[CMP25:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] +// CHECK5-NEXT: br i1 [[CMP25]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE]] ], [ [[TMP30]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND26:%.*]] +// CHECK5: omp.inner.for.cond26: +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP27:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]] +// CHECK5-NEXT: br i1 [[CMP27]], label [[OMP_INNER_FOR_BODY28:%.*]], label [[OMP_INNER_FOR_END33:%.*]] +// CHECK5: omp.inner.for.body28: +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP34]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I24]], align 4 +// CHECK5-NEXT: [[TMP35:%.*]] = load float, float* @flag, align 4 +// CHECK5-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP35]], 0.000000e+00 +// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK5: omp_if.then: +// CHECK5-NEXT: [[TMP36:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2) +// CHECK5-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK5-NEXT: br i1 [[TMP37]], label [[DOTCANCEL_EXIT29:%.*]], label [[DOTCANCEL_CONTINUE30:%.*]] +// CHECK5: .cancel.exit29: +// CHECK5-NEXT: br label [[CANCEL_EXIT34:%.*]] +// CHECK5: cancel.exit19: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) +// CHECK5-NEXT: br label [[CANCEL_CONT20]] +// CHECK5: .cancel.continue30: +// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK5: omp_if.else: +// CHECK5-NEXT: br label [[OMP_IF_END]] +// CHECK5: omp_if.end: +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC31:%.*]] +// CHECK5: omp.inner.for.inc31: +// CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP38]], 1 +// CHECK5-NEXT: store i32 [[ADD32]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND26]] +// CHECK5: omp.inner.for.end33: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP0]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: cancel.exit34: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP0]]) +// CHECK5-NEXT: br label [[CANCEL_CONT35:%.*]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: br label [[CANCEL_CONT35]] +// CHECK5: cancel.cont35: +// CHECK5-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[TMP0]]) +// CHECK5-NEXT: [[TMP39:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) +// CHECK5-NEXT: [[TMP40:%.*]] = bitcast i8* [[TMP39]] to %struct.kmp_task_t_with_privates* +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP40]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP39]]) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) // CHECK5-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK5-NEXT: br label [[FOR_COND7:%.*]] -// CHECK5: for.cond7: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP10]], [[TMP11]] -// CHECK5-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END13:%.*]] -// CHECK5: for.body9: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[R]], align 4 -// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD10]], i32* [[R]], align 4 -// CHECK5-NEXT: br label [[FOR_INC11:%.*]] -// CHECK5: for.inc11: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK5-NEXT: store i32 [[INC12]], i32* [[I6]], align 4 -// CHECK5-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end13: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: ret i32 [[TMP15]] +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i32* [[R]]) +// CHECK5-NEXT: [[TMP43:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: ret i32 [[TMP43]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8***, align 8 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i8*** [[ARGV]], i8**** [[ARGV_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGV_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load float, float* @flag, align 4 +// CHECK5-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP2]], 0.000000e+00 +// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK5: omp_if.then: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1) +// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 +// CHECK5-NEXT: br i1 [[TMP6]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK5: .cancel.exit: +// CHECK5-NEXT: br label [[RETURN:%.*]] +// CHECK5: .cancel.continue: +// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK5: omp_if.else: +// CHECK5-NEXT: br label [[OMP_IF_END]] +// CHECK5: omp_if.end: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP7]] to i8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i8**, i8*** [[TMP0]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP8]], i64 0 +// CHECK5-NEXT: [[TMP9:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 +// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP9]], i64 0 +// CHECK5-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]]) +// CHECK5-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK5-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK5: .cancel.exit2: +// CHECK5-NEXT: br label [[RETURN]] +// CHECK5: .cancel.continue3: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i8**, i8*** [[TMP0]], align 8 +// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8*, i8** [[TMP15]], i64 0 +// CHECK5-NEXT: [[TMP16:%.*]] = load i8*, i8** [[ARRAYIDX4]], align 8 +// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i8, i8* [[TMP16]], i64 0 +// CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[ARRAYIDX5]], align 1 +// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP17]] to i32 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV6]], [[TMP14]] +// CHECK5-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD]] to i8 +// CHECK5-NEXT: store i8 [[CONV7]], i8* [[ARRAYIDX5]], align 1 +// CHECK5-NEXT: br label [[RETURN]] +// CHECK5: return: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK5-NEXT: [[CLEANUP_DEST_SLOT_I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK5-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]]) +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13 +// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13 +// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13 +// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13 +// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13 +// CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 +// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13 +// CHECK5-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]] +// CHECK5-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK5-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.*]], label [[DOTCANCEL_CONTINUE_I:%.*]] +// CHECK5: .cancel.exit.i: +// CHECK5-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 +// CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK5: .cancel.continue.i: +// CHECK5-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 +// CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK5: .omp_outlined..1.exit: +// CHECK5-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 0 +// CHECK5-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 0 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ +// CHECK5-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] +// CHECK5-NEXT: ] +// CHECK5: .omp.sections.case: +// CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) +// CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK5-NEXT: br i1 [[TMP10]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK5: .cancel.exit: +// CHECK5-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK5: .cancel.continue: +// CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK5: .omp.sections.exit: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK5-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK5-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK5: cancel.cont: +// CHECK5-NEXT: ret void +// CHECK5: cancel.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK5-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 1 +// CHECK5-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 1 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ +// CHECK5-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] +// CHECK5-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]] +// CHECK5-NEXT: ] +// CHECK5: .omp.sections.case: +// CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) +// CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK5-NEXT: br i1 [[TMP10]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK5: .cancel.exit: +// CHECK5-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK5: .cancel.continue: +// CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK5: .omp.sections.case1: +// CHECK5-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) +// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK5: .cancel.exit2: +// CHECK5-NEXT: br label [[CANCEL_EXIT]] +// CHECK5: .cancel.continue3: +// CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK5: .omp.sections.exit: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK5-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK5: cancel.cont: +// CHECK5-NEXT: ret void +// CHECK5: cancel.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK5-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[R_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[R3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[R]], i32** [[R_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[R_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[R3]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB5]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], i32 2) +// CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK5-NEXT: br i1 [[TMP19]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK5: .cancel.exit: +// CHECK5-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK5: .cancel.continue: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[R3]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP24]]) +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast i32* [[R3]] to i8* +// CHECK5-NEXT: store i8* [[TMP26]], i8** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK5-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 [[TMP28]], i32 1, i64 8, i8* [[TMP29]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: switch i32 [[TMP30]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK5-NEXT: ] +// CHECK5: .omp.reduction.case1: +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB7]], i32 [[TMP28]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK5: cancel.exit: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP34]]) +// CHECK5-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK5: .omp.reduction.case2: +// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK5-NEXT: [[TMP36:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP35]] monotonic, align 4 +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK5: .omp.reduction.default: +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: br label [[CANCEL_CONT]] +// CHECK5: cancel.cont: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK5-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK5-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -2636,66 +3185,615 @@ // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_LB_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_UB_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_ST_3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_IL_4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_IV_5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 // CHECK6-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 // CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK6-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8*, i8** [[TMP4]], i64 0 -// CHECK6-NEXT: [[TMP5:%.*]] = load i8*, i8** [[ARRAYIDX2]], align 8 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, i8* [[TMP5]], i64 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load i8, i8* [[ARRAYIDX3]], align 1 -// CHECK6-NEXT: [[CONV4:%.*]] = sext i8 [[TMP6]] to i32 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[TMP3]] -// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK6-NEXT: store i8 [[CONV5]], i8* [[ARRAYIDX3]], align 1 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i8*** [[ARGV_ADDR]], i32* [[ARGC_ADDR]]) +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0 +// CHECK6-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 0 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: switch i32 [[TMP7]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ +// CHECK6-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.sections.case: +// CHECK6-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) +// CHECK6-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK6-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK6: .cancel.exit: +// CHECK6-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK6: .cancel.continue: +// CHECK6-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK6: .omp.sections.exit: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) +// CHECK6-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK6: cancel.cont: +// CHECK6-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP0]]) +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_1]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_3]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_4]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_4]], i32* [[DOTOMP_SECTIONS_LB_1]], i32* [[DOTOMP_SECTIONS_UB_2]], i32* [[DOTOMP_SECTIONS_ST_3]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP11]], 1 +// CHECK6-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 1 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_SECTIONS_UB_2]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_SECTIONS_IV_5]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND6:%.*]] +// CHECK6: omp.inner.for.cond6: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY8:%.*]], label [[OMP_INNER_FOR_END18:%.*]] +// CHECK6: omp.inner.for.body8: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 +// CHECK6-NEXT: switch i32 [[TMP17]], label [[DOTOMP_SECTIONS_EXIT15:%.*]] [ +// CHECK6-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE9:%.*]] +// CHECK6-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE12:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.sections.case9: +// CHECK6-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) +// CHECK6-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK6-NEXT: br i1 [[TMP19]], label [[DOTCANCEL_EXIT10:%.*]], label [[DOTCANCEL_CONTINUE11:%.*]] +// CHECK6: .cancel.exit10: +// CHECK6-NEXT: br label [[CANCEL_EXIT19:%.*]] +// CHECK6: cancel.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) +// CHECK6-NEXT: br label [[CANCEL_CONT]] +// CHECK6: .cancel.continue11: +// CHECK6-NEXT: br label [[DOTOMP_SECTIONS_EXIT15]] +// CHECK6: .omp.sections.case12: +// CHECK6-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) +// CHECK6-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK6-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT13:%.*]], label [[DOTCANCEL_CONTINUE14:%.*]] +// CHECK6: .cancel.exit13: +// CHECK6-NEXT: br label [[CANCEL_EXIT19]] +// CHECK6: .cancel.continue14: +// CHECK6-NEXT: br label [[DOTOMP_SECTIONS_EXIT15]] +// CHECK6: .omp.sections.exit15: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]] +// CHECK6: omp.inner.for.inc16: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 +// CHECK6-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK6-NEXT: store i32 [[INC17]], i32* [[DOTOMP_SECTIONS_IV_5]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND6]] +// CHECK6: omp.inner.for.end18: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) +// CHECK6-NEXT: br label [[CANCEL_CONT20:%.*]] +// CHECK6: cancel.cont20: +// CHECK6-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB22:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB22]], i32* [[DOTCAPTURE_EXPR_21]], align 4 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP23:%.*]] = icmp slt i32 0, [[TMP25]] +// CHECK6-NEXT: br i1 [[CMP23]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK6-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK6-NEXT: [[CMP25:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] +// CHECK6-NEXT: br i1 [[CMP25]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE]] ], [ [[TMP30]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND26:%.*]] +// CHECK6: omp.inner.for.cond26: +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP27:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]] +// CHECK6-NEXT: br i1 [[CMP27]], label [[OMP_INNER_FOR_BODY28:%.*]], label [[OMP_INNER_FOR_END33:%.*]] +// CHECK6: omp.inner.for.body28: +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP34]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I24]], align 4 +// CHECK6-NEXT: [[TMP35:%.*]] = load float, float* @flag, align 4 +// CHECK6-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP35]], 0.000000e+00 +// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK6: omp_if.then: +// CHECK6-NEXT: [[TMP36:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2) +// CHECK6-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK6-NEXT: br i1 [[TMP37]], label [[DOTCANCEL_EXIT29:%.*]], label [[DOTCANCEL_CONTINUE30:%.*]] +// CHECK6: .cancel.exit29: +// CHECK6-NEXT: br label [[CANCEL_EXIT34:%.*]] +// CHECK6: cancel.exit19: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) +// CHECK6-NEXT: br label [[CANCEL_CONT20]] +// CHECK6: .cancel.continue30: +// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK6: omp_if.else: +// CHECK6-NEXT: br label [[OMP_IF_END]] +// CHECK6: omp_if.end: +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC31:%.*]] +// CHECK6: omp.inner.for.inc31: +// CHECK6-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP38]], 1 +// CHECK6-NEXT: store i32 [[ADD32]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND26]] +// CHECK6: omp.inner.for.end33: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: cancel.exit34: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP0]]) +// CHECK6-NEXT: br label [[CANCEL_CONT35:%.*]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: br label [[CANCEL_CONT35]] +// CHECK6: cancel.cont35: +// CHECK6-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[TMP0]]) +// CHECK6-NEXT: [[TMP39:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) +// CHECK6-NEXT: [[TMP40:%.*]] = bitcast i8* [[TMP39]] to %struct.kmp_task_t_with_privates* +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP40]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP39]]) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) // CHECK6-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK6-NEXT: br label [[FOR_COND7:%.*]] -// CHECK6: for.cond7: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP10]], [[TMP11]] -// CHECK6-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END13:%.*]] -// CHECK6: for.body9: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[R]], align 4 -// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD10]], i32* [[R]], align 4 -// CHECK6-NEXT: br label [[FOR_INC11:%.*]] -// CHECK6: for.inc11: -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK6-NEXT: store i32 [[INC12]], i32* [[I6]], align 4 -// CHECK6-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end13: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: ret i32 [[TMP15]] +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i32* [[R]]) +// CHECK6-NEXT: [[TMP43:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: ret i32 [[TMP43]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8***, align 8 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i8*** [[ARGV]], i8**** [[ARGV_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGV_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load float, float* @flag, align 4 +// CHECK6-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP2]], 0.000000e+00 +// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK6: omp_if.then: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1) +// CHECK6-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 +// CHECK6-NEXT: br i1 [[TMP6]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK6: .cancel.exit: +// CHECK6-NEXT: br label [[RETURN:%.*]] +// CHECK6: .cancel.continue: +// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK6: omp_if.else: +// CHECK6-NEXT: br label [[OMP_IF_END]] +// CHECK6: omp_if.end: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP7]] to i8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i8**, i8*** [[TMP0]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP8]], i64 0 +// CHECK6-NEXT: [[TMP9:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 +// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP9]], i64 0 +// CHECK6-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]]) +// CHECK6-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK6-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK6: .cancel.exit2: +// CHECK6-NEXT: br label [[RETURN]] +// CHECK6: .cancel.continue3: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i8**, i8*** [[TMP0]], align 8 +// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8*, i8** [[TMP15]], i64 0 +// CHECK6-NEXT: [[TMP16:%.*]] = load i8*, i8** [[ARRAYIDX4]], align 8 +// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i8, i8* [[TMP16]], i64 0 +// CHECK6-NEXT: [[TMP17:%.*]] = load i8, i8* [[ARRAYIDX5]], align 1 +// CHECK6-NEXT: [[CONV6:%.*]] = sext i8 [[TMP17]] to i32 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV6]], [[TMP14]] +// CHECK6-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD]] to i8 +// CHECK6-NEXT: store i8 [[CONV7]], i8* [[ARRAYIDX5]], align 1 +// CHECK6-NEXT: br label [[RETURN]] +// CHECK6: return: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK6-NEXT: [[CLEANUP_DEST_SLOT_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK6-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13 +// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13 +// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13 +// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13 +// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13 +// CHECK6-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 +// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13 +// CHECK6-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]] +// CHECK6-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK6-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.*]], label [[DOTCANCEL_CONTINUE_I:%.*]] +// CHECK6: .cancel.exit.i: +// CHECK6-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK6: .cancel.continue.i: +// CHECK6-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK6: .omp_outlined..1.exit: +// CHECK6-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 0 +// CHECK6-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 0 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ +// CHECK6-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.sections.case: +// CHECK6-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) +// CHECK6-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK6-NEXT: br i1 [[TMP10]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK6: .cancel.exit: +// CHECK6-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK6: .cancel.continue: +// CHECK6-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK6: .omp.sections.exit: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK6-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK6-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK6: cancel.cont: +// CHECK6-NEXT: ret void +// CHECK6: cancel.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK6-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 1 +// CHECK6-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 1 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ +// CHECK6-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] +// CHECK6-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.sections.case: +// CHECK6-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) +// CHECK6-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK6-NEXT: br i1 [[TMP10]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK6: .cancel.exit: +// CHECK6-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK6: .cancel.continue: +// CHECK6-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK6: .omp.sections.case1: +// CHECK6-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) +// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK6: .cancel.exit2: +// CHECK6-NEXT: br label [[CANCEL_EXIT]] +// CHECK6: .cancel.continue3: +// CHECK6-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK6: .omp.sections.exit: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK6-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK6-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK6: cancel.cont: +// CHECK6-NEXT: ret void +// CHECK6: cancel.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK6-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[R_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[R3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[R]], i32** [[R_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[R_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[R3]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB5]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], i32 2) +// CHECK6-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK6-NEXT: br i1 [[TMP19]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK6: .cancel.exit: +// CHECK6-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK6: .cancel.continue: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[R3]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP24]]) +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast i32* [[R3]] to i8* +// CHECK6-NEXT: store i8* [[TMP26]], i8** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK6-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 [[TMP28]], i32 1, i64 8, i8* [[TMP29]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: switch i32 [[TMP30]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.reduction.case1: +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB7]], i32 [[TMP28]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: cancel.exit: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP34]]) +// CHECK6-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK6: .omp.reduction.case2: +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK6-NEXT: [[TMP36:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP35]] monotonic, align 4 +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.default: +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: br label [[CANCEL_CONT]] +// CHECK6: cancel.cont: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK6-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main @@ -2704,279 +3802,287 @@ // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK7-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTOMP_SECTIONS_LB_1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTOMP_SECTIONS_UB_2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTOMP_SECTIONS_ST_3:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTOMP_SECTIONS_IL_4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTOMP_SECTIONS_IV_5:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[P_LOWERBOUND:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[P_UPPERBOUND:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[P_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[P_LASTITER26:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[P_LOWERBOUND27:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[P_UPPERBOUND28:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[P_STRIDE29:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_33:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I35:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 // CHECK7-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 // CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i8*** [[ARGV_ADDR]], i32* [[ARGC_ADDR]]) -// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0 -// CHECK7-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 0 -// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: switch i32 [[TMP7]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ -// CHECK7-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK7-NEXT: br label [[OMP_PARALLEL:%.*]] +// CHECK7: omp_parallel: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i8***)* @main..omp_par to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i8*** [[ARGV_ADDR]]) +// CHECK7-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] +// CHECK7: omp.par.outlined.exit: +// CHECK7-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] +// CHECK7: omp.par.exit.split: +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_PREHEADER:%.*]] +// CHECK7: omp_section_loop.preheader: +// CHECK7-NEXT: store i32 0, i32* [[P_LOWERBOUND]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[P_UPPERBOUND]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[P_STRIDE]], align 4 +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 34, i32* [[P_LASTITER]], i32* [[P_LOWERBOUND]], i32* [[P_UPPERBOUND]], i32* [[P_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[P_LOWERBOUND]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[P_UPPERBOUND]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], [[TMP0]] +// CHECK7-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 1 +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_HEADER:%.*]] +// CHECK7: omp_section_loop.header: +// CHECK7-NEXT: [[OMP_SECTION_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_SECTION_LOOP_PREHEADER]] ], [ [[OMP_SECTION_LOOP_NEXT:%.*]], [[OMP_SECTION_LOOP_INC:%.*]] ] +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_COND:%.*]] +// CHECK7: omp_section_loop.cond: +// CHECK7-NEXT: [[OMP_SECTION_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_SECTION_LOOP_IV]], [[TMP3]] +// CHECK7-NEXT: br i1 [[OMP_SECTION_LOOP_CMP]], label [[OMP_SECTION_LOOP_BODY:%.*]], label [[OMP_SECTION_LOOP_EXIT:%.*]] +// CHECK7: omp_section_loop.body: +// CHECK7-NEXT: [[TMP4:%.*]] = add i32 [[OMP_SECTION_LOOP_IV]], [[TMP0]] +// CHECK7-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 1 +// CHECK7-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 0 +// CHECK7-NEXT: switch i32 [[TMP6]], label [[OMP_SECTION_LOOP_INC]] [ +// CHECK7-NEXT: i32 0, label [[OMP_SECTION_LOOP_BODY_CASE:%.*]] // CHECK7-NEXT: ] -// CHECK7: .omp.sections.case: -// CHECK7-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) -// CHECK7-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK7-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK7: .cancel.exit: -// CHECK7-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK7: .cancel.continue: -// CHECK7-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] -// CHECK7: .omp.sections.exit: -// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK7: omp.inner.for.end: -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) -// CHECK7-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK7: cancel.cont: -// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP0]]) -// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_1]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_3]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_4]], align 4 -// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_4]], i32* [[DOTOMP_SECTIONS_LB_1]], i32* [[DOTOMP_SECTIONS_UB_2]], i32* [[DOTOMP_SECTIONS_ST_3]], i32 1, i32 1) -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 -// CHECK7-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP11]], 1 -// CHECK7-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 1 -// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_SECTIONS_UB_2]], align 4 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_1]], align 4 -// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_SECTIONS_IV_5]], align 4 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND6:%.*]] -// CHECK7: omp.inner.for.cond6: -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 -// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY8:%.*]], label [[OMP_INNER_FOR_END18:%.*]] -// CHECK7: omp.inner.for.body8: -// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 -// CHECK7-NEXT: switch i32 [[TMP17]], label [[DOTOMP_SECTIONS_EXIT15:%.*]] [ -// CHECK7-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE9:%.*]] -// CHECK7-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE12:%.*]] +// CHECK7: omp_section_loop.inc: +// CHECK7-NEXT: [[OMP_SECTION_LOOP_NEXT]] = add nuw i32 [[OMP_SECTION_LOOP_IV]], 1 +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_HEADER]] +// CHECK7: omp_section_loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_AFTER:%.*]] +// CHECK7: omp_section_loop.after: +// CHECK7-NEXT: br label [[OMP_SECTIONS_END:%.*]] +// CHECK7: omp_sections.end: +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_PREHEADER12:%.*]] +// CHECK7: omp_section_loop.preheader12: +// CHECK7-NEXT: store i32 0, i32* [[P_LOWERBOUND27]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[P_UPPERBOUND28]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[P_STRIDE29]], align 4 +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM30:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]], i32 34, i32* [[P_LASTITER26]], i32* [[P_LOWERBOUND27]], i32* [[P_UPPERBOUND28]], i32* [[P_STRIDE29]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[P_LOWERBOUND27]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[P_UPPERBOUND28]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], [[TMP7]] +// CHECK7-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 1 +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_HEADER13:%.*]] +// CHECK7: omp_section_loop.header13: +// CHECK7-NEXT: [[OMP_SECTION_LOOP_IV19:%.*]] = phi i32 [ 0, [[OMP_SECTION_LOOP_PREHEADER12]] ], [ [[OMP_SECTION_LOOP_NEXT21:%.*]], [[OMP_SECTION_LOOP_INC16:%.*]] ] +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_COND14:%.*]] +// CHECK7: omp_section_loop.cond14: +// CHECK7-NEXT: [[OMP_SECTION_LOOP_CMP20:%.*]] = icmp ult i32 [[OMP_SECTION_LOOP_IV19]], [[TMP10]] +// CHECK7-NEXT: br i1 [[OMP_SECTION_LOOP_CMP20]], label [[OMP_SECTION_LOOP_BODY15:%.*]], label [[OMP_SECTION_LOOP_EXIT17:%.*]] +// CHECK7: omp_section_loop.body15: +// CHECK7-NEXT: [[TMP11:%.*]] = add i32 [[OMP_SECTION_LOOP_IV19]], [[TMP7]] +// CHECK7-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK7-NEXT: [[TMP13:%.*]] = add i32 [[TMP12]], 0 +// CHECK7-NEXT: switch i32 [[TMP13]], label [[OMP_SECTION_LOOP_INC16]] [ +// CHECK7-NEXT: i32 0, label [[OMP_SECTION_LOOP_BODY_CASE22:%.*]] +// CHECK7-NEXT: i32 1, label [[OMP_SECTION_LOOP_BODY_CASE24:%.*]] // CHECK7-NEXT: ] -// CHECK7: .omp.sections.case9: -// CHECK7-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) -// CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK7-NEXT: br i1 [[TMP19]], label [[DOTCANCEL_EXIT10:%.*]], label [[DOTCANCEL_CONTINUE11:%.*]] -// CHECK7: .cancel.exit10: -// CHECK7-NEXT: br label [[CANCEL_EXIT19:%.*]] -// CHECK7: cancel.exit: -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) -// CHECK7-NEXT: br label [[CANCEL_CONT]] -// CHECK7: .cancel.continue11: -// CHECK7-NEXT: br label [[DOTOMP_SECTIONS_EXIT15]] -// CHECK7: .omp.sections.case12: -// CHECK7-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) -// CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK7-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT13:%.*]], label [[DOTCANCEL_CONTINUE14:%.*]] -// CHECK7: .cancel.exit13: -// CHECK7-NEXT: br label [[CANCEL_EXIT19]] -// CHECK7: .cancel.continue14: -// CHECK7-NEXT: br label [[DOTOMP_SECTIONS_EXIT15]] -// CHECK7: .omp.sections.exit15: -// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]] -// CHECK7: omp.inner.for.inc16: -// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 -// CHECK7-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK7-NEXT: store i32 [[INC17]], i32* [[DOTOMP_SECTIONS_IV_5]], align 4 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND6]] -// CHECK7: omp.inner.for.end18: -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) -// CHECK7-NEXT: br label [[CANCEL_CONT20:%.*]] -// CHECK7: cancel.cont20: -// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK7: omp_section_loop.inc16: +// CHECK7-NEXT: [[OMP_SECTION_LOOP_NEXT21]] = add nuw i32 [[OMP_SECTION_LOOP_IV19]], 1 +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_HEADER13]] +// CHECK7: omp_section_loop.exit17: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]]) +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM31:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM31]]) +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_AFTER18:%.*]] +// CHECK7: omp_section_loop.after18: +// CHECK7-NEXT: br label [[OMP_SECTIONS_END32:%.*]] +// CHECK7: omp_sections.end32: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 0 // CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK7-NEXT: [[SUB22:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK7-NEXT: store i32 [[SUB22]], i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK7-NEXT: [[SUB34:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB34]], i32* [[DOTCAPTURE_EXPR_33]], align 4 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[CMP23:%.*]] = icmp slt i32 0, [[TMP25]] -// CHECK7-NEXT: br i1 [[CMP23]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK7: omp.precond.then: // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK7-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 +// CHECK7-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK7-NEXT: [[CMP25:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] -// CHECK7-NEXT: br i1 [[CMP25]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM36:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM36]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 +// CHECK7-NEXT: [[CMP37:%.*]] = icmp sgt i32 [[TMP18]], [[TMP19]] +// CHECK7-NEXT: br i1 [[CMP37]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK7: cond.true: -// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 // CHECK7-NEXT: br label [[COND_END:%.*]] // CHECK7: cond.false: -// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: br label [[COND_END]] // CHECK7: cond.end: -// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE]] ], [ [[TMP30]], [[COND_FALSE]] ] +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP20]], [[COND_TRUE]] ], [ [[TMP21]], [[COND_FALSE]] ] // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK7-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND26:%.*]] -// CHECK7: omp.inner.for.cond26: -// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK7-NEXT: [[CMP27:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]] -// CHECK7-NEXT: br i1 [[CMP27]], label [[OMP_INNER_FOR_BODY28:%.*]], label [[OMP_INNER_FOR_END33:%.*]] -// CHECK7: omp.inner.for.body28: -// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP34]], 1 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I24]], align 4 -// CHECK7-NEXT: [[TMP35:%.*]] = load float, float* @flag, align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP35]], 0.000000e+00 -// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP38:%.*]] = icmp sle i32 [[TMP23]], [[TMP24]] +// CHECK7-NEXT: br i1 [[CMP38]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP25]], 1 +// CHECK7-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD39]], i32* [[I35]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load float, float* @flag, align 4 +// CHECK7-NEXT: [[TOBOOL40:%.*]] = fcmp une float [[TMP26]], 0.000000e+00 +// CHECK7-NEXT: br i1 [[TOBOOL40]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK7: omp_if.then: -// CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2) -// CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK7-NEXT: br i1 [[TMP37]], label [[DOTCANCEL_EXIT29:%.*]], label [[DOTCANCEL_CONTINUE30:%.*]] -// CHECK7: .cancel.exit29: -// CHECK7-NEXT: br label [[CANCEL_EXIT34:%.*]] -// CHECK7: cancel.exit19: -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) -// CHECK7-NEXT: br label [[CANCEL_CONT20]] -// CHECK7: .cancel.continue30: +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) +// CHECK7-NEXT: [[TMP27:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]], i32 2) +// CHECK7-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK7-NEXT: br i1 [[TMP28]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK7: .cancel.exit: +// CHECK7-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK7: omp_section_loop.body.case: +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM9:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9]], i32 3) +// CHECK7-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP29]], 0 +// CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_SECTION_LOOP_BODY_CASE_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE_CNCL:%.*]] +// CHECK7: omp_section_loop.body.case.split: +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_EXIT]] +// CHECK7: omp_section_loop.body.case.cncl: +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_EXIT]] +// CHECK7: omp_section_loop.body.case22: +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]], i32 3) +// CHECK7-NEXT: [[TMP32:%.*]] = icmp eq i32 [[TMP31]], 0 +// CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_SECTION_LOOP_BODY_CASE22_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE22_CNCL:%.*]] +// CHECK7: omp_section_loop.body.case22.split: +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] +// CHECK7: omp_section_loop.body.case22.cncl: +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] +// CHECK7: omp_section_loop.body.case24: +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM25:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: [[TMP33:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM25]], i32 3) +// CHECK7-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP33]], 0 +// CHECK7-NEXT: br i1 [[TMP34]], label [[OMP_SECTION_LOOP_BODY_CASE24_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE24_CNCL:%.*]] +// CHECK7: omp_section_loop.body.case24.split: +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] +// CHECK7: omp_section_loop.body.case24.cncl: +// CHECK7-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] +// CHECK7: .cancel.continue: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: -// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC31:%.*]] -// CHECK7: omp.inner.for.inc31: -// CHECK7-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP38]], 1 -// CHECK7-NEXT: store i32 [[ADD32]], i32* [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND26]] -// CHECK7: omp.inner.for.end33: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK7-NEXT: store i32 [[ADD42]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP0]]) +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM44:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM44]]) // CHECK7-NEXT: br label [[OMP_PRECOND_END]] -// CHECK7: cancel.exit34: -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP0]]) -// CHECK7-NEXT: br label [[CANCEL_CONT35:%.*]] +// CHECK7: cancel.exit: +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM43:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM43]]) +// CHECK7-NEXT: br label [[CANCEL_CONT:%.*]] // CHECK7: omp.precond.end: -// CHECK7-NEXT: br label [[CANCEL_CONT35]] -// CHECK7: cancel.cont35: -// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP39:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// CHECK7-NEXT: [[TMP40:%.*]] = bitcast i8* [[TMP39]] to %struct.kmp_task_t_with_privates* -// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP40]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP39]]) +// CHECK7-NEXT: br label [[CANCEL_CONT]] +// CHECK7: cancel.cont: +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM45:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM45]]) +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM46:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB14:[0-9]+]]) +// CHECK7-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM46]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) +// CHECK7-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM47:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB14]]) +// CHECK7-NEXT: [[TMP39:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM47]], i8* [[TMP36]]) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) // CHECK7-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i32* [[R]]) -// CHECK7-NEXT: [[TMP43:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK7-NEXT: ret i32 [[TMP43]] +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i32* [[R]]) +// CHECK7-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: ret i32 [[TMP40]] // // -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8***, align 8 -// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK7-NEXT: store i8*** [[ARGV]], i8**** [[ARGV_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGV_ADDR]], align 8 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load float, float* @flag, align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP2]], 0.000000e+00 -// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK7: omp_if.then: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1) -// CHECK7-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 -// CHECK7-NEXT: br i1 [[TMP6]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK7: .cancel.exit: -// CHECK7-NEXT: br label [[RETURN:%.*]] -// CHECK7: .cancel.continue: -// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK7: omp_if.else: -// CHECK7-NEXT: br label [[OMP_IF_END]] -// CHECK7: omp_if.end: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[TMP7]] to i8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP8]], i64 0 -// CHECK7-NEXT: [[TMP9:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP9]], i64 0 -// CHECK7-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK7-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]]) -// CHECK7-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK7-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK7: .cancel.exit2: -// CHECK7-NEXT: br label [[RETURN]] -// CHECK7: .cancel.continue3: -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK7-NEXT: [[TMP15:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8*, i8** [[TMP15]], i64 0 -// CHECK7-NEXT: [[TMP16:%.*]] = load i8*, i8** [[ARRAYIDX4]], align 8 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i8, i8* [[TMP16]], i64 0 -// CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[ARRAYIDX5]], align 1 -// CHECK7-NEXT: [[CONV6:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV6]], [[TMP14]] -// CHECK7-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK7-NEXT: store i8 [[CONV7]], i8* [[ARRAYIDX5]], align 1 -// CHECK7-NEXT: br label [[RETURN]] -// CHECK7: return: +// CHECK7-LABEL: define {{[^@]+}}@main..omp_par +// CHECK7-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[ARGC_ADDR:%.*]], i8*** [[ARGV_ADDR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-NEXT: omp.par.entry: +// CHECK7-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 +// CHECK7-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 +// CHECK7-NEXT: br label [[OMP_PAR_REGION:%.*]] +// CHECK7: omp.par.outlined.exit.exitStub: // CHECK7-NEXT: ret void +// CHECK7: omp.par.region: +// CHECK7-NEXT: [[TMP1:%.*]] = load float, float* @flag, align 4 +// CHECK7-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP1]], 0.000000e+00 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[TMP13:%.*]], label [[TMP2:%.*]] +// CHECK7: 2: +// CHECK7-NEXT: br label [[TMP3:%.*]] +// CHECK7: 3: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[TMP4]] to i8 +// CHECK7-NEXT: [[TMP5:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP5]], i64 0 +// CHECK7-NEXT: [[TMP6:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 +// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, i8* [[TMP6]], i64 0 +// CHECK7-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX2]], align 1 +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[DOTCONT:%.*]], label [[DOTCNCL4:%.*]] +// CHECK7: .cncl4: +// CHECK7-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] +// CHECK7: .cont: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 +// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i8*, i8** [[TMP10]], i64 0 +// CHECK7-NEXT: [[TMP11:%.*]] = load i8*, i8** [[ARRAYIDX5]], align 8 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i8, i8* [[TMP11]], i64 0 +// CHECK7-NEXT: [[TMP12:%.*]] = load i8, i8* [[ARRAYIDX6]], align 1 +// CHECK7-NEXT: [[CONV7:%.*]] = sext i8 [[TMP12]] to i32 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV7]], [[TMP9]] +// CHECK7-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD]] to i8 +// CHECK7-NEXT: store i8 [[CONV8]], i8* [[ARRAYIDX6]], align 1 +// CHECK7-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] +// CHECK7: omp.par.pre_finalize: +// CHECK7-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB]] +// CHECK7: 13: +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 1) +// CHECK7-NEXT: [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0 +// CHECK7-NEXT: br i1 [[TMP15]], label [[DOTSPLIT:%.*]], label [[DOTCNCL:%.*]] +// CHECK7: .cncl: +// CHECK7-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB]] +// CHECK7: .split: +// CHECK7-NEXT: br label [[TMP3]] // // // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. @@ -3012,23 +4118,23 @@ // CHECK7-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13 // CHECK7-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 // CHECK7-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13 -// CHECK7-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK7-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.*]], label [[DOTCANCEL_CONTINUE_I:%.*]] +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]] +// CHECK7-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]] +// CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK7-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.*]], label [[DOTCANCEL_CONTINUE_I:%.*]] // CHECK7: .cancel.exit.i: // CHECK7-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 -// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK7: .cancel.continue.i: // CHECK7-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 -// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK7: .omp_outlined..1.exit: +// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] +// CHECK7: .omp_outlined..exit: // CHECK7-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 // CHECK7-NEXT: ret i32 0 // // -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3043,53 +4149,55 @@ // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 0 -// CHECK7-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 0 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB17:[0-9]+]]) +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB15:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0 +// CHECK7-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 0 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK7-NEXT: switch i32 [[TMP6]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ // CHECK7-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] // CHECK7-NEXT: ] // CHECK7: .omp.sections.case: -// CHECK7-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) -// CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 -// CHECK7-NEXT: br i1 [[TMP10]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK7: .cancel.exit: -// CHECK7-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK7: .cancel.continue: +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 3) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[DOTOMP_SECTIONS_CASE_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE_CNCL:%.*]] +// CHECK7: .omp.sections.case.split: // CHECK7-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK7: .omp.sections.case.cncl: +// CHECK7-NEXT: br label [[CANCEL_CONT:%.*]] // CHECK7: .omp.sections.exit: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK7-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK7: omp.inner.for.end: -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK7-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB19:[0-9]+]]) +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) +// CHECK7-NEXT: br label [[CANCEL_CONT]] // CHECK7: cancel.cont: // CHECK7-NEXT: ret void // CHECK7: cancel.exit: -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB19]]) +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) // CHECK7-NEXT: br label [[CANCEL_CONT]] // // -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3104,62 +4212,65 @@ // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 1 -// CHECK7-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 1 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB21:[0-9]+]]) +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 1 +// CHECK7-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 1 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK7-NEXT: switch i32 [[TMP6]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ // CHECK7-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] -// CHECK7-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]] +// CHECK7-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE2:%.*]] // CHECK7-NEXT: ] // CHECK7: .omp.sections.case: -// CHECK7-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) -// CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 -// CHECK7-NEXT: br i1 [[TMP10]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK7: .cancel.exit: -// CHECK7-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK7: .cancel.continue: +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 3) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[DOTOMP_SECTIONS_CASE_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE_CNCL:%.*]] +// CHECK7: .omp.sections.case.split: // CHECK7-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] -// CHECK7: .omp.sections.case1: -// CHECK7-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) -// CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK7-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK7: .cancel.exit2: -// CHECK7-NEXT: br label [[CANCEL_EXIT]] -// CHECK7: .cancel.continue3: +// CHECK7: .omp.sections.case.cncl: +// CHECK7-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK7: .omp.sections.case2: +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32 3) +// CHECK7-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0 +// CHECK7-NEXT: br i1 [[TMP10]], label [[DOTOMP_SECTIONS_CASE2_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE2_CNCL:%.*]] +// CHECK7: .omp.sections.case2.split: // CHECK7-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK7: .omp.sections.case2.cncl: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END]] // CHECK7: .omp.sections.exit: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK7-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK7: omp.inner.for.end: -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK7-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB23:[0-9]+]]) +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM5]]) +// CHECK7-NEXT: br label [[CANCEL_CONT]] // CHECK7: cancel.cont: // CHECK7-NEXT: ret void // CHECK7: cancel.exit: -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB23]]) +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM4]]) // CHECK7-NEXT: br label [[CANCEL_CONT]] // // -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3201,87 +4312,82 @@ // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK7-NEXT: store i32 0, i32* [[R3]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB5]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB25:[0-9]+]]) +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]] // CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK7: cond.true: -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK7-NEXT: br label [[COND_END:%.*]] // CHECK7: cond.false: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: br label [[COND_END]] // CHECK7: cond.end: -// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK7-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK7-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK7-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], i32 2) -// CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK7-NEXT: br i1 [[TMP19]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM7:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB27:[0-9]+]]) +// CHECK7-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM7]], i32 2) +// CHECK7-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK7-NEXT: br i1 [[TMP15]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK7: .cancel.exit: // CHECK7-NEXT: br label [[CANCEL_EXIT:%.*]] // CHECK7: .cancel.continue: -// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] -// CHECK7-NEXT: store i32 [[ADD7]], i32* [[R3]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], [[TMP16]] +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[R3]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: -// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP24]]) -// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK7-NEXT: [[TMP26:%.*]] = bitcast i32* [[R3]] to i8* -// CHECK7-NEXT: store i8* [[TMP26]], i8** [[TMP25]], align 8 -// CHECK7-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK7-NEXT: [[TMP29:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK7-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 [[TMP28]], i32 1, i64 8, i8* [[TMP29]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK7-NEXT: switch i32 [[TMP30]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29:[0-9]+]]) +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i32* [[R3]] to i8* +// CHECK7-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8 +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29]]) +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK7-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB30:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM12]], i32 1, i64 8, i8* [[TMP21]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK7-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK7-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK7-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK7-NEXT: ] // CHECK7: .omp.reduction.case1: -// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK7-NEXT: store i32 [[ADD9]], i32* [[TMP1]], align 4 -// CHECK7-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB7]], i32 [[TMP28]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK7-NEXT: store i32 [[ADD13]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB30]], i32 [[OMP_GLOBAL_THREAD_NUM12]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK7-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK7: cancel.exit: -// CHECK7-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP34]]) +// CHECK7-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29]]) +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) // CHECK7-NEXT: br label [[CANCEL_CONT:%.*]] // CHECK7: .omp.reduction.case2: -// CHECK7-NEXT: [[TMP35:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK7-NEXT: [[TMP36:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP35]] monotonic, align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP25]] monotonic, align 4 // CHECK7-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK7: .omp.reduction.default: // CHECK7-NEXT: br label [[OMP_PRECOND_END]] @@ -3321,279 +4427,287 @@ // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK8-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTOMP_SECTIONS_LB_1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTOMP_SECTIONS_UB_2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTOMP_SECTIONS_ST_3:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTOMP_SECTIONS_IL_4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTOMP_SECTIONS_IV_5:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[P_LOWERBOUND:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[P_UPPERBOUND:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[P_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[P_LASTITER26:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[P_LOWERBOUND27:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[P_UPPERBOUND28:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[P_STRIDE29:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_33:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I35:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 // CHECK8-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 // CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i8*** [[ARGV_ADDR]], i32* [[ARGC_ADDR]]) -// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0 -// CHECK8-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 0 -// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: switch i32 [[TMP7]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ -// CHECK8-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK8-NEXT: br label [[OMP_PARALLEL:%.*]] +// CHECK8: omp_parallel: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i8***)* @main..omp_par to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i8*** [[ARGV_ADDR]]) +// CHECK8-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] +// CHECK8: omp.par.outlined.exit: +// CHECK8-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] +// CHECK8: omp.par.exit.split: +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_PREHEADER:%.*]] +// CHECK8: omp_section_loop.preheader: +// CHECK8-NEXT: store i32 0, i32* [[P_LOWERBOUND]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[P_UPPERBOUND]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[P_STRIDE]], align 4 +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 34, i32* [[P_LASTITER]], i32* [[P_LOWERBOUND]], i32* [[P_UPPERBOUND]], i32* [[P_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[P_LOWERBOUND]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[P_UPPERBOUND]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], [[TMP0]] +// CHECK8-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 1 +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_HEADER:%.*]] +// CHECK8: omp_section_loop.header: +// CHECK8-NEXT: [[OMP_SECTION_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_SECTION_LOOP_PREHEADER]] ], [ [[OMP_SECTION_LOOP_NEXT:%.*]], [[OMP_SECTION_LOOP_INC:%.*]] ] +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_COND:%.*]] +// CHECK8: omp_section_loop.cond: +// CHECK8-NEXT: [[OMP_SECTION_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_SECTION_LOOP_IV]], [[TMP3]] +// CHECK8-NEXT: br i1 [[OMP_SECTION_LOOP_CMP]], label [[OMP_SECTION_LOOP_BODY:%.*]], label [[OMP_SECTION_LOOP_EXIT:%.*]] +// CHECK8: omp_section_loop.body: +// CHECK8-NEXT: [[TMP4:%.*]] = add i32 [[OMP_SECTION_LOOP_IV]], [[TMP0]] +// CHECK8-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 1 +// CHECK8-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 0 +// CHECK8-NEXT: switch i32 [[TMP6]], label [[OMP_SECTION_LOOP_INC]] [ +// CHECK8-NEXT: i32 0, label [[OMP_SECTION_LOOP_BODY_CASE:%.*]] // CHECK8-NEXT: ] -// CHECK8: .omp.sections.case: -// CHECK8-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) -// CHECK8-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK8-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK8: .cancel.exit: -// CHECK8-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK8: .cancel.continue: -// CHECK8-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] -// CHECK8: .omp.sections.exit: -// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK8: omp.inner.for.end: -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) -// CHECK8-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK8: cancel.cont: -// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP0]]) -// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_1]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_3]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_4]], align 4 -// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_4]], i32* [[DOTOMP_SECTIONS_LB_1]], i32* [[DOTOMP_SECTIONS_UB_2]], i32* [[DOTOMP_SECTIONS_ST_3]], i32 1, i32 1) -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 -// CHECK8-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP11]], 1 -// CHECK8-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 1 -// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_SECTIONS_UB_2]], align 4 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_1]], align 4 -// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_SECTIONS_IV_5]], align 4 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND6:%.*]] -// CHECK8: omp.inner.for.cond6: -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 -// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_2]], align 4 -// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY8:%.*]], label [[OMP_INNER_FOR_END18:%.*]] -// CHECK8: omp.inner.for.body8: -// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 -// CHECK8-NEXT: switch i32 [[TMP17]], label [[DOTOMP_SECTIONS_EXIT15:%.*]] [ -// CHECK8-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE9:%.*]] -// CHECK8-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE12:%.*]] +// CHECK8: omp_section_loop.inc: +// CHECK8-NEXT: [[OMP_SECTION_LOOP_NEXT]] = add nuw i32 [[OMP_SECTION_LOOP_IV]], 1 +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_HEADER]] +// CHECK8: omp_section_loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_AFTER:%.*]] +// CHECK8: omp_section_loop.after: +// CHECK8-NEXT: br label [[OMP_SECTIONS_END:%.*]] +// CHECK8: omp_sections.end: +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_PREHEADER12:%.*]] +// CHECK8: omp_section_loop.preheader12: +// CHECK8-NEXT: store i32 0, i32* [[P_LOWERBOUND27]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[P_UPPERBOUND28]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[P_STRIDE29]], align 4 +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM30:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]], i32 34, i32* [[P_LASTITER26]], i32* [[P_LOWERBOUND27]], i32* [[P_UPPERBOUND28]], i32* [[P_STRIDE29]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[P_LOWERBOUND27]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[P_UPPERBOUND28]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], [[TMP7]] +// CHECK8-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 1 +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_HEADER13:%.*]] +// CHECK8: omp_section_loop.header13: +// CHECK8-NEXT: [[OMP_SECTION_LOOP_IV19:%.*]] = phi i32 [ 0, [[OMP_SECTION_LOOP_PREHEADER12]] ], [ [[OMP_SECTION_LOOP_NEXT21:%.*]], [[OMP_SECTION_LOOP_INC16:%.*]] ] +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_COND14:%.*]] +// CHECK8: omp_section_loop.cond14: +// CHECK8-NEXT: [[OMP_SECTION_LOOP_CMP20:%.*]] = icmp ult i32 [[OMP_SECTION_LOOP_IV19]], [[TMP10]] +// CHECK8-NEXT: br i1 [[OMP_SECTION_LOOP_CMP20]], label [[OMP_SECTION_LOOP_BODY15:%.*]], label [[OMP_SECTION_LOOP_EXIT17:%.*]] +// CHECK8: omp_section_loop.body15: +// CHECK8-NEXT: [[TMP11:%.*]] = add i32 [[OMP_SECTION_LOOP_IV19]], [[TMP7]] +// CHECK8-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK8-NEXT: [[TMP13:%.*]] = add i32 [[TMP12]], 0 +// CHECK8-NEXT: switch i32 [[TMP13]], label [[OMP_SECTION_LOOP_INC16]] [ +// CHECK8-NEXT: i32 0, label [[OMP_SECTION_LOOP_BODY_CASE22:%.*]] +// CHECK8-NEXT: i32 1, label [[OMP_SECTION_LOOP_BODY_CASE24:%.*]] // CHECK8-NEXT: ] -// CHECK8: .omp.sections.case9: -// CHECK8-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) -// CHECK8-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK8-NEXT: br i1 [[TMP19]], label [[DOTCANCEL_EXIT10:%.*]], label [[DOTCANCEL_CONTINUE11:%.*]] -// CHECK8: .cancel.exit10: -// CHECK8-NEXT: br label [[CANCEL_EXIT19:%.*]] -// CHECK8: cancel.exit: -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) -// CHECK8-NEXT: br label [[CANCEL_CONT]] -// CHECK8: .cancel.continue11: -// CHECK8-NEXT: br label [[DOTOMP_SECTIONS_EXIT15]] -// CHECK8: .omp.sections.case12: -// CHECK8-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) -// CHECK8-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK8-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT13:%.*]], label [[DOTCANCEL_CONTINUE14:%.*]] -// CHECK8: .cancel.exit13: -// CHECK8-NEXT: br label [[CANCEL_EXIT19]] -// CHECK8: .cancel.continue14: -// CHECK8-NEXT: br label [[DOTOMP_SECTIONS_EXIT15]] -// CHECK8: .omp.sections.exit15: -// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]] -// CHECK8: omp.inner.for.inc16: -// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_5]], align 4 -// CHECK8-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK8-NEXT: store i32 [[INC17]], i32* [[DOTOMP_SECTIONS_IV_5]], align 4 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND6]] -// CHECK8: omp.inner.for.end18: -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) -// CHECK8-NEXT: br label [[CANCEL_CONT20:%.*]] -// CHECK8: cancel.cont20: -// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK8: omp_section_loop.inc16: +// CHECK8-NEXT: [[OMP_SECTION_LOOP_NEXT21]] = add nuw i32 [[OMP_SECTION_LOOP_IV19]], 1 +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_HEADER13]] +// CHECK8: omp_section_loop.exit17: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]]) +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM31:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM31]]) +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_AFTER18:%.*]] +// CHECK8: omp_section_loop.after18: +// CHECK8-NEXT: br label [[OMP_SECTIONS_END32:%.*]] +// CHECK8: omp_sections.end32: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 0 // CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK8-NEXT: [[SUB22:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK8-NEXT: store i32 [[SUB22]], i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK8-NEXT: [[SUB34:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB34]], i32* [[DOTCAPTURE_EXPR_33]], align 4 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[CMP23:%.*]] = icmp slt i32 0, [[TMP25]] -// CHECK8-NEXT: br i1 [[CMP23]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK8: omp.precond.then: // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK8-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 +// CHECK8-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK8-NEXT: [[CMP25:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] -// CHECK8-NEXT: br i1 [[CMP25]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM36:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM36]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 +// CHECK8-NEXT: [[CMP37:%.*]] = icmp sgt i32 [[TMP18]], [[TMP19]] +// CHECK8-NEXT: br i1 [[CMP37]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK8: cond.true: -// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 // CHECK8-NEXT: br label [[COND_END:%.*]] // CHECK8: cond.false: -// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: br label [[COND_END]] // CHECK8: cond.end: -// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE]] ], [ [[TMP30]], [[COND_FALSE]] ] +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP20]], [[COND_TRUE]] ], [ [[TMP21]], [[COND_FALSE]] ] // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK8-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND26:%.*]] -// CHECK8: omp.inner.for.cond26: -// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK8-NEXT: [[CMP27:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]] -// CHECK8-NEXT: br i1 [[CMP27]], label [[OMP_INNER_FOR_BODY28:%.*]], label [[OMP_INNER_FOR_END33:%.*]] -// CHECK8: omp.inner.for.body28: -// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP34]], 1 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I24]], align 4 -// CHECK8-NEXT: [[TMP35:%.*]] = load float, float* @flag, align 4 -// CHECK8-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP35]], 0.000000e+00 -// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP38:%.*]] = icmp sle i32 [[TMP23]], [[TMP24]] +// CHECK8-NEXT: br i1 [[CMP38]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP25]], 1 +// CHECK8-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD39]], i32* [[I35]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load float, float* @flag, align 4 +// CHECK8-NEXT: [[TOBOOL40:%.*]] = fcmp une float [[TMP26]], 0.000000e+00 +// CHECK8-NEXT: br i1 [[TOBOOL40]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK8: omp_if.then: -// CHECK8-NEXT: [[TMP36:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2) -// CHECK8-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK8-NEXT: br i1 [[TMP37]], label [[DOTCANCEL_EXIT29:%.*]], label [[DOTCANCEL_CONTINUE30:%.*]] -// CHECK8: .cancel.exit29: -// CHECK8-NEXT: br label [[CANCEL_EXIT34:%.*]] -// CHECK8: cancel.exit19: -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) -// CHECK8-NEXT: br label [[CANCEL_CONT20]] -// CHECK8: .cancel.continue30: +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) +// CHECK8-NEXT: [[TMP27:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]], i32 2) +// CHECK8-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK8-NEXT: br i1 [[TMP28]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK8: .cancel.exit: +// CHECK8-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK8: omp_section_loop.body.case: +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM9:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: [[TMP29:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9]], i32 3) +// CHECK8-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP29]], 0 +// CHECK8-NEXT: br i1 [[TMP30]], label [[OMP_SECTION_LOOP_BODY_CASE_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE_CNCL:%.*]] +// CHECK8: omp_section_loop.body.case.split: +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_EXIT]] +// CHECK8: omp_section_loop.body.case.cncl: +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_EXIT]] +// CHECK8: omp_section_loop.body.case22: +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]], i32 3) +// CHECK8-NEXT: [[TMP32:%.*]] = icmp eq i32 [[TMP31]], 0 +// CHECK8-NEXT: br i1 [[TMP32]], label [[OMP_SECTION_LOOP_BODY_CASE22_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE22_CNCL:%.*]] +// CHECK8: omp_section_loop.body.case22.split: +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] +// CHECK8: omp_section_loop.body.case22.cncl: +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] +// CHECK8: omp_section_loop.body.case24: +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM25:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: [[TMP33:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM25]], i32 3) +// CHECK8-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP33]], 0 +// CHECK8-NEXT: br i1 [[TMP34]], label [[OMP_SECTION_LOOP_BODY_CASE24_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE24_CNCL:%.*]] +// CHECK8: omp_section_loop.body.case24.split: +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] +// CHECK8: omp_section_loop.body.case24.cncl: +// CHECK8-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] +// CHECK8: .cancel.continue: // CHECK8-NEXT: br label [[OMP_IF_END:%.*]] // CHECK8: omp_if.else: // CHECK8-NEXT: br label [[OMP_IF_END]] // CHECK8: omp_if.end: // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: -// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC31:%.*]] -// CHECK8: omp.inner.for.inc31: -// CHECK8-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP38]], 1 -// CHECK8-NEXT: store i32 [[ADD32]], i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND26]] -// CHECK8: omp.inner.for.end33: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK8-NEXT: store i32 [[ADD42]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP0]]) +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM44:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM44]]) // CHECK8-NEXT: br label [[OMP_PRECOND_END]] -// CHECK8: cancel.exit34: -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP0]]) -// CHECK8-NEXT: br label [[CANCEL_CONT35:%.*]] +// CHECK8: cancel.exit: +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM43:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM43]]) +// CHECK8-NEXT: br label [[CANCEL_CONT:%.*]] // CHECK8: omp.precond.end: -// CHECK8-NEXT: br label [[CANCEL_CONT35]] -// CHECK8: cancel.cont35: -// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP39:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// CHECK8-NEXT: [[TMP40:%.*]] = bitcast i8* [[TMP39]] to %struct.kmp_task_t_with_privates* -// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP40]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP39]]) +// CHECK8-NEXT: br label [[CANCEL_CONT]] +// CHECK8: cancel.cont: +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM45:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM45]]) +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM46:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB14:[0-9]+]]) +// CHECK8-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM46]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) +// CHECK8-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM47:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB14]]) +// CHECK8-NEXT: [[TMP39:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM47]], i8* [[TMP36]]) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) // CHECK8-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i32* [[R]]) -// CHECK8-NEXT: [[TMP43:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK8-NEXT: ret i32 [[TMP43]] +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i32* [[R]]) +// CHECK8-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: ret i32 [[TMP40]] // // -// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8***, align 8 -// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK8-NEXT: store i8*** [[ARGV]], i8**** [[ARGV_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGV_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load float, float* @flag, align 4 -// CHECK8-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP2]], 0.000000e+00 -// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK8: omp_if.then: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1) -// CHECK8-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 -// CHECK8-NEXT: br i1 [[TMP6]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK8: .cancel.exit: -// CHECK8-NEXT: br label [[RETURN:%.*]] -// CHECK8: .cancel.continue: -// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK8: omp_if.else: -// CHECK8-NEXT: br label [[OMP_IF_END]] -// CHECK8: omp_if.end: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = trunc i32 [[TMP7]] to i8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP8]], i64 0 -// CHECK8-NEXT: [[TMP9:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP9]], i64 0 -// CHECK8-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK8-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]]) -// CHECK8-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK8-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK8: .cancel.exit2: -// CHECK8-NEXT: br label [[RETURN]] -// CHECK8: .cancel.continue3: -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK8-NEXT: [[TMP15:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8*, i8** [[TMP15]], i64 0 -// CHECK8-NEXT: [[TMP16:%.*]] = load i8*, i8** [[ARRAYIDX4]], align 8 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i8, i8* [[TMP16]], i64 0 -// CHECK8-NEXT: [[TMP17:%.*]] = load i8, i8* [[ARRAYIDX5]], align 1 -// CHECK8-NEXT: [[CONV6:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV6]], [[TMP14]] -// CHECK8-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK8-NEXT: store i8 [[CONV7]], i8* [[ARRAYIDX5]], align 1 -// CHECK8-NEXT: br label [[RETURN]] -// CHECK8: return: +// CHECK8-LABEL: define {{[^@]+}}@main..omp_par +// CHECK8-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[ARGC_ADDR:%.*]], i8*** [[ARGV_ADDR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-NEXT: omp.par.entry: +// CHECK8-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 +// CHECK8-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 +// CHECK8-NEXT: br label [[OMP_PAR_REGION:%.*]] +// CHECK8: omp.par.outlined.exit.exitStub: // CHECK8-NEXT: ret void +// CHECK8: omp.par.region: +// CHECK8-NEXT: [[TMP1:%.*]] = load float, float* @flag, align 4 +// CHECK8-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP1]], 0.000000e+00 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[TMP13:%.*]], label [[TMP2:%.*]] +// CHECK8: 2: +// CHECK8-NEXT: br label [[TMP3:%.*]] +// CHECK8: 3: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i32 [[TMP4]] to i8 +// CHECK8-NEXT: [[TMP5:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP5]], i64 0 +// CHECK8-NEXT: [[TMP6:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 +// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, i8* [[TMP6]], i64 0 +// CHECK8-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX2]], align 1 +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[DOTCONT:%.*]], label [[DOTCNCL4:%.*]] +// CHECK8: .cncl4: +// CHECK8-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] +// CHECK8: .cont: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 +// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i8*, i8** [[TMP10]], i64 0 +// CHECK8-NEXT: [[TMP11:%.*]] = load i8*, i8** [[ARRAYIDX5]], align 8 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i8, i8* [[TMP11]], i64 0 +// CHECK8-NEXT: [[TMP12:%.*]] = load i8, i8* [[ARRAYIDX6]], align 1 +// CHECK8-NEXT: [[CONV7:%.*]] = sext i8 [[TMP12]] to i32 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV7]], [[TMP9]] +// CHECK8-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD]] to i8 +// CHECK8-NEXT: store i8 [[CONV8]], i8* [[ARRAYIDX6]], align 1 +// CHECK8-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] +// CHECK8: omp.par.pre_finalize: +// CHECK8-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB]] +// CHECK8: 13: +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 1) +// CHECK8-NEXT: [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0 +// CHECK8-NEXT: br i1 [[TMP15]], label [[DOTSPLIT:%.*]], label [[DOTCNCL:%.*]] +// CHECK8: .cncl: +// CHECK8-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB]] +// CHECK8: .split: +// CHECK8-NEXT: br label [[TMP3]] // // // CHECK8-LABEL: define {{[^@]+}}@.omp_task_entry. @@ -3629,23 +4743,23 @@ // CHECK8-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13 // CHECK8-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 // CHECK8-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13 -// CHECK8-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK8-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.*]], label [[DOTCANCEL_CONTINUE_I:%.*]] +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]] +// CHECK8-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]] +// CHECK8-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK8-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.*]], label [[DOTCANCEL_CONTINUE_I:%.*]] // CHECK8: .cancel.exit.i: // CHECK8-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 -// CHECK8-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK8-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK8: .cancel.continue.i: // CHECK8-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 -// CHECK8-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK8: .omp_outlined..1.exit: +// CHECK8-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] +// CHECK8: .omp_outlined..exit: // CHECK8-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 // CHECK8-NEXT: ret i32 0 // // -// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3660,53 +4774,55 @@ // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 0 -// CHECK8-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 0 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB17:[0-9]+]]) +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB15:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0 +// CHECK8-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 0 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK8-NEXT: switch i32 [[TMP6]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ // CHECK8-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] // CHECK8-NEXT: ] // CHECK8: .omp.sections.case: -// CHECK8-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) -// CHECK8-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 -// CHECK8-NEXT: br i1 [[TMP10]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK8: .cancel.exit: -// CHECK8-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK8: .cancel.continue: +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 3) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[DOTOMP_SECTIONS_CASE_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE_CNCL:%.*]] +// CHECK8: .omp.sections.case.split: // CHECK8-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK8: .omp.sections.case.cncl: +// CHECK8-NEXT: br label [[CANCEL_CONT:%.*]] // CHECK8: .omp.sections.exit: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK8-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK8: omp.inner.for.end: -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK8-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB19:[0-9]+]]) +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) +// CHECK8-NEXT: br label [[CANCEL_CONT]] // CHECK8: cancel.cont: // CHECK8-NEXT: ret void // CHECK8: cancel.exit: -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB19]]) +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) // CHECK8-NEXT: br label [[CANCEL_CONT]] // // -// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3721,62 +4837,65 @@ // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 1 -// CHECK8-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 1 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB21:[0-9]+]]) +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 1 +// CHECK8-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 1 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK8-NEXT: switch i32 [[TMP6]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ // CHECK8-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] -// CHECK8-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]] +// CHECK8-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE2:%.*]] // CHECK8-NEXT: ] // CHECK8: .omp.sections.case: -// CHECK8-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) -// CHECK8-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 -// CHECK8-NEXT: br i1 [[TMP10]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK8: .cancel.exit: -// CHECK8-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK8: .cancel.continue: +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 3) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[DOTOMP_SECTIONS_CASE_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE_CNCL:%.*]] +// CHECK8: .omp.sections.case.split: // CHECK8-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] -// CHECK8: .omp.sections.case1: -// CHECK8-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 3) -// CHECK8-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK8-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK8: .cancel.exit2: -// CHECK8-NEXT: br label [[CANCEL_EXIT]] -// CHECK8: .cancel.continue3: +// CHECK8: .omp.sections.case.cncl: +// CHECK8-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK8: .omp.sections.case2: +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32 3) +// CHECK8-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0 +// CHECK8-NEXT: br i1 [[TMP10]], label [[DOTOMP_SECTIONS_CASE2_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE2_CNCL:%.*]] +// CHECK8: .omp.sections.case2.split: // CHECK8-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] +// CHECK8: .omp.sections.case2.cncl: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END]] // CHECK8: .omp.sections.exit: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 +// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK8-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK8: omp.inner.for.end: -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK8-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB23:[0-9]+]]) +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM5]]) +// CHECK8-NEXT: br label [[CANCEL_CONT]] // CHECK8: cancel.cont: // CHECK8-NEXT: ret void // CHECK8: cancel.exit: -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB23]]) +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM4]]) // CHECK8-NEXT: br label [[CANCEL_CONT]] // // -// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3818,87 +4937,82 @@ // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK8-NEXT: store i32 0, i32* [[R3]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB5]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB25:[0-9]+]]) +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]] // CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK8: cond.true: -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK8-NEXT: br label [[COND_END:%.*]] // CHECK8: cond.false: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: br label [[COND_END]] // CHECK8: cond.end: -// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK8-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK8-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK8-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], i32 2) -// CHECK8-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK8-NEXT: br i1 [[TMP19]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM7:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB27:[0-9]+]]) +// CHECK8-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM7]], i32 2) +// CHECK8-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK8-NEXT: br i1 [[TMP15]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK8: .cancel.exit: // CHECK8-NEXT: br label [[CANCEL_EXIT:%.*]] // CHECK8: .cancel.continue: -// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] -// CHECK8-NEXT: store i32 [[ADD7]], i32* [[R3]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], [[TMP16]] +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[R3]], align 4 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: -// CHECK8-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP24]]) -// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK8-NEXT: [[TMP26:%.*]] = bitcast i32* [[R3]] to i8* -// CHECK8-NEXT: store i8* [[TMP26]], i8** [[TMP25]], align 8 -// CHECK8-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK8-NEXT: [[TMP29:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK8-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 [[TMP28]], i32 1, i64 8, i8* [[TMP29]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK8-NEXT: switch i32 [[TMP30]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29:[0-9]+]]) +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i32* [[R3]] to i8* +// CHECK8-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8 +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29]]) +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK8-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB30:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM12]], i32 1, i64 8, i8* [[TMP21]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK8-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK8-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK8-NEXT: ] // CHECK8: .omp.reduction.case1: -// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK8-NEXT: store i32 [[ADD9]], i32* [[TMP1]], align 4 -// CHECK8-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB7]], i32 [[TMP28]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK8-NEXT: store i32 [[ADD13]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB30]], i32 [[OMP_GLOBAL_THREAD_NUM12]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK8-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK8: cancel.exit: -// CHECK8-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB5]], i32 [[TMP34]]) +// CHECK8-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29]]) +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) // CHECK8-NEXT: br label [[CANCEL_CONT:%.*]] // CHECK8: .omp.reduction.case2: -// CHECK8-NEXT: [[TMP35:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK8-NEXT: [[TMP36:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP35]] monotonic, align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[R3]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP25]] monotonic, align 4 // CHECK8-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK8: .omp.reduction.default: // CHECK8-NEXT: br label [[OMP_PRECOND_END]] @@ -3931,1389 +5045,3 @@ // CHECK8-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 // CHECK8-NEXT: ret void // -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK9-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[P_LOWERBOUND:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[P_UPPERBOUND:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[P_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[P_LASTITER26:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[P_LOWERBOUND27:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[P_UPPERBOUND28:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[P_STRIDE29:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_33:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I35:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 -// CHECK9-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK9-NEXT: br label [[OMP_PARALLEL:%.*]] -// CHECK9: omp_parallel: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i8***)* @main..omp_par to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i8*** [[ARGV_ADDR]]) -// CHECK9-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] -// CHECK9: omp.par.outlined.exit: -// CHECK9-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] -// CHECK9: omp.par.exit.split: -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_PREHEADER:%.*]] -// CHECK9: omp_section_loop.preheader: -// CHECK9-NEXT: store i32 0, i32* [[P_LOWERBOUND]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[P_UPPERBOUND]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[P_STRIDE]], align 4 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 34, i32* [[P_LASTITER]], i32* [[P_LOWERBOUND]], i32* [[P_UPPERBOUND]], i32* [[P_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[P_LOWERBOUND]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[P_UPPERBOUND]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], [[TMP0]] -// CHECK9-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 1 -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_HEADER:%.*]] -// CHECK9: omp_section_loop.header: -// CHECK9-NEXT: [[OMP_SECTION_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_SECTION_LOOP_PREHEADER]] ], [ [[OMP_SECTION_LOOP_NEXT:%.*]], [[OMP_SECTION_LOOP_INC:%.*]] ] -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_COND:%.*]] -// CHECK9: omp_section_loop.cond: -// CHECK9-NEXT: [[OMP_SECTION_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_SECTION_LOOP_IV]], [[TMP3]] -// CHECK9-NEXT: br i1 [[OMP_SECTION_LOOP_CMP]], label [[OMP_SECTION_LOOP_BODY:%.*]], label [[OMP_SECTION_LOOP_EXIT:%.*]] -// CHECK9: omp_section_loop.body: -// CHECK9-NEXT: [[TMP4:%.*]] = add i32 [[OMP_SECTION_LOOP_IV]], [[TMP0]] -// CHECK9-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 1 -// CHECK9-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 0 -// CHECK9-NEXT: switch i32 [[TMP6]], label [[OMP_SECTION_LOOP_INC]] [ -// CHECK9-NEXT: i32 0, label [[OMP_SECTION_LOOP_BODY_CASE:%.*]] -// CHECK9-NEXT: ] -// CHECK9: omp_section_loop.inc: -// CHECK9-NEXT: [[OMP_SECTION_LOOP_NEXT]] = add nuw i32 [[OMP_SECTION_LOOP_IV]], 1 -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_HEADER]] -// CHECK9: omp_section_loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_AFTER:%.*]] -// CHECK9: omp_section_loop.after: -// CHECK9-NEXT: br label [[OMP_SECTIONS_END:%.*]] -// CHECK9: omp_sections.end: -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_PREHEADER12:%.*]] -// CHECK9: omp_section_loop.preheader12: -// CHECK9-NEXT: store i32 0, i32* [[P_LOWERBOUND27]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[P_UPPERBOUND28]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[P_STRIDE29]], align 4 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM30:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]], i32 34, i32* [[P_LASTITER26]], i32* [[P_LOWERBOUND27]], i32* [[P_UPPERBOUND28]], i32* [[P_STRIDE29]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[P_LOWERBOUND27]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[P_UPPERBOUND28]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], [[TMP7]] -// CHECK9-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 1 -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_HEADER13:%.*]] -// CHECK9: omp_section_loop.header13: -// CHECK9-NEXT: [[OMP_SECTION_LOOP_IV19:%.*]] = phi i32 [ 0, [[OMP_SECTION_LOOP_PREHEADER12]] ], [ [[OMP_SECTION_LOOP_NEXT21:%.*]], [[OMP_SECTION_LOOP_INC16:%.*]] ] -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_COND14:%.*]] -// CHECK9: omp_section_loop.cond14: -// CHECK9-NEXT: [[OMP_SECTION_LOOP_CMP20:%.*]] = icmp ult i32 [[OMP_SECTION_LOOP_IV19]], [[TMP10]] -// CHECK9-NEXT: br i1 [[OMP_SECTION_LOOP_CMP20]], label [[OMP_SECTION_LOOP_BODY15:%.*]], label [[OMP_SECTION_LOOP_EXIT17:%.*]] -// CHECK9: omp_section_loop.body15: -// CHECK9-NEXT: [[TMP11:%.*]] = add i32 [[OMP_SECTION_LOOP_IV19]], [[TMP7]] -// CHECK9-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 -// CHECK9-NEXT: [[TMP13:%.*]] = add i32 [[TMP12]], 0 -// CHECK9-NEXT: switch i32 [[TMP13]], label [[OMP_SECTION_LOOP_INC16]] [ -// CHECK9-NEXT: i32 0, label [[OMP_SECTION_LOOP_BODY_CASE22:%.*]] -// CHECK9-NEXT: i32 1, label [[OMP_SECTION_LOOP_BODY_CASE24:%.*]] -// CHECK9-NEXT: ] -// CHECK9: omp_section_loop.inc16: -// CHECK9-NEXT: [[OMP_SECTION_LOOP_NEXT21]] = add nuw i32 [[OMP_SECTION_LOOP_IV19]], 1 -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_HEADER13]] -// CHECK9: omp_section_loop.exit17: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]]) -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM31:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM31]]) -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_AFTER18:%.*]] -// CHECK9: omp_section_loop.after18: -// CHECK9-NEXT: br label [[OMP_SECTIONS_END32:%.*]] -// CHECK9: omp_sections.end32: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB34:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB34]], i32* [[DOTCAPTURE_EXPR_33]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 -// CHECK9-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM36:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM36]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 -// CHECK9-NEXT: [[CMP37:%.*]] = icmp sgt i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: br i1 [[CMP37]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP20]], [[COND_TRUE]] ], [ [[TMP21]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP38:%.*]] = icmp sle i32 [[TMP23]], [[TMP24]] -// CHECK9-NEXT: br i1 [[CMP38]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP25]], 1 -// CHECK9-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD39]], i32* [[I35]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load float, float* @flag, align 4 -// CHECK9-NEXT: [[TOBOOL40:%.*]] = fcmp une float [[TMP26]], 0.000000e+00 -// CHECK9-NEXT: br i1 [[TOBOOL40]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK9: omp_if.then: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) -// CHECK9-NEXT: [[TMP27:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]], i32 2) -// CHECK9-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK9-NEXT: br i1 [[TMP28]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK9: .cancel.exit: -// CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK9: omp_section_loop.body.case: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM9:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9]], i32 3) -// CHECK9-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP29]], 0 -// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_SECTION_LOOP_BODY_CASE_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE_CNCL:%.*]] -// CHECK9: omp_section_loop.body.case.split: -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_EXIT]] -// CHECK9: omp_section_loop.body.case.cncl: -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_EXIT]] -// CHECK9: omp_section_loop.body.case22: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]], i32 3) -// CHECK9-NEXT: [[TMP32:%.*]] = icmp eq i32 [[TMP31]], 0 -// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_SECTION_LOOP_BODY_CASE22_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE22_CNCL:%.*]] -// CHECK9: omp_section_loop.body.case22.split: -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] -// CHECK9: omp_section_loop.body.case22.cncl: -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] -// CHECK9: omp_section_loop.body.case24: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM25:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: [[TMP33:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM25]], i32 3) -// CHECK9-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP33]], 0 -// CHECK9-NEXT: br i1 [[TMP34]], label [[OMP_SECTION_LOOP_BODY_CASE24_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE24_CNCL:%.*]] -// CHECK9: omp_section_loop.body.case24.split: -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] -// CHECK9: omp_section_loop.body.case24.cncl: -// CHECK9-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] -// CHECK9: .cancel.continue: -// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK9: omp_if.else: -// CHECK9-NEXT: br label [[OMP_IF_END]] -// CHECK9: omp_if.end: -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK9-NEXT: store i32 [[ADD42]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM44:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM44]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: cancel.exit: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM43:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM43]]) -// CHECK9-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: br label [[CANCEL_CONT]] -// CHECK9: cancel.cont: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM45:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM45]]) -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM46:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB14:[0-9]+]]) -// CHECK9-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM46]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM47:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB14]]) -// CHECK9-NEXT: [[TMP39:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM47]], i8* [[TMP36]]) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i32* [[R]]) -// CHECK9-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: ret i32 [[TMP40]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main..omp_par -// CHECK9-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[ARGC_ADDR:%.*]], i8*** [[ARGV_ADDR:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK9-NEXT: omp.par.entry: -// CHECK9-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 -// CHECK9-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 -// CHECK9-NEXT: br label [[OMP_PAR_REGION:%.*]] -// CHECK9: omp.par.outlined.exit.exitStub: -// CHECK9-NEXT: ret void -// CHECK9: omp.par.region: -// CHECK9-NEXT: [[TMP1:%.*]] = load float, float* @flag, align 4 -// CHECK9-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP1]], 0.000000e+00 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[TMP13:%.*]], label [[TMP2:%.*]] -// CHECK9: 2: -// CHECK9-NEXT: br label [[TMP3:%.*]] -// CHECK9: 3: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i32 [[TMP4]] to i8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP5]], i64 0 -// CHECK9-NEXT: [[TMP6:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, i8* [[TMP6]], i64 0 -// CHECK9-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX2]], align 1 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[DOTCONT:%.*]], label [[DOTCNCL4:%.*]] -// CHECK9: .cncl4: -// CHECK9-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] -// CHECK9: .cont: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i8*, i8** [[TMP10]], i64 0 -// CHECK9-NEXT: [[TMP11:%.*]] = load i8*, i8** [[ARRAYIDX5]], align 8 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i8, i8* [[TMP11]], i64 0 -// CHECK9-NEXT: [[TMP12:%.*]] = load i8, i8* [[ARRAYIDX6]], align 1 -// CHECK9-NEXT: [[CONV7:%.*]] = sext i8 [[TMP12]] to i32 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV7]], [[TMP9]] -// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK9-NEXT: store i8 [[CONV8]], i8* [[ARRAYIDX6]], align 1 -// CHECK9-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] -// CHECK9: omp.par.pre_finalize: -// CHECK9-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB]] -// CHECK9: 13: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 1) -// CHECK9-NEXT: [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0 -// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTSPLIT:%.*]], label [[DOTCNCL:%.*]] -// CHECK9: .cncl: -// CHECK9-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB]] -// CHECK9: .split: -// CHECK9-NEXT: br label [[TMP3]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK9-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK9-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK9-NEXT: [[CLEANUP_DEST_SLOT_I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK9-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]]) -// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) -// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) -// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13 -// CHECK9-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13 -// CHECK9-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13 -// CHECK9-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13 -// CHECK9-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13 -// CHECK9-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 -// CHECK9-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]] -// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.*]], label [[DOTCANCEL_CONTINUE_I:%.*]] -// CHECK9: .cancel.exit.i: -// CHECK9-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 -// CHECK9-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]] -// CHECK9: .cancel.continue.i: -// CHECK9-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 -// CHECK9-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] -// CHECK9: .omp_outlined..exit: -// CHECK9-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB17:[0-9]+]]) -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB15:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0 -// CHECK9-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 0 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK9-NEXT: switch i32 [[TMP6]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ -// CHECK9-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] -// CHECK9-NEXT: ] -// CHECK9: .omp.sections.case: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 3) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[DOTOMP_SECTIONS_CASE_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE_CNCL:%.*]] -// CHECK9: .omp.sections.case.split: -// CHECK9-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] -// CHECK9: .omp.sections.case.cncl: -// CHECK9-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK9: .omp.sections.exit: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB19:[0-9]+]]) -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) -// CHECK9-NEXT: br label [[CANCEL_CONT]] -// CHECK9: cancel.cont: -// CHECK9-NEXT: ret void -// CHECK9: cancel.exit: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB19]]) -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) -// CHECK9-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB21:[0-9]+]]) -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 1 -// CHECK9-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 1 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK9-NEXT: switch i32 [[TMP6]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ -// CHECK9-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] -// CHECK9-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE2:%.*]] -// CHECK9-NEXT: ] -// CHECK9: .omp.sections.case: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 3) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[DOTOMP_SECTIONS_CASE_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE_CNCL:%.*]] -// CHECK9: .omp.sections.case.split: -// CHECK9-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] -// CHECK9: .omp.sections.case.cncl: -// CHECK9-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK9: .omp.sections.case2: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32 3) -// CHECK9-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0 -// CHECK9-NEXT: br i1 [[TMP10]], label [[DOTOMP_SECTIONS_CASE2_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE2_CNCL:%.*]] -// CHECK9: .omp.sections.case2.split: -// CHECK9-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] -// CHECK9: .omp.sections.case2.cncl: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END]] -// CHECK9: .omp.sections.exit: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB23:[0-9]+]]) -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM5]]) -// CHECK9-NEXT: br label [[CANCEL_CONT]] -// CHECK9: cancel.cont: -// CHECK9-NEXT: ret void -// CHECK9: cancel.exit: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB23]]) -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM4]]) -// CHECK9-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[R_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[R3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[R]], i32** [[R_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[R_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[R3]], align 4 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB25:[0-9]+]]) -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM7:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB27:[0-9]+]]) -// CHECK9-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM7]], i32 2) -// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK9: .cancel.exit: -// CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK9: .cancel.continue: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], [[TMP16]] -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[R3]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29:[0-9]+]]) -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i32* [[R3]] to i8* -// CHECK9-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8 -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29]]) -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB30:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM12]], i32 1, i64 8, i8* [[TMP21]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK9-NEXT: ] -// CHECK9: .omp.reduction.case1: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK9-NEXT: store i32 [[ADD13]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB30]], i32 [[OMP_GLOBAL_THREAD_NUM12]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: cancel.exit: -// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29]]) -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) -// CHECK9-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK9: .omp.reduction.case2: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP25]] monotonic, align 4 -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.default: -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: br label [[CANCEL_CONT]] -// CHECK9: cancel.cont: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK9-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK10-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[P_LOWERBOUND:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[P_UPPERBOUND:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[P_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[P_LASTITER26:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[P_LOWERBOUND27:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[P_UPPERBOUND28:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[P_STRIDE29:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_33:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I35:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 -// CHECK10-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK10-NEXT: br label [[OMP_PARALLEL:%.*]] -// CHECK10: omp_parallel: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i8***)* @main..omp_par to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i8*** [[ARGV_ADDR]]) -// CHECK10-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] -// CHECK10: omp.par.outlined.exit: -// CHECK10-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] -// CHECK10: omp.par.exit.split: -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_PREHEADER:%.*]] -// CHECK10: omp_section_loop.preheader: -// CHECK10-NEXT: store i32 0, i32* [[P_LOWERBOUND]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[P_UPPERBOUND]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[P_STRIDE]], align 4 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 34, i32* [[P_LASTITER]], i32* [[P_LOWERBOUND]], i32* [[P_UPPERBOUND]], i32* [[P_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[P_LOWERBOUND]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[P_UPPERBOUND]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], [[TMP0]] -// CHECK10-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 1 -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_HEADER:%.*]] -// CHECK10: omp_section_loop.header: -// CHECK10-NEXT: [[OMP_SECTION_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_SECTION_LOOP_PREHEADER]] ], [ [[OMP_SECTION_LOOP_NEXT:%.*]], [[OMP_SECTION_LOOP_INC:%.*]] ] -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_COND:%.*]] -// CHECK10: omp_section_loop.cond: -// CHECK10-NEXT: [[OMP_SECTION_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_SECTION_LOOP_IV]], [[TMP3]] -// CHECK10-NEXT: br i1 [[OMP_SECTION_LOOP_CMP]], label [[OMP_SECTION_LOOP_BODY:%.*]], label [[OMP_SECTION_LOOP_EXIT:%.*]] -// CHECK10: omp_section_loop.body: -// CHECK10-NEXT: [[TMP4:%.*]] = add i32 [[OMP_SECTION_LOOP_IV]], [[TMP0]] -// CHECK10-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 1 -// CHECK10-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 0 -// CHECK10-NEXT: switch i32 [[TMP6]], label [[OMP_SECTION_LOOP_INC]] [ -// CHECK10-NEXT: i32 0, label [[OMP_SECTION_LOOP_BODY_CASE:%.*]] -// CHECK10-NEXT: ] -// CHECK10: omp_section_loop.inc: -// CHECK10-NEXT: [[OMP_SECTION_LOOP_NEXT]] = add nuw i32 [[OMP_SECTION_LOOP_IV]], 1 -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_HEADER]] -// CHECK10: omp_section_loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_AFTER:%.*]] -// CHECK10: omp_section_loop.after: -// CHECK10-NEXT: br label [[OMP_SECTIONS_END:%.*]] -// CHECK10: omp_sections.end: -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_PREHEADER12:%.*]] -// CHECK10: omp_section_loop.preheader12: -// CHECK10-NEXT: store i32 0, i32* [[P_LOWERBOUND27]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[P_UPPERBOUND28]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[P_STRIDE29]], align 4 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM30:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]], i32 34, i32* [[P_LASTITER26]], i32* [[P_LOWERBOUND27]], i32* [[P_UPPERBOUND28]], i32* [[P_STRIDE29]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[P_LOWERBOUND27]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[P_UPPERBOUND28]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], [[TMP7]] -// CHECK10-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 1 -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_HEADER13:%.*]] -// CHECK10: omp_section_loop.header13: -// CHECK10-NEXT: [[OMP_SECTION_LOOP_IV19:%.*]] = phi i32 [ 0, [[OMP_SECTION_LOOP_PREHEADER12]] ], [ [[OMP_SECTION_LOOP_NEXT21:%.*]], [[OMP_SECTION_LOOP_INC16:%.*]] ] -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_COND14:%.*]] -// CHECK10: omp_section_loop.cond14: -// CHECK10-NEXT: [[OMP_SECTION_LOOP_CMP20:%.*]] = icmp ult i32 [[OMP_SECTION_LOOP_IV19]], [[TMP10]] -// CHECK10-NEXT: br i1 [[OMP_SECTION_LOOP_CMP20]], label [[OMP_SECTION_LOOP_BODY15:%.*]], label [[OMP_SECTION_LOOP_EXIT17:%.*]] -// CHECK10: omp_section_loop.body15: -// CHECK10-NEXT: [[TMP11:%.*]] = add i32 [[OMP_SECTION_LOOP_IV19]], [[TMP7]] -// CHECK10-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 -// CHECK10-NEXT: [[TMP13:%.*]] = add i32 [[TMP12]], 0 -// CHECK10-NEXT: switch i32 [[TMP13]], label [[OMP_SECTION_LOOP_INC16]] [ -// CHECK10-NEXT: i32 0, label [[OMP_SECTION_LOOP_BODY_CASE22:%.*]] -// CHECK10-NEXT: i32 1, label [[OMP_SECTION_LOOP_BODY_CASE24:%.*]] -// CHECK10-NEXT: ] -// CHECK10: omp_section_loop.inc16: -// CHECK10-NEXT: [[OMP_SECTION_LOOP_NEXT21]] = add nuw i32 [[OMP_SECTION_LOOP_IV19]], 1 -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_HEADER13]] -// CHECK10: omp_section_loop.exit17: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]]) -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM31:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM31]]) -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_AFTER18:%.*]] -// CHECK10: omp_section_loop.after18: -// CHECK10-NEXT: br label [[OMP_SECTIONS_END32:%.*]] -// CHECK10: omp_sections.end32: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB34:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB34]], i32* [[DOTCAPTURE_EXPR_33]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 -// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM36:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM36]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 -// CHECK10-NEXT: [[CMP37:%.*]] = icmp sgt i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: br i1 [[CMP37]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_33]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP20]], [[COND_TRUE]] ], [ [[TMP21]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP38:%.*]] = icmp sle i32 [[TMP23]], [[TMP24]] -// CHECK10-NEXT: br i1 [[CMP38]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP25]], 1 -// CHECK10-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD39]], i32* [[I35]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load float, float* @flag, align 4 -// CHECK10-NEXT: [[TOBOOL40:%.*]] = fcmp une float [[TMP26]], 0.000000e+00 -// CHECK10-NEXT: br i1 [[TOBOOL40]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK10: omp_if.then: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) -// CHECK10-NEXT: [[TMP27:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]], i32 2) -// CHECK10-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK10-NEXT: br i1 [[TMP28]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK10: .cancel.exit: -// CHECK10-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK10: omp_section_loop.body.case: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM9:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9]], i32 3) -// CHECK10-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP29]], 0 -// CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_SECTION_LOOP_BODY_CASE_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE_CNCL:%.*]] -// CHECK10: omp_section_loop.body.case.split: -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_EXIT]] -// CHECK10: omp_section_loop.body.case.cncl: -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_EXIT]] -// CHECK10: omp_section_loop.body.case22: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]], i32 3) -// CHECK10-NEXT: [[TMP32:%.*]] = icmp eq i32 [[TMP31]], 0 -// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_SECTION_LOOP_BODY_CASE22_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE22_CNCL:%.*]] -// CHECK10: omp_section_loop.body.case22.split: -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] -// CHECK10: omp_section_loop.body.case22.cncl: -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] -// CHECK10: omp_section_loop.body.case24: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM25:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: [[TMP33:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM25]], i32 3) -// CHECK10-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP33]], 0 -// CHECK10-NEXT: br i1 [[TMP34]], label [[OMP_SECTION_LOOP_BODY_CASE24_SPLIT:%.*]], label [[OMP_SECTION_LOOP_BODY_CASE24_CNCL:%.*]] -// CHECK10: omp_section_loop.body.case24.split: -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] -// CHECK10: omp_section_loop.body.case24.cncl: -// CHECK10-NEXT: br label [[OMP_SECTION_LOOP_EXIT17]] -// CHECK10: .cancel.continue: -// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK10: omp_if.else: -// CHECK10-NEXT: br label [[OMP_IF_END]] -// CHECK10: omp_if.end: -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK10-NEXT: store i32 [[ADD42]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM44:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM44]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: cancel.exit: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM43:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM43]]) -// CHECK10-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: br label [[CANCEL_CONT]] -// CHECK10: cancel.cont: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM45:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM45]]) -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM46:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB14:[0-9]+]]) -// CHECK10-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM46]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM47:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB14]]) -// CHECK10-NEXT: [[TMP39:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM47]], i8* [[TMP36]]) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]], i32* [[R]]) -// CHECK10-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: ret i32 [[TMP40]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@main..omp_par -// CHECK10-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[ARGC_ADDR:%.*]], i8*** [[ARGV_ADDR:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK10-NEXT: omp.par.entry: -// CHECK10-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 -// CHECK10-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 -// CHECK10-NEXT: br label [[OMP_PAR_REGION:%.*]] -// CHECK10: omp.par.outlined.exit.exitStub: -// CHECK10-NEXT: ret void -// CHECK10: omp.par.region: -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* @flag, align 4 -// CHECK10-NEXT: [[TOBOOL:%.*]] = fcmp une float [[TMP1]], 0.000000e+00 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[TMP13:%.*]], label [[TMP2:%.*]] -// CHECK10: 2: -// CHECK10-NEXT: br label [[TMP3:%.*]] -// CHECK10: 3: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i32 [[TMP4]] to i8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP5]], i64 0 -// CHECK10-NEXT: [[TMP6:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, i8* [[TMP6]], i64 0 -// CHECK10-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX2]], align 1 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[DOTCONT:%.*]], label [[DOTCNCL4:%.*]] -// CHECK10: .cncl4: -// CHECK10-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] -// CHECK10: .cont: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i8*, i8** [[TMP10]], i64 0 -// CHECK10-NEXT: [[TMP11:%.*]] = load i8*, i8** [[ARRAYIDX5]], align 8 -// CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i8, i8* [[TMP11]], i64 0 -// CHECK10-NEXT: [[TMP12:%.*]] = load i8, i8* [[ARRAYIDX6]], align 1 -// CHECK10-NEXT: [[CONV7:%.*]] = sext i8 [[TMP12]] to i32 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV7]], [[TMP9]] -// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK10-NEXT: store i8 [[CONV8]], i8* [[ARRAYIDX6]], align 1 -// CHECK10-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] -// CHECK10: omp.par.pre_finalize: -// CHECK10-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB]] -// CHECK10: 13: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 1) -// CHECK10-NEXT: [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0 -// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTSPLIT:%.*]], label [[DOTCNCL:%.*]] -// CHECK10: .cncl: -// CHECK10-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB]] -// CHECK10: .split: -// CHECK10-NEXT: br label [[TMP3]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK10-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK10-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK10-NEXT: [[CLEANUP_DEST_SLOT_I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK10-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]]) -// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) -// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) -// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13 -// CHECK10-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13 -// CHECK10-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13 -// CHECK10-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13 -// CHECK10-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13 -// CHECK10-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 -// CHECK10-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]] -// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.*]], label [[DOTCANCEL_CONTINUE_I:%.*]] -// CHECK10: .cancel.exit.i: -// CHECK10-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 -// CHECK10-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]] -// CHECK10: .cancel.continue.i: -// CHECK10-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 -// CHECK10-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] -// CHECK10: .omp_outlined..exit: -// CHECK10-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13 -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB17:[0-9]+]]) -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB15:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0 -// CHECK10-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 0 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK10-NEXT: switch i32 [[TMP6]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ -// CHECK10-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] -// CHECK10-NEXT: ] -// CHECK10: .omp.sections.case: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 3) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[DOTOMP_SECTIONS_CASE_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE_CNCL:%.*]] -// CHECK10: .omp.sections.case.split: -// CHECK10-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] -// CHECK10: .omp.sections.case.cncl: -// CHECK10-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK10: .omp.sections.exit: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB19:[0-9]+]]) -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) -// CHECK10-NEXT: br label [[CANCEL_CONT]] -// CHECK10: cancel.cont: -// CHECK10-NEXT: ret void -// CHECK10: cancel.exit: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB19]]) -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) -// CHECK10-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB21:[0-9]+]]) -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 1 -// CHECK10-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 1 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK10-NEXT: switch i32 [[TMP6]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ -// CHECK10-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] -// CHECK10-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE2:%.*]] -// CHECK10-NEXT: ] -// CHECK10: .omp.sections.case: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32 3) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[DOTOMP_SECTIONS_CASE_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE_CNCL:%.*]] -// CHECK10: .omp.sections.case.split: -// CHECK10-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] -// CHECK10: .omp.sections.case.cncl: -// CHECK10-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK10: .omp.sections.case2: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32 3) -// CHECK10-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0 -// CHECK10-NEXT: br i1 [[TMP10]], label [[DOTOMP_SECTIONS_CASE2_SPLIT:%.*]], label [[DOTOMP_SECTIONS_CASE2_CNCL:%.*]] -// CHECK10: .omp.sections.case2.split: -// CHECK10-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] -// CHECK10: .omp.sections.case2.cncl: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END]] -// CHECK10: .omp.sections.exit: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB23:[0-9]+]]) -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM5]]) -// CHECK10-NEXT: br label [[CANCEL_CONT]] -// CHECK10: cancel.cont: -// CHECK10-NEXT: ret void -// CHECK10: cancel.exit: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB23]]) -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB15]], i32 [[OMP_GLOBAL_THREAD_NUM4]]) -// CHECK10-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[R_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[R3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[R]], i32** [[R_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[R_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[R3]], align 4 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB25:[0-9]+]]) -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM7:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB27:[0-9]+]]) -// CHECK10-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM7]], i32 2) -// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK10: .cancel.exit: -// CHECK10-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK10: .cancel.continue: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], [[TMP16]] -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[R3]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29:[0-9]+]]) -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i32* [[R3]] to i8* -// CHECK10-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8 -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29]]) -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK10-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB30:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM12]], i32 1, i64 8, i8* [[TMP21]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK10-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK10-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK10-NEXT: ] -// CHECK10: .omp.reduction.case1: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK10-NEXT: store i32 [[ADD13]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB30]], i32 [[OMP_GLOBAL_THREAD_NUM12]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK10: cancel.exit: -// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB29]]) -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) -// CHECK10-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK10: .omp.reduction.case2: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[R3]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP25]] monotonic, align 4 -// CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK10: .omp.reduction.default: -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: br label [[CANCEL_CONT]] -// CHECK10: cancel.cont: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK10-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK11-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK11-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK11-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8*, i8** [[TMP4]], i64 0 -// CHECK11-NEXT: [[TMP5:%.*]] = load i8*, i8** [[ARRAYIDX2]], align 8 -// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, i8* [[TMP5]], i64 0 -// CHECK11-NEXT: [[TMP6:%.*]] = load i8, i8* [[ARRAYIDX3]], align 1 -// CHECK11-NEXT: [[CONV4:%.*]] = sext i8 [[TMP6]] to i32 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[TMP3]] -// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK11-NEXT: store i8 [[CONV5]], i8* [[ARRAYIDX3]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK11-NEXT: br label [[FOR_COND7:%.*]] -// CHECK11: for.cond7: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END13:%.*]] -// CHECK11: for.body9: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[R]], align 4 -// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[R]], align 4 -// CHECK11-NEXT: br label [[FOR_INC11:%.*]] -// CHECK11: for.inc11: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK11-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: store i32 [[INC12]], i32* [[I6]], align 4 -// CHECK11-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK11: for.end13: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: ret i32 [[TMP15]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK12-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK12-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK12-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8*, i8** [[TMP4]], i64 0 -// CHECK12-NEXT: [[TMP5:%.*]] = load i8*, i8** [[ARRAYIDX2]], align 8 -// CHECK12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, i8* [[TMP5]], i64 0 -// CHECK12-NEXT: [[TMP6:%.*]] = load i8, i8* [[ARRAYIDX3]], align 1 -// CHECK12-NEXT: [[CONV4:%.*]] = sext i8 [[TMP6]] to i32 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[TMP3]] -// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK12-NEXT: store i8 [[CONV5]], i8* [[ARRAYIDX3]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK12-NEXT: br label [[FOR_COND7:%.*]] -// CHECK12: for.cond7: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END13:%.*]] -// CHECK12: for.body9: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[R]], align 4 -// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[R]], align 4 -// CHECK12-NEXT: br label [[FOR_INC11:%.*]] -// CHECK12: for.inc11: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK12-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[INC12]], i32* [[I6]], align 4 -// CHECK12-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK12: for.end13: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: ret i32 [[TMP15]] -// diff --git a/clang/test/OpenMP/cancellation_point_codegen.cpp b/clang/test/OpenMP/cancellation_point_codegen.cpp --- a/clang/test/OpenMP/cancellation_point_codegen.cpp +++ b/clang/test/OpenMP/cancellation_point_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1335,107 +1335,3 @@ // CHECK2: cancel.cont: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK3-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK3-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3:%.*]] -// CHECK3: for.cond3: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK3-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK3: for.body5: -// CHECK3-NEXT: br label [[FOR_INC6:%.*]] -// CHECK3: for.inc6: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK3-NEXT: store i32 [[INC7]], i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end8: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: ret i32 [[TMP9]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK4-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK4-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3:%.*]] -// CHECK4: for.cond3: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK4-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK4: for.body5: -// CHECK4-NEXT: br label [[FOR_INC6:%.*]] -// CHECK4: for.inc6: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK4-NEXT: store i32 [[INC7]], i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end8: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: ret i32 [[TMP9]] -// diff --git a/clang/test/OpenMP/debug-info-complex-byval.cpp b/clang/test/OpenMP/debug-info-complex-byval.cpp --- a/clang/test/OpenMP/debug-info-complex-byval.cpp +++ b/clang/test/OpenMP/debug-info-complex-byval.cpp @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // RUN: %clang_cc1 -fopenmp -x c++ %s -verify -debug-info-kind=limited -triple x86_64-unknown-unknown -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -triple x86_64-unknown-unknown -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -triple x86_64-unknown-unknown -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics void a() { @@ -61,11 +61,3 @@ // CHECK1-NEXT: call void @.omp_outlined._debug__(i32* [[TMP0]], i32* [[TMP1]], <2 x float> [[TMP3]]) #[[ATTR4:[0-9]+]], !dbg [[DBG37]] // CHECK1-NEXT: ret void, !dbg [[DBG37]] // -// -// CHECK2-LABEL: define {{[^@]+}}@_Z1av -// CHECK2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[B:%.*]] = alloca { float, float }, align 4 -// CHECK2-NEXT: call void @llvm.dbg.declare(metadata { float, float }* [[B]], metadata [[META10:![0-9]+]], metadata !DIExpression()), !dbg [[DBG12:![0-9]+]] -// CHECK2-NEXT: ret void, !dbg [[DBG13:![0-9]+]] -// diff --git a/clang/test/OpenMP/debug-info-openmp-array.cpp b/clang/test/OpenMP/debug-info-openmp-array.cpp --- a/clang/test/OpenMP/debug-info-openmp-array.cpp +++ b/clang/test/OpenMP/debug-info-openmp-array.cpp @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // RUN: %clang_cc1 -triple x86_64-unknown-linux -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics void f(int m) { @@ -175,46 +175,3 @@ // CHECK1-NEXT: call void @.omp_outlined._debug__(i32* [[TMP3]], i32* [[TMP4]], i32* [[TMP5]], i64 [[TMP1]], i32* [[TMP6]]) #[[ATTR4:[0-9]+]], !dbg [[DBG71]] // CHECK1-NEXT: ret void, !dbg [[DBG71]] // -// -// CHECK2-LABEL: define {{[^@]+}}@_Z1fi -// CHECK2-SAME: (i32 [[M:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK2-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[M_ADDR]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG12:![0-9]+]] -// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[I]], metadata [[META13:![0-9]+]], metadata !DIExpression()), !dbg [[DBG14:![0-9]+]] -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[M_ADDR]], align 4, !dbg [[DBG15:![0-9]+]] -// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG16:![0-9]+]] -// CHECK2-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG16]] -// CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG16]] -// CHECK2-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG16]] -// CHECK2-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG16]] -// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META17:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]] -// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA]], metadata [[META20:![0-9]+]], metadata !DIExpression()), !dbg [[DBG24:![0-9]+]] -// CHECK2-NEXT: store i32 0, i32* [[I]], align 4, !dbg [[DBG25:![0-9]+]] -// CHECK2-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK2: for.cond: -// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG29:![0-9]+]] -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4, !dbg [[DBG31:![0-9]+]] -// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]], !dbg [[DBG32:![0-9]+]] -// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG33:![0-9]+]] -// CHECK2: for.body: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG34:![0-9]+]] -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64, !dbg [[DBG37:![0-9]+]] -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]], !dbg [[DBG37]] -// CHECK2-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !dbg [[DBG38:![0-9]+]] -// CHECK2-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG39:![0-9]+]] -// CHECK2: for.inc: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG40:![0-9]+]] -// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1, !dbg [[DBG40]] -// CHECK2-NEXT: store i32 [[INC]], i32* [[I]], align 4, !dbg [[DBG40]] -// CHECK2-NEXT: br label [[FOR_COND]], !dbg [[DBG41:![0-9]+]], !llvm.loop [[LOOP42:![0-9]+]] -// CHECK2: for.end: -// CHECK2-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG45:![0-9]+]] -// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]), !dbg [[DBG45]] -// CHECK2-NEXT: ret void, !dbg [[DBG45]] -// diff --git a/clang/test/OpenMP/distribute_codegen.cpp b/clang/test/OpenMP/distribute_codegen.cpp --- a/clang/test/OpenMP/distribute_codegen.cpp +++ b/clang/test/OpenMP/distribute_codegen.cpp @@ -14,38 +14,38 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -6708,4558 +6708,2134 @@ // CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK9-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK9-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK9-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK9: for.end: +// CHECK9-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] +// CHECK9-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK9-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] +// CHECK9-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK9-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK9-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] +// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 +// CHECK9-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] +// CHECK9-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] +// CHECK9-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK9: for.end: +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK9-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK9-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK9-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK9-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] +// CHECK9-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK9-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] +// CHECK9-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK9-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK9-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] +// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 +// CHECK9-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] +// CHECK9-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] +// CHECK9-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end: +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK9-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK9-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK9-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] +// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 +// CHECK9-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] +// CHECK9-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] +// CHECK9-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] +// CHECK9-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] +// CHECK9-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] +// CHECK9-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] +// CHECK9-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 +// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] +// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] +// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 +// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK9-SAME: () #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK9-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK9-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK9-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK9: for.end: +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I5:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 +// CHECK9-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// CHECK9-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK9-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] +// CHECK9-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 +// CHECK9-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK9-SAME: () #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 +// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK9-NEXT: ret i32 [[CALL]] +// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) +// CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK9-SAME: () #[[ATTR0]] comdat { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK9-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 // CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 // CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 // CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 // CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK10-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK10-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK10-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: +// CHECK10-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] +// CHECK10-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] +// CHECK10-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK10-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK10-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] +// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 +// CHECK10-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] +// CHECK10-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] +// CHECK10-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 // CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 // CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 // CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 // CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK10: for.end: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK10-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK10-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK10-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK10-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] +// CHECK10-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] +// CHECK10-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK10-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK10-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] +// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 +// CHECK10-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] +// CHECK10-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] +// CHECK10-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 // CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 // CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 // CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 // CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK10-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK10-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK10-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 +// CHECK10-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] +// CHECK10-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] +// CHECK10-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] +// CHECK10-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] +// CHECK10-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] +// CHECK10-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 +// CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] +// CHECK10-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 +// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] +// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] +// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 +// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK10-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK10-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK10: for.end: +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I5:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 +// CHECK10-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// CHECK10-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK10-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK10-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 +// CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] +// CHECK10-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 +// CHECK10-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 +// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK10-NEXT: ret i32 [[CALL]] +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) +// CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK10-SAME: () #[[ATTR0]] comdat { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK10-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 // CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK11-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK11-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK11-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK11-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK11-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK11: for.end: +// CHECK11-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] +// CHECK11-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] +// CHECK11-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK11-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] +// CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 +// CHECK11-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] +// CHECK11-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] +// CHECK11-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 // CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK11-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK11-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK11: for.end: +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK11-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK11-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK11-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK11-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] +// CHECK11-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] +// CHECK11-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK11-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] +// CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 +// CHECK11-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] +// CHECK11-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] +// CHECK11-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 // CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK11-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK11-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end: +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK11-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK11-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK11-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] +// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 +// CHECK11-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] +// CHECK11-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] +// CHECK11-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] +// CHECK11-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] +// CHECK11-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] +// CHECK11-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] +// CHECK11-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] +// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK11-SAME: () #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 +// CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK11-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK11-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK11-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK11: for.end: +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I5:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 +// CHECK11-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// CHECK11-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK11-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] +// CHECK11-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 +// CHECK11-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK11-SAME: () #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 +// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK11-NEXT: ret i32 [[CALL]] +// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) +// CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK11-SAME: () #[[ATTR0]] comdat { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK11-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 // CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 // CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 // CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 // CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK12-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK12-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK12-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK12-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK12-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK12: for.end: +// CHECK12-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] +// CHECK12-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] +// CHECK12-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK12-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] +// CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 +// CHECK12-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] +// CHECK12-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] +// CHECK12-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 // CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 // CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 // CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 // CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK12-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK12-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK12: for.end: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK12-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK12-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK12-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK12-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] +// CHECK12-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] +// CHECK12-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK12-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] +// CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 +// CHECK12-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] +// CHECK12-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] +// CHECK12-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 // CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 // CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 // CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 // CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK12-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK12-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK12-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK12-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK12-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] +// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 +// CHECK12-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] +// CHECK12-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] +// CHECK12-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] +// CHECK12-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] +// CHECK12-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] +// CHECK12-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] +// CHECK12-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] +// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] +// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK12-SAME: () #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 +// CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK12-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK12-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK12-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK12: for.end: +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I5:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 +// CHECK12-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// CHECK12-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK12-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK12-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 +// CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] +// CHECK12-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 +// CHECK12-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK12-SAME: () #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 +// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK12-NEXT: ret i32 [[CALL]] +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) +// CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK12-SAME: () #[[ATTR0]] comdat { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK13-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK13-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK13-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK13-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK13-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK13-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK13-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK13-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK13-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK13-NEXT: ret i32 [[CALL]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK13-SAME: () #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK14-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK14-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK14-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK14-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK14-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK14-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK14-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK14-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK14-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK14-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK14-NEXT: ret i32 [[CALL]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK14-SAME: () #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK15-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK15-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK15-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK15-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK15-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK15-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK15-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK15-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK15-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK15-SAME: () #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK15-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK15-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK15-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK15-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK15-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK15-SAME: () #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK15-NEXT: ret i32 [[CALL]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK15-SAME: () #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK16-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK16-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK16-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK16-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK16-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK16-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK16-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK16-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK16-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK16-SAME: () #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK16-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK16-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK16-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK16-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK16-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK16-SAME: () #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK16-NEXT: ret i32 [[CALL]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK16-SAME: () #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret i32 0 -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 -// CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 -// CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 -// CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] -// CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] -// CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 -// CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] -// CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] -// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] -// CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] -// CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 -// CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 -// CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 -// CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] -// CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] -// CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] -// CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 -// CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] -// CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] -// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] -// CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] -// CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 -// CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 -// CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 -// CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 -// CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] -// CHECK17-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK17-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] -// CHECK17-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK17-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] -// CHECK17-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] -// CHECK17-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 -// CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] -// CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 -// CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] -// CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] -// CHECK17-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I5:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 -// CHECK17-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK17-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] -// CHECK17-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 -// CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 -// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] -// CHECK17-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 -// CHECK17-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 -// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 -// CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 -// CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 -// CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] -// CHECK18-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK18-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] -// CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 -// CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] -// CHECK18-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] -// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] -// CHECK18-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK18-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] -// CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 -// CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 -// CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 -// CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] -// CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] -// CHECK18-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK18-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] -// CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 -// CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] -// CHECK18-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] -// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] -// CHECK18-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK18-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] -// CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 -// CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 -// CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 -// CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 -// CHECK18-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] -// CHECK18-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK18-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] -// CHECK18-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK18-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] -// CHECK18-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] -// CHECK18-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 -// CHECK18-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] -// CHECK18-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 -// CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] -// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] -// CHECK18-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I5:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 -// CHECK18-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK18-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] -// CHECK18-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 -// CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK18-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 -// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] -// CHECK18-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 -// CHECK18-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 -// CHECK18-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 -// CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 -// CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 -// CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] -// CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] -// CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] -// CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] -// CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] -// CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] -// CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 -// CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 -// CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 -// CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] -// CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] -// CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] -// CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] -// CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] -// CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] -// CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] -// CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 -// CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 -// CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 -// CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] -// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 -// CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] -// CHECK19-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] -// CHECK19-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK19-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] -// CHECK19-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] -// CHECK19-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] -// CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 -// CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] -// CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] -// CHECK19-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I5:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 -// CHECK19-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK19-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] -// CHECK19-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 -// CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 -// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK19-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK19-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] -// CHECK19-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 -// CHECK19-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK19-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 -// CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 -// CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 -// CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 -// CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] -// CHECK20-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] -// CHECK20-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] -// CHECK20-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] -// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] -// CHECK20-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] -// CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 -// CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 -// CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 -// CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] -// CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] -// CHECK20-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] -// CHECK20-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] -// CHECK20-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] -// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] -// CHECK20-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] -// CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 -// CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 -// CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 -// CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] -// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 -// CHECK20-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] -// CHECK20-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] -// CHECK20-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK20-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] -// CHECK20-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] -// CHECK20-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] -// CHECK20-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 -// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] -// CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] -// CHECK20-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I5:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 -// CHECK20-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK20-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] -// CHECK20-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 -// CHECK20-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 -// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK20-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK20-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK20-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] -// CHECK20-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 -// CHECK20-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK20-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 -// CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK21-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK21-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK21-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK21-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK21-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK21-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK21-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK21-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK21-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK21-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK21-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK21-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK21-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK21-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK21-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK21-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK21-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK21-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK21-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK21-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK21-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK21-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK21-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK21-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK21-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK21-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK21-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK21-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK21-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK21-SAME: () #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: ret i32 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK22-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK22-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK22-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK22-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK22-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK22-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK22-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK22-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK22-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK22-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK22-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK22-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK22-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK22-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK22-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK22-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK22-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK22-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK22-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK22-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK22-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK22-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK22-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK22-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK22-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK22-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK22-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK22-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK22-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK22-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK22-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK22-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK22-NEXT: ret i32 [[CALL]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK22-SAME: () #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: ret i32 0 -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK23-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK23-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK23-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK23-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK23-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK23-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK23-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK23-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK23-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK23-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK23-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK23-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK23-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK23-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK23-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK23-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK23-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK23-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK23-SAME: () #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK23-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK23-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK23-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK23-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK23-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK23-SAME: () #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK23-NEXT: ret i32 [[CALL]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK23-SAME: () #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: ret i32 0 -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK24-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK24-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK24-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK24-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK24-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK24-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK24-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK24-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK24-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK24-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK24-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK24-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK24-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK24-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK24-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK24-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK24-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK24-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK24-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK24-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK24-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK24-SAME: () #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK24-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK24-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK24-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK24-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK24-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK24-SAME: () #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK24-NEXT: ret i32 [[CALL]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK24-SAME: () #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: ret i32 0 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK12-NEXT: ret void // diff --git a/clang/test/OpenMP/distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_firstprivate_codegen.cpp --- a/clang/test/OpenMP/distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_firstprivate_codegen.cpp @@ -6,26 +6,26 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -832,16 +832,662 @@ // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK5-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done3: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP39]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done6: +// CHECK5-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK5-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] +// CHECK5-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done15: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP32]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done6: +// CHECK5-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* +// CHECK5-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK5-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done14: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -850,16 +1496,662 @@ // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK6-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done3: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP39]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done6: +// CHECK6-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK6-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] +// CHECK6-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done15: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK6-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP32]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done6: +// CHECK6-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* +// CHECK6-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK6-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done14: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main @@ -868,16 +2160,652 @@ // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK7-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP39]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done6: +// CHECK7-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK7-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP26]] +// CHECK7-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP28]] +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK7-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done14: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP32]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done6: +// CHECK7-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK7-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK7-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP24]] +// CHECK7-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP26]] +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done13: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main @@ -886,3766 +2814,650 @@ // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP39]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done6: -// CHECK9-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK9-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] -// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done15: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP32]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done6: -// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* -// CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) -// CHECK9-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done14: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK10-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP39]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done6: -// CHECK10-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK10-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] -// CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done15: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP32]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done6: -// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* -// CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) -// CHECK10-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done14: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP39]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done6: -// CHECK11-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) -// CHECK11-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP26]] -// CHECK11-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP28]] -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done14: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP32]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done6: -// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) -// CHECK11-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP24]] -// CHECK11-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP26]] -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done13: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK12-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP39]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done6: -// CHECK12-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) -// CHECK12-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] -// CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP26]] -// CHECK12-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP28]] -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK12-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done14: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK12-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP32]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done6: -// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* -// CHECK12-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) -// CHECK12-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP24]] -// CHECK12-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP26]] -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done13: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK8-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP39]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done6: +// CHECK8-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK8-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] +// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP26]] +// CHECK8-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP28]] +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK8-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done14: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK8-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP32]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done6: +// CHECK8-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK8-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP24]] +// CHECK8-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP26]] +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done13: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_lastprivate_codegen.cpp --- a/clang/test/OpenMP/distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_lastprivate_codegen.cpp @@ -6,26 +6,26 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -810,16 +810,699 @@ // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK5-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done3: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP39]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK5-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: store i32 [[TMP26]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP30]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done14: +// CHECK5-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP6]] to i8* +// CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) +// CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK5-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done16: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP32]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK5-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP29]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done13: +// CHECK5-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* +// CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done15: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -828,16 +1511,699 @@ // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK6-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done3: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP39]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK6-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: store i32 [[TMP26]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP30]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done14: +// CHECK6-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP6]] to i8* +// CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) +// CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK6-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done16: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK6-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP32]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK6-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP29]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done13: +// CHECK6-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* +// CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done15: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main @@ -846,16 +2212,689 @@ // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK7-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP39]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK7-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP16]] +// CHECK7-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP18]] +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK7-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: store i32 [[TMP26]], i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done13: +// CHECK7-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP6]] to i8* +// CHECK7-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) +// CHECK7-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK7-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done15: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP32]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK7-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK7-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP29]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done12: +// CHECK7-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* +// CHECK7-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done14: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main @@ -864,3918 +2903,687 @@ // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP39]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK9-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: store i32 [[TMP26]], i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP30]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done14: -// CHECK9-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK9-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) -// CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK9-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done16: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP32]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP29]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done13: -// CHECK9-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* -// CHECK9-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done15: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK10-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP39]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK10-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP26]], i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP30]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done14: -// CHECK10-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK10-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) -// CHECK10-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK10-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done16: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP32]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK10-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP29]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done13: -// CHECK10-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* -// CHECK10-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done15: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP39]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK11-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP16]] -// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP18]] -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK11-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: store i32 [[TMP26]], i32* [[TMP0]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done13: -// CHECK11-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK11-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) -// CHECK11-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK11-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done15: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP32]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK11-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP15]] -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP17]] -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK11-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP29]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done12: -// CHECK11-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* -// CHECK11-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done14: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK12-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP39]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK12-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP16]] -// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP18]] -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK12-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK12-NEXT: store i32 [[TMP26]], i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done13: -// CHECK12-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK12-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) -// CHECK12-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK12-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done15: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK12-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP32]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK12-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP15]] -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP17]] -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK12-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK12-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP29]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done12: -// CHECK12-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* -// CHECK12-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done14: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done6: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done6: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done5: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done5: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK8-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP39]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK8-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP16]] +// CHECK8-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP18]] +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK8-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK8-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: store i32 [[TMP26]], i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done13: +// CHECK8-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP6]] to i8* +// CHECK8-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) +// CHECK8-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK8-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done15: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK8-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP32]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK8-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP15]] +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP17]] +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK8-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP29]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done12: +// CHECK8-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* +// CHECK8-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done14: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_codegen.cpp @@ -7,26 +7,26 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -7816,24 +7816,4428 @@ // CHECK5-NEXT: [[C:%.*]] = alloca double*, align 8 // CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[CH_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED32:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[CH_CASTED46:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED48:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS50:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS51:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS52:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED62:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS64:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS65:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS66:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP67:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_68:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_69:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[CH_CASTED76:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED78:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS80:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS81:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS82:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP83:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_84:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_85:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store i32 10000, i32* [[N]], align 4 // CHECK5-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[N]], i32** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: store double** [[A]], double*** [[TMP1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK5-NEXT: store double** [[B]], double*** [[TMP2]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK5-NEXT: store double** [[C]], double*** [[TMP3]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 -// CHECK5-NEXT: store i32* [[CH]], i32** [[TMP4]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(40) [[REF_TMP]]) +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[A]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double*, double** [[B]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load double*, double** [[C]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to double** +// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double** +// CHECK5-NEXT: store double* [[TMP3]], double** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to double** +// CHECK5-NEXT: store double* [[TMP3]], double** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double** +// CHECK5-NEXT: store double* [[TMP4]], double** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double** +// CHECK5-NEXT: store double* [[TMP4]], double** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369(i64 [[TMP1]], double* [[TMP2]], double* [[TMP3]], double* [[TMP4]]) #[[ATTR2:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK5-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = load double*, double** [[A]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = load double*, double** [[B]], align 8 +// CHECK5-NEXT: [[TMP37:%.*]] = load double*, double** [[C]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP41]], align 8 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP42]], align 8 +// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to double** +// CHECK5-NEXT: store double* [[TMP35]], double** [[TMP44]], align 8 +// CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to double** +// CHECK5-NEXT: store double* [[TMP35]], double** [[TMP46]], align 8 +// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** +// CHECK5-NEXT: store double* [[TMP36]], double** [[TMP49]], align 8 +// CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** +// CHECK5-NEXT: store double* [[TMP36]], double** [[TMP51]], align 8 +// CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP52]], align 8 +// CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** +// CHECK5-NEXT: store double* [[TMP37]], double** [[TMP54]], align 8 +// CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to double** +// CHECK5-NEXT: store double* [[TMP37]], double** [[TMP56]], align 8 +// CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP57]], align 8 +// CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK5-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK5-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP61]], 0 +// CHECK5-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK5-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK5-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP62]], 1 +// CHECK5-NEXT: [[TMP63:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) +// CHECK5-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 +// CHECK5-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK5: omp_offload.failed15: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408(i64 [[TMP34]], double* [[TMP35]], double* [[TMP36]], double* [[TMP37]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK5: omp_offload.cont16: +// CHECK5-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK5-NEXT: [[CONV17:%.*]] = bitcast i64* [[CH_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP66]], i32* [[CONV17]], align 4 +// CHECK5-NEXT: [[TMP67:%.*]] = load i64, i64* [[CH_CASTED]], align 8 +// CHECK5-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* +// CHECK5-NEXT: store i32 [[TMP68]], i32* [[CONV19]], align 4 +// CHECK5-NEXT: [[TMP69:%.*]] = load i64, i64* [[N_CASTED18]], align 8 +// CHECK5-NEXT: [[TMP70:%.*]] = load double*, double** [[A]], align 8 +// CHECK5-NEXT: [[TMP71:%.*]] = load double*, double** [[B]], align 8 +// CHECK5-NEXT: [[TMP72:%.*]] = load double*, double** [[C]], align 8 +// CHECK5-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* +// CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP74]], align 8 +// CHECK5-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP76]], align 8 +// CHECK5-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP77]], align 8 +// CHECK5-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* +// CHECK5-NEXT: store i64 [[TMP69]], i64* [[TMP79]], align 8 +// CHECK5-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK5-NEXT: store i64 [[TMP69]], i64* [[TMP81]], align 8 +// CHECK5-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP82]], align 8 +// CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to double** +// CHECK5-NEXT: store double* [[TMP70]], double** [[TMP84]], align 8 +// CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to double** +// CHECK5-NEXT: store double* [[TMP70]], double** [[TMP86]], align 8 +// CHECK5-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP87]], align 8 +// CHECK5-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** +// CHECK5-NEXT: store double* [[TMP71]], double** [[TMP89]], align 8 +// CHECK5-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to double** +// CHECK5-NEXT: store double* [[TMP71]], double** [[TMP91]], align 8 +// CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP92]], align 8 +// CHECK5-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** +// CHECK5-NEXT: store double* [[TMP72]], double** [[TMP94]], align 8 +// CHECK5-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to double** +// CHECK5-NEXT: store double* [[TMP72]], double** [[TMP96]], align 8 +// CHECK5-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP97]], align 8 +// CHECK5-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK5-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK5-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP101]], 0 +// CHECK5-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// CHECK5-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 +// CHECK5-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK5-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK5-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP102]], 1 +// CHECK5-NEXT: [[TMP103:%.*]] = zext i32 [[ADD29]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) +// CHECK5-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 +// CHECK5-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK5: omp_offload.failed30: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447(i64 [[TMP67]], i64 [[TMP69]], double* [[TMP70]], double* [[TMP71]], double* [[TMP72]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK5: omp_offload.cont31: +// CHECK5-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV33:%.*]] = bitcast i64* [[N_CASTED32]] to i32* +// CHECK5-NEXT: store i32 [[TMP106]], i32* [[CONV33]], align 4 +// CHECK5-NEXT: [[TMP107:%.*]] = load i64, i64* [[N_CASTED32]], align 8 +// CHECK5-NEXT: [[TMP108:%.*]] = load double*, double** [[A]], align 8 +// CHECK5-NEXT: [[TMP109:%.*]] = load double*, double** [[B]], align 8 +// CHECK5-NEXT: [[TMP110:%.*]] = load double*, double** [[C]], align 8 +// CHECK5-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* +// CHECK5-NEXT: store i64 [[TMP107]], i64* [[TMP112]], align 8 +// CHECK5-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* +// CHECK5-NEXT: store i64 [[TMP107]], i64* [[TMP114]], align 8 +// CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP115]], align 8 +// CHECK5-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to double** +// CHECK5-NEXT: store double* [[TMP108]], double** [[TMP117]], align 8 +// CHECK5-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to double** +// CHECK5-NEXT: store double* [[TMP108]], double** [[TMP119]], align 8 +// CHECK5-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP120]], align 8 +// CHECK5-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to double** +// CHECK5-NEXT: store double* [[TMP109]], double** [[TMP122]], align 8 +// CHECK5-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** +// CHECK5-NEXT: store double* [[TMP109]], double** [[TMP124]], align 8 +// CHECK5-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP125]], align 8 +// CHECK5-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** +// CHECK5-NEXT: store double* [[TMP110]], double** [[TMP127]], align 8 +// CHECK5-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** +// CHECK5-NEXT: store double* [[TMP110]], double** [[TMP129]], align 8 +// CHECK5-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP130]], align 8 +// CHECK5-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK5-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK5-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP134]], 0 +// CHECK5-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 +// CHECK5-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 +// CHECK5-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK5-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK5-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP135]], 1 +// CHECK5-NEXT: [[TMP136:%.*]] = zext i32 [[ADD43]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) +// CHECK5-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 +// CHECK5-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] +// CHECK5: omp_offload.failed44: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478(i64 [[TMP107]], double* [[TMP108]], double* [[TMP109]], double* [[TMP110]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT45]] +// CHECK5: omp_offload.cont45: +// CHECK5-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK5-NEXT: [[CONV47:%.*]] = bitcast i64* [[CH_CASTED46]] to i32* +// CHECK5-NEXT: store i32 [[TMP139]], i32* [[CONV47]], align 4 +// CHECK5-NEXT: [[TMP140:%.*]] = load i64, i64* [[CH_CASTED46]], align 8 +// CHECK5-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV49:%.*]] = bitcast i64* [[N_CASTED48]] to i32* +// CHECK5-NEXT: store i32 [[TMP141]], i32* [[CONV49]], align 4 +// CHECK5-NEXT: [[TMP142:%.*]] = load i64, i64* [[N_CASTED48]], align 8 +// CHECK5-NEXT: [[TMP143:%.*]] = load double*, double** [[A]], align 8 +// CHECK5-NEXT: [[TMP144:%.*]] = load double*, double** [[B]], align 8 +// CHECK5-NEXT: [[TMP145:%.*]] = load double*, double** [[C]], align 8 +// CHECK5-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* +// CHECK5-NEXT: store i64 [[TMP140]], i64* [[TMP147]], align 8 +// CHECK5-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* +// CHECK5-NEXT: store i64 [[TMP140]], i64* [[TMP149]], align 8 +// CHECK5-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP150]], align 8 +// CHECK5-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i64* +// CHECK5-NEXT: store i64 [[TMP142]], i64* [[TMP152]], align 8 +// CHECK5-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i64* +// CHECK5-NEXT: store i64 [[TMP142]], i64* [[TMP154]], align 8 +// CHECK5-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP155]], align 8 +// CHECK5-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to double** +// CHECK5-NEXT: store double* [[TMP143]], double** [[TMP157]], align 8 +// CHECK5-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to double** +// CHECK5-NEXT: store double* [[TMP143]], double** [[TMP159]], align 8 +// CHECK5-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP160]], align 8 +// CHECK5-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to double** +// CHECK5-NEXT: store double* [[TMP144]], double** [[TMP162]], align 8 +// CHECK5-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to double** +// CHECK5-NEXT: store double* [[TMP144]], double** [[TMP164]], align 8 +// CHECK5-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP165]], align 8 +// CHECK5-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to double** +// CHECK5-NEXT: store double* [[TMP145]], double** [[TMP167]], align 8 +// CHECK5-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to double** +// CHECK5-NEXT: store double* [[TMP145]], double** [[TMP169]], align 8 +// CHECK5-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP170]], align 8 +// CHECK5-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK5-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK5-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP174]], 0 +// CHECK5-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 +// CHECK5-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 +// CHECK5-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK5-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK5-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP175]], 1 +// CHECK5-NEXT: [[TMP176:%.*]] = zext i32 [[ADD59]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) +// CHECK5-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 +// CHECK5-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] +// CHECK5: omp_offload.failed60: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506(i64 [[TMP140]], i64 [[TMP142]], double* [[TMP143]], double* [[TMP144]], double* [[TMP145]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT61]] +// CHECK5: omp_offload.cont61: +// CHECK5-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV63:%.*]] = bitcast i64* [[N_CASTED62]] to i32* +// CHECK5-NEXT: store i32 [[TMP179]], i32* [[CONV63]], align 4 +// CHECK5-NEXT: [[TMP180:%.*]] = load i64, i64* [[N_CASTED62]], align 8 +// CHECK5-NEXT: [[TMP181:%.*]] = load double*, double** [[A]], align 8 +// CHECK5-NEXT: [[TMP182:%.*]] = load double*, double** [[B]], align 8 +// CHECK5-NEXT: [[TMP183:%.*]] = load double*, double** [[C]], align 8 +// CHECK5-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i64* +// CHECK5-NEXT: store i64 [[TMP180]], i64* [[TMP185]], align 8 +// CHECK5-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i64* +// CHECK5-NEXT: store i64 [[TMP180]], i64* [[TMP187]], align 8 +// CHECK5-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP188]], align 8 +// CHECK5-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to double** +// CHECK5-NEXT: store double* [[TMP181]], double** [[TMP190]], align 8 +// CHECK5-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to double** +// CHECK5-NEXT: store double* [[TMP181]], double** [[TMP192]], align 8 +// CHECK5-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP193]], align 8 +// CHECK5-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to double** +// CHECK5-NEXT: store double* [[TMP182]], double** [[TMP195]], align 8 +// CHECK5-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to double** +// CHECK5-NEXT: store double* [[TMP182]], double** [[TMP197]], align 8 +// CHECK5-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP198]], align 8 +// CHECK5-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to double** +// CHECK5-NEXT: store double* [[TMP183]], double** [[TMP200]], align 8 +// CHECK5-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to double** +// CHECK5-NEXT: store double* [[TMP183]], double** [[TMP202]], align 8 +// CHECK5-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP203]], align 8 +// CHECK5-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_68]], align 4 +// CHECK5-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_68]], align 4 +// CHECK5-NEXT: [[SUB70:%.*]] = sub nsw i32 [[TMP207]], 0 +// CHECK5-NEXT: [[DIV71:%.*]] = sdiv i32 [[SUB70]], 1 +// CHECK5-NEXT: [[SUB72:%.*]] = sub nsw i32 [[DIV71]], 1 +// CHECK5-NEXT: store i32 [[SUB72]], i32* [[DOTCAPTURE_EXPR_69]], align 4 +// CHECK5-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_69]], align 4 +// CHECK5-NEXT: [[ADD73:%.*]] = add nsw i32 [[TMP208]], 1 +// CHECK5-NEXT: [[TMP209:%.*]] = zext i32 [[ADD73]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) +// CHECK5-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 +// CHECK5-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED74:%.*]], label [[OMP_OFFLOAD_CONT75:%.*]] +// CHECK5: omp_offload.failed74: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536(i64 [[TMP180]], double* [[TMP181]], double* [[TMP182]], double* [[TMP183]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT75]] +// CHECK5: omp_offload.cont75: +// CHECK5-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK5-NEXT: [[CONV77:%.*]] = bitcast i64* [[CH_CASTED76]] to i32* +// CHECK5-NEXT: store i32 [[TMP212]], i32* [[CONV77]], align 4 +// CHECK5-NEXT: [[TMP213:%.*]] = load i64, i64* [[CH_CASTED76]], align 8 +// CHECK5-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV79:%.*]] = bitcast i64* [[N_CASTED78]] to i32* +// CHECK5-NEXT: store i32 [[TMP214]], i32* [[CONV79]], align 4 +// CHECK5-NEXT: [[TMP215:%.*]] = load i64, i64* [[N_CASTED78]], align 8 +// CHECK5-NEXT: [[TMP216:%.*]] = load double*, double** [[A]], align 8 +// CHECK5-NEXT: [[TMP217:%.*]] = load double*, double** [[B]], align 8 +// CHECK5-NEXT: [[TMP218:%.*]] = load double*, double** [[C]], align 8 +// CHECK5-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i64* +// CHECK5-NEXT: store i64 [[TMP213]], i64* [[TMP220]], align 8 +// CHECK5-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i64* +// CHECK5-NEXT: store i64 [[TMP213]], i64* [[TMP222]], align 8 +// CHECK5-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP223]], align 8 +// CHECK5-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i64* +// CHECK5-NEXT: store i64 [[TMP215]], i64* [[TMP225]], align 8 +// CHECK5-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i64* +// CHECK5-NEXT: store i64 [[TMP215]], i64* [[TMP227]], align 8 +// CHECK5-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP228]], align 8 +// CHECK5-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to double** +// CHECK5-NEXT: store double* [[TMP216]], double** [[TMP230]], align 8 +// CHECK5-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to double** +// CHECK5-NEXT: store double* [[TMP216]], double** [[TMP232]], align 8 +// CHECK5-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP233]], align 8 +// CHECK5-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to double** +// CHECK5-NEXT: store double* [[TMP217]], double** [[TMP235]], align 8 +// CHECK5-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to double** +// CHECK5-NEXT: store double* [[TMP217]], double** [[TMP237]], align 8 +// CHECK5-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP238]], align 8 +// CHECK5-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to double** +// CHECK5-NEXT: store double* [[TMP218]], double** [[TMP240]], align 8 +// CHECK5-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to double** +// CHECK5-NEXT: store double* [[TMP218]], double** [[TMP242]], align 8 +// CHECK5-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP243]], align 8 +// CHECK5-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_84]], align 4 +// CHECK5-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_84]], align 4 +// CHECK5-NEXT: [[SUB86:%.*]] = sub nsw i32 [[TMP247]], 0 +// CHECK5-NEXT: [[DIV87:%.*]] = sdiv i32 [[SUB86]], 1 +// CHECK5-NEXT: [[SUB88:%.*]] = sub nsw i32 [[DIV87]], 1 +// CHECK5-NEXT: store i32 [[SUB88]], i32* [[DOTCAPTURE_EXPR_85]], align 4 +// CHECK5-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_85]], align 4 +// CHECK5-NEXT: [[ADD89:%.*]] = add nsw i32 [[TMP248]], 1 +// CHECK5-NEXT: [[TMP249:%.*]] = zext i32 [[ADD89]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) +// CHECK5-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.24, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 +// CHECK5-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED90:%.*]], label [[OMP_OFFLOAD_CONT91:%.*]] +// CHECK5: omp_offload.failed90: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i64 [[TMP213]], i64 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT91]] +// CHECK5: omp_offload.cont91: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: ret i32 [[CALL]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 +// CHECK5-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] +// CHECK5-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 +// CHECK5-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK5-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] +// CHECK5-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 +// CHECK5-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] +// CHECK5-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 +// CHECK5-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK5-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] +// CHECK5-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 +// CHECK5-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK5: cond.true10: +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END12:%.*]] +// CHECK5: cond.false11: +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END12]] +// CHECK5: cond.end12: +// CHECK5-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE10]] ], [ [[TMP32]], [[COND_FALSE11]] ] +// CHECK5-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] +// CHECK5-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 +// CHECK5-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK5-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] +// CHECK5-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 +// CHECK5-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] +// CHECK5-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 +// CHECK5-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK5-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] +// CHECK5-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 +// CHECK5-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i64 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[CONV7]], [[TMP14]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CONV9:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[CONV9]], [[COND_FALSE]] ] +// CHECK5-NEXT: [[CONV10:%.*]] = trunc i64 [[COND]] to i32 +// CHECK5-NEXT: store i32 [[CONV10]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK5-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM13]] +// CHECK5-NEXT: [[TMP28:%.*]] = load double, double* [[ARRAYIDX14]], align 8 +// CHECK5-NEXT: [[ADD15:%.*]] = fadd double [[TMP25]], [[TMP28]] +// CHECK5-NEXT: [[TMP29:%.*]] = load double*, double** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK5-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP30]] to i64 +// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP29]], i64 [[IDXPROM16]] +// CHECK5-NEXT: store double [[ADD15]], double* [[ARRAYIDX17]], align 8 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK5-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] +// CHECK5-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] +// CHECK5-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 +// CHECK5-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..19 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP21:%.*]] = load double*, double** [[TMP2]], align 8, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP21]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX]], align 8, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP24:%.*]] = load double*, double** [[TMP3]], align 8, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP24]], i64 [[IDXPROM6]] +// CHECK5-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX7]], align 8, !llvm.access.group !18 +// CHECK5-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]] +// CHECK5-NEXT: [[TMP27:%.*]] = load double*, double** [[TMP1]], align 8, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP27]], i64 [[IDXPROM9]] +// CHECK5-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !18 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 +// CHECK5-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**, i64)* @.omp_outlined..23 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i64 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..23 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP22:%.*]] = load double*, double** [[TMP2]], align 8, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP22]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX]], align 8, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP25:%.*]] = load double*, double** [[TMP3]], align 8, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds double, double* [[TMP25]], i64 [[IDXPROM8]] +// CHECK5-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX9]], align 8, !llvm.access.group !21 +// CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]] +// CHECK5-NEXT: [[TMP28:%.*]] = load double*, double** [[TMP1]], align 8, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP28]], i64 [[IDXPROM11]] +// CHECK5-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !21 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[B:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[C:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[CH:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[CH_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED32:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[CH_CASTED46:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED48:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS50:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS51:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS52:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED62:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS64:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS65:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS66:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP67:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_68:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_69:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[CH_CASTED76:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED78:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS80:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS81:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS82:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP83:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_84:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_85:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 10000, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 100, i32* [[CH]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32** +// CHECK5-NEXT: store i32* [[TMP2]], i32** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32** +// CHECK5-NEXT: store i32* [[TMP2]], i32** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32** +// CHECK5-NEXT: store i32* [[TMP3]], i32** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32** +// CHECK5-NEXT: store i32* [[TMP3]], i32** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK5-NEXT: store i32* [[TMP4]], i32** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32** +// CHECK5-NEXT: store i32* [[TMP4]], i32** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP30]]) +// CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42(i64 [[TMP1]], i32* [[TMP2]], i32* [[TMP3]], i32* [[TMP4]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK5-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK5-NEXT: [[TMP37:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP41]], align 8 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP42]], align 8 +// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32** +// CHECK5-NEXT: store i32* [[TMP35]], i32** [[TMP44]], align 8 +// CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32** +// CHECK5-NEXT: store i32* [[TMP35]], i32** [[TMP46]], align 8 +// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK5-NEXT: store i32* [[TMP36]], i32** [[TMP49]], align 8 +// CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK5-NEXT: store i32* [[TMP36]], i32** [[TMP51]], align 8 +// CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP52]], align 8 +// CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32** +// CHECK5-NEXT: store i32* [[TMP37]], i32** [[TMP54]], align 8 +// CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32** +// CHECK5-NEXT: store i32* [[TMP37]], i32** [[TMP56]], align 8 +// CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP57]], align 8 +// CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK5-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK5-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP61]], 0 +// CHECK5-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK5-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK5-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP62]], 1 +// CHECK5-NEXT: [[TMP63:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) +// CHECK5-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.32, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.33, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 +// CHECK5-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK5: omp_offload.failed15: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51(i64 [[TMP34]], i32* [[TMP35]], i32* [[TMP36]], i32* [[TMP37]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK5: omp_offload.cont16: +// CHECK5-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK5-NEXT: [[CONV17:%.*]] = bitcast i64* [[CH_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP66]], i32* [[CONV17]], align 4 +// CHECK5-NEXT: [[TMP67:%.*]] = load i64, i64* [[CH_CASTED]], align 8 +// CHECK5-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* +// CHECK5-NEXT: store i32 [[TMP68]], i32* [[CONV19]], align 4 +// CHECK5-NEXT: [[TMP69:%.*]] = load i64, i64* [[N_CASTED18]], align 8 +// CHECK5-NEXT: [[TMP70:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK5-NEXT: [[TMP71:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK5-NEXT: [[TMP72:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK5-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* +// CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP74]], align 8 +// CHECK5-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP76]], align 8 +// CHECK5-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP77]], align 8 +// CHECK5-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* +// CHECK5-NEXT: store i64 [[TMP69]], i64* [[TMP79]], align 8 +// CHECK5-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK5-NEXT: store i64 [[TMP69]], i64* [[TMP81]], align 8 +// CHECK5-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP82]], align 8 +// CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK5-NEXT: store i32* [[TMP70]], i32** [[TMP84]], align 8 +// CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** +// CHECK5-NEXT: store i32* [[TMP70]], i32** [[TMP86]], align 8 +// CHECK5-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP87]], align 8 +// CHECK5-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK5-NEXT: store i32* [[TMP71]], i32** [[TMP89]], align 8 +// CHECK5-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** +// CHECK5-NEXT: store i32* [[TMP71]], i32** [[TMP91]], align 8 +// CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP92]], align 8 +// CHECK5-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to i32** +// CHECK5-NEXT: store i32* [[TMP72]], i32** [[TMP94]], align 8 +// CHECK5-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32** +// CHECK5-NEXT: store i32* [[TMP72]], i32** [[TMP96]], align 8 +// CHECK5-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP97]], align 8 +// CHECK5-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK5-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK5-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP101]], 0 +// CHECK5-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// CHECK5-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 +// CHECK5-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK5-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK5-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP102]], 1 +// CHECK5-NEXT: [[TMP103:%.*]] = zext i32 [[ADD29]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) +// CHECK5-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.36, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.37, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 +// CHECK5-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK5: omp_offload.failed30: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59(i64 [[TMP67]], i64 [[TMP69]], i32* [[TMP70]], i32* [[TMP71]], i32* [[TMP72]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK5: omp_offload.cont31: +// CHECK5-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV33:%.*]] = bitcast i64* [[N_CASTED32]] to i32* +// CHECK5-NEXT: store i32 [[TMP106]], i32* [[CONV33]], align 4 +// CHECK5-NEXT: [[TMP107:%.*]] = load i64, i64* [[N_CASTED32]], align 8 +// CHECK5-NEXT: [[TMP108:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK5-NEXT: [[TMP109:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK5-NEXT: [[TMP110:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK5-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* +// CHECK5-NEXT: store i64 [[TMP107]], i64* [[TMP112]], align 8 +// CHECK5-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* +// CHECK5-NEXT: store i64 [[TMP107]], i64* [[TMP114]], align 8 +// CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP115]], align 8 +// CHECK5-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** +// CHECK5-NEXT: store i32* [[TMP108]], i32** [[TMP117]], align 8 +// CHECK5-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** +// CHECK5-NEXT: store i32* [[TMP108]], i32** [[TMP119]], align 8 +// CHECK5-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP120]], align 8 +// CHECK5-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** +// CHECK5-NEXT: store i32* [[TMP109]], i32** [[TMP122]], align 8 +// CHECK5-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32** +// CHECK5-NEXT: store i32* [[TMP109]], i32** [[TMP124]], align 8 +// CHECK5-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP125]], align 8 +// CHECK5-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32** +// CHECK5-NEXT: store i32* [[TMP110]], i32** [[TMP127]], align 8 +// CHECK5-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32** +// CHECK5-NEXT: store i32* [[TMP110]], i32** [[TMP129]], align 8 +// CHECK5-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP130]], align 8 +// CHECK5-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK5-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK5-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP134]], 0 +// CHECK5-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 +// CHECK5-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 +// CHECK5-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK5-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK5-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP135]], 1 +// CHECK5-NEXT: [[TMP136:%.*]] = zext i32 [[ADD43]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) +// CHECK5-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.40, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.41, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 +// CHECK5-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] +// CHECK5: omp_offload.failed44: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67(i64 [[TMP107]], i32* [[TMP108]], i32* [[TMP109]], i32* [[TMP110]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT45]] +// CHECK5: omp_offload.cont45: +// CHECK5-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK5-NEXT: [[CONV47:%.*]] = bitcast i64* [[CH_CASTED46]] to i32* +// CHECK5-NEXT: store i32 [[TMP139]], i32* [[CONV47]], align 4 +// CHECK5-NEXT: [[TMP140:%.*]] = load i64, i64* [[CH_CASTED46]], align 8 +// CHECK5-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV49:%.*]] = bitcast i64* [[N_CASTED48]] to i32* +// CHECK5-NEXT: store i32 [[TMP141]], i32* [[CONV49]], align 4 +// CHECK5-NEXT: [[TMP142:%.*]] = load i64, i64* [[N_CASTED48]], align 8 +// CHECK5-NEXT: [[TMP143:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK5-NEXT: [[TMP144:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK5-NEXT: [[TMP145:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK5-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* +// CHECK5-NEXT: store i64 [[TMP140]], i64* [[TMP147]], align 8 +// CHECK5-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* +// CHECK5-NEXT: store i64 [[TMP140]], i64* [[TMP149]], align 8 +// CHECK5-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP150]], align 8 +// CHECK5-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i64* +// CHECK5-NEXT: store i64 [[TMP142]], i64* [[TMP152]], align 8 +// CHECK5-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i64* +// CHECK5-NEXT: store i64 [[TMP142]], i64* [[TMP154]], align 8 +// CHECK5-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP155]], align 8 +// CHECK5-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** +// CHECK5-NEXT: store i32* [[TMP143]], i32** [[TMP157]], align 8 +// CHECK5-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** +// CHECK5-NEXT: store i32* [[TMP143]], i32** [[TMP159]], align 8 +// CHECK5-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP160]], align 8 +// CHECK5-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32** +// CHECK5-NEXT: store i32* [[TMP144]], i32** [[TMP162]], align 8 +// CHECK5-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32** +// CHECK5-NEXT: store i32* [[TMP144]], i32** [[TMP164]], align 8 +// CHECK5-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP165]], align 8 +// CHECK5-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to i32** +// CHECK5-NEXT: store i32* [[TMP145]], i32** [[TMP167]], align 8 +// CHECK5-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to i32** +// CHECK5-NEXT: store i32* [[TMP145]], i32** [[TMP169]], align 8 +// CHECK5-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP170]], align 8 +// CHECK5-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK5-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK5-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP174]], 0 +// CHECK5-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 +// CHECK5-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 +// CHECK5-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK5-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK5-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP175]], 1 +// CHECK5-NEXT: [[TMP176:%.*]] = zext i32 [[ADD59]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) +// CHECK5-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.44, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.45, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 +// CHECK5-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] +// CHECK5: omp_offload.failed60: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i64 [[TMP140]], i64 [[TMP142]], i32* [[TMP143]], i32* [[TMP144]], i32* [[TMP145]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT61]] +// CHECK5: omp_offload.cont61: +// CHECK5-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV63:%.*]] = bitcast i64* [[N_CASTED62]] to i32* +// CHECK5-NEXT: store i32 [[TMP179]], i32* [[CONV63]], align 4 +// CHECK5-NEXT: [[TMP180:%.*]] = load i64, i64* [[N_CASTED62]], align 8 +// CHECK5-NEXT: [[TMP181:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK5-NEXT: [[TMP182:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK5-NEXT: [[TMP183:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK5-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i64* +// CHECK5-NEXT: store i64 [[TMP180]], i64* [[TMP185]], align 8 +// CHECK5-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i64* +// CHECK5-NEXT: store i64 [[TMP180]], i64* [[TMP187]], align 8 +// CHECK5-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP188]], align 8 +// CHECK5-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to i32** +// CHECK5-NEXT: store i32* [[TMP181]], i32** [[TMP190]], align 8 +// CHECK5-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to i32** +// CHECK5-NEXT: store i32* [[TMP181]], i32** [[TMP192]], align 8 +// CHECK5-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP193]], align 8 +// CHECK5-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to i32** +// CHECK5-NEXT: store i32* [[TMP182]], i32** [[TMP195]], align 8 +// CHECK5-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to i32** +// CHECK5-NEXT: store i32* [[TMP182]], i32** [[TMP197]], align 8 +// CHECK5-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP198]], align 8 +// CHECK5-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to i32** +// CHECK5-NEXT: store i32* [[TMP183]], i32** [[TMP200]], align 8 +// CHECK5-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to i32** +// CHECK5-NEXT: store i32* [[TMP183]], i32** [[TMP202]], align 8 +// CHECK5-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP203]], align 8 +// CHECK5-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_68]], align 4 +// CHECK5-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_68]], align 4 +// CHECK5-NEXT: [[SUB70:%.*]] = sub nsw i32 [[TMP207]], 0 +// CHECK5-NEXT: [[DIV71:%.*]] = sdiv i32 [[SUB70]], 1 +// CHECK5-NEXT: [[SUB72:%.*]] = sub nsw i32 [[DIV71]], 1 +// CHECK5-NEXT: store i32 [[SUB72]], i32* [[DOTCAPTURE_EXPR_69]], align 4 +// CHECK5-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_69]], align 4 +// CHECK5-NEXT: [[ADD73:%.*]] = add nsw i32 [[TMP208]], 1 +// CHECK5-NEXT: [[TMP209:%.*]] = zext i32 [[ADD73]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) +// CHECK5-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.48, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.49, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 +// CHECK5-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED74:%.*]], label [[OMP_OFFLOAD_CONT75:%.*]] +// CHECK5: omp_offload.failed74: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83(i64 [[TMP180]], i32* [[TMP181]], i32* [[TMP182]], i32* [[TMP183]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT75]] +// CHECK5: omp_offload.cont75: +// CHECK5-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK5-NEXT: [[CONV77:%.*]] = bitcast i64* [[CH_CASTED76]] to i32* +// CHECK5-NEXT: store i32 [[TMP212]], i32* [[CONV77]], align 4 +// CHECK5-NEXT: [[TMP213:%.*]] = load i64, i64* [[CH_CASTED76]], align 8 +// CHECK5-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV79:%.*]] = bitcast i64* [[N_CASTED78]] to i32* +// CHECK5-NEXT: store i32 [[TMP214]], i32* [[CONV79]], align 4 +// CHECK5-NEXT: [[TMP215:%.*]] = load i64, i64* [[N_CASTED78]], align 8 +// CHECK5-NEXT: [[TMP216:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK5-NEXT: [[TMP217:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK5-NEXT: [[TMP218:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK5-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i64* +// CHECK5-NEXT: store i64 [[TMP213]], i64* [[TMP220]], align 8 +// CHECK5-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i64* +// CHECK5-NEXT: store i64 [[TMP213]], i64* [[TMP222]], align 8 +// CHECK5-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP223]], align 8 +// CHECK5-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i64* +// CHECK5-NEXT: store i64 [[TMP215]], i64* [[TMP225]], align 8 +// CHECK5-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i64* +// CHECK5-NEXT: store i64 [[TMP215]], i64* [[TMP227]], align 8 +// CHECK5-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP228]], align 8 +// CHECK5-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to i32** +// CHECK5-NEXT: store i32* [[TMP216]], i32** [[TMP230]], align 8 +// CHECK5-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to i32** +// CHECK5-NEXT: store i32* [[TMP216]], i32** [[TMP232]], align 8 +// CHECK5-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP233]], align 8 +// CHECK5-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to i32** +// CHECK5-NEXT: store i32* [[TMP217]], i32** [[TMP235]], align 8 +// CHECK5-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to i32** +// CHECK5-NEXT: store i32* [[TMP217]], i32** [[TMP237]], align 8 +// CHECK5-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP238]], align 8 +// CHECK5-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to i32** +// CHECK5-NEXT: store i32* [[TMP218]], i32** [[TMP240]], align 8 +// CHECK5-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to i32** +// CHECK5-NEXT: store i32* [[TMP218]], i32** [[TMP242]], align 8 +// CHECK5-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP243]], align 8 +// CHECK5-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_84]], align 4 +// CHECK5-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_84]], align 4 +// CHECK5-NEXT: [[SUB86:%.*]] = sub nsw i32 [[TMP247]], 0 +// CHECK5-NEXT: [[DIV87:%.*]] = sdiv i32 [[SUB86]], 1 +// CHECK5-NEXT: [[SUB88:%.*]] = sub nsw i32 [[DIV87]], 1 +// CHECK5-NEXT: store i32 [[SUB88]], i32* [[DOTCAPTURE_EXPR_85]], align 4 +// CHECK5-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_85]], align 4 +// CHECK5-NEXT: [[ADD89:%.*]] = add nsw i32 [[TMP248]], 1 +// CHECK5-NEXT: [[TMP249:%.*]] = zext i32 [[ADD89]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) +// CHECK5-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.52, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.53, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 +// CHECK5-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED90:%.*]], label [[OMP_OFFLOAD_CONT91:%.*]] +// CHECK5: omp_offload.failed90: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91(i64 [[TMP213]], i64 [[TMP215]], i32* [[TMP216]], i32* [[TMP217]], i32* [[TMP218]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT91]] +// CHECK5: omp_offload.cont91: // CHECK5-NEXT: ret i32 0 // // +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 +// CHECK5-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..27 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP21]], i32 2) +// CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK5-NEXT: br i1 [[TMP23]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK5: .cancel.exit: +// CHECK5-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK5: .cancel.continue: +// CHECK5-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM7]] +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] +// CHECK5-NEXT: [[TMP30:%.*]] = load i32*, i32** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP31]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i64 [[IDXPROM10]] +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: cancel.exit: +// CHECK5-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK5-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: br label [[CANCEL_CONT]] +// CHECK5: cancel.cont: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 +// CHECK5-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..31 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..31 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK5-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 +// CHECK5-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..34 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..34 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..35 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK5: cond.true10: +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END12:%.*]] +// CHECK5: cond.false11: +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END12]] +// CHECK5: cond.end12: +// CHECK5-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE10]] ], [ [[TMP32]], [[COND_FALSE11]] ] +// CHECK5-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..35 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK5-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 +// CHECK5-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..38 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..38 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..39 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..39 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK5-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 +// CHECK5-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..42 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..42 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**, i64)* @.omp_outlined..43 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i64 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..43 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[CONV7]], [[TMP14]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CONV9:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[CONV9]], [[COND_FALSE]] ] +// CHECK5-NEXT: [[CONV10:%.*]] = trunc i64 [[COND]] to i32 +// CHECK5-NEXT: store i32 [[CONV10]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK5-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM13]] +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX14]], align 4 +// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP25]], [[TMP28]] +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK5-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP30]] to i64 +// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i32, i32* [[TMP29]], i64 [[IDXPROM16]] +// CHECK5-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX17]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK5-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] +// CHECK5-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] +// CHECK5-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 +// CHECK5-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..46 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..46 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..47 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..47 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[TMP2]], align 8, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP3]], align 8, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM6]] +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP26]] +// CHECK5-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP1]], align 8, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM9]] +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX10]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 +// CHECK5-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..50 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..50 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**, i64)* @.omp_outlined..51 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i64 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..51 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[TMP2]], align 8, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP22]], i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[TMP3]], align 8, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[TMP25]], i64 [[IDXPROM8]] +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP27]] +// CHECK5-NEXT: [[TMP28:%.*]] = load i32*, i32** [[TMP1]], align 8, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[TMP28]], i64 [[IDXPROM11]] +// CHECK5-NEXT: store i32 [[ADD10]], i32* [[ARRAYIDX12]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@main // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: @@ -7843,24 +12247,4428 @@ // CHECK6-NEXT: [[C:%.*]] = alloca double*, align 8 // CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[CH_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED32:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[CH_CASTED46:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED48:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS50:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS51:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS52:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED62:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS64:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS65:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS66:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP67:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_68:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_69:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[CH_CASTED76:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED78:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS80:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS81:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS82:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP83:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_84:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_85:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store i32 10000, i32* [[N]], align 4 // CHECK6-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[N]], i32** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: store double** [[A]], double*** [[TMP1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK6-NEXT: store double** [[B]], double*** [[TMP2]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK6-NEXT: store double** [[C]], double*** [[TMP3]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 -// CHECK6-NEXT: store i32* [[CH]], i32** [[TMP4]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(40) [[REF_TMP]]) +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[A]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double*, double** [[B]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load double*, double** [[C]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to double** +// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double** +// CHECK6-NEXT: store double* [[TMP3]], double** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to double** +// CHECK6-NEXT: store double* [[TMP3]], double** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double** +// CHECK6-NEXT: store double* [[TMP4]], double** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double** +// CHECK6-NEXT: store double* [[TMP4]], double** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK6-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK6-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369(i64 [[TMP1]], double* [[TMP2]], double* [[TMP3]], double* [[TMP4]]) #[[ATTR2:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK6-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = load double*, double** [[A]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = load double*, double** [[B]], align 8 +// CHECK6-NEXT: [[TMP37:%.*]] = load double*, double** [[C]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP42]], align 8 +// CHECK6-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to double** +// CHECK6-NEXT: store double* [[TMP35]], double** [[TMP44]], align 8 +// CHECK6-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to double** +// CHECK6-NEXT: store double* [[TMP35]], double** [[TMP46]], align 8 +// CHECK6-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK6-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** +// CHECK6-NEXT: store double* [[TMP36]], double** [[TMP49]], align 8 +// CHECK6-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** +// CHECK6-NEXT: store double* [[TMP36]], double** [[TMP51]], align 8 +// CHECK6-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP52]], align 8 +// CHECK6-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** +// CHECK6-NEXT: store double* [[TMP37]], double** [[TMP54]], align 8 +// CHECK6-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to double** +// CHECK6-NEXT: store double* [[TMP37]], double** [[TMP56]], align 8 +// CHECK6-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP57]], align 8 +// CHECK6-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK6-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK6-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP61]], 0 +// CHECK6-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK6-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK6-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP62]], 1 +// CHECK6-NEXT: [[TMP63:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) +// CHECK6-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 +// CHECK6-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK6: omp_offload.failed15: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408(i64 [[TMP34]], double* [[TMP35]], double* [[TMP36]], double* [[TMP37]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK6: omp_offload.cont16: +// CHECK6-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK6-NEXT: [[CONV17:%.*]] = bitcast i64* [[CH_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP66]], i32* [[CONV17]], align 4 +// CHECK6-NEXT: [[TMP67:%.*]] = load i64, i64* [[CH_CASTED]], align 8 +// CHECK6-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* +// CHECK6-NEXT: store i32 [[TMP68]], i32* [[CONV19]], align 4 +// CHECK6-NEXT: [[TMP69:%.*]] = load i64, i64* [[N_CASTED18]], align 8 +// CHECK6-NEXT: [[TMP70:%.*]] = load double*, double** [[A]], align 8 +// CHECK6-NEXT: [[TMP71:%.*]] = load double*, double** [[B]], align 8 +// CHECK6-NEXT: [[TMP72:%.*]] = load double*, double** [[C]], align 8 +// CHECK6-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* +// CHECK6-NEXT: store i64 [[TMP67]], i64* [[TMP74]], align 8 +// CHECK6-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK6-NEXT: store i64 [[TMP67]], i64* [[TMP76]], align 8 +// CHECK6-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP77]], align 8 +// CHECK6-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* +// CHECK6-NEXT: store i64 [[TMP69]], i64* [[TMP79]], align 8 +// CHECK6-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK6-NEXT: store i64 [[TMP69]], i64* [[TMP81]], align 8 +// CHECK6-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP82]], align 8 +// CHECK6-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to double** +// CHECK6-NEXT: store double* [[TMP70]], double** [[TMP84]], align 8 +// CHECK6-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to double** +// CHECK6-NEXT: store double* [[TMP70]], double** [[TMP86]], align 8 +// CHECK6-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP87]], align 8 +// CHECK6-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** +// CHECK6-NEXT: store double* [[TMP71]], double** [[TMP89]], align 8 +// CHECK6-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to double** +// CHECK6-NEXT: store double* [[TMP71]], double** [[TMP91]], align 8 +// CHECK6-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP92]], align 8 +// CHECK6-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** +// CHECK6-NEXT: store double* [[TMP72]], double** [[TMP94]], align 8 +// CHECK6-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to double** +// CHECK6-NEXT: store double* [[TMP72]], double** [[TMP96]], align 8 +// CHECK6-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP97]], align 8 +// CHECK6-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK6-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK6-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP101]], 0 +// CHECK6-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// CHECK6-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 +// CHECK6-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK6-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK6-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP102]], 1 +// CHECK6-NEXT: [[TMP103:%.*]] = zext i32 [[ADD29]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) +// CHECK6-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 +// CHECK6-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK6: omp_offload.failed30: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447(i64 [[TMP67]], i64 [[TMP69]], double* [[TMP70]], double* [[TMP71]], double* [[TMP72]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK6: omp_offload.cont31: +// CHECK6-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV33:%.*]] = bitcast i64* [[N_CASTED32]] to i32* +// CHECK6-NEXT: store i32 [[TMP106]], i32* [[CONV33]], align 4 +// CHECK6-NEXT: [[TMP107:%.*]] = load i64, i64* [[N_CASTED32]], align 8 +// CHECK6-NEXT: [[TMP108:%.*]] = load double*, double** [[A]], align 8 +// CHECK6-NEXT: [[TMP109:%.*]] = load double*, double** [[B]], align 8 +// CHECK6-NEXT: [[TMP110:%.*]] = load double*, double** [[C]], align 8 +// CHECK6-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* +// CHECK6-NEXT: store i64 [[TMP107]], i64* [[TMP112]], align 8 +// CHECK6-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* +// CHECK6-NEXT: store i64 [[TMP107]], i64* [[TMP114]], align 8 +// CHECK6-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP115]], align 8 +// CHECK6-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to double** +// CHECK6-NEXT: store double* [[TMP108]], double** [[TMP117]], align 8 +// CHECK6-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to double** +// CHECK6-NEXT: store double* [[TMP108]], double** [[TMP119]], align 8 +// CHECK6-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP120]], align 8 +// CHECK6-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to double** +// CHECK6-NEXT: store double* [[TMP109]], double** [[TMP122]], align 8 +// CHECK6-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** +// CHECK6-NEXT: store double* [[TMP109]], double** [[TMP124]], align 8 +// CHECK6-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP125]], align 8 +// CHECK6-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** +// CHECK6-NEXT: store double* [[TMP110]], double** [[TMP127]], align 8 +// CHECK6-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** +// CHECK6-NEXT: store double* [[TMP110]], double** [[TMP129]], align 8 +// CHECK6-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP130]], align 8 +// CHECK6-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK6-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK6-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP134]], 0 +// CHECK6-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 +// CHECK6-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 +// CHECK6-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK6-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK6-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP135]], 1 +// CHECK6-NEXT: [[TMP136:%.*]] = zext i32 [[ADD43]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) +// CHECK6-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 +// CHECK6-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] +// CHECK6: omp_offload.failed44: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478(i64 [[TMP107]], double* [[TMP108]], double* [[TMP109]], double* [[TMP110]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT45]] +// CHECK6: omp_offload.cont45: +// CHECK6-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK6-NEXT: [[CONV47:%.*]] = bitcast i64* [[CH_CASTED46]] to i32* +// CHECK6-NEXT: store i32 [[TMP139]], i32* [[CONV47]], align 4 +// CHECK6-NEXT: [[TMP140:%.*]] = load i64, i64* [[CH_CASTED46]], align 8 +// CHECK6-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV49:%.*]] = bitcast i64* [[N_CASTED48]] to i32* +// CHECK6-NEXT: store i32 [[TMP141]], i32* [[CONV49]], align 4 +// CHECK6-NEXT: [[TMP142:%.*]] = load i64, i64* [[N_CASTED48]], align 8 +// CHECK6-NEXT: [[TMP143:%.*]] = load double*, double** [[A]], align 8 +// CHECK6-NEXT: [[TMP144:%.*]] = load double*, double** [[B]], align 8 +// CHECK6-NEXT: [[TMP145:%.*]] = load double*, double** [[C]], align 8 +// CHECK6-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* +// CHECK6-NEXT: store i64 [[TMP140]], i64* [[TMP147]], align 8 +// CHECK6-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* +// CHECK6-NEXT: store i64 [[TMP140]], i64* [[TMP149]], align 8 +// CHECK6-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP150]], align 8 +// CHECK6-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i64* +// CHECK6-NEXT: store i64 [[TMP142]], i64* [[TMP152]], align 8 +// CHECK6-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i64* +// CHECK6-NEXT: store i64 [[TMP142]], i64* [[TMP154]], align 8 +// CHECK6-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP155]], align 8 +// CHECK6-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to double** +// CHECK6-NEXT: store double* [[TMP143]], double** [[TMP157]], align 8 +// CHECK6-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to double** +// CHECK6-NEXT: store double* [[TMP143]], double** [[TMP159]], align 8 +// CHECK6-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP160]], align 8 +// CHECK6-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to double** +// CHECK6-NEXT: store double* [[TMP144]], double** [[TMP162]], align 8 +// CHECK6-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to double** +// CHECK6-NEXT: store double* [[TMP144]], double** [[TMP164]], align 8 +// CHECK6-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP165]], align 8 +// CHECK6-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to double** +// CHECK6-NEXT: store double* [[TMP145]], double** [[TMP167]], align 8 +// CHECK6-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to double** +// CHECK6-NEXT: store double* [[TMP145]], double** [[TMP169]], align 8 +// CHECK6-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP170]], align 8 +// CHECK6-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK6-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK6-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP174]], 0 +// CHECK6-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 +// CHECK6-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 +// CHECK6-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK6-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK6-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP175]], 1 +// CHECK6-NEXT: [[TMP176:%.*]] = zext i32 [[ADD59]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) +// CHECK6-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 +// CHECK6-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] +// CHECK6: omp_offload.failed60: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506(i64 [[TMP140]], i64 [[TMP142]], double* [[TMP143]], double* [[TMP144]], double* [[TMP145]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT61]] +// CHECK6: omp_offload.cont61: +// CHECK6-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV63:%.*]] = bitcast i64* [[N_CASTED62]] to i32* +// CHECK6-NEXT: store i32 [[TMP179]], i32* [[CONV63]], align 4 +// CHECK6-NEXT: [[TMP180:%.*]] = load i64, i64* [[N_CASTED62]], align 8 +// CHECK6-NEXT: [[TMP181:%.*]] = load double*, double** [[A]], align 8 +// CHECK6-NEXT: [[TMP182:%.*]] = load double*, double** [[B]], align 8 +// CHECK6-NEXT: [[TMP183:%.*]] = load double*, double** [[C]], align 8 +// CHECK6-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i64* +// CHECK6-NEXT: store i64 [[TMP180]], i64* [[TMP185]], align 8 +// CHECK6-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i64* +// CHECK6-NEXT: store i64 [[TMP180]], i64* [[TMP187]], align 8 +// CHECK6-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP188]], align 8 +// CHECK6-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to double** +// CHECK6-NEXT: store double* [[TMP181]], double** [[TMP190]], align 8 +// CHECK6-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to double** +// CHECK6-NEXT: store double* [[TMP181]], double** [[TMP192]], align 8 +// CHECK6-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP193]], align 8 +// CHECK6-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to double** +// CHECK6-NEXT: store double* [[TMP182]], double** [[TMP195]], align 8 +// CHECK6-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to double** +// CHECK6-NEXT: store double* [[TMP182]], double** [[TMP197]], align 8 +// CHECK6-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP198]], align 8 +// CHECK6-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to double** +// CHECK6-NEXT: store double* [[TMP183]], double** [[TMP200]], align 8 +// CHECK6-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to double** +// CHECK6-NEXT: store double* [[TMP183]], double** [[TMP202]], align 8 +// CHECK6-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP203]], align 8 +// CHECK6-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_68]], align 4 +// CHECK6-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_68]], align 4 +// CHECK6-NEXT: [[SUB70:%.*]] = sub nsw i32 [[TMP207]], 0 +// CHECK6-NEXT: [[DIV71:%.*]] = sdiv i32 [[SUB70]], 1 +// CHECK6-NEXT: [[SUB72:%.*]] = sub nsw i32 [[DIV71]], 1 +// CHECK6-NEXT: store i32 [[SUB72]], i32* [[DOTCAPTURE_EXPR_69]], align 4 +// CHECK6-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_69]], align 4 +// CHECK6-NEXT: [[ADD73:%.*]] = add nsw i32 [[TMP208]], 1 +// CHECK6-NEXT: [[TMP209:%.*]] = zext i32 [[ADD73]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) +// CHECK6-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 +// CHECK6-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED74:%.*]], label [[OMP_OFFLOAD_CONT75:%.*]] +// CHECK6: omp_offload.failed74: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536(i64 [[TMP180]], double* [[TMP181]], double* [[TMP182]], double* [[TMP183]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT75]] +// CHECK6: omp_offload.cont75: +// CHECK6-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK6-NEXT: [[CONV77:%.*]] = bitcast i64* [[CH_CASTED76]] to i32* +// CHECK6-NEXT: store i32 [[TMP212]], i32* [[CONV77]], align 4 +// CHECK6-NEXT: [[TMP213:%.*]] = load i64, i64* [[CH_CASTED76]], align 8 +// CHECK6-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV79:%.*]] = bitcast i64* [[N_CASTED78]] to i32* +// CHECK6-NEXT: store i32 [[TMP214]], i32* [[CONV79]], align 4 +// CHECK6-NEXT: [[TMP215:%.*]] = load i64, i64* [[N_CASTED78]], align 8 +// CHECK6-NEXT: [[TMP216:%.*]] = load double*, double** [[A]], align 8 +// CHECK6-NEXT: [[TMP217:%.*]] = load double*, double** [[B]], align 8 +// CHECK6-NEXT: [[TMP218:%.*]] = load double*, double** [[C]], align 8 +// CHECK6-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i64* +// CHECK6-NEXT: store i64 [[TMP213]], i64* [[TMP220]], align 8 +// CHECK6-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i64* +// CHECK6-NEXT: store i64 [[TMP213]], i64* [[TMP222]], align 8 +// CHECK6-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP223]], align 8 +// CHECK6-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i64* +// CHECK6-NEXT: store i64 [[TMP215]], i64* [[TMP225]], align 8 +// CHECK6-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i64* +// CHECK6-NEXT: store i64 [[TMP215]], i64* [[TMP227]], align 8 +// CHECK6-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP228]], align 8 +// CHECK6-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to double** +// CHECK6-NEXT: store double* [[TMP216]], double** [[TMP230]], align 8 +// CHECK6-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to double** +// CHECK6-NEXT: store double* [[TMP216]], double** [[TMP232]], align 8 +// CHECK6-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP233]], align 8 +// CHECK6-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to double** +// CHECK6-NEXT: store double* [[TMP217]], double** [[TMP235]], align 8 +// CHECK6-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to double** +// CHECK6-NEXT: store double* [[TMP217]], double** [[TMP237]], align 8 +// CHECK6-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP238]], align 8 +// CHECK6-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to double** +// CHECK6-NEXT: store double* [[TMP218]], double** [[TMP240]], align 8 +// CHECK6-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to double** +// CHECK6-NEXT: store double* [[TMP218]], double** [[TMP242]], align 8 +// CHECK6-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP243]], align 8 +// CHECK6-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_84]], align 4 +// CHECK6-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_84]], align 4 +// CHECK6-NEXT: [[SUB86:%.*]] = sub nsw i32 [[TMP247]], 0 +// CHECK6-NEXT: [[DIV87:%.*]] = sdiv i32 [[SUB86]], 1 +// CHECK6-NEXT: [[SUB88:%.*]] = sub nsw i32 [[DIV87]], 1 +// CHECK6-NEXT: store i32 [[SUB88]], i32* [[DOTCAPTURE_EXPR_85]], align 4 +// CHECK6-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_85]], align 4 +// CHECK6-NEXT: [[ADD89:%.*]] = add nsw i32 [[TMP248]], 1 +// CHECK6-NEXT: [[TMP249:%.*]] = zext i32 [[ADD89]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) +// CHECK6-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.24, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 +// CHECK6-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED90:%.*]], label [[OMP_OFFLOAD_CONT91:%.*]] +// CHECK6: omp_offload.failed90: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i64 [[TMP213]], i64 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT91]] +// CHECK6: omp_offload.cont91: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: ret i32 [[CALL]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 +// CHECK6-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] +// CHECK6-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 +// CHECK6-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK6-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] +// CHECK6-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 +// CHECK6-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] +// CHECK6-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 +// CHECK6-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK6-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] +// CHECK6-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 +// CHECK6-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK6: cond.true10: +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END12:%.*]] +// CHECK6: cond.false11: +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END12]] +// CHECK6: cond.end12: +// CHECK6-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE10]] ], [ [[TMP32]], [[COND_FALSE11]] ] +// CHECK6-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] +// CHECK6-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 +// CHECK6-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK6-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] +// CHECK6-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 +// CHECK6-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] +// CHECK6-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 +// CHECK6-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK6-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] +// CHECK6-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 +// CHECK6-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i64 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[CONV7]], [[TMP14]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CONV9:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[CONV9]], [[COND_FALSE]] ] +// CHECK6-NEXT: [[CONV10:%.*]] = trunc i64 [[COND]] to i32 +// CHECK6-NEXT: store i32 [[CONV10]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK6-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK6-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM13]] +// CHECK6-NEXT: [[TMP28:%.*]] = load double, double* [[ARRAYIDX14]], align 8 +// CHECK6-NEXT: [[ADD15:%.*]] = fadd double [[TMP25]], [[TMP28]] +// CHECK6-NEXT: [[TMP29:%.*]] = load double*, double** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK6-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP30]] to i64 +// CHECK6-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP29]], i64 [[IDXPROM16]] +// CHECK6-NEXT: store double [[ADD15]], double* [[ARRAYIDX17]], align 8 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK6-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] +// CHECK6-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] +// CHECK6-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 +// CHECK6-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..19 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK6-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP21:%.*]] = load double*, double** [[TMP2]], align 8, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP21]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX]], align 8, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP24:%.*]] = load double*, double** [[TMP3]], align 8, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP24]], i64 [[IDXPROM6]] +// CHECK6-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX7]], align 8, !llvm.access.group !18 +// CHECK6-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]] +// CHECK6-NEXT: [[TMP27:%.*]] = load double*, double** [[TMP1]], align 8, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP27]], i64 [[IDXPROM9]] +// CHECK6-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !18 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 +// CHECK6-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**, i64)* @.omp_outlined..23 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i64 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..23 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK6-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP22:%.*]] = load double*, double** [[TMP2]], align 8, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP22]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX]], align 8, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP25:%.*]] = load double*, double** [[TMP3]], align 8, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds double, double* [[TMP25]], i64 [[IDXPROM8]] +// CHECK6-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX9]], align 8, !llvm.access.group !21 +// CHECK6-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]] +// CHECK6-NEXT: [[TMP28:%.*]] = load double*, double** [[TMP1]], align 8, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP28]], i64 [[IDXPROM11]] +// CHECK6-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !21 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[B:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[C:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[CH:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[CH_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED32:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[CH_CASTED46:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED48:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS50:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS51:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS52:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED62:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS64:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS65:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS66:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP67:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_68:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_69:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[CH_CASTED76:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED78:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS80:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS81:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS82:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP83:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_84:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_85:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 10000, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 100, i32* [[CH]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32** +// CHECK6-NEXT: store i32* [[TMP2]], i32** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32** +// CHECK6-NEXT: store i32* [[TMP2]], i32** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32** +// CHECK6-NEXT: store i32* [[TMP3]], i32** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32** +// CHECK6-NEXT: store i32* [[TMP3]], i32** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK6-NEXT: store i32* [[TMP4]], i32** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32** +// CHECK6-NEXT: store i32* [[TMP4]], i32** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP30]]) +// CHECK6-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK6-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42(i64 [[TMP1]], i32* [[TMP2]], i32* [[TMP3]], i32* [[TMP4]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK6-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK6-NEXT: [[TMP37:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP42]], align 8 +// CHECK6-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32** +// CHECK6-NEXT: store i32* [[TMP35]], i32** [[TMP44]], align 8 +// CHECK6-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32** +// CHECK6-NEXT: store i32* [[TMP35]], i32** [[TMP46]], align 8 +// CHECK6-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK6-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK6-NEXT: store i32* [[TMP36]], i32** [[TMP49]], align 8 +// CHECK6-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK6-NEXT: store i32* [[TMP36]], i32** [[TMP51]], align 8 +// CHECK6-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP52]], align 8 +// CHECK6-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32** +// CHECK6-NEXT: store i32* [[TMP37]], i32** [[TMP54]], align 8 +// CHECK6-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32** +// CHECK6-NEXT: store i32* [[TMP37]], i32** [[TMP56]], align 8 +// CHECK6-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP57]], align 8 +// CHECK6-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK6-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK6-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP61]], 0 +// CHECK6-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK6-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK6-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP62]], 1 +// CHECK6-NEXT: [[TMP63:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) +// CHECK6-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.32, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.33, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 +// CHECK6-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK6: omp_offload.failed15: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51(i64 [[TMP34]], i32* [[TMP35]], i32* [[TMP36]], i32* [[TMP37]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK6: omp_offload.cont16: +// CHECK6-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK6-NEXT: [[CONV17:%.*]] = bitcast i64* [[CH_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP66]], i32* [[CONV17]], align 4 +// CHECK6-NEXT: [[TMP67:%.*]] = load i64, i64* [[CH_CASTED]], align 8 +// CHECK6-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* +// CHECK6-NEXT: store i32 [[TMP68]], i32* [[CONV19]], align 4 +// CHECK6-NEXT: [[TMP69:%.*]] = load i64, i64* [[N_CASTED18]], align 8 +// CHECK6-NEXT: [[TMP70:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK6-NEXT: [[TMP71:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK6-NEXT: [[TMP72:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK6-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* +// CHECK6-NEXT: store i64 [[TMP67]], i64* [[TMP74]], align 8 +// CHECK6-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK6-NEXT: store i64 [[TMP67]], i64* [[TMP76]], align 8 +// CHECK6-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP77]], align 8 +// CHECK6-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* +// CHECK6-NEXT: store i64 [[TMP69]], i64* [[TMP79]], align 8 +// CHECK6-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK6-NEXT: store i64 [[TMP69]], i64* [[TMP81]], align 8 +// CHECK6-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP82]], align 8 +// CHECK6-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK6-NEXT: store i32* [[TMP70]], i32** [[TMP84]], align 8 +// CHECK6-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** +// CHECK6-NEXT: store i32* [[TMP70]], i32** [[TMP86]], align 8 +// CHECK6-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP87]], align 8 +// CHECK6-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK6-NEXT: store i32* [[TMP71]], i32** [[TMP89]], align 8 +// CHECK6-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** +// CHECK6-NEXT: store i32* [[TMP71]], i32** [[TMP91]], align 8 +// CHECK6-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP92]], align 8 +// CHECK6-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to i32** +// CHECK6-NEXT: store i32* [[TMP72]], i32** [[TMP94]], align 8 +// CHECK6-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32** +// CHECK6-NEXT: store i32* [[TMP72]], i32** [[TMP96]], align 8 +// CHECK6-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP97]], align 8 +// CHECK6-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK6-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK6-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP101]], 0 +// CHECK6-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// CHECK6-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 +// CHECK6-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK6-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK6-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP102]], 1 +// CHECK6-NEXT: [[TMP103:%.*]] = zext i32 [[ADD29]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) +// CHECK6-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.36, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.37, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 +// CHECK6-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK6: omp_offload.failed30: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59(i64 [[TMP67]], i64 [[TMP69]], i32* [[TMP70]], i32* [[TMP71]], i32* [[TMP72]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK6: omp_offload.cont31: +// CHECK6-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV33:%.*]] = bitcast i64* [[N_CASTED32]] to i32* +// CHECK6-NEXT: store i32 [[TMP106]], i32* [[CONV33]], align 4 +// CHECK6-NEXT: [[TMP107:%.*]] = load i64, i64* [[N_CASTED32]], align 8 +// CHECK6-NEXT: [[TMP108:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK6-NEXT: [[TMP109:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK6-NEXT: [[TMP110:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK6-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* +// CHECK6-NEXT: store i64 [[TMP107]], i64* [[TMP112]], align 8 +// CHECK6-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* +// CHECK6-NEXT: store i64 [[TMP107]], i64* [[TMP114]], align 8 +// CHECK6-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP115]], align 8 +// CHECK6-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** +// CHECK6-NEXT: store i32* [[TMP108]], i32** [[TMP117]], align 8 +// CHECK6-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** +// CHECK6-NEXT: store i32* [[TMP108]], i32** [[TMP119]], align 8 +// CHECK6-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP120]], align 8 +// CHECK6-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** +// CHECK6-NEXT: store i32* [[TMP109]], i32** [[TMP122]], align 8 +// CHECK6-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32** +// CHECK6-NEXT: store i32* [[TMP109]], i32** [[TMP124]], align 8 +// CHECK6-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP125]], align 8 +// CHECK6-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32** +// CHECK6-NEXT: store i32* [[TMP110]], i32** [[TMP127]], align 8 +// CHECK6-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32** +// CHECK6-NEXT: store i32* [[TMP110]], i32** [[TMP129]], align 8 +// CHECK6-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP130]], align 8 +// CHECK6-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK6-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK6-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP134]], 0 +// CHECK6-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 +// CHECK6-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 +// CHECK6-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK6-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK6-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP135]], 1 +// CHECK6-NEXT: [[TMP136:%.*]] = zext i32 [[ADD43]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) +// CHECK6-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.40, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.41, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 +// CHECK6-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] +// CHECK6: omp_offload.failed44: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67(i64 [[TMP107]], i32* [[TMP108]], i32* [[TMP109]], i32* [[TMP110]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT45]] +// CHECK6: omp_offload.cont45: +// CHECK6-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK6-NEXT: [[CONV47:%.*]] = bitcast i64* [[CH_CASTED46]] to i32* +// CHECK6-NEXT: store i32 [[TMP139]], i32* [[CONV47]], align 4 +// CHECK6-NEXT: [[TMP140:%.*]] = load i64, i64* [[CH_CASTED46]], align 8 +// CHECK6-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV49:%.*]] = bitcast i64* [[N_CASTED48]] to i32* +// CHECK6-NEXT: store i32 [[TMP141]], i32* [[CONV49]], align 4 +// CHECK6-NEXT: [[TMP142:%.*]] = load i64, i64* [[N_CASTED48]], align 8 +// CHECK6-NEXT: [[TMP143:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK6-NEXT: [[TMP144:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK6-NEXT: [[TMP145:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK6-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* +// CHECK6-NEXT: store i64 [[TMP140]], i64* [[TMP147]], align 8 +// CHECK6-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* +// CHECK6-NEXT: store i64 [[TMP140]], i64* [[TMP149]], align 8 +// CHECK6-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP150]], align 8 +// CHECK6-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i64* +// CHECK6-NEXT: store i64 [[TMP142]], i64* [[TMP152]], align 8 +// CHECK6-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i64* +// CHECK6-NEXT: store i64 [[TMP142]], i64* [[TMP154]], align 8 +// CHECK6-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP155]], align 8 +// CHECK6-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** +// CHECK6-NEXT: store i32* [[TMP143]], i32** [[TMP157]], align 8 +// CHECK6-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** +// CHECK6-NEXT: store i32* [[TMP143]], i32** [[TMP159]], align 8 +// CHECK6-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP160]], align 8 +// CHECK6-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32** +// CHECK6-NEXT: store i32* [[TMP144]], i32** [[TMP162]], align 8 +// CHECK6-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32** +// CHECK6-NEXT: store i32* [[TMP144]], i32** [[TMP164]], align 8 +// CHECK6-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP165]], align 8 +// CHECK6-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to i32** +// CHECK6-NEXT: store i32* [[TMP145]], i32** [[TMP167]], align 8 +// CHECK6-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to i32** +// CHECK6-NEXT: store i32* [[TMP145]], i32** [[TMP169]], align 8 +// CHECK6-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP170]], align 8 +// CHECK6-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK6-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK6-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP174]], 0 +// CHECK6-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 +// CHECK6-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 +// CHECK6-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK6-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK6-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP175]], 1 +// CHECK6-NEXT: [[TMP176:%.*]] = zext i32 [[ADD59]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) +// CHECK6-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.44, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.45, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 +// CHECK6-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] +// CHECK6: omp_offload.failed60: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i64 [[TMP140]], i64 [[TMP142]], i32* [[TMP143]], i32* [[TMP144]], i32* [[TMP145]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT61]] +// CHECK6: omp_offload.cont61: +// CHECK6-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV63:%.*]] = bitcast i64* [[N_CASTED62]] to i32* +// CHECK6-NEXT: store i32 [[TMP179]], i32* [[CONV63]], align 4 +// CHECK6-NEXT: [[TMP180:%.*]] = load i64, i64* [[N_CASTED62]], align 8 +// CHECK6-NEXT: [[TMP181:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK6-NEXT: [[TMP182:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK6-NEXT: [[TMP183:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK6-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i64* +// CHECK6-NEXT: store i64 [[TMP180]], i64* [[TMP185]], align 8 +// CHECK6-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i64* +// CHECK6-NEXT: store i64 [[TMP180]], i64* [[TMP187]], align 8 +// CHECK6-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP188]], align 8 +// CHECK6-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to i32** +// CHECK6-NEXT: store i32* [[TMP181]], i32** [[TMP190]], align 8 +// CHECK6-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to i32** +// CHECK6-NEXT: store i32* [[TMP181]], i32** [[TMP192]], align 8 +// CHECK6-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP193]], align 8 +// CHECK6-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to i32** +// CHECK6-NEXT: store i32* [[TMP182]], i32** [[TMP195]], align 8 +// CHECK6-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to i32** +// CHECK6-NEXT: store i32* [[TMP182]], i32** [[TMP197]], align 8 +// CHECK6-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP198]], align 8 +// CHECK6-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to i32** +// CHECK6-NEXT: store i32* [[TMP183]], i32** [[TMP200]], align 8 +// CHECK6-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to i32** +// CHECK6-NEXT: store i32* [[TMP183]], i32** [[TMP202]], align 8 +// CHECK6-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP203]], align 8 +// CHECK6-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_68]], align 4 +// CHECK6-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_68]], align 4 +// CHECK6-NEXT: [[SUB70:%.*]] = sub nsw i32 [[TMP207]], 0 +// CHECK6-NEXT: [[DIV71:%.*]] = sdiv i32 [[SUB70]], 1 +// CHECK6-NEXT: [[SUB72:%.*]] = sub nsw i32 [[DIV71]], 1 +// CHECK6-NEXT: store i32 [[SUB72]], i32* [[DOTCAPTURE_EXPR_69]], align 4 +// CHECK6-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_69]], align 4 +// CHECK6-NEXT: [[ADD73:%.*]] = add nsw i32 [[TMP208]], 1 +// CHECK6-NEXT: [[TMP209:%.*]] = zext i32 [[ADD73]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) +// CHECK6-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.48, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.49, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 +// CHECK6-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED74:%.*]], label [[OMP_OFFLOAD_CONT75:%.*]] +// CHECK6: omp_offload.failed74: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83(i64 [[TMP180]], i32* [[TMP181]], i32* [[TMP182]], i32* [[TMP183]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT75]] +// CHECK6: omp_offload.cont75: +// CHECK6-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK6-NEXT: [[CONV77:%.*]] = bitcast i64* [[CH_CASTED76]] to i32* +// CHECK6-NEXT: store i32 [[TMP212]], i32* [[CONV77]], align 4 +// CHECK6-NEXT: [[TMP213:%.*]] = load i64, i64* [[CH_CASTED76]], align 8 +// CHECK6-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV79:%.*]] = bitcast i64* [[N_CASTED78]] to i32* +// CHECK6-NEXT: store i32 [[TMP214]], i32* [[CONV79]], align 4 +// CHECK6-NEXT: [[TMP215:%.*]] = load i64, i64* [[N_CASTED78]], align 8 +// CHECK6-NEXT: [[TMP216:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK6-NEXT: [[TMP217:%.*]] = load i32*, i32** [[B]], align 8 +// CHECK6-NEXT: [[TMP218:%.*]] = load i32*, i32** [[C]], align 8 +// CHECK6-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i64* +// CHECK6-NEXT: store i64 [[TMP213]], i64* [[TMP220]], align 8 +// CHECK6-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i64* +// CHECK6-NEXT: store i64 [[TMP213]], i64* [[TMP222]], align 8 +// CHECK6-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP223]], align 8 +// CHECK6-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i64* +// CHECK6-NEXT: store i64 [[TMP215]], i64* [[TMP225]], align 8 +// CHECK6-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i64* +// CHECK6-NEXT: store i64 [[TMP215]], i64* [[TMP227]], align 8 +// CHECK6-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP228]], align 8 +// CHECK6-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to i32** +// CHECK6-NEXT: store i32* [[TMP216]], i32** [[TMP230]], align 8 +// CHECK6-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to i32** +// CHECK6-NEXT: store i32* [[TMP216]], i32** [[TMP232]], align 8 +// CHECK6-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP233]], align 8 +// CHECK6-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to i32** +// CHECK6-NEXT: store i32* [[TMP217]], i32** [[TMP235]], align 8 +// CHECK6-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to i32** +// CHECK6-NEXT: store i32* [[TMP217]], i32** [[TMP237]], align 8 +// CHECK6-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP238]], align 8 +// CHECK6-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to i32** +// CHECK6-NEXT: store i32* [[TMP218]], i32** [[TMP240]], align 8 +// CHECK6-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to i32** +// CHECK6-NEXT: store i32* [[TMP218]], i32** [[TMP242]], align 8 +// CHECK6-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP243]], align 8 +// CHECK6-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_84]], align 4 +// CHECK6-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_84]], align 4 +// CHECK6-NEXT: [[SUB86:%.*]] = sub nsw i32 [[TMP247]], 0 +// CHECK6-NEXT: [[DIV87:%.*]] = sdiv i32 [[SUB86]], 1 +// CHECK6-NEXT: [[SUB88:%.*]] = sub nsw i32 [[DIV87]], 1 +// CHECK6-NEXT: store i32 [[SUB88]], i32* [[DOTCAPTURE_EXPR_85]], align 4 +// CHECK6-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_85]], align 4 +// CHECK6-NEXT: [[ADD89:%.*]] = add nsw i32 [[TMP248]], 1 +// CHECK6-NEXT: [[TMP249:%.*]] = zext i32 [[ADD89]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) +// CHECK6-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.52, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.53, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 +// CHECK6-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED90:%.*]], label [[OMP_OFFLOAD_CONT91:%.*]] +// CHECK6: omp_offload.failed90: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91(i64 [[TMP213]], i64 [[TMP215]], i32* [[TMP216]], i32* [[TMP217]], i32* [[TMP218]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT91]] +// CHECK6: omp_offload.cont91: // CHECK6-NEXT: ret i32 0 // // +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 +// CHECK6-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..27 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP21]], i32 2) +// CHECK6-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK6-NEXT: br i1 [[TMP23]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK6: .cancel.exit: +// CHECK6-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK6: .cancel.continue: +// CHECK6-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM7]] +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] +// CHECK6-NEXT: [[TMP30:%.*]] = load i32*, i32** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP31]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i64 [[IDXPROM10]] +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: cancel.exit: +// CHECK6-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK6-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: br label [[CANCEL_CONT]] +// CHECK6: cancel.cont: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 +// CHECK6-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..31 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..31 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK6-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 +// CHECK6-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..34 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..34 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..35 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK6: cond.true10: +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END12:%.*]] +// CHECK6: cond.false11: +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END12]] +// CHECK6: cond.end12: +// CHECK6-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE10]] ], [ [[TMP32]], [[COND_FALSE11]] ] +// CHECK6-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..35 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK6-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 +// CHECK6-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..38 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..38 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..39 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..39 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK6-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 +// CHECK6-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..42 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..42 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**, i64)* @.omp_outlined..43 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i64 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..43 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[CONV7]], [[TMP14]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CONV9:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[CONV9]], [[COND_FALSE]] ] +// CHECK6-NEXT: [[CONV10:%.*]] = trunc i64 [[COND]] to i32 +// CHECK6-NEXT: store i32 [[CONV10]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK6-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK6-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM13]] +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX14]], align 4 +// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP25]], [[TMP28]] +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK6-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP30]] to i64 +// CHECK6-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i32, i32* [[TMP29]], i64 [[IDXPROM16]] +// CHECK6-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX17]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK6-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] +// CHECK6-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] +// CHECK6-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 +// CHECK6-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..46 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..46 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..47 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..47 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK6-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[TMP2]], align 8, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP3]], align 8, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM6]] +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP26]] +// CHECK6-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP1]], align 8, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM9]] +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX10]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 +// CHECK6-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..50 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..50 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**, i64)* @.omp_outlined..51 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i64 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..51 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK6-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[TMP2]], align 8, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP22]], i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32*, i32** [[TMP3]], align 8, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[TMP25]], i64 [[IDXPROM8]] +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP27]] +// CHECK6-NEXT: [[TMP28:%.*]] = load i32*, i32** [[TMP1]], align 8, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[TMP28]], i64 [[IDXPROM11]] +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[ARRAYIDX12]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void +// +// // CHECK7-LABEL: define {{[^@]+}}@main // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: @@ -7870,24 +16678,4276 @@ // CHECK7-NEXT: [[C:%.*]] = alloca double*, align 4 // CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP7:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CH_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED16:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS17:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS18:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS19:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED29:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP33:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_34:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_35:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CH_CASTED42:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED43:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS44:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS45:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS46:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP47:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_48:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_49:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED56:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS57:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS58:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS59:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP60:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_62:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CH_CASTED69:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED70:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS71:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS72:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS73:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP74:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_76:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store i32 10000, i32* [[N]], align 4 // CHECK7-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store i32* [[N]], i32** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: store double** [[A]], double*** [[TMP1]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store double** [[B]], double*** [[TMP2]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: store double** [[C]], double*** [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 -// CHECK7-NEXT: store i32* [[CH]], i32** [[TMP4]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(20) [[REF_TMP]]) +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[A]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double*, double** [[B]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load double*, double** [[C]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to double** +// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double** +// CHECK7-NEXT: store double* [[TMP3]], double** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to double** +// CHECK7-NEXT: store double* [[TMP3]], double** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double** +// CHECK7-NEXT: store double* [[TMP4]], double** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double** +// CHECK7-NEXT: store double* [[TMP4]], double** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369(i32 [[TMP1]], double* [[TMP2]], double* [[TMP3]], double* [[TMP4]]) #[[ATTR2:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = load double*, double** [[A]], align 4 +// CHECK7-NEXT: [[TMP36:%.*]] = load double*, double** [[B]], align 4 +// CHECK7-NEXT: [[TMP37:%.*]] = load double*, double** [[C]], align 4 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP39]], align 4 +// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP41]], align 4 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to double** +// CHECK7-NEXT: store double* [[TMP35]], double** [[TMP44]], align 4 +// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to double** +// CHECK7-NEXT: store double* [[TMP35]], double** [[TMP46]], align 4 +// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP47]], align 4 +// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** +// CHECK7-NEXT: store double* [[TMP36]], double** [[TMP49]], align 4 +// CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** +// CHECK7-NEXT: store double* [[TMP36]], double** [[TMP51]], align 4 +// CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP52]], align 4 +// CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** +// CHECK7-NEXT: store double* [[TMP37]], double** [[TMP54]], align 4 +// CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to double** +// CHECK7-NEXT: store double* [[TMP37]], double** [[TMP56]], align 4 +// CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP57]], align 4 +// CHECK7-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK7-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK7-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP61]], 0 +// CHECK7-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK7-NEXT: [[SUB12:%.*]] = sub nsw i32 [[DIV11]], 1 +// CHECK7-NEXT: store i32 [[SUB12]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP62]], 1 +// CHECK7-NEXT: [[TMP63:%.*]] = zext i32 [[ADD13]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) +// CHECK7-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 +// CHECK7-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] +// CHECK7: omp_offload.failed14: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408(i32 [[TMP34]], double* [[TMP35]], double* [[TMP36]], double* [[TMP37]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT15]] +// CHECK7: omp_offload.cont15: +// CHECK7-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK7-NEXT: store i32 [[TMP66]], i32* [[CH_CASTED]], align 4 +// CHECK7-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH_CASTED]], align 4 +// CHECK7-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP68]], i32* [[N_CASTED16]], align 4 +// CHECK7-NEXT: [[TMP69:%.*]] = load i32, i32* [[N_CASTED16]], align 4 +// CHECK7-NEXT: [[TMP70:%.*]] = load double*, double** [[A]], align 4 +// CHECK7-NEXT: [[TMP71:%.*]] = load double*, double** [[B]], align 4 +// CHECK7-NEXT: [[TMP72:%.*]] = load double*, double** [[C]], align 4 +// CHECK7-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK7-NEXT: store i32 [[TMP67]], i32* [[TMP74]], align 4 +// CHECK7-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK7-NEXT: store i32 [[TMP67]], i32* [[TMP76]], align 4 +// CHECK7-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK7-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK7-NEXT: store i32 [[TMP69]], i32* [[TMP79]], align 4 +// CHECK7-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK7-NEXT: store i32 [[TMP69]], i32* [[TMP81]], align 4 +// CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to double** +// CHECK7-NEXT: store double* [[TMP70]], double** [[TMP84]], align 4 +// CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to double** +// CHECK7-NEXT: store double* [[TMP70]], double** [[TMP86]], align 4 +// CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP87]], align 4 +// CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** +// CHECK7-NEXT: store double* [[TMP71]], double** [[TMP89]], align 4 +// CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to double** +// CHECK7-NEXT: store double* [[TMP71]], double** [[TMP91]], align 4 +// CHECK7-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP92]], align 4 +// CHECK7-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** +// CHECK7-NEXT: store double* [[TMP72]], double** [[TMP94]], align 4 +// CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to double** +// CHECK7-NEXT: store double* [[TMP72]], double** [[TMP96]], align 4 +// CHECK7-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP97]], align 4 +// CHECK7-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK7-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK7-NEXT: [[SUB23:%.*]] = sub nsw i32 [[TMP101]], 0 +// CHECK7-NEXT: [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1 +// CHECK7-NEXT: [[SUB25:%.*]] = sub nsw i32 [[DIV24]], 1 +// CHECK7-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK7-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP102]], 1 +// CHECK7-NEXT: [[TMP103:%.*]] = zext i32 [[ADD26]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) +// CHECK7-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 +// CHECK7-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] +// CHECK7: omp_offload.failed27: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447(i32 [[TMP67]], i32 [[TMP69]], double* [[TMP70]], double* [[TMP71]], double* [[TMP72]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT28]] +// CHECK7: omp_offload.cont28: +// CHECK7-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP106]], i32* [[N_CASTED29]], align 4 +// CHECK7-NEXT: [[TMP107:%.*]] = load i32, i32* [[N_CASTED29]], align 4 +// CHECK7-NEXT: [[TMP108:%.*]] = load double*, double** [[A]], align 4 +// CHECK7-NEXT: [[TMP109:%.*]] = load double*, double** [[B]], align 4 +// CHECK7-NEXT: [[TMP110:%.*]] = load double*, double** [[C]], align 4 +// CHECK7-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* +// CHECK7-NEXT: store i32 [[TMP107]], i32* [[TMP112]], align 4 +// CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* +// CHECK7-NEXT: store i32 [[TMP107]], i32* [[TMP114]], align 4 +// CHECK7-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP115]], align 4 +// CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to double** +// CHECK7-NEXT: store double* [[TMP108]], double** [[TMP117]], align 4 +// CHECK7-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to double** +// CHECK7-NEXT: store double* [[TMP108]], double** [[TMP119]], align 4 +// CHECK7-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP120]], align 4 +// CHECK7-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to double** +// CHECK7-NEXT: store double* [[TMP109]], double** [[TMP122]], align 4 +// CHECK7-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** +// CHECK7-NEXT: store double* [[TMP109]], double** [[TMP124]], align 4 +// CHECK7-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP125]], align 4 +// CHECK7-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** +// CHECK7-NEXT: store double* [[TMP110]], double** [[TMP127]], align 4 +// CHECK7-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** +// CHECK7-NEXT: store double* [[TMP110]], double** [[TMP129]], align 4 +// CHECK7-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP130]], align 4 +// CHECK7-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_34]], align 4 +// CHECK7-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_34]], align 4 +// CHECK7-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP134]], 0 +// CHECK7-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 +// CHECK7-NEXT: [[SUB38:%.*]] = sub nsw i32 [[DIV37]], 1 +// CHECK7-NEXT: store i32 [[SUB38]], i32* [[DOTCAPTURE_EXPR_35]], align 4 +// CHECK7-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_35]], align 4 +// CHECK7-NEXT: [[ADD39:%.*]] = add nsw i32 [[TMP135]], 1 +// CHECK7-NEXT: [[TMP136:%.*]] = zext i32 [[ADD39]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) +// CHECK7-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 +// CHECK7-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED40:%.*]], label [[OMP_OFFLOAD_CONT41:%.*]] +// CHECK7: omp_offload.failed40: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478(i32 [[TMP107]], double* [[TMP108]], double* [[TMP109]], double* [[TMP110]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT41]] +// CHECK7: omp_offload.cont41: +// CHECK7-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK7-NEXT: store i32 [[TMP139]], i32* [[CH_CASTED42]], align 4 +// CHECK7-NEXT: [[TMP140:%.*]] = load i32, i32* [[CH_CASTED42]], align 4 +// CHECK7-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP141]], i32* [[N_CASTED43]], align 4 +// CHECK7-NEXT: [[TMP142:%.*]] = load i32, i32* [[N_CASTED43]], align 4 +// CHECK7-NEXT: [[TMP143:%.*]] = load double*, double** [[A]], align 4 +// CHECK7-NEXT: [[TMP144:%.*]] = load double*, double** [[B]], align 4 +// CHECK7-NEXT: [[TMP145:%.*]] = load double*, double** [[C]], align 4 +// CHECK7-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* +// CHECK7-NEXT: store i32 [[TMP140]], i32* [[TMP147]], align 4 +// CHECK7-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* +// CHECK7-NEXT: store i32 [[TMP140]], i32* [[TMP149]], align 4 +// CHECK7-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP150]], align 4 +// CHECK7-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i32* +// CHECK7-NEXT: store i32 [[TMP142]], i32* [[TMP152]], align 4 +// CHECK7-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i32* +// CHECK7-NEXT: store i32 [[TMP142]], i32* [[TMP154]], align 4 +// CHECK7-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP155]], align 4 +// CHECK7-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to double** +// CHECK7-NEXT: store double* [[TMP143]], double** [[TMP157]], align 4 +// CHECK7-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to double** +// CHECK7-NEXT: store double* [[TMP143]], double** [[TMP159]], align 4 +// CHECK7-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP160]], align 4 +// CHECK7-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to double** +// CHECK7-NEXT: store double* [[TMP144]], double** [[TMP162]], align 4 +// CHECK7-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to double** +// CHECK7-NEXT: store double* [[TMP144]], double** [[TMP164]], align 4 +// CHECK7-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP165]], align 4 +// CHECK7-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to double** +// CHECK7-NEXT: store double* [[TMP145]], double** [[TMP167]], align 4 +// CHECK7-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to double** +// CHECK7-NEXT: store double* [[TMP145]], double** [[TMP169]], align 4 +// CHECK7-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP170]], align 4 +// CHECK7-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_48]], align 4 +// CHECK7-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_48]], align 4 +// CHECK7-NEXT: [[SUB50:%.*]] = sub nsw i32 [[TMP174]], 0 +// CHECK7-NEXT: [[DIV51:%.*]] = sdiv i32 [[SUB50]], 1 +// CHECK7-NEXT: [[SUB52:%.*]] = sub nsw i32 [[DIV51]], 1 +// CHECK7-NEXT: store i32 [[SUB52]], i32* [[DOTCAPTURE_EXPR_49]], align 4 +// CHECK7-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_49]], align 4 +// CHECK7-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP175]], 1 +// CHECK7-NEXT: [[TMP176:%.*]] = zext i32 [[ADD53]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) +// CHECK7-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 +// CHECK7-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED54:%.*]], label [[OMP_OFFLOAD_CONT55:%.*]] +// CHECK7: omp_offload.failed54: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506(i32 [[TMP140]], i32 [[TMP142]], double* [[TMP143]], double* [[TMP144]], double* [[TMP145]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT55]] +// CHECK7: omp_offload.cont55: +// CHECK7-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP179]], i32* [[N_CASTED56]], align 4 +// CHECK7-NEXT: [[TMP180:%.*]] = load i32, i32* [[N_CASTED56]], align 4 +// CHECK7-NEXT: [[TMP181:%.*]] = load double*, double** [[A]], align 4 +// CHECK7-NEXT: [[TMP182:%.*]] = load double*, double** [[B]], align 4 +// CHECK7-NEXT: [[TMP183:%.*]] = load double*, double** [[C]], align 4 +// CHECK7-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i32* +// CHECK7-NEXT: store i32 [[TMP180]], i32* [[TMP185]], align 4 +// CHECK7-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i32* +// CHECK7-NEXT: store i32 [[TMP180]], i32* [[TMP187]], align 4 +// CHECK7-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP188]], align 4 +// CHECK7-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to double** +// CHECK7-NEXT: store double* [[TMP181]], double** [[TMP190]], align 4 +// CHECK7-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to double** +// CHECK7-NEXT: store double* [[TMP181]], double** [[TMP192]], align 4 +// CHECK7-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP193]], align 4 +// CHECK7-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to double** +// CHECK7-NEXT: store double* [[TMP182]], double** [[TMP195]], align 4 +// CHECK7-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to double** +// CHECK7-NEXT: store double* [[TMP182]], double** [[TMP197]], align 4 +// CHECK7-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP198]], align 4 +// CHECK7-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to double** +// CHECK7-NEXT: store double* [[TMP183]], double** [[TMP200]], align 4 +// CHECK7-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to double** +// CHECK7-NEXT: store double* [[TMP183]], double** [[TMP202]], align 4 +// CHECK7-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP203]], align 4 +// CHECK7-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK7-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK7-NEXT: [[SUB63:%.*]] = sub nsw i32 [[TMP207]], 0 +// CHECK7-NEXT: [[DIV64:%.*]] = sdiv i32 [[SUB63]], 1 +// CHECK7-NEXT: [[SUB65:%.*]] = sub nsw i32 [[DIV64]], 1 +// CHECK7-NEXT: store i32 [[SUB65]], i32* [[DOTCAPTURE_EXPR_62]], align 4 +// CHECK7-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_62]], align 4 +// CHECK7-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP208]], 1 +// CHECK7-NEXT: [[TMP209:%.*]] = zext i32 [[ADD66]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) +// CHECK7-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 +// CHECK7-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED67:%.*]], label [[OMP_OFFLOAD_CONT68:%.*]] +// CHECK7: omp_offload.failed67: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536(i32 [[TMP180]], double* [[TMP181]], double* [[TMP182]], double* [[TMP183]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT68]] +// CHECK7: omp_offload.cont68: +// CHECK7-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK7-NEXT: store i32 [[TMP212]], i32* [[CH_CASTED69]], align 4 +// CHECK7-NEXT: [[TMP213:%.*]] = load i32, i32* [[CH_CASTED69]], align 4 +// CHECK7-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP214]], i32* [[N_CASTED70]], align 4 +// CHECK7-NEXT: [[TMP215:%.*]] = load i32, i32* [[N_CASTED70]], align 4 +// CHECK7-NEXT: [[TMP216:%.*]] = load double*, double** [[A]], align 4 +// CHECK7-NEXT: [[TMP217:%.*]] = load double*, double** [[B]], align 4 +// CHECK7-NEXT: [[TMP218:%.*]] = load double*, double** [[C]], align 4 +// CHECK7-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i32* +// CHECK7-NEXT: store i32 [[TMP213]], i32* [[TMP220]], align 4 +// CHECK7-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i32* +// CHECK7-NEXT: store i32 [[TMP213]], i32* [[TMP222]], align 4 +// CHECK7-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP223]], align 4 +// CHECK7-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i32* +// CHECK7-NEXT: store i32 [[TMP215]], i32* [[TMP225]], align 4 +// CHECK7-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i32* +// CHECK7-NEXT: store i32 [[TMP215]], i32* [[TMP227]], align 4 +// CHECK7-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP228]], align 4 +// CHECK7-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to double** +// CHECK7-NEXT: store double* [[TMP216]], double** [[TMP230]], align 4 +// CHECK7-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to double** +// CHECK7-NEXT: store double* [[TMP216]], double** [[TMP232]], align 4 +// CHECK7-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP233]], align 4 +// CHECK7-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to double** +// CHECK7-NEXT: store double* [[TMP217]], double** [[TMP235]], align 4 +// CHECK7-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to double** +// CHECK7-NEXT: store double* [[TMP217]], double** [[TMP237]], align 4 +// CHECK7-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP238]], align 4 +// CHECK7-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to double** +// CHECK7-NEXT: store double* [[TMP218]], double** [[TMP240]], align 4 +// CHECK7-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to double** +// CHECK7-NEXT: store double* [[TMP218]], double** [[TMP242]], align 4 +// CHECK7-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP243]], align 4 +// CHECK7-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_75]], align 4 +// CHECK7-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_75]], align 4 +// CHECK7-NEXT: [[SUB77:%.*]] = sub nsw i32 [[TMP247]], 0 +// CHECK7-NEXT: [[DIV78:%.*]] = sdiv i32 [[SUB77]], 1 +// CHECK7-NEXT: [[SUB79:%.*]] = sub nsw i32 [[DIV78]], 1 +// CHECK7-NEXT: store i32 [[SUB79]], i32* [[DOTCAPTURE_EXPR_76]], align 4 +// CHECK7-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_76]], align 4 +// CHECK7-NEXT: [[ADD80:%.*]] = add nsw i32 [[TMP248]], 1 +// CHECK7-NEXT: [[TMP249:%.*]] = zext i32 [[ADD80]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) +// CHECK7-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.24, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 +// CHECK7-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED81:%.*]], label [[OMP_OFFLOAD_CONT82:%.*]] +// CHECK7: omp_offload.failed81: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i32 [[TMP213]], i32 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT82]] +// CHECK7: omp_offload.cont82: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: ret i32 [[CALL]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 +// CHECK7-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] +// CHECK7-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] +// CHECK7-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] +// CHECK7-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 +// CHECK7-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] +// CHECK7-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] +// CHECK7-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] +// CHECK7-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 +// CHECK7-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] +// CHECK7-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK7: cond.true10: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END12:%.*]] +// CHECK7: cond.false11: +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END12]] +// CHECK7: cond.end12: +// CHECK7-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE10]] ], [ [[TMP30]], [[COND_FALSE11]] ] +// CHECK7-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] +// CHECK7-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] +// CHECK7-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] +// CHECK7-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 +// CHECK7-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] +// CHECK7-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] +// CHECK7-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] +// CHECK7-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 +// CHECK7-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp ugt i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] +// CHECK7-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] +// CHECK7-NEXT: [[TMP28:%.*]] = load double, double* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = fadd double [[TMP25]], [[TMP28]] +// CHECK7-NEXT: [[TMP29:%.*]] = load double*, double** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP29]], i32 [[TMP30]] +// CHECK7-NEXT: store double [[ADD9]], double* [[ARRAYIDX10]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK7-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] +// CHECK7-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] +// CHECK7-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 +// CHECK7-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..19 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK7-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[TMP21:%.*]] = load double*, double** [[TMP2]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP21]], i32 [[TMP22]] +// CHECK7-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[TMP24:%.*]] = load double*, double** [[TMP3]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds double, double* [[TMP24]], i32 [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX5]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]] +// CHECK7-NEXT: [[TMP27:%.*]] = load double*, double** [[TMP1]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP27]], i32 [[TMP28]] +// CHECK7-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 +// CHECK7-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**, i32)* @.omp_outlined..23 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..23 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK7-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP22:%.*]] = load double*, double** [[TMP2]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP22]], i32 [[TMP23]] +// CHECK7-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP25:%.*]] = load double*, double** [[TMP3]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP25]], i32 [[TMP26]] +// CHECK7-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX6]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]] +// CHECK7-NEXT: [[TMP28:%.*]] = load double*, double** [[TMP1]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP28]], i32 [[TMP29]] +// CHECK7-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR3:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[B:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[C:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CH:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP7:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CH_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED16:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS17:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS18:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS19:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED29:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP33:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_34:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_35:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CH_CASTED42:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED43:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS44:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS45:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS46:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP47:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_48:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_49:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED56:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS57:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS58:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS59:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP60:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_62:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CH_CASTED69:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED70:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS71:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS72:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS73:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP74:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_76:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 10000, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 100, i32* [[CH]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32** +// CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32** +// CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32** +// CHECK7-NEXT: store i32* [[TMP3]], i32** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32** +// CHECK7-NEXT: store i32* [[TMP3]], i32** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK7-NEXT: store i32* [[TMP4]], i32** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32** +// CHECK7-NEXT: store i32* [[TMP4]], i32** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP30]]) +// CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42(i32 [[TMP1]], i32* [[TMP2]], i32* [[TMP3]], i32* [[TMP4]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK7-NEXT: [[TMP36:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK7-NEXT: [[TMP37:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP39]], align 4 +// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP41]], align 4 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32** +// CHECK7-NEXT: store i32* [[TMP35]], i32** [[TMP44]], align 4 +// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32** +// CHECK7-NEXT: store i32* [[TMP35]], i32** [[TMP46]], align 4 +// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP47]], align 4 +// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK7-NEXT: store i32* [[TMP36]], i32** [[TMP49]], align 4 +// CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK7-NEXT: store i32* [[TMP36]], i32** [[TMP51]], align 4 +// CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP52]], align 4 +// CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32** +// CHECK7-NEXT: store i32* [[TMP37]], i32** [[TMP54]], align 4 +// CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32** +// CHECK7-NEXT: store i32* [[TMP37]], i32** [[TMP56]], align 4 +// CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP57]], align 4 +// CHECK7-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK7-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK7-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP61]], 0 +// CHECK7-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK7-NEXT: [[SUB12:%.*]] = sub nsw i32 [[DIV11]], 1 +// CHECK7-NEXT: store i32 [[SUB12]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP62]], 1 +// CHECK7-NEXT: [[TMP63:%.*]] = zext i32 [[ADD13]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) +// CHECK7-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.32, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.33, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 +// CHECK7-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] +// CHECK7: omp_offload.failed14: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51(i32 [[TMP34]], i32* [[TMP35]], i32* [[TMP36]], i32* [[TMP37]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT15]] +// CHECK7: omp_offload.cont15: +// CHECK7-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK7-NEXT: store i32 [[TMP66]], i32* [[CH_CASTED]], align 4 +// CHECK7-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH_CASTED]], align 4 +// CHECK7-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP68]], i32* [[N_CASTED16]], align 4 +// CHECK7-NEXT: [[TMP69:%.*]] = load i32, i32* [[N_CASTED16]], align 4 +// CHECK7-NEXT: [[TMP70:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK7-NEXT: [[TMP71:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK7-NEXT: [[TMP72:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK7-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK7-NEXT: store i32 [[TMP67]], i32* [[TMP74]], align 4 +// CHECK7-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK7-NEXT: store i32 [[TMP67]], i32* [[TMP76]], align 4 +// CHECK7-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK7-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK7-NEXT: store i32 [[TMP69]], i32* [[TMP79]], align 4 +// CHECK7-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK7-NEXT: store i32 [[TMP69]], i32* [[TMP81]], align 4 +// CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK7-NEXT: store i32* [[TMP70]], i32** [[TMP84]], align 4 +// CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** +// CHECK7-NEXT: store i32* [[TMP70]], i32** [[TMP86]], align 4 +// CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP87]], align 4 +// CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK7-NEXT: store i32* [[TMP71]], i32** [[TMP89]], align 4 +// CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** +// CHECK7-NEXT: store i32* [[TMP71]], i32** [[TMP91]], align 4 +// CHECK7-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP92]], align 4 +// CHECK7-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to i32** +// CHECK7-NEXT: store i32* [[TMP72]], i32** [[TMP94]], align 4 +// CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32** +// CHECK7-NEXT: store i32* [[TMP72]], i32** [[TMP96]], align 4 +// CHECK7-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP97]], align 4 +// CHECK7-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK7-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK7-NEXT: [[SUB23:%.*]] = sub nsw i32 [[TMP101]], 0 +// CHECK7-NEXT: [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1 +// CHECK7-NEXT: [[SUB25:%.*]] = sub nsw i32 [[DIV24]], 1 +// CHECK7-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK7-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP102]], 1 +// CHECK7-NEXT: [[TMP103:%.*]] = zext i32 [[ADD26]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) +// CHECK7-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.36, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.37, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 +// CHECK7-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] +// CHECK7: omp_offload.failed27: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59(i32 [[TMP67]], i32 [[TMP69]], i32* [[TMP70]], i32* [[TMP71]], i32* [[TMP72]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT28]] +// CHECK7: omp_offload.cont28: +// CHECK7-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP106]], i32* [[N_CASTED29]], align 4 +// CHECK7-NEXT: [[TMP107:%.*]] = load i32, i32* [[N_CASTED29]], align 4 +// CHECK7-NEXT: [[TMP108:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK7-NEXT: [[TMP109:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK7-NEXT: [[TMP110:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK7-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* +// CHECK7-NEXT: store i32 [[TMP107]], i32* [[TMP112]], align 4 +// CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* +// CHECK7-NEXT: store i32 [[TMP107]], i32* [[TMP114]], align 4 +// CHECK7-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP115]], align 4 +// CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** +// CHECK7-NEXT: store i32* [[TMP108]], i32** [[TMP117]], align 4 +// CHECK7-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** +// CHECK7-NEXT: store i32* [[TMP108]], i32** [[TMP119]], align 4 +// CHECK7-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP120]], align 4 +// CHECK7-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** +// CHECK7-NEXT: store i32* [[TMP109]], i32** [[TMP122]], align 4 +// CHECK7-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32** +// CHECK7-NEXT: store i32* [[TMP109]], i32** [[TMP124]], align 4 +// CHECK7-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP125]], align 4 +// CHECK7-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32** +// CHECK7-NEXT: store i32* [[TMP110]], i32** [[TMP127]], align 4 +// CHECK7-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32** +// CHECK7-NEXT: store i32* [[TMP110]], i32** [[TMP129]], align 4 +// CHECK7-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP130]], align 4 +// CHECK7-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_34]], align 4 +// CHECK7-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_34]], align 4 +// CHECK7-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP134]], 0 +// CHECK7-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 +// CHECK7-NEXT: [[SUB38:%.*]] = sub nsw i32 [[DIV37]], 1 +// CHECK7-NEXT: store i32 [[SUB38]], i32* [[DOTCAPTURE_EXPR_35]], align 4 +// CHECK7-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_35]], align 4 +// CHECK7-NEXT: [[ADD39:%.*]] = add nsw i32 [[TMP135]], 1 +// CHECK7-NEXT: [[TMP136:%.*]] = zext i32 [[ADD39]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) +// CHECK7-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.40, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.41, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 +// CHECK7-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED40:%.*]], label [[OMP_OFFLOAD_CONT41:%.*]] +// CHECK7: omp_offload.failed40: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67(i32 [[TMP107]], i32* [[TMP108]], i32* [[TMP109]], i32* [[TMP110]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT41]] +// CHECK7: omp_offload.cont41: +// CHECK7-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK7-NEXT: store i32 [[TMP139]], i32* [[CH_CASTED42]], align 4 +// CHECK7-NEXT: [[TMP140:%.*]] = load i32, i32* [[CH_CASTED42]], align 4 +// CHECK7-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP141]], i32* [[N_CASTED43]], align 4 +// CHECK7-NEXT: [[TMP142:%.*]] = load i32, i32* [[N_CASTED43]], align 4 +// CHECK7-NEXT: [[TMP143:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK7-NEXT: [[TMP144:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK7-NEXT: [[TMP145:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK7-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* +// CHECK7-NEXT: store i32 [[TMP140]], i32* [[TMP147]], align 4 +// CHECK7-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* +// CHECK7-NEXT: store i32 [[TMP140]], i32* [[TMP149]], align 4 +// CHECK7-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP150]], align 4 +// CHECK7-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i32* +// CHECK7-NEXT: store i32 [[TMP142]], i32* [[TMP152]], align 4 +// CHECK7-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i32* +// CHECK7-NEXT: store i32 [[TMP142]], i32* [[TMP154]], align 4 +// CHECK7-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP155]], align 4 +// CHECK7-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** +// CHECK7-NEXT: store i32* [[TMP143]], i32** [[TMP157]], align 4 +// CHECK7-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** +// CHECK7-NEXT: store i32* [[TMP143]], i32** [[TMP159]], align 4 +// CHECK7-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP160]], align 4 +// CHECK7-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32** +// CHECK7-NEXT: store i32* [[TMP144]], i32** [[TMP162]], align 4 +// CHECK7-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32** +// CHECK7-NEXT: store i32* [[TMP144]], i32** [[TMP164]], align 4 +// CHECK7-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP165]], align 4 +// CHECK7-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to i32** +// CHECK7-NEXT: store i32* [[TMP145]], i32** [[TMP167]], align 4 +// CHECK7-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to i32** +// CHECK7-NEXT: store i32* [[TMP145]], i32** [[TMP169]], align 4 +// CHECK7-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP170]], align 4 +// CHECK7-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_48]], align 4 +// CHECK7-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_48]], align 4 +// CHECK7-NEXT: [[SUB50:%.*]] = sub nsw i32 [[TMP174]], 0 +// CHECK7-NEXT: [[DIV51:%.*]] = sdiv i32 [[SUB50]], 1 +// CHECK7-NEXT: [[SUB52:%.*]] = sub nsw i32 [[DIV51]], 1 +// CHECK7-NEXT: store i32 [[SUB52]], i32* [[DOTCAPTURE_EXPR_49]], align 4 +// CHECK7-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_49]], align 4 +// CHECK7-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP175]], 1 +// CHECK7-NEXT: [[TMP176:%.*]] = zext i32 [[ADD53]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) +// CHECK7-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.44, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.45, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 +// CHECK7-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED54:%.*]], label [[OMP_OFFLOAD_CONT55:%.*]] +// CHECK7: omp_offload.failed54: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32 [[TMP140]], i32 [[TMP142]], i32* [[TMP143]], i32* [[TMP144]], i32* [[TMP145]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT55]] +// CHECK7: omp_offload.cont55: +// CHECK7-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP179]], i32* [[N_CASTED56]], align 4 +// CHECK7-NEXT: [[TMP180:%.*]] = load i32, i32* [[N_CASTED56]], align 4 +// CHECK7-NEXT: [[TMP181:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK7-NEXT: [[TMP182:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK7-NEXT: [[TMP183:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK7-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i32* +// CHECK7-NEXT: store i32 [[TMP180]], i32* [[TMP185]], align 4 +// CHECK7-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i32* +// CHECK7-NEXT: store i32 [[TMP180]], i32* [[TMP187]], align 4 +// CHECK7-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP188]], align 4 +// CHECK7-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to i32** +// CHECK7-NEXT: store i32* [[TMP181]], i32** [[TMP190]], align 4 +// CHECK7-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to i32** +// CHECK7-NEXT: store i32* [[TMP181]], i32** [[TMP192]], align 4 +// CHECK7-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP193]], align 4 +// CHECK7-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to i32** +// CHECK7-NEXT: store i32* [[TMP182]], i32** [[TMP195]], align 4 +// CHECK7-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to i32** +// CHECK7-NEXT: store i32* [[TMP182]], i32** [[TMP197]], align 4 +// CHECK7-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP198]], align 4 +// CHECK7-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to i32** +// CHECK7-NEXT: store i32* [[TMP183]], i32** [[TMP200]], align 4 +// CHECK7-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to i32** +// CHECK7-NEXT: store i32* [[TMP183]], i32** [[TMP202]], align 4 +// CHECK7-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP203]], align 4 +// CHECK7-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK7-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK7-NEXT: [[SUB63:%.*]] = sub nsw i32 [[TMP207]], 0 +// CHECK7-NEXT: [[DIV64:%.*]] = sdiv i32 [[SUB63]], 1 +// CHECK7-NEXT: [[SUB65:%.*]] = sub nsw i32 [[DIV64]], 1 +// CHECK7-NEXT: store i32 [[SUB65]], i32* [[DOTCAPTURE_EXPR_62]], align 4 +// CHECK7-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_62]], align 4 +// CHECK7-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP208]], 1 +// CHECK7-NEXT: [[TMP209:%.*]] = zext i32 [[ADD66]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) +// CHECK7-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.48, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.49, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 +// CHECK7-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED67:%.*]], label [[OMP_OFFLOAD_CONT68:%.*]] +// CHECK7: omp_offload.failed67: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83(i32 [[TMP180]], i32* [[TMP181]], i32* [[TMP182]], i32* [[TMP183]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT68]] +// CHECK7: omp_offload.cont68: +// CHECK7-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK7-NEXT: store i32 [[TMP212]], i32* [[CH_CASTED69]], align 4 +// CHECK7-NEXT: [[TMP213:%.*]] = load i32, i32* [[CH_CASTED69]], align 4 +// CHECK7-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP214]], i32* [[N_CASTED70]], align 4 +// CHECK7-NEXT: [[TMP215:%.*]] = load i32, i32* [[N_CASTED70]], align 4 +// CHECK7-NEXT: [[TMP216:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK7-NEXT: [[TMP217:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK7-NEXT: [[TMP218:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK7-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i32* +// CHECK7-NEXT: store i32 [[TMP213]], i32* [[TMP220]], align 4 +// CHECK7-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i32* +// CHECK7-NEXT: store i32 [[TMP213]], i32* [[TMP222]], align 4 +// CHECK7-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP223]], align 4 +// CHECK7-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i32* +// CHECK7-NEXT: store i32 [[TMP215]], i32* [[TMP225]], align 4 +// CHECK7-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i32* +// CHECK7-NEXT: store i32 [[TMP215]], i32* [[TMP227]], align 4 +// CHECK7-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP228]], align 4 +// CHECK7-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to i32** +// CHECK7-NEXT: store i32* [[TMP216]], i32** [[TMP230]], align 4 +// CHECK7-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to i32** +// CHECK7-NEXT: store i32* [[TMP216]], i32** [[TMP232]], align 4 +// CHECK7-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP233]], align 4 +// CHECK7-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to i32** +// CHECK7-NEXT: store i32* [[TMP217]], i32** [[TMP235]], align 4 +// CHECK7-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to i32** +// CHECK7-NEXT: store i32* [[TMP217]], i32** [[TMP237]], align 4 +// CHECK7-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP238]], align 4 +// CHECK7-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to i32** +// CHECK7-NEXT: store i32* [[TMP218]], i32** [[TMP240]], align 4 +// CHECK7-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to i32** +// CHECK7-NEXT: store i32* [[TMP218]], i32** [[TMP242]], align 4 +// CHECK7-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP243]], align 4 +// CHECK7-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_75]], align 4 +// CHECK7-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_75]], align 4 +// CHECK7-NEXT: [[SUB77:%.*]] = sub nsw i32 [[TMP247]], 0 +// CHECK7-NEXT: [[DIV78:%.*]] = sdiv i32 [[SUB77]], 1 +// CHECK7-NEXT: [[SUB79:%.*]] = sub nsw i32 [[DIV78]], 1 +// CHECK7-NEXT: store i32 [[SUB79]], i32* [[DOTCAPTURE_EXPR_76]], align 4 +// CHECK7-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_76]], align 4 +// CHECK7-NEXT: [[ADD80:%.*]] = add nsw i32 [[TMP248]], 1 +// CHECK7-NEXT: [[TMP249:%.*]] = zext i32 [[ADD80]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) +// CHECK7-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.52, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.53, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 +// CHECK7-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED81:%.*]], label [[OMP_OFFLOAD_CONT82:%.*]] +// CHECK7: omp_offload.failed81: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91(i32 [[TMP213]], i32 [[TMP215]], i32* [[TMP216]], i32* [[TMP217]], i32* [[TMP218]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT82]] +// CHECK7: omp_offload.cont82: // CHECK7-NEXT: ret i32 0 // // +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 +// CHECK7-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..27 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP21]], i32 2) +// CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK7-NEXT: br i1 [[TMP23]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK7: .cancel.exit: +// CHECK7-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK7: .cancel.continue: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] +// CHECK7-NEXT: [[TMP30:%.*]] = load i32*, i32** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i32 [[TMP31]] +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP32]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: cancel.exit: +// CHECK7-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK7-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: br label [[CANCEL_CONT]] +// CHECK7: cancel.cont: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 +// CHECK7-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..31 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..31 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 +// CHECK7-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..34 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..34 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..35 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] +// CHECK7-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK7: cond.true10: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END12:%.*]] +// CHECK7: cond.false11: +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END12]] +// CHECK7: cond.end12: +// CHECK7-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE10]] ], [ [[TMP30]], [[COND_FALSE11]] ] +// CHECK7-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..35 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 +// CHECK7-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..38 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..38 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..39 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..39 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 +// CHECK7-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..42 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..42 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**, i32)* @.omp_outlined..43 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..43 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp ugt i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP28]] +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP29]], i32 [[TMP30]] +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX10]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK7-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] +// CHECK7-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] +// CHECK7-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 +// CHECK7-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..46 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..46 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..47 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..47 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK7-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[TMP2]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i32 [[TMP22]] +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP3]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX5]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP26]] +// CHECK7-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP1]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX7]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 +// CHECK7-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..50 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..50 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**, i32)* @.omp_outlined..51 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..51 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK7-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32*, i32** [[TMP2]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP22]], i32 [[TMP23]] +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[TMP3]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP25]], i32 [[TMP26]] +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], [[TMP27]] +// CHECK7-NEXT: [[TMP28:%.*]] = load i32*, i32** [[TMP1]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP28]], i32 [[TMP29]] +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void +// +// // CHECK8-LABEL: define {{[^@]+}}@main // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: @@ -7897,19312 +20957,4272 @@ // CHECK8-NEXT: [[C:%.*]] = alloca double*, align 4 // CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP7:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CH_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED16:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS17:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS18:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS19:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED29:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP33:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_34:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_35:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CH_CASTED42:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED43:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS44:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS45:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS46:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP47:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_48:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_49:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED56:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS57:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS58:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS59:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP60:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_62:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CH_CASTED69:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED70:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS71:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS72:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS73:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP74:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_76:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store i32 10000, i32* [[N]], align 4 // CHECK8-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store i32* [[N]], i32** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: store double** [[A]], double*** [[TMP1]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK8-NEXT: store double** [[B]], double*** [[TMP2]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK8-NEXT: store double** [[C]], double*** [[TMP3]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 -// CHECK8-NEXT: store i32* [[CH]], i32** [[TMP4]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(20) [[REF_TMP]]) +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[A]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double*, double** [[B]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load double*, double** [[C]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to double** +// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double** +// CHECK8-NEXT: store double* [[TMP3]], double** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to double** +// CHECK8-NEXT: store double* [[TMP3]], double** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double** +// CHECK8-NEXT: store double* [[TMP4]], double** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double** +// CHECK8-NEXT: store double* [[TMP4]], double** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK8-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK8-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369(i32 [[TMP1]], double* [[TMP2]], double* [[TMP3]], double* [[TMP4]]) #[[ATTR2:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = load double*, double** [[A]], align 4 +// CHECK8-NEXT: [[TMP36:%.*]] = load double*, double** [[B]], align 4 +// CHECK8-NEXT: [[TMP37:%.*]] = load double*, double** [[C]], align 4 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP39]], align 4 +// CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP41]], align 4 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to double** +// CHECK8-NEXT: store double* [[TMP35]], double** [[TMP44]], align 4 +// CHECK8-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to double** +// CHECK8-NEXT: store double* [[TMP35]], double** [[TMP46]], align 4 +// CHECK8-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP47]], align 4 +// CHECK8-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** +// CHECK8-NEXT: store double* [[TMP36]], double** [[TMP49]], align 4 +// CHECK8-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** +// CHECK8-NEXT: store double* [[TMP36]], double** [[TMP51]], align 4 +// CHECK8-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP52]], align 4 +// CHECK8-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** +// CHECK8-NEXT: store double* [[TMP37]], double** [[TMP54]], align 4 +// CHECK8-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to double** +// CHECK8-NEXT: store double* [[TMP37]], double** [[TMP56]], align 4 +// CHECK8-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP57]], align 4 +// CHECK8-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK8-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK8-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP61]], 0 +// CHECK8-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK8-NEXT: [[SUB12:%.*]] = sub nsw i32 [[DIV11]], 1 +// CHECK8-NEXT: store i32 [[SUB12]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP62]], 1 +// CHECK8-NEXT: [[TMP63:%.*]] = zext i32 [[ADD13]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) +// CHECK8-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 +// CHECK8-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] +// CHECK8: omp_offload.failed14: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408(i32 [[TMP34]], double* [[TMP35]], double* [[TMP36]], double* [[TMP37]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT15]] +// CHECK8: omp_offload.cont15: +// CHECK8-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK8-NEXT: store i32 [[TMP66]], i32* [[CH_CASTED]], align 4 +// CHECK8-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH_CASTED]], align 4 +// CHECK8-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP68]], i32* [[N_CASTED16]], align 4 +// CHECK8-NEXT: [[TMP69:%.*]] = load i32, i32* [[N_CASTED16]], align 4 +// CHECK8-NEXT: [[TMP70:%.*]] = load double*, double** [[A]], align 4 +// CHECK8-NEXT: [[TMP71:%.*]] = load double*, double** [[B]], align 4 +// CHECK8-NEXT: [[TMP72:%.*]] = load double*, double** [[C]], align 4 +// CHECK8-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK8-NEXT: store i32 [[TMP67]], i32* [[TMP74]], align 4 +// CHECK8-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK8-NEXT: store i32 [[TMP67]], i32* [[TMP76]], align 4 +// CHECK8-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK8-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK8-NEXT: store i32 [[TMP69]], i32* [[TMP79]], align 4 +// CHECK8-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK8-NEXT: store i32 [[TMP69]], i32* [[TMP81]], align 4 +// CHECK8-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK8-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to double** +// CHECK8-NEXT: store double* [[TMP70]], double** [[TMP84]], align 4 +// CHECK8-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to double** +// CHECK8-NEXT: store double* [[TMP70]], double** [[TMP86]], align 4 +// CHECK8-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP87]], align 4 +// CHECK8-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** +// CHECK8-NEXT: store double* [[TMP71]], double** [[TMP89]], align 4 +// CHECK8-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to double** +// CHECK8-NEXT: store double* [[TMP71]], double** [[TMP91]], align 4 +// CHECK8-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP92]], align 4 +// CHECK8-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** +// CHECK8-NEXT: store double* [[TMP72]], double** [[TMP94]], align 4 +// CHECK8-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to double** +// CHECK8-NEXT: store double* [[TMP72]], double** [[TMP96]], align 4 +// CHECK8-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP97]], align 4 +// CHECK8-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK8-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK8-NEXT: [[SUB23:%.*]] = sub nsw i32 [[TMP101]], 0 +// CHECK8-NEXT: [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1 +// CHECK8-NEXT: [[SUB25:%.*]] = sub nsw i32 [[DIV24]], 1 +// CHECK8-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK8-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK8-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP102]], 1 +// CHECK8-NEXT: [[TMP103:%.*]] = zext i32 [[ADD26]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) +// CHECK8-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 +// CHECK8-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] +// CHECK8: omp_offload.failed27: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447(i32 [[TMP67]], i32 [[TMP69]], double* [[TMP70]], double* [[TMP71]], double* [[TMP72]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT28]] +// CHECK8: omp_offload.cont28: +// CHECK8-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP106]], i32* [[N_CASTED29]], align 4 +// CHECK8-NEXT: [[TMP107:%.*]] = load i32, i32* [[N_CASTED29]], align 4 +// CHECK8-NEXT: [[TMP108:%.*]] = load double*, double** [[A]], align 4 +// CHECK8-NEXT: [[TMP109:%.*]] = load double*, double** [[B]], align 4 +// CHECK8-NEXT: [[TMP110:%.*]] = load double*, double** [[C]], align 4 +// CHECK8-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* +// CHECK8-NEXT: store i32 [[TMP107]], i32* [[TMP112]], align 4 +// CHECK8-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* +// CHECK8-NEXT: store i32 [[TMP107]], i32* [[TMP114]], align 4 +// CHECK8-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP115]], align 4 +// CHECK8-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to double** +// CHECK8-NEXT: store double* [[TMP108]], double** [[TMP117]], align 4 +// CHECK8-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to double** +// CHECK8-NEXT: store double* [[TMP108]], double** [[TMP119]], align 4 +// CHECK8-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP120]], align 4 +// CHECK8-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to double** +// CHECK8-NEXT: store double* [[TMP109]], double** [[TMP122]], align 4 +// CHECK8-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** +// CHECK8-NEXT: store double* [[TMP109]], double** [[TMP124]], align 4 +// CHECK8-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP125]], align 4 +// CHECK8-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** +// CHECK8-NEXT: store double* [[TMP110]], double** [[TMP127]], align 4 +// CHECK8-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** +// CHECK8-NEXT: store double* [[TMP110]], double** [[TMP129]], align 4 +// CHECK8-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP130]], align 4 +// CHECK8-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_34]], align 4 +// CHECK8-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_34]], align 4 +// CHECK8-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP134]], 0 +// CHECK8-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 +// CHECK8-NEXT: [[SUB38:%.*]] = sub nsw i32 [[DIV37]], 1 +// CHECK8-NEXT: store i32 [[SUB38]], i32* [[DOTCAPTURE_EXPR_35]], align 4 +// CHECK8-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_35]], align 4 +// CHECK8-NEXT: [[ADD39:%.*]] = add nsw i32 [[TMP135]], 1 +// CHECK8-NEXT: [[TMP136:%.*]] = zext i32 [[ADD39]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) +// CHECK8-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 +// CHECK8-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED40:%.*]], label [[OMP_OFFLOAD_CONT41:%.*]] +// CHECK8: omp_offload.failed40: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478(i32 [[TMP107]], double* [[TMP108]], double* [[TMP109]], double* [[TMP110]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT41]] +// CHECK8: omp_offload.cont41: +// CHECK8-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK8-NEXT: store i32 [[TMP139]], i32* [[CH_CASTED42]], align 4 +// CHECK8-NEXT: [[TMP140:%.*]] = load i32, i32* [[CH_CASTED42]], align 4 +// CHECK8-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP141]], i32* [[N_CASTED43]], align 4 +// CHECK8-NEXT: [[TMP142:%.*]] = load i32, i32* [[N_CASTED43]], align 4 +// CHECK8-NEXT: [[TMP143:%.*]] = load double*, double** [[A]], align 4 +// CHECK8-NEXT: [[TMP144:%.*]] = load double*, double** [[B]], align 4 +// CHECK8-NEXT: [[TMP145:%.*]] = load double*, double** [[C]], align 4 +// CHECK8-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* +// CHECK8-NEXT: store i32 [[TMP140]], i32* [[TMP147]], align 4 +// CHECK8-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* +// CHECK8-NEXT: store i32 [[TMP140]], i32* [[TMP149]], align 4 +// CHECK8-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP150]], align 4 +// CHECK8-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i32* +// CHECK8-NEXT: store i32 [[TMP142]], i32* [[TMP152]], align 4 +// CHECK8-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i32* +// CHECK8-NEXT: store i32 [[TMP142]], i32* [[TMP154]], align 4 +// CHECK8-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP155]], align 4 +// CHECK8-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to double** +// CHECK8-NEXT: store double* [[TMP143]], double** [[TMP157]], align 4 +// CHECK8-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to double** +// CHECK8-NEXT: store double* [[TMP143]], double** [[TMP159]], align 4 +// CHECK8-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP160]], align 4 +// CHECK8-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to double** +// CHECK8-NEXT: store double* [[TMP144]], double** [[TMP162]], align 4 +// CHECK8-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to double** +// CHECK8-NEXT: store double* [[TMP144]], double** [[TMP164]], align 4 +// CHECK8-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP165]], align 4 +// CHECK8-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to double** +// CHECK8-NEXT: store double* [[TMP145]], double** [[TMP167]], align 4 +// CHECK8-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to double** +// CHECK8-NEXT: store double* [[TMP145]], double** [[TMP169]], align 4 +// CHECK8-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP170]], align 4 +// CHECK8-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_48]], align 4 +// CHECK8-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_48]], align 4 +// CHECK8-NEXT: [[SUB50:%.*]] = sub nsw i32 [[TMP174]], 0 +// CHECK8-NEXT: [[DIV51:%.*]] = sdiv i32 [[SUB50]], 1 +// CHECK8-NEXT: [[SUB52:%.*]] = sub nsw i32 [[DIV51]], 1 +// CHECK8-NEXT: store i32 [[SUB52]], i32* [[DOTCAPTURE_EXPR_49]], align 4 +// CHECK8-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_49]], align 4 +// CHECK8-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP175]], 1 +// CHECK8-NEXT: [[TMP176:%.*]] = zext i32 [[ADD53]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) +// CHECK8-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 +// CHECK8-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED54:%.*]], label [[OMP_OFFLOAD_CONT55:%.*]] +// CHECK8: omp_offload.failed54: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506(i32 [[TMP140]], i32 [[TMP142]], double* [[TMP143]], double* [[TMP144]], double* [[TMP145]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT55]] +// CHECK8: omp_offload.cont55: +// CHECK8-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP179]], i32* [[N_CASTED56]], align 4 +// CHECK8-NEXT: [[TMP180:%.*]] = load i32, i32* [[N_CASTED56]], align 4 +// CHECK8-NEXT: [[TMP181:%.*]] = load double*, double** [[A]], align 4 +// CHECK8-NEXT: [[TMP182:%.*]] = load double*, double** [[B]], align 4 +// CHECK8-NEXT: [[TMP183:%.*]] = load double*, double** [[C]], align 4 +// CHECK8-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i32* +// CHECK8-NEXT: store i32 [[TMP180]], i32* [[TMP185]], align 4 +// CHECK8-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i32* +// CHECK8-NEXT: store i32 [[TMP180]], i32* [[TMP187]], align 4 +// CHECK8-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP188]], align 4 +// CHECK8-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to double** +// CHECK8-NEXT: store double* [[TMP181]], double** [[TMP190]], align 4 +// CHECK8-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to double** +// CHECK8-NEXT: store double* [[TMP181]], double** [[TMP192]], align 4 +// CHECK8-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP193]], align 4 +// CHECK8-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to double** +// CHECK8-NEXT: store double* [[TMP182]], double** [[TMP195]], align 4 +// CHECK8-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to double** +// CHECK8-NEXT: store double* [[TMP182]], double** [[TMP197]], align 4 +// CHECK8-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP198]], align 4 +// CHECK8-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to double** +// CHECK8-NEXT: store double* [[TMP183]], double** [[TMP200]], align 4 +// CHECK8-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to double** +// CHECK8-NEXT: store double* [[TMP183]], double** [[TMP202]], align 4 +// CHECK8-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP203]], align 4 +// CHECK8-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK8-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK8-NEXT: [[SUB63:%.*]] = sub nsw i32 [[TMP207]], 0 +// CHECK8-NEXT: [[DIV64:%.*]] = sdiv i32 [[SUB63]], 1 +// CHECK8-NEXT: [[SUB65:%.*]] = sub nsw i32 [[DIV64]], 1 +// CHECK8-NEXT: store i32 [[SUB65]], i32* [[DOTCAPTURE_EXPR_62]], align 4 +// CHECK8-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_62]], align 4 +// CHECK8-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP208]], 1 +// CHECK8-NEXT: [[TMP209:%.*]] = zext i32 [[ADD66]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) +// CHECK8-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 +// CHECK8-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED67:%.*]], label [[OMP_OFFLOAD_CONT68:%.*]] +// CHECK8: omp_offload.failed67: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536(i32 [[TMP180]], double* [[TMP181]], double* [[TMP182]], double* [[TMP183]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT68]] +// CHECK8: omp_offload.cont68: +// CHECK8-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK8-NEXT: store i32 [[TMP212]], i32* [[CH_CASTED69]], align 4 +// CHECK8-NEXT: [[TMP213:%.*]] = load i32, i32* [[CH_CASTED69]], align 4 +// CHECK8-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP214]], i32* [[N_CASTED70]], align 4 +// CHECK8-NEXT: [[TMP215:%.*]] = load i32, i32* [[N_CASTED70]], align 4 +// CHECK8-NEXT: [[TMP216:%.*]] = load double*, double** [[A]], align 4 +// CHECK8-NEXT: [[TMP217:%.*]] = load double*, double** [[B]], align 4 +// CHECK8-NEXT: [[TMP218:%.*]] = load double*, double** [[C]], align 4 +// CHECK8-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i32* +// CHECK8-NEXT: store i32 [[TMP213]], i32* [[TMP220]], align 4 +// CHECK8-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i32* +// CHECK8-NEXT: store i32 [[TMP213]], i32* [[TMP222]], align 4 +// CHECK8-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP223]], align 4 +// CHECK8-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i32* +// CHECK8-NEXT: store i32 [[TMP215]], i32* [[TMP225]], align 4 +// CHECK8-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i32* +// CHECK8-NEXT: store i32 [[TMP215]], i32* [[TMP227]], align 4 +// CHECK8-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP228]], align 4 +// CHECK8-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to double** +// CHECK8-NEXT: store double* [[TMP216]], double** [[TMP230]], align 4 +// CHECK8-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to double** +// CHECK8-NEXT: store double* [[TMP216]], double** [[TMP232]], align 4 +// CHECK8-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP233]], align 4 +// CHECK8-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to double** +// CHECK8-NEXT: store double* [[TMP217]], double** [[TMP235]], align 4 +// CHECK8-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to double** +// CHECK8-NEXT: store double* [[TMP217]], double** [[TMP237]], align 4 +// CHECK8-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP238]], align 4 +// CHECK8-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to double** +// CHECK8-NEXT: store double* [[TMP218]], double** [[TMP240]], align 4 +// CHECK8-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to double** +// CHECK8-NEXT: store double* [[TMP218]], double** [[TMP242]], align 4 +// CHECK8-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP243]], align 4 +// CHECK8-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_75]], align 4 +// CHECK8-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_75]], align 4 +// CHECK8-NEXT: [[SUB77:%.*]] = sub nsw i32 [[TMP247]], 0 +// CHECK8-NEXT: [[DIV78:%.*]] = sdiv i32 [[SUB77]], 1 +// CHECK8-NEXT: [[SUB79:%.*]] = sub nsw i32 [[DIV78]], 1 +// CHECK8-NEXT: store i32 [[SUB79]], i32* [[DOTCAPTURE_EXPR_76]], align 4 +// CHECK8-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_76]], align 4 +// CHECK8-NEXT: [[ADD80:%.*]] = add nsw i32 [[TMP248]], 1 +// CHECK8-NEXT: [[TMP249:%.*]] = zext i32 [[ADD80]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) +// CHECK8-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.24, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 +// CHECK8-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED81:%.*]], label [[OMP_OFFLOAD_CONT82:%.*]] +// CHECK8: omp_offload.failed81: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i32 [[TMP213]], i32 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT82]] +// CHECK8: omp_offload.cont82: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: ret i32 [[CALL]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 +// CHECK8-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] +// CHECK8-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] +// CHECK8-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] +// CHECK8-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 +// CHECK8-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] +// CHECK8-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] +// CHECK8-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] +// CHECK8-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 +// CHECK8-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] +// CHECK8-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK8: cond.true10: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END12:%.*]] +// CHECK8: cond.false11: +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END12]] +// CHECK8: cond.end12: +// CHECK8-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE10]] ], [ [[TMP30]], [[COND_FALSE11]] ] +// CHECK8-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] +// CHECK8-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] +// CHECK8-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] +// CHECK8-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 +// CHECK8-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] +// CHECK8-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] +// CHECK8-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] +// CHECK8-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 +// CHECK8-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp ugt i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] +// CHECK8-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] +// CHECK8-NEXT: [[TMP28:%.*]] = load double, double* [[ARRAYIDX8]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = fadd double [[TMP25]], [[TMP28]] +// CHECK8-NEXT: [[TMP29:%.*]] = load double*, double** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP29]], i32 [[TMP30]] +// CHECK8-NEXT: store double [[ADD9]], double* [[ARRAYIDX10]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK8-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] +// CHECK8-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] +// CHECK8-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 +// CHECK8-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..19 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK8-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[TMP21:%.*]] = load double*, double** [[TMP2]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP21]], i32 [[TMP22]] +// CHECK8-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[TMP24:%.*]] = load double*, double** [[TMP3]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds double, double* [[TMP24]], i32 [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX5]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]] +// CHECK8-NEXT: [[TMP27:%.*]] = load double*, double** [[TMP1]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP27]], i32 [[TMP28]] +// CHECK8-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 +// CHECK8-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**, i32)* @.omp_outlined..23 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..23 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK8-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP22:%.*]] = load double*, double** [[TMP2]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP22]], i32 [[TMP23]] +// CHECK8-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP25:%.*]] = load double*, double** [[TMP3]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP25]], i32 [[TMP26]] +// CHECK8-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX6]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]] +// CHECK8-NEXT: [[TMP28:%.*]] = load double*, double** [[TMP1]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP28]], i32 [[TMP29]] +// CHECK8-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR3:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[B:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[C:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CH:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP7:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CH_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED16:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS17:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS18:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS19:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED29:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP33:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_34:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_35:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CH_CASTED42:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED43:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS44:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS45:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS46:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP47:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_48:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_49:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED56:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS57:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS58:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS59:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP60:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_62:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CH_CASTED69:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED70:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS71:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS72:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS73:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP74:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_76:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 10000, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 100, i32* [[CH]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32** +// CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32** +// CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32** +// CHECK8-NEXT: store i32* [[TMP3]], i32** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32** +// CHECK8-NEXT: store i32* [[TMP3]], i32** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK8-NEXT: store i32* [[TMP4]], i32** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32** +// CHECK8-NEXT: store i32* [[TMP4]], i32** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP30]]) +// CHECK8-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK8-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42(i32 [[TMP1]], i32* [[TMP2]], i32* [[TMP3]], i32* [[TMP4]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK8-NEXT: [[TMP36:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK8-NEXT: [[TMP37:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP39]], align 4 +// CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP41]], align 4 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32** +// CHECK8-NEXT: store i32* [[TMP35]], i32** [[TMP44]], align 4 +// CHECK8-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32** +// CHECK8-NEXT: store i32* [[TMP35]], i32** [[TMP46]], align 4 +// CHECK8-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP47]], align 4 +// CHECK8-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK8-NEXT: store i32* [[TMP36]], i32** [[TMP49]], align 4 +// CHECK8-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK8-NEXT: store i32* [[TMP36]], i32** [[TMP51]], align 4 +// CHECK8-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP52]], align 4 +// CHECK8-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32** +// CHECK8-NEXT: store i32* [[TMP37]], i32** [[TMP54]], align 4 +// CHECK8-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32** +// CHECK8-NEXT: store i32* [[TMP37]], i32** [[TMP56]], align 4 +// CHECK8-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP57]], align 4 +// CHECK8-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK8-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK8-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP61]], 0 +// CHECK8-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK8-NEXT: [[SUB12:%.*]] = sub nsw i32 [[DIV11]], 1 +// CHECK8-NEXT: store i32 [[SUB12]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP62]], 1 +// CHECK8-NEXT: [[TMP63:%.*]] = zext i32 [[ADD13]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) +// CHECK8-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.32, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.33, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 +// CHECK8-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] +// CHECK8: omp_offload.failed14: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51(i32 [[TMP34]], i32* [[TMP35]], i32* [[TMP36]], i32* [[TMP37]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT15]] +// CHECK8: omp_offload.cont15: +// CHECK8-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK8-NEXT: store i32 [[TMP66]], i32* [[CH_CASTED]], align 4 +// CHECK8-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH_CASTED]], align 4 +// CHECK8-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP68]], i32* [[N_CASTED16]], align 4 +// CHECK8-NEXT: [[TMP69:%.*]] = load i32, i32* [[N_CASTED16]], align 4 +// CHECK8-NEXT: [[TMP70:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK8-NEXT: [[TMP71:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK8-NEXT: [[TMP72:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK8-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK8-NEXT: store i32 [[TMP67]], i32* [[TMP74]], align 4 +// CHECK8-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK8-NEXT: store i32 [[TMP67]], i32* [[TMP76]], align 4 +// CHECK8-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK8-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK8-NEXT: store i32 [[TMP69]], i32* [[TMP79]], align 4 +// CHECK8-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK8-NEXT: store i32 [[TMP69]], i32* [[TMP81]], align 4 +// CHECK8-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK8-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK8-NEXT: store i32* [[TMP70]], i32** [[TMP84]], align 4 +// CHECK8-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** +// CHECK8-NEXT: store i32* [[TMP70]], i32** [[TMP86]], align 4 +// CHECK8-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP87]], align 4 +// CHECK8-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK8-NEXT: store i32* [[TMP71]], i32** [[TMP89]], align 4 +// CHECK8-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** +// CHECK8-NEXT: store i32* [[TMP71]], i32** [[TMP91]], align 4 +// CHECK8-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP92]], align 4 +// CHECK8-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to i32** +// CHECK8-NEXT: store i32* [[TMP72]], i32** [[TMP94]], align 4 +// CHECK8-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32** +// CHECK8-NEXT: store i32* [[TMP72]], i32** [[TMP96]], align 4 +// CHECK8-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP97]], align 4 +// CHECK8-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK8-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 +// CHECK8-NEXT: [[SUB23:%.*]] = sub nsw i32 [[TMP101]], 0 +// CHECK8-NEXT: [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1 +// CHECK8-NEXT: [[SUB25:%.*]] = sub nsw i32 [[DIV24]], 1 +// CHECK8-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK8-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK8-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP102]], 1 +// CHECK8-NEXT: [[TMP103:%.*]] = zext i32 [[ADD26]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) +// CHECK8-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.36, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.37, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 +// CHECK8-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] +// CHECK8: omp_offload.failed27: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59(i32 [[TMP67]], i32 [[TMP69]], i32* [[TMP70]], i32* [[TMP71]], i32* [[TMP72]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT28]] +// CHECK8: omp_offload.cont28: +// CHECK8-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP106]], i32* [[N_CASTED29]], align 4 +// CHECK8-NEXT: [[TMP107:%.*]] = load i32, i32* [[N_CASTED29]], align 4 +// CHECK8-NEXT: [[TMP108:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK8-NEXT: [[TMP109:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK8-NEXT: [[TMP110:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK8-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* +// CHECK8-NEXT: store i32 [[TMP107]], i32* [[TMP112]], align 4 +// CHECK8-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* +// CHECK8-NEXT: store i32 [[TMP107]], i32* [[TMP114]], align 4 +// CHECK8-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP115]], align 4 +// CHECK8-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** +// CHECK8-NEXT: store i32* [[TMP108]], i32** [[TMP117]], align 4 +// CHECK8-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** +// CHECK8-NEXT: store i32* [[TMP108]], i32** [[TMP119]], align 4 +// CHECK8-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP120]], align 4 +// CHECK8-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** +// CHECK8-NEXT: store i32* [[TMP109]], i32** [[TMP122]], align 4 +// CHECK8-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32** +// CHECK8-NEXT: store i32* [[TMP109]], i32** [[TMP124]], align 4 +// CHECK8-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP125]], align 4 +// CHECK8-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32** +// CHECK8-NEXT: store i32* [[TMP110]], i32** [[TMP127]], align 4 +// CHECK8-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32** +// CHECK8-NEXT: store i32* [[TMP110]], i32** [[TMP129]], align 4 +// CHECK8-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP130]], align 4 +// CHECK8-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_34]], align 4 +// CHECK8-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_34]], align 4 +// CHECK8-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP134]], 0 +// CHECK8-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 +// CHECK8-NEXT: [[SUB38:%.*]] = sub nsw i32 [[DIV37]], 1 +// CHECK8-NEXT: store i32 [[SUB38]], i32* [[DOTCAPTURE_EXPR_35]], align 4 +// CHECK8-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_35]], align 4 +// CHECK8-NEXT: [[ADD39:%.*]] = add nsw i32 [[TMP135]], 1 +// CHECK8-NEXT: [[TMP136:%.*]] = zext i32 [[ADD39]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) +// CHECK8-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.40, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.41, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 +// CHECK8-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED40:%.*]], label [[OMP_OFFLOAD_CONT41:%.*]] +// CHECK8: omp_offload.failed40: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67(i32 [[TMP107]], i32* [[TMP108]], i32* [[TMP109]], i32* [[TMP110]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT41]] +// CHECK8: omp_offload.cont41: +// CHECK8-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK8-NEXT: store i32 [[TMP139]], i32* [[CH_CASTED42]], align 4 +// CHECK8-NEXT: [[TMP140:%.*]] = load i32, i32* [[CH_CASTED42]], align 4 +// CHECK8-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP141]], i32* [[N_CASTED43]], align 4 +// CHECK8-NEXT: [[TMP142:%.*]] = load i32, i32* [[N_CASTED43]], align 4 +// CHECK8-NEXT: [[TMP143:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK8-NEXT: [[TMP144:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK8-NEXT: [[TMP145:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK8-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* +// CHECK8-NEXT: store i32 [[TMP140]], i32* [[TMP147]], align 4 +// CHECK8-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* +// CHECK8-NEXT: store i32 [[TMP140]], i32* [[TMP149]], align 4 +// CHECK8-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP150]], align 4 +// CHECK8-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i32* +// CHECK8-NEXT: store i32 [[TMP142]], i32* [[TMP152]], align 4 +// CHECK8-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i32* +// CHECK8-NEXT: store i32 [[TMP142]], i32* [[TMP154]], align 4 +// CHECK8-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP155]], align 4 +// CHECK8-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** +// CHECK8-NEXT: store i32* [[TMP143]], i32** [[TMP157]], align 4 +// CHECK8-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** +// CHECK8-NEXT: store i32* [[TMP143]], i32** [[TMP159]], align 4 +// CHECK8-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP160]], align 4 +// CHECK8-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32** +// CHECK8-NEXT: store i32* [[TMP144]], i32** [[TMP162]], align 4 +// CHECK8-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32** +// CHECK8-NEXT: store i32* [[TMP144]], i32** [[TMP164]], align 4 +// CHECK8-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP165]], align 4 +// CHECK8-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to i32** +// CHECK8-NEXT: store i32* [[TMP145]], i32** [[TMP167]], align 4 +// CHECK8-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to i32** +// CHECK8-NEXT: store i32* [[TMP145]], i32** [[TMP169]], align 4 +// CHECK8-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP170]], align 4 +// CHECK8-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_48]], align 4 +// CHECK8-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_48]], align 4 +// CHECK8-NEXT: [[SUB50:%.*]] = sub nsw i32 [[TMP174]], 0 +// CHECK8-NEXT: [[DIV51:%.*]] = sdiv i32 [[SUB50]], 1 +// CHECK8-NEXT: [[SUB52:%.*]] = sub nsw i32 [[DIV51]], 1 +// CHECK8-NEXT: store i32 [[SUB52]], i32* [[DOTCAPTURE_EXPR_49]], align 4 +// CHECK8-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_49]], align 4 +// CHECK8-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP175]], 1 +// CHECK8-NEXT: [[TMP176:%.*]] = zext i32 [[ADD53]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) +// CHECK8-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.44, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.45, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 +// CHECK8-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED54:%.*]], label [[OMP_OFFLOAD_CONT55:%.*]] +// CHECK8: omp_offload.failed54: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32 [[TMP140]], i32 [[TMP142]], i32* [[TMP143]], i32* [[TMP144]], i32* [[TMP145]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT55]] +// CHECK8: omp_offload.cont55: +// CHECK8-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP179]], i32* [[N_CASTED56]], align 4 +// CHECK8-NEXT: [[TMP180:%.*]] = load i32, i32* [[N_CASTED56]], align 4 +// CHECK8-NEXT: [[TMP181:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK8-NEXT: [[TMP182:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK8-NEXT: [[TMP183:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK8-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i32* +// CHECK8-NEXT: store i32 [[TMP180]], i32* [[TMP185]], align 4 +// CHECK8-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i32* +// CHECK8-NEXT: store i32 [[TMP180]], i32* [[TMP187]], align 4 +// CHECK8-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP188]], align 4 +// CHECK8-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to i32** +// CHECK8-NEXT: store i32* [[TMP181]], i32** [[TMP190]], align 4 +// CHECK8-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to i32** +// CHECK8-NEXT: store i32* [[TMP181]], i32** [[TMP192]], align 4 +// CHECK8-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP193]], align 4 +// CHECK8-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to i32** +// CHECK8-NEXT: store i32* [[TMP182]], i32** [[TMP195]], align 4 +// CHECK8-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to i32** +// CHECK8-NEXT: store i32* [[TMP182]], i32** [[TMP197]], align 4 +// CHECK8-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP198]], align 4 +// CHECK8-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to i32** +// CHECK8-NEXT: store i32* [[TMP183]], i32** [[TMP200]], align 4 +// CHECK8-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to i32** +// CHECK8-NEXT: store i32* [[TMP183]], i32** [[TMP202]], align 4 +// CHECK8-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP203]], align 4 +// CHECK8-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK8-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK8-NEXT: [[SUB63:%.*]] = sub nsw i32 [[TMP207]], 0 +// CHECK8-NEXT: [[DIV64:%.*]] = sdiv i32 [[SUB63]], 1 +// CHECK8-NEXT: [[SUB65:%.*]] = sub nsw i32 [[DIV64]], 1 +// CHECK8-NEXT: store i32 [[SUB65]], i32* [[DOTCAPTURE_EXPR_62]], align 4 +// CHECK8-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_62]], align 4 +// CHECK8-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP208]], 1 +// CHECK8-NEXT: [[TMP209:%.*]] = zext i32 [[ADD66]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) +// CHECK8-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.48, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.49, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 +// CHECK8-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED67:%.*]], label [[OMP_OFFLOAD_CONT68:%.*]] +// CHECK8: omp_offload.failed67: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83(i32 [[TMP180]], i32* [[TMP181]], i32* [[TMP182]], i32* [[TMP183]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT68]] +// CHECK8: omp_offload.cont68: +// CHECK8-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 +// CHECK8-NEXT: store i32 [[TMP212]], i32* [[CH_CASTED69]], align 4 +// CHECK8-NEXT: [[TMP213:%.*]] = load i32, i32* [[CH_CASTED69]], align 4 +// CHECK8-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP214]], i32* [[N_CASTED70]], align 4 +// CHECK8-NEXT: [[TMP215:%.*]] = load i32, i32* [[N_CASTED70]], align 4 +// CHECK8-NEXT: [[TMP216:%.*]] = load i32*, i32** [[A]], align 4 +// CHECK8-NEXT: [[TMP217:%.*]] = load i32*, i32** [[B]], align 4 +// CHECK8-NEXT: [[TMP218:%.*]] = load i32*, i32** [[C]], align 4 +// CHECK8-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i32* +// CHECK8-NEXT: store i32 [[TMP213]], i32* [[TMP220]], align 4 +// CHECK8-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i32* +// CHECK8-NEXT: store i32 [[TMP213]], i32* [[TMP222]], align 4 +// CHECK8-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP223]], align 4 +// CHECK8-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i32* +// CHECK8-NEXT: store i32 [[TMP215]], i32* [[TMP225]], align 4 +// CHECK8-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i32* +// CHECK8-NEXT: store i32 [[TMP215]], i32* [[TMP227]], align 4 +// CHECK8-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP228]], align 4 +// CHECK8-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to i32** +// CHECK8-NEXT: store i32* [[TMP216]], i32** [[TMP230]], align 4 +// CHECK8-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to i32** +// CHECK8-NEXT: store i32* [[TMP216]], i32** [[TMP232]], align 4 +// CHECK8-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP233]], align 4 +// CHECK8-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to i32** +// CHECK8-NEXT: store i32* [[TMP217]], i32** [[TMP235]], align 4 +// CHECK8-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to i32** +// CHECK8-NEXT: store i32* [[TMP217]], i32** [[TMP237]], align 4 +// CHECK8-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP238]], align 4 +// CHECK8-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to i32** +// CHECK8-NEXT: store i32* [[TMP218]], i32** [[TMP240]], align 4 +// CHECK8-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to i32** +// CHECK8-NEXT: store i32* [[TMP218]], i32** [[TMP242]], align 4 +// CHECK8-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP243]], align 4 +// CHECK8-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_75]], align 4 +// CHECK8-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_75]], align 4 +// CHECK8-NEXT: [[SUB77:%.*]] = sub nsw i32 [[TMP247]], 0 +// CHECK8-NEXT: [[DIV78:%.*]] = sdiv i32 [[SUB77]], 1 +// CHECK8-NEXT: [[SUB79:%.*]] = sub nsw i32 [[DIV78]], 1 +// CHECK8-NEXT: store i32 [[SUB79]], i32* [[DOTCAPTURE_EXPR_76]], align 4 +// CHECK8-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_76]], align 4 +// CHECK8-NEXT: [[ADD80:%.*]] = add nsw i32 [[TMP248]], 1 +// CHECK8-NEXT: [[TMP249:%.*]] = zext i32 [[ADD80]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) +// CHECK8-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.52, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.53, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 +// CHECK8-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED81:%.*]], label [[OMP_OFFLOAD_CONT82:%.*]] +// CHECK8: omp_offload.failed81: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91(i32 [[TMP213]], i32 [[TMP215]], i32* [[TMP216]], i32* [[TMP217]], i32* [[TMP218]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT82]] +// CHECK8: omp_offload.cont82: // CHECK8-NEXT: ret i32 0 // // -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[B:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[C:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[CH_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED32:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[CH_CASTED46:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED48:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS50:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS51:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS52:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED62:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS64:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS65:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS66:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP67:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_68:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_69:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[CH_CASTED76:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED78:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS80:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS81:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS82:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP83:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_84:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_85:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double*, double** [[A]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double*, double** [[B]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load double*, double** [[C]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to double** -// CHECK9-NEXT: store double* [[TMP2]], double** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK9-NEXT: store double* [[TMP2]], double** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double** -// CHECK9-NEXT: store double* [[TMP3]], double** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to double** -// CHECK9-NEXT: store double* [[TMP3]], double** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double** -// CHECK9-NEXT: store double* [[TMP4]], double** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double** -// CHECK9-NEXT: store double* [[TMP4]], double** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369(i64 [[TMP1]], double* [[TMP2]], double* [[TMP3]], double* [[TMP4]]) #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = load double*, double** [[A]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = load double*, double** [[B]], align 8 -// CHECK9-NEXT: [[TMP37:%.*]] = load double*, double** [[C]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP41]], align 8 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP42]], align 8 -// CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to double** -// CHECK9-NEXT: store double* [[TMP35]], double** [[TMP44]], align 8 -// CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to double** -// CHECK9-NEXT: store double* [[TMP35]], double** [[TMP46]], align 8 -// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** -// CHECK9-NEXT: store double* [[TMP36]], double** [[TMP49]], align 8 -// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** -// CHECK9-NEXT: store double* [[TMP36]], double** [[TMP51]], align 8 -// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP52]], align 8 -// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** -// CHECK9-NEXT: store double* [[TMP37]], double** [[TMP54]], align 8 -// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to double** -// CHECK9-NEXT: store double* [[TMP37]], double** [[TMP56]], align 8 -// CHECK9-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP57]], align 8 -// CHECK9-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK9-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP61]], 0 -// CHECK9-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK9-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK9-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP62]], 1 -// CHECK9-NEXT: [[TMP63:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) -// CHECK9-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 -// CHECK9-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK9: omp_offload.failed15: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408(i64 [[TMP34]], double* [[TMP35]], double* [[TMP36]], double* [[TMP37]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK9: omp_offload.cont16: -// CHECK9-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[CH_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP66]], i32* [[CONV17]], align 4 -// CHECK9-NEXT: [[TMP67:%.*]] = load i64, i64* [[CH_CASTED]], align 8 -// CHECK9-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* -// CHECK9-NEXT: store i32 [[TMP68]], i32* [[CONV19]], align 4 -// CHECK9-NEXT: [[TMP69:%.*]] = load i64, i64* [[N_CASTED18]], align 8 -// CHECK9-NEXT: [[TMP70:%.*]] = load double*, double** [[A]], align 8 -// CHECK9-NEXT: [[TMP71:%.*]] = load double*, double** [[B]], align 8 -// CHECK9-NEXT: [[TMP72:%.*]] = load double*, double** [[C]], align 8 -// CHECK9-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* -// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP74]], align 8 -// CHECK9-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP76]], align 8 -// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP77]], align 8 -// CHECK9-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* -// CHECK9-NEXT: store i64 [[TMP69]], i64* [[TMP79]], align 8 -// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK9-NEXT: store i64 [[TMP69]], i64* [[TMP81]], align 8 -// CHECK9-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP82]], align 8 -// CHECK9-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to double** -// CHECK9-NEXT: store double* [[TMP70]], double** [[TMP84]], align 8 -// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to double** -// CHECK9-NEXT: store double* [[TMP70]], double** [[TMP86]], align 8 -// CHECK9-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP87]], align 8 -// CHECK9-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** -// CHECK9-NEXT: store double* [[TMP71]], double** [[TMP89]], align 8 -// CHECK9-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to double** -// CHECK9-NEXT: store double* [[TMP71]], double** [[TMP91]], align 8 -// CHECK9-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK9-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** -// CHECK9-NEXT: store double* [[TMP72]], double** [[TMP94]], align 8 -// CHECK9-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to double** -// CHECK9-NEXT: store double* [[TMP72]], double** [[TMP96]], align 8 -// CHECK9-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP97]], align 8 -// CHECK9-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK9-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK9-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP101]], 0 -// CHECK9-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// CHECK9-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 -// CHECK9-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK9-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK9-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP102]], 1 -// CHECK9-NEXT: [[TMP103:%.*]] = zext i32 [[ADD29]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) -// CHECK9-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 -// CHECK9-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK9: omp_offload.failed30: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447(i64 [[TMP67]], i64 [[TMP69]], double* [[TMP70]], double* [[TMP71]], double* [[TMP72]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK9: omp_offload.cont31: -// CHECK9-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV33:%.*]] = bitcast i64* [[N_CASTED32]] to i32* -// CHECK9-NEXT: store i32 [[TMP106]], i32* [[CONV33]], align 4 -// CHECK9-NEXT: [[TMP107:%.*]] = load i64, i64* [[N_CASTED32]], align 8 -// CHECK9-NEXT: [[TMP108:%.*]] = load double*, double** [[A]], align 8 -// CHECK9-NEXT: [[TMP109:%.*]] = load double*, double** [[B]], align 8 -// CHECK9-NEXT: [[TMP110:%.*]] = load double*, double** [[C]], align 8 -// CHECK9-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* -// CHECK9-NEXT: store i64 [[TMP107]], i64* [[TMP112]], align 8 -// CHECK9-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* -// CHECK9-NEXT: store i64 [[TMP107]], i64* [[TMP114]], align 8 -// CHECK9-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP115]], align 8 -// CHECK9-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to double** -// CHECK9-NEXT: store double* [[TMP108]], double** [[TMP117]], align 8 -// CHECK9-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to double** -// CHECK9-NEXT: store double* [[TMP108]], double** [[TMP119]], align 8 -// CHECK9-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP120]], align 8 -// CHECK9-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to double** -// CHECK9-NEXT: store double* [[TMP109]], double** [[TMP122]], align 8 -// CHECK9-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** -// CHECK9-NEXT: store double* [[TMP109]], double** [[TMP124]], align 8 -// CHECK9-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP125]], align 8 -// CHECK9-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** -// CHECK9-NEXT: store double* [[TMP110]], double** [[TMP127]], align 8 -// CHECK9-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** -// CHECK9-NEXT: store double* [[TMP110]], double** [[TMP129]], align 8 -// CHECK9-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP130]], align 8 -// CHECK9-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK9-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK9-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP134]], 0 -// CHECK9-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 -// CHECK9-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 -// CHECK9-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK9-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK9-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP135]], 1 -// CHECK9-NEXT: [[TMP136:%.*]] = zext i32 [[ADD43]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) -// CHECK9-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 -// CHECK9-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] -// CHECK9: omp_offload.failed44: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478(i64 [[TMP107]], double* [[TMP108]], double* [[TMP109]], double* [[TMP110]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT45]] -// CHECK9: omp_offload.cont45: -// CHECK9-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK9-NEXT: [[CONV47:%.*]] = bitcast i64* [[CH_CASTED46]] to i32* -// CHECK9-NEXT: store i32 [[TMP139]], i32* [[CONV47]], align 4 -// CHECK9-NEXT: [[TMP140:%.*]] = load i64, i64* [[CH_CASTED46]], align 8 -// CHECK9-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV49:%.*]] = bitcast i64* [[N_CASTED48]] to i32* -// CHECK9-NEXT: store i32 [[TMP141]], i32* [[CONV49]], align 4 -// CHECK9-NEXT: [[TMP142:%.*]] = load i64, i64* [[N_CASTED48]], align 8 -// CHECK9-NEXT: [[TMP143:%.*]] = load double*, double** [[A]], align 8 -// CHECK9-NEXT: [[TMP144:%.*]] = load double*, double** [[B]], align 8 -// CHECK9-NEXT: [[TMP145:%.*]] = load double*, double** [[C]], align 8 -// CHECK9-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* -// CHECK9-NEXT: store i64 [[TMP140]], i64* [[TMP147]], align 8 -// CHECK9-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* -// CHECK9-NEXT: store i64 [[TMP140]], i64* [[TMP149]], align 8 -// CHECK9-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP150]], align 8 -// CHECK9-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i64* -// CHECK9-NEXT: store i64 [[TMP142]], i64* [[TMP152]], align 8 -// CHECK9-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i64* -// CHECK9-NEXT: store i64 [[TMP142]], i64* [[TMP154]], align 8 -// CHECK9-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP155]], align 8 -// CHECK9-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to double** -// CHECK9-NEXT: store double* [[TMP143]], double** [[TMP157]], align 8 -// CHECK9-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to double** -// CHECK9-NEXT: store double* [[TMP143]], double** [[TMP159]], align 8 -// CHECK9-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP160]], align 8 -// CHECK9-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to double** -// CHECK9-NEXT: store double* [[TMP144]], double** [[TMP162]], align 8 -// CHECK9-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to double** -// CHECK9-NEXT: store double* [[TMP144]], double** [[TMP164]], align 8 -// CHECK9-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP165]], align 8 -// CHECK9-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to double** -// CHECK9-NEXT: store double* [[TMP145]], double** [[TMP167]], align 8 -// CHECK9-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to double** -// CHECK9-NEXT: store double* [[TMP145]], double** [[TMP169]], align 8 -// CHECK9-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP170]], align 8 -// CHECK9-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK9-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK9-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP174]], 0 -// CHECK9-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 -// CHECK9-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 -// CHECK9-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK9-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK9-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP175]], 1 -// CHECK9-NEXT: [[TMP176:%.*]] = zext i32 [[ADD59]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) -// CHECK9-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 -// CHECK9-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] -// CHECK9: omp_offload.failed60: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506(i64 [[TMP140]], i64 [[TMP142]], double* [[TMP143]], double* [[TMP144]], double* [[TMP145]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT61]] -// CHECK9: omp_offload.cont61: -// CHECK9-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV63:%.*]] = bitcast i64* [[N_CASTED62]] to i32* -// CHECK9-NEXT: store i32 [[TMP179]], i32* [[CONV63]], align 4 -// CHECK9-NEXT: [[TMP180:%.*]] = load i64, i64* [[N_CASTED62]], align 8 -// CHECK9-NEXT: [[TMP181:%.*]] = load double*, double** [[A]], align 8 -// CHECK9-NEXT: [[TMP182:%.*]] = load double*, double** [[B]], align 8 -// CHECK9-NEXT: [[TMP183:%.*]] = load double*, double** [[C]], align 8 -// CHECK9-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i64* -// CHECK9-NEXT: store i64 [[TMP180]], i64* [[TMP185]], align 8 -// CHECK9-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i64* -// CHECK9-NEXT: store i64 [[TMP180]], i64* [[TMP187]], align 8 -// CHECK9-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP188]], align 8 -// CHECK9-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to double** -// CHECK9-NEXT: store double* [[TMP181]], double** [[TMP190]], align 8 -// CHECK9-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to double** -// CHECK9-NEXT: store double* [[TMP181]], double** [[TMP192]], align 8 -// CHECK9-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP193]], align 8 -// CHECK9-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to double** -// CHECK9-NEXT: store double* [[TMP182]], double** [[TMP195]], align 8 -// CHECK9-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to double** -// CHECK9-NEXT: store double* [[TMP182]], double** [[TMP197]], align 8 -// CHECK9-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP198]], align 8 -// CHECK9-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to double** -// CHECK9-NEXT: store double* [[TMP183]], double** [[TMP200]], align 8 -// CHECK9-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to double** -// CHECK9-NEXT: store double* [[TMP183]], double** [[TMP202]], align 8 -// CHECK9-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP203]], align 8 -// CHECK9-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_68]], align 4 -// CHECK9-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_68]], align 4 -// CHECK9-NEXT: [[SUB70:%.*]] = sub nsw i32 [[TMP207]], 0 -// CHECK9-NEXT: [[DIV71:%.*]] = sdiv i32 [[SUB70]], 1 -// CHECK9-NEXT: [[SUB72:%.*]] = sub nsw i32 [[DIV71]], 1 -// CHECK9-NEXT: store i32 [[SUB72]], i32* [[DOTCAPTURE_EXPR_69]], align 4 -// CHECK9-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_69]], align 4 -// CHECK9-NEXT: [[ADD73:%.*]] = add nsw i32 [[TMP208]], 1 -// CHECK9-NEXT: [[TMP209:%.*]] = zext i32 [[ADD73]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) -// CHECK9-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 -// CHECK9-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED74:%.*]], label [[OMP_OFFLOAD_CONT75:%.*]] -// CHECK9: omp_offload.failed74: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536(i64 [[TMP180]], double* [[TMP181]], double* [[TMP182]], double* [[TMP183]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT75]] -// CHECK9: omp_offload.cont75: -// CHECK9-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK9-NEXT: [[CONV77:%.*]] = bitcast i64* [[CH_CASTED76]] to i32* -// CHECK9-NEXT: store i32 [[TMP212]], i32* [[CONV77]], align 4 -// CHECK9-NEXT: [[TMP213:%.*]] = load i64, i64* [[CH_CASTED76]], align 8 -// CHECK9-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV79:%.*]] = bitcast i64* [[N_CASTED78]] to i32* -// CHECK9-NEXT: store i32 [[TMP214]], i32* [[CONV79]], align 4 -// CHECK9-NEXT: [[TMP215:%.*]] = load i64, i64* [[N_CASTED78]], align 8 -// CHECK9-NEXT: [[TMP216:%.*]] = load double*, double** [[A]], align 8 -// CHECK9-NEXT: [[TMP217:%.*]] = load double*, double** [[B]], align 8 -// CHECK9-NEXT: [[TMP218:%.*]] = load double*, double** [[C]], align 8 -// CHECK9-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i64* -// CHECK9-NEXT: store i64 [[TMP213]], i64* [[TMP220]], align 8 -// CHECK9-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i64* -// CHECK9-NEXT: store i64 [[TMP213]], i64* [[TMP222]], align 8 -// CHECK9-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP223]], align 8 -// CHECK9-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i64* -// CHECK9-NEXT: store i64 [[TMP215]], i64* [[TMP225]], align 8 -// CHECK9-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i64* -// CHECK9-NEXT: store i64 [[TMP215]], i64* [[TMP227]], align 8 -// CHECK9-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP228]], align 8 -// CHECK9-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to double** -// CHECK9-NEXT: store double* [[TMP216]], double** [[TMP230]], align 8 -// CHECK9-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to double** -// CHECK9-NEXT: store double* [[TMP216]], double** [[TMP232]], align 8 -// CHECK9-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP233]], align 8 -// CHECK9-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to double** -// CHECK9-NEXT: store double* [[TMP217]], double** [[TMP235]], align 8 -// CHECK9-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to double** -// CHECK9-NEXT: store double* [[TMP217]], double** [[TMP237]], align 8 -// CHECK9-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP238]], align 8 -// CHECK9-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to double** -// CHECK9-NEXT: store double* [[TMP218]], double** [[TMP240]], align 8 -// CHECK9-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to double** -// CHECK9-NEXT: store double* [[TMP218]], double** [[TMP242]], align 8 -// CHECK9-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP243]], align 8 -// CHECK9-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_84]], align 4 -// CHECK9-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_84]], align 4 -// CHECK9-NEXT: [[SUB86:%.*]] = sub nsw i32 [[TMP247]], 0 -// CHECK9-NEXT: [[DIV87:%.*]] = sdiv i32 [[SUB86]], 1 -// CHECK9-NEXT: [[SUB88:%.*]] = sub nsw i32 [[DIV87]], 1 -// CHECK9-NEXT: store i32 [[SUB88]], i32* [[DOTCAPTURE_EXPR_85]], align 4 -// CHECK9-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_85]], align 4 -// CHECK9-NEXT: [[ADD89:%.*]] = add nsw i32 [[TMP248]], 1 -// CHECK9-NEXT: [[TMP249:%.*]] = zext i32 [[ADD89]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) -// CHECK9-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.24, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 -// CHECK9-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED90:%.*]], label [[OMP_OFFLOAD_CONT91:%.*]] -// CHECK9: omp_offload.failed90: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i64 [[TMP213]], i64 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT91]] -// CHECK9: omp_offload.cont91: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 -// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] -// CHECK9-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 -// CHECK9-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK9-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] -// CHECK9-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 -// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] -// CHECK9-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 -// CHECK9-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK9-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] -// CHECK9-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 -// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK9: cond.true10: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END12:%.*]] -// CHECK9: cond.false11: -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END12]] -// CHECK9: cond.end12: -// CHECK9-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE10]] ], [ [[TMP32]], [[COND_FALSE11]] ] -// CHECK9-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] -// CHECK9-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 -// CHECK9-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK9-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] -// CHECK9-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 -// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] -// CHECK9-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 -// CHECK9-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK9-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] -// CHECK9-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 -// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i64 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK9: omp.dispatch.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[CONV7]], [[TMP14]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CONV9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[CONV9]], [[COND_FALSE]] ] -// CHECK9-NEXT: [[CONV10:%.*]] = trunc i64 [[COND]] to i32 -// CHECK9-NEXT: store i32 [[CONV10]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK9: omp.dispatch.body: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK9-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM13]] -// CHECK9-NEXT: [[TMP28:%.*]] = load double, double* [[ARRAYIDX14]], align 8 -// CHECK9-NEXT: [[ADD15:%.*]] = fadd double [[TMP25]], [[TMP28]] -// CHECK9-NEXT: [[TMP29:%.*]] = load double*, double** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK9-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP30]] to i64 -// CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP29]], i64 [[IDXPROM16]] -// CHECK9-NEXT: store double [[ADD15]], double* [[ARRAYIDX17]], align 8 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK9-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK9: omp.dispatch.inc: -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] -// CHECK9-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] -// CHECK9-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK9: omp.dispatch.end: -// CHECK9-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 -// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK9: omp.dispatch.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK9: omp.dispatch.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP21:%.*]] = load double*, double** [[TMP2]], align 8, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP21]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX]], align 8, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP24:%.*]] = load double*, double** [[TMP3]], align 8, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP24]], i64 [[IDXPROM6]] -// CHECK9-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX7]], align 8, !llvm.access.group !18 -// CHECK9-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]] -// CHECK9-NEXT: [[TMP27:%.*]] = load double*, double** [[TMP1]], align 8, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP27]], i64 [[IDXPROM9]] -// CHECK9-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !18 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK9: omp.dispatch.inc: -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK9: omp.dispatch.end: -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 -// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**, i64)* @.omp_outlined..23 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i64 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK9: omp.dispatch.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK9: omp.dispatch.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[TMP22:%.*]] = load double*, double** [[TMP2]], align 8, !llvm.access.group !21 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP22]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX]], align 8, !llvm.access.group !21 -// CHECK9-NEXT: [[TMP25:%.*]] = load double*, double** [[TMP3]], align 8, !llvm.access.group !21 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds double, double* [[TMP25]], i64 [[IDXPROM8]] -// CHECK9-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX9]], align 8, !llvm.access.group !21 -// CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]] -// CHECK9-NEXT: [[TMP28:%.*]] = load double*, double** [[TMP1]], align 8, !llvm.access.group !21 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP28]], i64 [[IDXPROM11]] -// CHECK9-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !21 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK9: omp.dispatch.inc: -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK9: omp.dispatch.end: -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[C:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[CH_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED32:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[CH_CASTED46:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED48:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS50:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS51:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS52:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED62:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS64:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS65:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS66:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP67:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_68:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_69:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[CH_CASTED76:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED78:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS80:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS81:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS82:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP83:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_84:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_85:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32** -// CHECK9-NEXT: store i32* [[TMP2]], i32** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32** -// CHECK9-NEXT: store i32* [[TMP2]], i32** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32** -// CHECK9-NEXT: store i32* [[TMP3]], i32** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32** -// CHECK9-NEXT: store i32* [[TMP3]], i32** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK9-NEXT: store i32* [[TMP4]], i32** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32** -// CHECK9-NEXT: store i32* [[TMP4]], i32** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP30]]) -// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42(i64 [[TMP1]], i32* [[TMP2]], i32* [[TMP3]], i32* [[TMP4]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK9-NEXT: [[TMP37:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP41]], align 8 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP42]], align 8 -// CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32** -// CHECK9-NEXT: store i32* [[TMP35]], i32** [[TMP44]], align 8 -// CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32** -// CHECK9-NEXT: store i32* [[TMP35]], i32** [[TMP46]], align 8 -// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK9-NEXT: store i32* [[TMP36]], i32** [[TMP49]], align 8 -// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK9-NEXT: store i32* [[TMP36]], i32** [[TMP51]], align 8 -// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP52]], align 8 -// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32** -// CHECK9-NEXT: store i32* [[TMP37]], i32** [[TMP54]], align 8 -// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32** -// CHECK9-NEXT: store i32* [[TMP37]], i32** [[TMP56]], align 8 -// CHECK9-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP57]], align 8 -// CHECK9-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK9-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP61]], 0 -// CHECK9-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK9-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK9-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP62]], 1 -// CHECK9-NEXT: [[TMP63:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) -// CHECK9-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.32, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.33, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 -// CHECK9-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK9: omp_offload.failed15: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51(i64 [[TMP34]], i32* [[TMP35]], i32* [[TMP36]], i32* [[TMP37]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK9: omp_offload.cont16: -// CHECK9-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[CH_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP66]], i32* [[CONV17]], align 4 -// CHECK9-NEXT: [[TMP67:%.*]] = load i64, i64* [[CH_CASTED]], align 8 -// CHECK9-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* -// CHECK9-NEXT: store i32 [[TMP68]], i32* [[CONV19]], align 4 -// CHECK9-NEXT: [[TMP69:%.*]] = load i64, i64* [[N_CASTED18]], align 8 -// CHECK9-NEXT: [[TMP70:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK9-NEXT: [[TMP71:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK9-NEXT: [[TMP72:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK9-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* -// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP74]], align 8 -// CHECK9-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP76]], align 8 -// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP77]], align 8 -// CHECK9-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* -// CHECK9-NEXT: store i64 [[TMP69]], i64* [[TMP79]], align 8 -// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK9-NEXT: store i64 [[TMP69]], i64* [[TMP81]], align 8 -// CHECK9-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP82]], align 8 -// CHECK9-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK9-NEXT: store i32* [[TMP70]], i32** [[TMP84]], align 8 -// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** -// CHECK9-NEXT: store i32* [[TMP70]], i32** [[TMP86]], align 8 -// CHECK9-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP87]], align 8 -// CHECK9-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK9-NEXT: store i32* [[TMP71]], i32** [[TMP89]], align 8 -// CHECK9-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** -// CHECK9-NEXT: store i32* [[TMP71]], i32** [[TMP91]], align 8 -// CHECK9-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK9-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to i32** -// CHECK9-NEXT: store i32* [[TMP72]], i32** [[TMP94]], align 8 -// CHECK9-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32** -// CHECK9-NEXT: store i32* [[TMP72]], i32** [[TMP96]], align 8 -// CHECK9-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP97]], align 8 -// CHECK9-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK9-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK9-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP101]], 0 -// CHECK9-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// CHECK9-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 -// CHECK9-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK9-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK9-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP102]], 1 -// CHECK9-NEXT: [[TMP103:%.*]] = zext i32 [[ADD29]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) -// CHECK9-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.36, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.37, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 -// CHECK9-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK9: omp_offload.failed30: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59(i64 [[TMP67]], i64 [[TMP69]], i32* [[TMP70]], i32* [[TMP71]], i32* [[TMP72]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK9: omp_offload.cont31: -// CHECK9-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV33:%.*]] = bitcast i64* [[N_CASTED32]] to i32* -// CHECK9-NEXT: store i32 [[TMP106]], i32* [[CONV33]], align 4 -// CHECK9-NEXT: [[TMP107:%.*]] = load i64, i64* [[N_CASTED32]], align 8 -// CHECK9-NEXT: [[TMP108:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK9-NEXT: [[TMP109:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK9-NEXT: [[TMP110:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK9-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* -// CHECK9-NEXT: store i64 [[TMP107]], i64* [[TMP112]], align 8 -// CHECK9-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* -// CHECK9-NEXT: store i64 [[TMP107]], i64* [[TMP114]], align 8 -// CHECK9-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP115]], align 8 -// CHECK9-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** -// CHECK9-NEXT: store i32* [[TMP108]], i32** [[TMP117]], align 8 -// CHECK9-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** -// CHECK9-NEXT: store i32* [[TMP108]], i32** [[TMP119]], align 8 -// CHECK9-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP120]], align 8 -// CHECK9-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** -// CHECK9-NEXT: store i32* [[TMP109]], i32** [[TMP122]], align 8 -// CHECK9-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32** -// CHECK9-NEXT: store i32* [[TMP109]], i32** [[TMP124]], align 8 -// CHECK9-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP125]], align 8 -// CHECK9-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32** -// CHECK9-NEXT: store i32* [[TMP110]], i32** [[TMP127]], align 8 -// CHECK9-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32** -// CHECK9-NEXT: store i32* [[TMP110]], i32** [[TMP129]], align 8 -// CHECK9-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP130]], align 8 -// CHECK9-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK9-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK9-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP134]], 0 -// CHECK9-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 -// CHECK9-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 -// CHECK9-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK9-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK9-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP135]], 1 -// CHECK9-NEXT: [[TMP136:%.*]] = zext i32 [[ADD43]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) -// CHECK9-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.40, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.41, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 -// CHECK9-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] -// CHECK9: omp_offload.failed44: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67(i64 [[TMP107]], i32* [[TMP108]], i32* [[TMP109]], i32* [[TMP110]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT45]] -// CHECK9: omp_offload.cont45: -// CHECK9-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK9-NEXT: [[CONV47:%.*]] = bitcast i64* [[CH_CASTED46]] to i32* -// CHECK9-NEXT: store i32 [[TMP139]], i32* [[CONV47]], align 4 -// CHECK9-NEXT: [[TMP140:%.*]] = load i64, i64* [[CH_CASTED46]], align 8 -// CHECK9-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV49:%.*]] = bitcast i64* [[N_CASTED48]] to i32* -// CHECK9-NEXT: store i32 [[TMP141]], i32* [[CONV49]], align 4 -// CHECK9-NEXT: [[TMP142:%.*]] = load i64, i64* [[N_CASTED48]], align 8 -// CHECK9-NEXT: [[TMP143:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK9-NEXT: [[TMP144:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK9-NEXT: [[TMP145:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK9-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* -// CHECK9-NEXT: store i64 [[TMP140]], i64* [[TMP147]], align 8 -// CHECK9-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* -// CHECK9-NEXT: store i64 [[TMP140]], i64* [[TMP149]], align 8 -// CHECK9-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP150]], align 8 -// CHECK9-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i64* -// CHECK9-NEXT: store i64 [[TMP142]], i64* [[TMP152]], align 8 -// CHECK9-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i64* -// CHECK9-NEXT: store i64 [[TMP142]], i64* [[TMP154]], align 8 -// CHECK9-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP155]], align 8 -// CHECK9-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** -// CHECK9-NEXT: store i32* [[TMP143]], i32** [[TMP157]], align 8 -// CHECK9-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** -// CHECK9-NEXT: store i32* [[TMP143]], i32** [[TMP159]], align 8 -// CHECK9-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP160]], align 8 -// CHECK9-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32** -// CHECK9-NEXT: store i32* [[TMP144]], i32** [[TMP162]], align 8 -// CHECK9-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32** -// CHECK9-NEXT: store i32* [[TMP144]], i32** [[TMP164]], align 8 -// CHECK9-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP165]], align 8 -// CHECK9-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to i32** -// CHECK9-NEXT: store i32* [[TMP145]], i32** [[TMP167]], align 8 -// CHECK9-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to i32** -// CHECK9-NEXT: store i32* [[TMP145]], i32** [[TMP169]], align 8 -// CHECK9-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP170]], align 8 -// CHECK9-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK9-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK9-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP174]], 0 -// CHECK9-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 -// CHECK9-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 -// CHECK9-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK9-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK9-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP175]], 1 -// CHECK9-NEXT: [[TMP176:%.*]] = zext i32 [[ADD59]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) -// CHECK9-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.44, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.45, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 -// CHECK9-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] -// CHECK9: omp_offload.failed60: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i64 [[TMP140]], i64 [[TMP142]], i32* [[TMP143]], i32* [[TMP144]], i32* [[TMP145]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT61]] -// CHECK9: omp_offload.cont61: -// CHECK9-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV63:%.*]] = bitcast i64* [[N_CASTED62]] to i32* -// CHECK9-NEXT: store i32 [[TMP179]], i32* [[CONV63]], align 4 -// CHECK9-NEXT: [[TMP180:%.*]] = load i64, i64* [[N_CASTED62]], align 8 -// CHECK9-NEXT: [[TMP181:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK9-NEXT: [[TMP182:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK9-NEXT: [[TMP183:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK9-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i64* -// CHECK9-NEXT: store i64 [[TMP180]], i64* [[TMP185]], align 8 -// CHECK9-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i64* -// CHECK9-NEXT: store i64 [[TMP180]], i64* [[TMP187]], align 8 -// CHECK9-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP188]], align 8 -// CHECK9-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to i32** -// CHECK9-NEXT: store i32* [[TMP181]], i32** [[TMP190]], align 8 -// CHECK9-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to i32** -// CHECK9-NEXT: store i32* [[TMP181]], i32** [[TMP192]], align 8 -// CHECK9-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP193]], align 8 -// CHECK9-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to i32** -// CHECK9-NEXT: store i32* [[TMP182]], i32** [[TMP195]], align 8 -// CHECK9-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to i32** -// CHECK9-NEXT: store i32* [[TMP182]], i32** [[TMP197]], align 8 -// CHECK9-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP198]], align 8 -// CHECK9-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to i32** -// CHECK9-NEXT: store i32* [[TMP183]], i32** [[TMP200]], align 8 -// CHECK9-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to i32** -// CHECK9-NEXT: store i32* [[TMP183]], i32** [[TMP202]], align 8 -// CHECK9-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP203]], align 8 -// CHECK9-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_68]], align 4 -// CHECK9-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_68]], align 4 -// CHECK9-NEXT: [[SUB70:%.*]] = sub nsw i32 [[TMP207]], 0 -// CHECK9-NEXT: [[DIV71:%.*]] = sdiv i32 [[SUB70]], 1 -// CHECK9-NEXT: [[SUB72:%.*]] = sub nsw i32 [[DIV71]], 1 -// CHECK9-NEXT: store i32 [[SUB72]], i32* [[DOTCAPTURE_EXPR_69]], align 4 -// CHECK9-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_69]], align 4 -// CHECK9-NEXT: [[ADD73:%.*]] = add nsw i32 [[TMP208]], 1 -// CHECK9-NEXT: [[TMP209:%.*]] = zext i32 [[ADD73]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) -// CHECK9-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.48, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.49, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 -// CHECK9-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED74:%.*]], label [[OMP_OFFLOAD_CONT75:%.*]] -// CHECK9: omp_offload.failed74: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83(i64 [[TMP180]], i32* [[TMP181]], i32* [[TMP182]], i32* [[TMP183]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT75]] -// CHECK9: omp_offload.cont75: -// CHECK9-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK9-NEXT: [[CONV77:%.*]] = bitcast i64* [[CH_CASTED76]] to i32* -// CHECK9-NEXT: store i32 [[TMP212]], i32* [[CONV77]], align 4 -// CHECK9-NEXT: [[TMP213:%.*]] = load i64, i64* [[CH_CASTED76]], align 8 -// CHECK9-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV79:%.*]] = bitcast i64* [[N_CASTED78]] to i32* -// CHECK9-NEXT: store i32 [[TMP214]], i32* [[CONV79]], align 4 -// CHECK9-NEXT: [[TMP215:%.*]] = load i64, i64* [[N_CASTED78]], align 8 -// CHECK9-NEXT: [[TMP216:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK9-NEXT: [[TMP217:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK9-NEXT: [[TMP218:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK9-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i64* -// CHECK9-NEXT: store i64 [[TMP213]], i64* [[TMP220]], align 8 -// CHECK9-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i64* -// CHECK9-NEXT: store i64 [[TMP213]], i64* [[TMP222]], align 8 -// CHECK9-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP223]], align 8 -// CHECK9-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i64* -// CHECK9-NEXT: store i64 [[TMP215]], i64* [[TMP225]], align 8 -// CHECK9-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i64* -// CHECK9-NEXT: store i64 [[TMP215]], i64* [[TMP227]], align 8 -// CHECK9-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP228]], align 8 -// CHECK9-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to i32** -// CHECK9-NEXT: store i32* [[TMP216]], i32** [[TMP230]], align 8 -// CHECK9-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to i32** -// CHECK9-NEXT: store i32* [[TMP216]], i32** [[TMP232]], align 8 -// CHECK9-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP233]], align 8 -// CHECK9-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to i32** -// CHECK9-NEXT: store i32* [[TMP217]], i32** [[TMP235]], align 8 -// CHECK9-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to i32** -// CHECK9-NEXT: store i32* [[TMP217]], i32** [[TMP237]], align 8 -// CHECK9-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP238]], align 8 -// CHECK9-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to i32** -// CHECK9-NEXT: store i32* [[TMP218]], i32** [[TMP240]], align 8 -// CHECK9-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to i32** -// CHECK9-NEXT: store i32* [[TMP218]], i32** [[TMP242]], align 8 -// CHECK9-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP243]], align 8 -// CHECK9-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_84]], align 4 -// CHECK9-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_84]], align 4 -// CHECK9-NEXT: [[SUB86:%.*]] = sub nsw i32 [[TMP247]], 0 -// CHECK9-NEXT: [[DIV87:%.*]] = sdiv i32 [[SUB86]], 1 -// CHECK9-NEXT: [[SUB88:%.*]] = sub nsw i32 [[DIV87]], 1 -// CHECK9-NEXT: store i32 [[SUB88]], i32* [[DOTCAPTURE_EXPR_85]], align 4 -// CHECK9-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_85]], align 4 -// CHECK9-NEXT: [[ADD89:%.*]] = add nsw i32 [[TMP248]], 1 -// CHECK9-NEXT: [[TMP249:%.*]] = zext i32 [[ADD89]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) -// CHECK9-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.52, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.53, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 -// CHECK9-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED90:%.*]], label [[OMP_OFFLOAD_CONT91:%.*]] -// CHECK9: omp_offload.failed90: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91(i64 [[TMP213]], i64 [[TMP215]], i32* [[TMP216]], i32* [[TMP217]], i32* [[TMP218]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT91]] -// CHECK9: omp_offload.cont91: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP21]], i32 2) -// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK9-NEXT: br i1 [[TMP23]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK9: .cancel.exit: -// CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK9: .cancel.continue: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM7]] -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK9-NEXT: [[TMP30:%.*]] = load i32*, i32** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i64 [[IDXPROM10]] -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: cancel.exit: -// CHECK9-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK9-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: br label [[CANCEL_CONT]] -// CHECK9: cancel.cont: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 -// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..31 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK9-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 -// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..34 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..35 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK9: cond.true10: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END12:%.*]] -// CHECK9: cond.false11: -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END12]] -// CHECK9: cond.end12: -// CHECK9-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE10]] ], [ [[TMP32]], [[COND_FALSE11]] ] -// CHECK9-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK9-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 -// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..38 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..39 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK9-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..42 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**, i64)* @.omp_outlined..43 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i64 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK9: omp.dispatch.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[CONV7]], [[TMP14]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CONV9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[CONV9]], [[COND_FALSE]] ] -// CHECK9-NEXT: [[CONV10:%.*]] = trunc i64 [[COND]] to i32 -// CHECK9-NEXT: store i32 [[CONV10]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK9: omp.dispatch.body: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK9-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM13]] -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX14]], align 4 -// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP25]], [[TMP28]] -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK9-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP30]] to i64 -// CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i32, i32* [[TMP29]], i64 [[IDXPROM16]] -// CHECK9-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX17]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK9-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK9: omp.dispatch.inc: -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] -// CHECK9-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] -// CHECK9-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK9: omp.dispatch.end: -// CHECK9-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 -// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..46 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..47 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK9: omp.dispatch.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK9: omp.dispatch.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[TMP2]], align 8, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP3]], align 8, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM6]] -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP26]] -// CHECK9-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP1]], align 8, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM9]] -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX10]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK9: omp.dispatch.inc: -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK9: omp.dispatch.end: -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 -// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..50 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**, i64)* @.omp_outlined..51 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i64 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK9: omp.dispatch.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK9: omp.dispatch.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[TMP2]], align 8, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP22]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32*, i32** [[TMP3]], align 8, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[TMP25]], i64 [[IDXPROM8]] -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP27]] -// CHECK9-NEXT: [[TMP28:%.*]] = load i32*, i32** [[TMP1]], align 8, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[TMP28]], i64 [[IDXPROM11]] -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[ARRAYIDX12]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK9: omp.dispatch.inc: -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK9: omp.dispatch.end: -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[B:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[C:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[CH_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED32:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[CH_CASTED46:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED48:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS50:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS51:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS52:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED62:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS64:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS65:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS66:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP67:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_68:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_69:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[CH_CASTED76:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED78:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS80:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS81:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS82:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP83:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_84:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_85:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double*, double** [[A]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double*, double** [[B]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load double*, double** [[C]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to double** -// CHECK10-NEXT: store double* [[TMP2]], double** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK10-NEXT: store double* [[TMP2]], double** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double** -// CHECK10-NEXT: store double* [[TMP3]], double** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to double** -// CHECK10-NEXT: store double* [[TMP3]], double** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double** -// CHECK10-NEXT: store double* [[TMP4]], double** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double** -// CHECK10-NEXT: store double* [[TMP4]], double** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369(i64 [[TMP1]], double* [[TMP2]], double* [[TMP3]], double* [[TMP4]]) #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = load double*, double** [[A]], align 8 -// CHECK10-NEXT: [[TMP36:%.*]] = load double*, double** [[B]], align 8 -// CHECK10-NEXT: [[TMP37:%.*]] = load double*, double** [[C]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP41]], align 8 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP42]], align 8 -// CHECK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to double** -// CHECK10-NEXT: store double* [[TMP35]], double** [[TMP44]], align 8 -// CHECK10-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to double** -// CHECK10-NEXT: store double* [[TMP35]], double** [[TMP46]], align 8 -// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** -// CHECK10-NEXT: store double* [[TMP36]], double** [[TMP49]], align 8 -// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** -// CHECK10-NEXT: store double* [[TMP36]], double** [[TMP51]], align 8 -// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP52]], align 8 -// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** -// CHECK10-NEXT: store double* [[TMP37]], double** [[TMP54]], align 8 -// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to double** -// CHECK10-NEXT: store double* [[TMP37]], double** [[TMP56]], align 8 -// CHECK10-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP57]], align 8 -// CHECK10-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK10-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK10-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP61]], 0 -// CHECK10-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK10-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK10-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP62]], 1 -// CHECK10-NEXT: [[TMP63:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) -// CHECK10-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 -// CHECK10-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK10: omp_offload.failed15: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408(i64 [[TMP34]], double* [[TMP35]], double* [[TMP36]], double* [[TMP37]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK10: omp_offload.cont16: -// CHECK10-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[CH_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP66]], i32* [[CONV17]], align 4 -// CHECK10-NEXT: [[TMP67:%.*]] = load i64, i64* [[CH_CASTED]], align 8 -// CHECK10-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* -// CHECK10-NEXT: store i32 [[TMP68]], i32* [[CONV19]], align 4 -// CHECK10-NEXT: [[TMP69:%.*]] = load i64, i64* [[N_CASTED18]], align 8 -// CHECK10-NEXT: [[TMP70:%.*]] = load double*, double** [[A]], align 8 -// CHECK10-NEXT: [[TMP71:%.*]] = load double*, double** [[B]], align 8 -// CHECK10-NEXT: [[TMP72:%.*]] = load double*, double** [[C]], align 8 -// CHECK10-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* -// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP74]], align 8 -// CHECK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP76]], align 8 -// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP77]], align 8 -// CHECK10-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* -// CHECK10-NEXT: store i64 [[TMP69]], i64* [[TMP79]], align 8 -// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK10-NEXT: store i64 [[TMP69]], i64* [[TMP81]], align 8 -// CHECK10-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP82]], align 8 -// CHECK10-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to double** -// CHECK10-NEXT: store double* [[TMP70]], double** [[TMP84]], align 8 -// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to double** -// CHECK10-NEXT: store double* [[TMP70]], double** [[TMP86]], align 8 -// CHECK10-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP87]], align 8 -// CHECK10-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** -// CHECK10-NEXT: store double* [[TMP71]], double** [[TMP89]], align 8 -// CHECK10-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to double** -// CHECK10-NEXT: store double* [[TMP71]], double** [[TMP91]], align 8 -// CHECK10-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK10-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** -// CHECK10-NEXT: store double* [[TMP72]], double** [[TMP94]], align 8 -// CHECK10-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to double** -// CHECK10-NEXT: store double* [[TMP72]], double** [[TMP96]], align 8 -// CHECK10-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP97]], align 8 -// CHECK10-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK10-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK10-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP101]], 0 -// CHECK10-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// CHECK10-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 -// CHECK10-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK10-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK10-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP102]], 1 -// CHECK10-NEXT: [[TMP103:%.*]] = zext i32 [[ADD29]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) -// CHECK10-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 -// CHECK10-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK10: omp_offload.failed30: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447(i64 [[TMP67]], i64 [[TMP69]], double* [[TMP70]], double* [[TMP71]], double* [[TMP72]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK10: omp_offload.cont31: -// CHECK10-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV33:%.*]] = bitcast i64* [[N_CASTED32]] to i32* -// CHECK10-NEXT: store i32 [[TMP106]], i32* [[CONV33]], align 4 -// CHECK10-NEXT: [[TMP107:%.*]] = load i64, i64* [[N_CASTED32]], align 8 -// CHECK10-NEXT: [[TMP108:%.*]] = load double*, double** [[A]], align 8 -// CHECK10-NEXT: [[TMP109:%.*]] = load double*, double** [[B]], align 8 -// CHECK10-NEXT: [[TMP110:%.*]] = load double*, double** [[C]], align 8 -// CHECK10-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* -// CHECK10-NEXT: store i64 [[TMP107]], i64* [[TMP112]], align 8 -// CHECK10-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* -// CHECK10-NEXT: store i64 [[TMP107]], i64* [[TMP114]], align 8 -// CHECK10-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP115]], align 8 -// CHECK10-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to double** -// CHECK10-NEXT: store double* [[TMP108]], double** [[TMP117]], align 8 -// CHECK10-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to double** -// CHECK10-NEXT: store double* [[TMP108]], double** [[TMP119]], align 8 -// CHECK10-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP120]], align 8 -// CHECK10-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to double** -// CHECK10-NEXT: store double* [[TMP109]], double** [[TMP122]], align 8 -// CHECK10-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** -// CHECK10-NEXT: store double* [[TMP109]], double** [[TMP124]], align 8 -// CHECK10-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP125]], align 8 -// CHECK10-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** -// CHECK10-NEXT: store double* [[TMP110]], double** [[TMP127]], align 8 -// CHECK10-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** -// CHECK10-NEXT: store double* [[TMP110]], double** [[TMP129]], align 8 -// CHECK10-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP130]], align 8 -// CHECK10-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK10-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK10-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP134]], 0 -// CHECK10-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 -// CHECK10-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 -// CHECK10-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK10-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK10-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP135]], 1 -// CHECK10-NEXT: [[TMP136:%.*]] = zext i32 [[ADD43]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) -// CHECK10-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 -// CHECK10-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] -// CHECK10: omp_offload.failed44: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478(i64 [[TMP107]], double* [[TMP108]], double* [[TMP109]], double* [[TMP110]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT45]] -// CHECK10: omp_offload.cont45: -// CHECK10-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK10-NEXT: [[CONV47:%.*]] = bitcast i64* [[CH_CASTED46]] to i32* -// CHECK10-NEXT: store i32 [[TMP139]], i32* [[CONV47]], align 4 -// CHECK10-NEXT: [[TMP140:%.*]] = load i64, i64* [[CH_CASTED46]], align 8 -// CHECK10-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV49:%.*]] = bitcast i64* [[N_CASTED48]] to i32* -// CHECK10-NEXT: store i32 [[TMP141]], i32* [[CONV49]], align 4 -// CHECK10-NEXT: [[TMP142:%.*]] = load i64, i64* [[N_CASTED48]], align 8 -// CHECK10-NEXT: [[TMP143:%.*]] = load double*, double** [[A]], align 8 -// CHECK10-NEXT: [[TMP144:%.*]] = load double*, double** [[B]], align 8 -// CHECK10-NEXT: [[TMP145:%.*]] = load double*, double** [[C]], align 8 -// CHECK10-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* -// CHECK10-NEXT: store i64 [[TMP140]], i64* [[TMP147]], align 8 -// CHECK10-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* -// CHECK10-NEXT: store i64 [[TMP140]], i64* [[TMP149]], align 8 -// CHECK10-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP150]], align 8 -// CHECK10-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i64* -// CHECK10-NEXT: store i64 [[TMP142]], i64* [[TMP152]], align 8 -// CHECK10-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i64* -// CHECK10-NEXT: store i64 [[TMP142]], i64* [[TMP154]], align 8 -// CHECK10-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP155]], align 8 -// CHECK10-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to double** -// CHECK10-NEXT: store double* [[TMP143]], double** [[TMP157]], align 8 -// CHECK10-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to double** -// CHECK10-NEXT: store double* [[TMP143]], double** [[TMP159]], align 8 -// CHECK10-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP160]], align 8 -// CHECK10-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to double** -// CHECK10-NEXT: store double* [[TMP144]], double** [[TMP162]], align 8 -// CHECK10-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to double** -// CHECK10-NEXT: store double* [[TMP144]], double** [[TMP164]], align 8 -// CHECK10-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP165]], align 8 -// CHECK10-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to double** -// CHECK10-NEXT: store double* [[TMP145]], double** [[TMP167]], align 8 -// CHECK10-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to double** -// CHECK10-NEXT: store double* [[TMP145]], double** [[TMP169]], align 8 -// CHECK10-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP170]], align 8 -// CHECK10-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK10-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK10-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP174]], 0 -// CHECK10-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 -// CHECK10-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 -// CHECK10-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK10-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK10-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP175]], 1 -// CHECK10-NEXT: [[TMP176:%.*]] = zext i32 [[ADD59]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) -// CHECK10-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 -// CHECK10-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] -// CHECK10: omp_offload.failed60: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506(i64 [[TMP140]], i64 [[TMP142]], double* [[TMP143]], double* [[TMP144]], double* [[TMP145]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT61]] -// CHECK10: omp_offload.cont61: -// CHECK10-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV63:%.*]] = bitcast i64* [[N_CASTED62]] to i32* -// CHECK10-NEXT: store i32 [[TMP179]], i32* [[CONV63]], align 4 -// CHECK10-NEXT: [[TMP180:%.*]] = load i64, i64* [[N_CASTED62]], align 8 -// CHECK10-NEXT: [[TMP181:%.*]] = load double*, double** [[A]], align 8 -// CHECK10-NEXT: [[TMP182:%.*]] = load double*, double** [[B]], align 8 -// CHECK10-NEXT: [[TMP183:%.*]] = load double*, double** [[C]], align 8 -// CHECK10-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i64* -// CHECK10-NEXT: store i64 [[TMP180]], i64* [[TMP185]], align 8 -// CHECK10-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i64* -// CHECK10-NEXT: store i64 [[TMP180]], i64* [[TMP187]], align 8 -// CHECK10-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP188]], align 8 -// CHECK10-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to double** -// CHECK10-NEXT: store double* [[TMP181]], double** [[TMP190]], align 8 -// CHECK10-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to double** -// CHECK10-NEXT: store double* [[TMP181]], double** [[TMP192]], align 8 -// CHECK10-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP193]], align 8 -// CHECK10-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to double** -// CHECK10-NEXT: store double* [[TMP182]], double** [[TMP195]], align 8 -// CHECK10-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to double** -// CHECK10-NEXT: store double* [[TMP182]], double** [[TMP197]], align 8 -// CHECK10-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP198]], align 8 -// CHECK10-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to double** -// CHECK10-NEXT: store double* [[TMP183]], double** [[TMP200]], align 8 -// CHECK10-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to double** -// CHECK10-NEXT: store double* [[TMP183]], double** [[TMP202]], align 8 -// CHECK10-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP203]], align 8 -// CHECK10-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_68]], align 4 -// CHECK10-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_68]], align 4 -// CHECK10-NEXT: [[SUB70:%.*]] = sub nsw i32 [[TMP207]], 0 -// CHECK10-NEXT: [[DIV71:%.*]] = sdiv i32 [[SUB70]], 1 -// CHECK10-NEXT: [[SUB72:%.*]] = sub nsw i32 [[DIV71]], 1 -// CHECK10-NEXT: store i32 [[SUB72]], i32* [[DOTCAPTURE_EXPR_69]], align 4 -// CHECK10-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_69]], align 4 -// CHECK10-NEXT: [[ADD73:%.*]] = add nsw i32 [[TMP208]], 1 -// CHECK10-NEXT: [[TMP209:%.*]] = zext i32 [[ADD73]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) -// CHECK10-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 -// CHECK10-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED74:%.*]], label [[OMP_OFFLOAD_CONT75:%.*]] -// CHECK10: omp_offload.failed74: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536(i64 [[TMP180]], double* [[TMP181]], double* [[TMP182]], double* [[TMP183]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT75]] -// CHECK10: omp_offload.cont75: -// CHECK10-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK10-NEXT: [[CONV77:%.*]] = bitcast i64* [[CH_CASTED76]] to i32* -// CHECK10-NEXT: store i32 [[TMP212]], i32* [[CONV77]], align 4 -// CHECK10-NEXT: [[TMP213:%.*]] = load i64, i64* [[CH_CASTED76]], align 8 -// CHECK10-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV79:%.*]] = bitcast i64* [[N_CASTED78]] to i32* -// CHECK10-NEXT: store i32 [[TMP214]], i32* [[CONV79]], align 4 -// CHECK10-NEXT: [[TMP215:%.*]] = load i64, i64* [[N_CASTED78]], align 8 -// CHECK10-NEXT: [[TMP216:%.*]] = load double*, double** [[A]], align 8 -// CHECK10-NEXT: [[TMP217:%.*]] = load double*, double** [[B]], align 8 -// CHECK10-NEXT: [[TMP218:%.*]] = load double*, double** [[C]], align 8 -// CHECK10-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i64* -// CHECK10-NEXT: store i64 [[TMP213]], i64* [[TMP220]], align 8 -// CHECK10-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i64* -// CHECK10-NEXT: store i64 [[TMP213]], i64* [[TMP222]], align 8 -// CHECK10-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP223]], align 8 -// CHECK10-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i64* -// CHECK10-NEXT: store i64 [[TMP215]], i64* [[TMP225]], align 8 -// CHECK10-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i64* -// CHECK10-NEXT: store i64 [[TMP215]], i64* [[TMP227]], align 8 -// CHECK10-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP228]], align 8 -// CHECK10-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to double** -// CHECK10-NEXT: store double* [[TMP216]], double** [[TMP230]], align 8 -// CHECK10-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to double** -// CHECK10-NEXT: store double* [[TMP216]], double** [[TMP232]], align 8 -// CHECK10-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP233]], align 8 -// CHECK10-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to double** -// CHECK10-NEXT: store double* [[TMP217]], double** [[TMP235]], align 8 -// CHECK10-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to double** -// CHECK10-NEXT: store double* [[TMP217]], double** [[TMP237]], align 8 -// CHECK10-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP238]], align 8 -// CHECK10-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to double** -// CHECK10-NEXT: store double* [[TMP218]], double** [[TMP240]], align 8 -// CHECK10-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to double** -// CHECK10-NEXT: store double* [[TMP218]], double** [[TMP242]], align 8 -// CHECK10-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP243]], align 8 -// CHECK10-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_84]], align 4 -// CHECK10-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_84]], align 4 -// CHECK10-NEXT: [[SUB86:%.*]] = sub nsw i32 [[TMP247]], 0 -// CHECK10-NEXT: [[DIV87:%.*]] = sdiv i32 [[SUB86]], 1 -// CHECK10-NEXT: [[SUB88:%.*]] = sub nsw i32 [[DIV87]], 1 -// CHECK10-NEXT: store i32 [[SUB88]], i32* [[DOTCAPTURE_EXPR_85]], align 4 -// CHECK10-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_85]], align 4 -// CHECK10-NEXT: [[ADD89:%.*]] = add nsw i32 [[TMP248]], 1 -// CHECK10-NEXT: [[TMP249:%.*]] = zext i32 [[ADD89]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) -// CHECK10-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.24, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 -// CHECK10-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED90:%.*]], label [[OMP_OFFLOAD_CONT91:%.*]] -// CHECK10: omp_offload.failed90: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i64 [[TMP213]], i64 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT91]] -// CHECK10: omp_offload.cont91: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 -// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] -// CHECK10-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 -// CHECK10-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK10-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] -// CHECK10-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 -// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] -// CHECK10-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 -// CHECK10-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK10-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] -// CHECK10-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 -// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] -// CHECK10-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK10: cond.true10: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END12:%.*]] -// CHECK10: cond.false11: -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END12]] -// CHECK10: cond.end12: -// CHECK10-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE10]] ], [ [[TMP32]], [[COND_FALSE11]] ] -// CHECK10-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] -// CHECK10-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 -// CHECK10-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK10-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] -// CHECK10-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 -// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM7]] -// CHECK10-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX8]], align 8 -// CHECK10-NEXT: [[ADD9:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK10-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM10]] -// CHECK10-NEXT: store double [[ADD9]], double* [[ARRAYIDX11]], align 8 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 -// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i64 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK10: omp.dispatch.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[CONV7]], [[TMP14]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CONV9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[CONV9]], [[COND_FALSE]] ] -// CHECK10-NEXT: [[CONV10:%.*]] = trunc i64 [[COND]] to i32 -// CHECK10-NEXT: store i32 [[CONV10]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK10: omp.dispatch.body: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP23]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK10-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP26]], i64 [[IDXPROM13]] -// CHECK10-NEXT: [[TMP28:%.*]] = load double, double* [[ARRAYIDX14]], align 8 -// CHECK10-NEXT: [[ADD15:%.*]] = fadd double [[TMP25]], [[TMP28]] -// CHECK10-NEXT: [[TMP29:%.*]] = load double*, double** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK10-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP30]] to i64 -// CHECK10-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP29]], i64 [[IDXPROM16]] -// CHECK10-NEXT: store double [[ADD15]], double* [[ARRAYIDX17]], align 8 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK10-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK10: omp.dispatch.inc: -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] -// CHECK10-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] -// CHECK10-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK10: omp.dispatch.end: -// CHECK10-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 -// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32* [[CONV]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK10: omp.dispatch.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK10: omp.dispatch.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP21:%.*]] = load double*, double** [[TMP2]], align 8, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP21]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX]], align 8, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP24:%.*]] = load double*, double** [[TMP3]], align 8, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP24]], i64 [[IDXPROM6]] -// CHECK10-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX7]], align 8, !llvm.access.group !18 -// CHECK10-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]] -// CHECK10-NEXT: [[TMP27:%.*]] = load double*, double** [[TMP1]], align 8, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP27]], i64 [[IDXPROM9]] -// CHECK10-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !18 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK10: omp.dispatch.inc: -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK10: omp.dispatch.end: -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 -// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double* [[B]], double** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double* [[C]], double** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, double**, double**, double**, i64)* @.omp_outlined..23 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i64 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca double**, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store double** [[A]], double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store double** [[B]], double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store double** [[C]], double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK10: omp.dispatch.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK10: omp.dispatch.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[TMP22:%.*]] = load double*, double** [[TMP2]], align 8, !llvm.access.group !21 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP22]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX]], align 8, !llvm.access.group !21 -// CHECK10-NEXT: [[TMP25:%.*]] = load double*, double** [[TMP3]], align 8, !llvm.access.group !21 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds double, double* [[TMP25]], i64 [[IDXPROM8]] -// CHECK10-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX9]], align 8, !llvm.access.group !21 -// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]] -// CHECK10-NEXT: [[TMP28:%.*]] = load double*, double** [[TMP1]], align 8, !llvm.access.group !21 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP28]], i64 [[IDXPROM11]] -// CHECK10-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !21 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK10: omp.dispatch.inc: -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK10: omp.dispatch.end: -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[C:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[CH_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED32:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[CH_CASTED46:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED48:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS50:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS51:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS52:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED62:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS64:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS65:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS66:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP67:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_68:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_69:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[CH_CASTED76:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED78:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS80:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS81:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS82:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP83:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_84:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_85:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32** -// CHECK10-NEXT: store i32* [[TMP2]], i32** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32** -// CHECK10-NEXT: store i32* [[TMP2]], i32** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32** -// CHECK10-NEXT: store i32* [[TMP3]], i32** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32** -// CHECK10-NEXT: store i32* [[TMP3]], i32** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK10-NEXT: store i32* [[TMP4]], i32** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32** -// CHECK10-NEXT: store i32* [[TMP4]], i32** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP30]]) -// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42(i64 [[TMP1]], i32* [[TMP2]], i32* [[TMP3]], i32* [[TMP4]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK10-NEXT: [[TMP36:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK10-NEXT: [[TMP37:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP41]], align 8 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP42]], align 8 -// CHECK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32** -// CHECK10-NEXT: store i32* [[TMP35]], i32** [[TMP44]], align 8 -// CHECK10-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32** -// CHECK10-NEXT: store i32* [[TMP35]], i32** [[TMP46]], align 8 -// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK10-NEXT: store i32* [[TMP36]], i32** [[TMP49]], align 8 -// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK10-NEXT: store i32* [[TMP36]], i32** [[TMP51]], align 8 -// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP52]], align 8 -// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32** -// CHECK10-NEXT: store i32* [[TMP37]], i32** [[TMP54]], align 8 -// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32** -// CHECK10-NEXT: store i32* [[TMP37]], i32** [[TMP56]], align 8 -// CHECK10-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP57]], align 8 -// CHECK10-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK10-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK10-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP61]], 0 -// CHECK10-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK10-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK10-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP62]], 1 -// CHECK10-NEXT: [[TMP63:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) -// CHECK10-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.32, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.33, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 -// CHECK10-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK10: omp_offload.failed15: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51(i64 [[TMP34]], i32* [[TMP35]], i32* [[TMP36]], i32* [[TMP37]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK10: omp_offload.cont16: -// CHECK10-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[CH_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP66]], i32* [[CONV17]], align 4 -// CHECK10-NEXT: [[TMP67:%.*]] = load i64, i64* [[CH_CASTED]], align 8 -// CHECK10-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* -// CHECK10-NEXT: store i32 [[TMP68]], i32* [[CONV19]], align 4 -// CHECK10-NEXT: [[TMP69:%.*]] = load i64, i64* [[N_CASTED18]], align 8 -// CHECK10-NEXT: [[TMP70:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK10-NEXT: [[TMP71:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK10-NEXT: [[TMP72:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK10-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* -// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP74]], align 8 -// CHECK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP76]], align 8 -// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP77]], align 8 -// CHECK10-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* -// CHECK10-NEXT: store i64 [[TMP69]], i64* [[TMP79]], align 8 -// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK10-NEXT: store i64 [[TMP69]], i64* [[TMP81]], align 8 -// CHECK10-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP82]], align 8 -// CHECK10-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK10-NEXT: store i32* [[TMP70]], i32** [[TMP84]], align 8 -// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** -// CHECK10-NEXT: store i32* [[TMP70]], i32** [[TMP86]], align 8 -// CHECK10-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP87]], align 8 -// CHECK10-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK10-NEXT: store i32* [[TMP71]], i32** [[TMP89]], align 8 -// CHECK10-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** -// CHECK10-NEXT: store i32* [[TMP71]], i32** [[TMP91]], align 8 -// CHECK10-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK10-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to i32** -// CHECK10-NEXT: store i32* [[TMP72]], i32** [[TMP94]], align 8 -// CHECK10-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32** -// CHECK10-NEXT: store i32* [[TMP72]], i32** [[TMP96]], align 8 -// CHECK10-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP97]], align 8 -// CHECK10-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK10-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK10-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP101]], 0 -// CHECK10-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// CHECK10-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 -// CHECK10-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK10-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK10-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP102]], 1 -// CHECK10-NEXT: [[TMP103:%.*]] = zext i32 [[ADD29]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) -// CHECK10-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.36, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.37, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 -// CHECK10-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK10: omp_offload.failed30: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59(i64 [[TMP67]], i64 [[TMP69]], i32* [[TMP70]], i32* [[TMP71]], i32* [[TMP72]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK10: omp_offload.cont31: -// CHECK10-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV33:%.*]] = bitcast i64* [[N_CASTED32]] to i32* -// CHECK10-NEXT: store i32 [[TMP106]], i32* [[CONV33]], align 4 -// CHECK10-NEXT: [[TMP107:%.*]] = load i64, i64* [[N_CASTED32]], align 8 -// CHECK10-NEXT: [[TMP108:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK10-NEXT: [[TMP109:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK10-NEXT: [[TMP110:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK10-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* -// CHECK10-NEXT: store i64 [[TMP107]], i64* [[TMP112]], align 8 -// CHECK10-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* -// CHECK10-NEXT: store i64 [[TMP107]], i64* [[TMP114]], align 8 -// CHECK10-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP115]], align 8 -// CHECK10-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** -// CHECK10-NEXT: store i32* [[TMP108]], i32** [[TMP117]], align 8 -// CHECK10-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** -// CHECK10-NEXT: store i32* [[TMP108]], i32** [[TMP119]], align 8 -// CHECK10-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP120]], align 8 -// CHECK10-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** -// CHECK10-NEXT: store i32* [[TMP109]], i32** [[TMP122]], align 8 -// CHECK10-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32** -// CHECK10-NEXT: store i32* [[TMP109]], i32** [[TMP124]], align 8 -// CHECK10-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP125]], align 8 -// CHECK10-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32** -// CHECK10-NEXT: store i32* [[TMP110]], i32** [[TMP127]], align 8 -// CHECK10-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32** -// CHECK10-NEXT: store i32* [[TMP110]], i32** [[TMP129]], align 8 -// CHECK10-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP130]], align 8 -// CHECK10-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK10-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK10-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP134]], 0 -// CHECK10-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 -// CHECK10-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 -// CHECK10-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK10-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK10-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP135]], 1 -// CHECK10-NEXT: [[TMP136:%.*]] = zext i32 [[ADD43]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) -// CHECK10-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.40, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.41, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 -// CHECK10-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] -// CHECK10: omp_offload.failed44: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67(i64 [[TMP107]], i32* [[TMP108]], i32* [[TMP109]], i32* [[TMP110]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT45]] -// CHECK10: omp_offload.cont45: -// CHECK10-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK10-NEXT: [[CONV47:%.*]] = bitcast i64* [[CH_CASTED46]] to i32* -// CHECK10-NEXT: store i32 [[TMP139]], i32* [[CONV47]], align 4 -// CHECK10-NEXT: [[TMP140:%.*]] = load i64, i64* [[CH_CASTED46]], align 8 -// CHECK10-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV49:%.*]] = bitcast i64* [[N_CASTED48]] to i32* -// CHECK10-NEXT: store i32 [[TMP141]], i32* [[CONV49]], align 4 -// CHECK10-NEXT: [[TMP142:%.*]] = load i64, i64* [[N_CASTED48]], align 8 -// CHECK10-NEXT: [[TMP143:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK10-NEXT: [[TMP144:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK10-NEXT: [[TMP145:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK10-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* -// CHECK10-NEXT: store i64 [[TMP140]], i64* [[TMP147]], align 8 -// CHECK10-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* -// CHECK10-NEXT: store i64 [[TMP140]], i64* [[TMP149]], align 8 -// CHECK10-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP150]], align 8 -// CHECK10-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i64* -// CHECK10-NEXT: store i64 [[TMP142]], i64* [[TMP152]], align 8 -// CHECK10-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i64* -// CHECK10-NEXT: store i64 [[TMP142]], i64* [[TMP154]], align 8 -// CHECK10-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP155]], align 8 -// CHECK10-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** -// CHECK10-NEXT: store i32* [[TMP143]], i32** [[TMP157]], align 8 -// CHECK10-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** -// CHECK10-NEXT: store i32* [[TMP143]], i32** [[TMP159]], align 8 -// CHECK10-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP160]], align 8 -// CHECK10-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32** -// CHECK10-NEXT: store i32* [[TMP144]], i32** [[TMP162]], align 8 -// CHECK10-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32** -// CHECK10-NEXT: store i32* [[TMP144]], i32** [[TMP164]], align 8 -// CHECK10-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP165]], align 8 -// CHECK10-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to i32** -// CHECK10-NEXT: store i32* [[TMP145]], i32** [[TMP167]], align 8 -// CHECK10-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to i32** -// CHECK10-NEXT: store i32* [[TMP145]], i32** [[TMP169]], align 8 -// CHECK10-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS52]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP170]], align 8 -// CHECK10-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS50]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS51]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK10-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK10-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP174]], 0 -// CHECK10-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 -// CHECK10-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 -// CHECK10-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK10-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK10-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP175]], 1 -// CHECK10-NEXT: [[TMP176:%.*]] = zext i32 [[ADD59]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) -// CHECK10-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.44, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.45, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 -// CHECK10-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] -// CHECK10: omp_offload.failed60: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i64 [[TMP140]], i64 [[TMP142]], i32* [[TMP143]], i32* [[TMP144]], i32* [[TMP145]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT61]] -// CHECK10: omp_offload.cont61: -// CHECK10-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV63:%.*]] = bitcast i64* [[N_CASTED62]] to i32* -// CHECK10-NEXT: store i32 [[TMP179]], i32* [[CONV63]], align 4 -// CHECK10-NEXT: [[TMP180:%.*]] = load i64, i64* [[N_CASTED62]], align 8 -// CHECK10-NEXT: [[TMP181:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK10-NEXT: [[TMP182:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK10-NEXT: [[TMP183:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK10-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i64* -// CHECK10-NEXT: store i64 [[TMP180]], i64* [[TMP185]], align 8 -// CHECK10-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i64* -// CHECK10-NEXT: store i64 [[TMP180]], i64* [[TMP187]], align 8 -// CHECK10-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP188]], align 8 -// CHECK10-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to i32** -// CHECK10-NEXT: store i32* [[TMP181]], i32** [[TMP190]], align 8 -// CHECK10-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to i32** -// CHECK10-NEXT: store i32* [[TMP181]], i32** [[TMP192]], align 8 -// CHECK10-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP193]], align 8 -// CHECK10-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to i32** -// CHECK10-NEXT: store i32* [[TMP182]], i32** [[TMP195]], align 8 -// CHECK10-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to i32** -// CHECK10-NEXT: store i32* [[TMP182]], i32** [[TMP197]], align 8 -// CHECK10-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP198]], align 8 -// CHECK10-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to i32** -// CHECK10-NEXT: store i32* [[TMP183]], i32** [[TMP200]], align 8 -// CHECK10-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to i32** -// CHECK10-NEXT: store i32* [[TMP183]], i32** [[TMP202]], align 8 -// CHECK10-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS66]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP203]], align 8 -// CHECK10-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS64]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS65]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_68]], align 4 -// CHECK10-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_68]], align 4 -// CHECK10-NEXT: [[SUB70:%.*]] = sub nsw i32 [[TMP207]], 0 -// CHECK10-NEXT: [[DIV71:%.*]] = sdiv i32 [[SUB70]], 1 -// CHECK10-NEXT: [[SUB72:%.*]] = sub nsw i32 [[DIV71]], 1 -// CHECK10-NEXT: store i32 [[SUB72]], i32* [[DOTCAPTURE_EXPR_69]], align 4 -// CHECK10-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_69]], align 4 -// CHECK10-NEXT: [[ADD73:%.*]] = add nsw i32 [[TMP208]], 1 -// CHECK10-NEXT: [[TMP209:%.*]] = zext i32 [[ADD73]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) -// CHECK10-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.48, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.49, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 -// CHECK10-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED74:%.*]], label [[OMP_OFFLOAD_CONT75:%.*]] -// CHECK10: omp_offload.failed74: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83(i64 [[TMP180]], i32* [[TMP181]], i32* [[TMP182]], i32* [[TMP183]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT75]] -// CHECK10: omp_offload.cont75: -// CHECK10-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK10-NEXT: [[CONV77:%.*]] = bitcast i64* [[CH_CASTED76]] to i32* -// CHECK10-NEXT: store i32 [[TMP212]], i32* [[CONV77]], align 4 -// CHECK10-NEXT: [[TMP213:%.*]] = load i64, i64* [[CH_CASTED76]], align 8 -// CHECK10-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV79:%.*]] = bitcast i64* [[N_CASTED78]] to i32* -// CHECK10-NEXT: store i32 [[TMP214]], i32* [[CONV79]], align 4 -// CHECK10-NEXT: [[TMP215:%.*]] = load i64, i64* [[N_CASTED78]], align 8 -// CHECK10-NEXT: [[TMP216:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK10-NEXT: [[TMP217:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK10-NEXT: [[TMP218:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK10-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i64* -// CHECK10-NEXT: store i64 [[TMP213]], i64* [[TMP220]], align 8 -// CHECK10-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i64* -// CHECK10-NEXT: store i64 [[TMP213]], i64* [[TMP222]], align 8 -// CHECK10-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP223]], align 8 -// CHECK10-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i64* -// CHECK10-NEXT: store i64 [[TMP215]], i64* [[TMP225]], align 8 -// CHECK10-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i64* -// CHECK10-NEXT: store i64 [[TMP215]], i64* [[TMP227]], align 8 -// CHECK10-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP228]], align 8 -// CHECK10-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to i32** -// CHECK10-NEXT: store i32* [[TMP216]], i32** [[TMP230]], align 8 -// CHECK10-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to i32** -// CHECK10-NEXT: store i32* [[TMP216]], i32** [[TMP232]], align 8 -// CHECK10-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP233]], align 8 -// CHECK10-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to i32** -// CHECK10-NEXT: store i32* [[TMP217]], i32** [[TMP235]], align 8 -// CHECK10-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to i32** -// CHECK10-NEXT: store i32* [[TMP217]], i32** [[TMP237]], align 8 -// CHECK10-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP238]], align 8 -// CHECK10-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to i32** -// CHECK10-NEXT: store i32* [[TMP218]], i32** [[TMP240]], align 8 -// CHECK10-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to i32** -// CHECK10-NEXT: store i32* [[TMP218]], i32** [[TMP242]], align 8 -// CHECK10-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS82]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP243]], align 8 -// CHECK10-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS80]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS81]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_84]], align 4 -// CHECK10-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_84]], align 4 -// CHECK10-NEXT: [[SUB86:%.*]] = sub nsw i32 [[TMP247]], 0 -// CHECK10-NEXT: [[DIV87:%.*]] = sdiv i32 [[SUB86]], 1 -// CHECK10-NEXT: [[SUB88:%.*]] = sub nsw i32 [[DIV87]], 1 -// CHECK10-NEXT: store i32 [[SUB88]], i32* [[DOTCAPTURE_EXPR_85]], align 4 -// CHECK10-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_85]], align 4 -// CHECK10-NEXT: [[ADD89:%.*]] = add nsw i32 [[TMP248]], 1 -// CHECK10-NEXT: [[TMP249:%.*]] = zext i32 [[ADD89]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) -// CHECK10-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.52, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.53, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 -// CHECK10-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED90:%.*]], label [[OMP_OFFLOAD_CONT91:%.*]] -// CHECK10: omp_offload.failed90: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91(i64 [[TMP213]], i64 [[TMP215]], i32* [[TMP216]], i32* [[TMP217]], i32* [[TMP218]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT91]] -// CHECK10: omp_offload.cont91: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP21]], i32 2) -// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK10-NEXT: br i1 [[TMP23]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK10: .cancel.exit: -// CHECK10-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK10: .cancel.continue: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM7]] -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK10-NEXT: [[TMP30:%.*]] = load i32*, i32** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i64 [[IDXPROM10]] -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: cancel.exit: -// CHECK10-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK10-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: br label [[CANCEL_CONT]] -// CHECK10: cancel.cont: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 -// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..31 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK10-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 -// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..34 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..35 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] -// CHECK10-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK10: cond.true10: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END12:%.*]] -// CHECK10: cond.false11: -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END12]] -// CHECK10: cond.end12: -// CHECK10-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE10]] ], [ [[TMP32]], [[COND_FALSE11]] ] -// CHECK10-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK10-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 -// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..38 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..39 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM7]] -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK10-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM10]] -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX11]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..42 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**, i64)* @.omp_outlined..43 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i64 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK10: omp.dispatch.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[CONV7]], [[TMP14]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CONV9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[CONV9]], [[COND_FALSE]] ] -// CHECK10-NEXT: [[CONV10:%.*]] = trunc i64 [[COND]] to i32 -// CHECK10-NEXT: store i32 [[CONV10]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK10: omp.dispatch.body: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK10-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i64 [[IDXPROM13]] -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX14]], align 4 -// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP25]], [[TMP28]] -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK10-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP30]] to i64 -// CHECK10-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i32, i32* [[TMP29]], i64 [[IDXPROM16]] -// CHECK10-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX17]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK10-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK10: omp.dispatch.inc: -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] -// CHECK10-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] -// CHECK10-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK10: omp.dispatch.end: -// CHECK10-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 -// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..46 to void (i32*, i32*, ...)*), i32* [[CONV]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**)* @.omp_outlined..47 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK10: omp.dispatch.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK10: omp.dispatch.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[TMP2]], align 8, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP3]], align 8, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM6]] -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP26]] -// CHECK10-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP1]], align 8, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM9]] -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX10]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK10: omp.dispatch.inc: -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK10: omp.dispatch.end: -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 -// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[CH]], i64* [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[CH_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..50 to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV1]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32**, i32**, i32**, i64)* @.omp_outlined..51 to void (i32*, i32*, ...)*), i64 [[TMP20]], i64 [[TMP22]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i64 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 -// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK10: omp.dispatch.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK10: omp.dispatch.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[TMP2]], align 8, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP22]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32*, i32** [[TMP3]], align 8, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[TMP25]], i64 [[IDXPROM8]] -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP27]] -// CHECK10-NEXT: [[TMP28:%.*]] = load i32*, i32** [[TMP1]], align 8, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[TMP28]], i64 [[IDXPROM11]] -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[ARRAYIDX12]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK10: omp.dispatch.inc: -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK10: omp.dispatch.end: -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[B:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[C:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP7:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CH_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED16:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS17:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS18:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS19:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED29:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP33:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_34:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_35:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CH_CASTED42:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED43:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS44:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS45:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS46:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP47:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_48:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_49:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED56:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS57:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS58:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS59:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP60:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_62:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CH_CASTED69:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED70:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS71:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS72:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS73:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP74:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_76:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double*, double** [[A]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double*, double** [[B]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load double*, double** [[C]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to double** -// CHECK11-NEXT: store double* [[TMP2]], double** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK11-NEXT: store double* [[TMP2]], double** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double** -// CHECK11-NEXT: store double* [[TMP3]], double** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to double** -// CHECK11-NEXT: store double* [[TMP3]], double** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double** -// CHECK11-NEXT: store double* [[TMP4]], double** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double** -// CHECK11-NEXT: store double* [[TMP4]], double** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369(i32 [[TMP1]], double* [[TMP2]], double* [[TMP3]], double* [[TMP4]]) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = load double*, double** [[A]], align 4 -// CHECK11-NEXT: [[TMP36:%.*]] = load double*, double** [[B]], align 4 -// CHECK11-NEXT: [[TMP37:%.*]] = load double*, double** [[C]], align 4 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP39]], align 4 -// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP41]], align 4 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to double** -// CHECK11-NEXT: store double* [[TMP35]], double** [[TMP44]], align 4 -// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to double** -// CHECK11-NEXT: store double* [[TMP35]], double** [[TMP46]], align 4 -// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP47]], align 4 -// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** -// CHECK11-NEXT: store double* [[TMP36]], double** [[TMP49]], align 4 -// CHECK11-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** -// CHECK11-NEXT: store double* [[TMP36]], double** [[TMP51]], align 4 -// CHECK11-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP52]], align 4 -// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** -// CHECK11-NEXT: store double* [[TMP37]], double** [[TMP54]], align 4 -// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to double** -// CHECK11-NEXT: store double* [[TMP37]], double** [[TMP56]], align 4 -// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP57]], align 4 -// CHECK11-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK11-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK11-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP61]], 0 -// CHECK11-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 -// CHECK11-NEXT: [[SUB12:%.*]] = sub nsw i32 [[DIV11]], 1 -// CHECK11-NEXT: store i32 [[SUB12]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP62]], 1 -// CHECK11-NEXT: [[TMP63:%.*]] = zext i32 [[ADD13]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) -// CHECK11-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 -// CHECK11-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] -// CHECK11: omp_offload.failed14: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408(i32 [[TMP34]], double* [[TMP35]], double* [[TMP36]], double* [[TMP37]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT15]] -// CHECK11: omp_offload.cont15: -// CHECK11-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK11-NEXT: store i32 [[TMP66]], i32* [[CH_CASTED]], align 4 -// CHECK11-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH_CASTED]], align 4 -// CHECK11-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP68]], i32* [[N_CASTED16]], align 4 -// CHECK11-NEXT: [[TMP69:%.*]] = load i32, i32* [[N_CASTED16]], align 4 -// CHECK11-NEXT: [[TMP70:%.*]] = load double*, double** [[A]], align 4 -// CHECK11-NEXT: [[TMP71:%.*]] = load double*, double** [[B]], align 4 -// CHECK11-NEXT: [[TMP72:%.*]] = load double*, double** [[C]], align 4 -// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK11-NEXT: store i32 [[TMP67]], i32* [[TMP74]], align 4 -// CHECK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* -// CHECK11-NEXT: store i32 [[TMP67]], i32* [[TMP76]], align 4 -// CHECK11-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP77]], align 4 -// CHECK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK11-NEXT: store i32 [[TMP69]], i32* [[TMP79]], align 4 -// CHECK11-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* -// CHECK11-NEXT: store i32 [[TMP69]], i32* [[TMP81]], align 4 -// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK11-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to double** -// CHECK11-NEXT: store double* [[TMP70]], double** [[TMP84]], align 4 -// CHECK11-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to double** -// CHECK11-NEXT: store double* [[TMP70]], double** [[TMP86]], align 4 -// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP87]], align 4 -// CHECK11-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** -// CHECK11-NEXT: store double* [[TMP71]], double** [[TMP89]], align 4 -// CHECK11-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to double** -// CHECK11-NEXT: store double* [[TMP71]], double** [[TMP91]], align 4 -// CHECK11-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP92]], align 4 -// CHECK11-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** -// CHECK11-NEXT: store double* [[TMP72]], double** [[TMP94]], align 4 -// CHECK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to double** -// CHECK11-NEXT: store double* [[TMP72]], double** [[TMP96]], align 4 -// CHECK11-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP97]], align 4 -// CHECK11-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK11-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK11-NEXT: [[SUB23:%.*]] = sub nsw i32 [[TMP101]], 0 -// CHECK11-NEXT: [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1 -// CHECK11-NEXT: [[SUB25:%.*]] = sub nsw i32 [[DIV24]], 1 -// CHECK11-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK11-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP102]], 1 -// CHECK11-NEXT: [[TMP103:%.*]] = zext i32 [[ADD26]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) -// CHECK11-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 -// CHECK11-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] -// CHECK11: omp_offload.failed27: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447(i32 [[TMP67]], i32 [[TMP69]], double* [[TMP70]], double* [[TMP71]], double* [[TMP72]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT28]] -// CHECK11: omp_offload.cont28: -// CHECK11-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP106]], i32* [[N_CASTED29]], align 4 -// CHECK11-NEXT: [[TMP107:%.*]] = load i32, i32* [[N_CASTED29]], align 4 -// CHECK11-NEXT: [[TMP108:%.*]] = load double*, double** [[A]], align 4 -// CHECK11-NEXT: [[TMP109:%.*]] = load double*, double** [[B]], align 4 -// CHECK11-NEXT: [[TMP110:%.*]] = load double*, double** [[C]], align 4 -// CHECK11-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* -// CHECK11-NEXT: store i32 [[TMP107]], i32* [[TMP112]], align 4 -// CHECK11-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* -// CHECK11-NEXT: store i32 [[TMP107]], i32* [[TMP114]], align 4 -// CHECK11-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP115]], align 4 -// CHECK11-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to double** -// CHECK11-NEXT: store double* [[TMP108]], double** [[TMP117]], align 4 -// CHECK11-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to double** -// CHECK11-NEXT: store double* [[TMP108]], double** [[TMP119]], align 4 -// CHECK11-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP120]], align 4 -// CHECK11-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to double** -// CHECK11-NEXT: store double* [[TMP109]], double** [[TMP122]], align 4 -// CHECK11-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** -// CHECK11-NEXT: store double* [[TMP109]], double** [[TMP124]], align 4 -// CHECK11-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP125]], align 4 -// CHECK11-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** -// CHECK11-NEXT: store double* [[TMP110]], double** [[TMP127]], align 4 -// CHECK11-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** -// CHECK11-NEXT: store double* [[TMP110]], double** [[TMP129]], align 4 -// CHECK11-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP130]], align 4 -// CHECK11-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_34]], align 4 -// CHECK11-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_34]], align 4 -// CHECK11-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP134]], 0 -// CHECK11-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 -// CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i32 [[DIV37]], 1 -// CHECK11-NEXT: store i32 [[SUB38]], i32* [[DOTCAPTURE_EXPR_35]], align 4 -// CHECK11-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_35]], align 4 -// CHECK11-NEXT: [[ADD39:%.*]] = add nsw i32 [[TMP135]], 1 -// CHECK11-NEXT: [[TMP136:%.*]] = zext i32 [[ADD39]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) -// CHECK11-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 -// CHECK11-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED40:%.*]], label [[OMP_OFFLOAD_CONT41:%.*]] -// CHECK11: omp_offload.failed40: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478(i32 [[TMP107]], double* [[TMP108]], double* [[TMP109]], double* [[TMP110]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT41]] -// CHECK11: omp_offload.cont41: -// CHECK11-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK11-NEXT: store i32 [[TMP139]], i32* [[CH_CASTED42]], align 4 -// CHECK11-NEXT: [[TMP140:%.*]] = load i32, i32* [[CH_CASTED42]], align 4 -// CHECK11-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP141]], i32* [[N_CASTED43]], align 4 -// CHECK11-NEXT: [[TMP142:%.*]] = load i32, i32* [[N_CASTED43]], align 4 -// CHECK11-NEXT: [[TMP143:%.*]] = load double*, double** [[A]], align 4 -// CHECK11-NEXT: [[TMP144:%.*]] = load double*, double** [[B]], align 4 -// CHECK11-NEXT: [[TMP145:%.*]] = load double*, double** [[C]], align 4 -// CHECK11-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* -// CHECK11-NEXT: store i32 [[TMP140]], i32* [[TMP147]], align 4 -// CHECK11-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* -// CHECK11-NEXT: store i32 [[TMP140]], i32* [[TMP149]], align 4 -// CHECK11-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP150]], align 4 -// CHECK11-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i32* -// CHECK11-NEXT: store i32 [[TMP142]], i32* [[TMP152]], align 4 -// CHECK11-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i32* -// CHECK11-NEXT: store i32 [[TMP142]], i32* [[TMP154]], align 4 -// CHECK11-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP155]], align 4 -// CHECK11-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to double** -// CHECK11-NEXT: store double* [[TMP143]], double** [[TMP157]], align 4 -// CHECK11-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to double** -// CHECK11-NEXT: store double* [[TMP143]], double** [[TMP159]], align 4 -// CHECK11-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP160]], align 4 -// CHECK11-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to double** -// CHECK11-NEXT: store double* [[TMP144]], double** [[TMP162]], align 4 -// CHECK11-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to double** -// CHECK11-NEXT: store double* [[TMP144]], double** [[TMP164]], align 4 -// CHECK11-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP165]], align 4 -// CHECK11-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to double** -// CHECK11-NEXT: store double* [[TMP145]], double** [[TMP167]], align 4 -// CHECK11-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to double** -// CHECK11-NEXT: store double* [[TMP145]], double** [[TMP169]], align 4 -// CHECK11-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP170]], align 4 -// CHECK11-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_48]], align 4 -// CHECK11-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_48]], align 4 -// CHECK11-NEXT: [[SUB50:%.*]] = sub nsw i32 [[TMP174]], 0 -// CHECK11-NEXT: [[DIV51:%.*]] = sdiv i32 [[SUB50]], 1 -// CHECK11-NEXT: [[SUB52:%.*]] = sub nsw i32 [[DIV51]], 1 -// CHECK11-NEXT: store i32 [[SUB52]], i32* [[DOTCAPTURE_EXPR_49]], align 4 -// CHECK11-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_49]], align 4 -// CHECK11-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP175]], 1 -// CHECK11-NEXT: [[TMP176:%.*]] = zext i32 [[ADD53]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) -// CHECK11-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 -// CHECK11-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED54:%.*]], label [[OMP_OFFLOAD_CONT55:%.*]] -// CHECK11: omp_offload.failed54: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506(i32 [[TMP140]], i32 [[TMP142]], double* [[TMP143]], double* [[TMP144]], double* [[TMP145]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT55]] -// CHECK11: omp_offload.cont55: -// CHECK11-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP179]], i32* [[N_CASTED56]], align 4 -// CHECK11-NEXT: [[TMP180:%.*]] = load i32, i32* [[N_CASTED56]], align 4 -// CHECK11-NEXT: [[TMP181:%.*]] = load double*, double** [[A]], align 4 -// CHECK11-NEXT: [[TMP182:%.*]] = load double*, double** [[B]], align 4 -// CHECK11-NEXT: [[TMP183:%.*]] = load double*, double** [[C]], align 4 -// CHECK11-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i32* -// CHECK11-NEXT: store i32 [[TMP180]], i32* [[TMP185]], align 4 -// CHECK11-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i32* -// CHECK11-NEXT: store i32 [[TMP180]], i32* [[TMP187]], align 4 -// CHECK11-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP188]], align 4 -// CHECK11-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to double** -// CHECK11-NEXT: store double* [[TMP181]], double** [[TMP190]], align 4 -// CHECK11-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to double** -// CHECK11-NEXT: store double* [[TMP181]], double** [[TMP192]], align 4 -// CHECK11-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP193]], align 4 -// CHECK11-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to double** -// CHECK11-NEXT: store double* [[TMP182]], double** [[TMP195]], align 4 -// CHECK11-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to double** -// CHECK11-NEXT: store double* [[TMP182]], double** [[TMP197]], align 4 -// CHECK11-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP198]], align 4 -// CHECK11-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to double** -// CHECK11-NEXT: store double* [[TMP183]], double** [[TMP200]], align 4 -// CHECK11-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to double** -// CHECK11-NEXT: store double* [[TMP183]], double** [[TMP202]], align 4 -// CHECK11-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP203]], align 4 -// CHECK11-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK11-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK11-NEXT: [[SUB63:%.*]] = sub nsw i32 [[TMP207]], 0 -// CHECK11-NEXT: [[DIV64:%.*]] = sdiv i32 [[SUB63]], 1 -// CHECK11-NEXT: [[SUB65:%.*]] = sub nsw i32 [[DIV64]], 1 -// CHECK11-NEXT: store i32 [[SUB65]], i32* [[DOTCAPTURE_EXPR_62]], align 4 -// CHECK11-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_62]], align 4 -// CHECK11-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP208]], 1 -// CHECK11-NEXT: [[TMP209:%.*]] = zext i32 [[ADD66]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) -// CHECK11-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 -// CHECK11-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED67:%.*]], label [[OMP_OFFLOAD_CONT68:%.*]] -// CHECK11: omp_offload.failed67: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536(i32 [[TMP180]], double* [[TMP181]], double* [[TMP182]], double* [[TMP183]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT68]] -// CHECK11: omp_offload.cont68: -// CHECK11-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK11-NEXT: store i32 [[TMP212]], i32* [[CH_CASTED69]], align 4 -// CHECK11-NEXT: [[TMP213:%.*]] = load i32, i32* [[CH_CASTED69]], align 4 -// CHECK11-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP214]], i32* [[N_CASTED70]], align 4 -// CHECK11-NEXT: [[TMP215:%.*]] = load i32, i32* [[N_CASTED70]], align 4 -// CHECK11-NEXT: [[TMP216:%.*]] = load double*, double** [[A]], align 4 -// CHECK11-NEXT: [[TMP217:%.*]] = load double*, double** [[B]], align 4 -// CHECK11-NEXT: [[TMP218:%.*]] = load double*, double** [[C]], align 4 -// CHECK11-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i32* -// CHECK11-NEXT: store i32 [[TMP213]], i32* [[TMP220]], align 4 -// CHECK11-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i32* -// CHECK11-NEXT: store i32 [[TMP213]], i32* [[TMP222]], align 4 -// CHECK11-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP223]], align 4 -// CHECK11-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i32* -// CHECK11-NEXT: store i32 [[TMP215]], i32* [[TMP225]], align 4 -// CHECK11-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i32* -// CHECK11-NEXT: store i32 [[TMP215]], i32* [[TMP227]], align 4 -// CHECK11-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP228]], align 4 -// CHECK11-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to double** -// CHECK11-NEXT: store double* [[TMP216]], double** [[TMP230]], align 4 -// CHECK11-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to double** -// CHECK11-NEXT: store double* [[TMP216]], double** [[TMP232]], align 4 -// CHECK11-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP233]], align 4 -// CHECK11-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to double** -// CHECK11-NEXT: store double* [[TMP217]], double** [[TMP235]], align 4 -// CHECK11-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to double** -// CHECK11-NEXT: store double* [[TMP217]], double** [[TMP237]], align 4 -// CHECK11-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP238]], align 4 -// CHECK11-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to double** -// CHECK11-NEXT: store double* [[TMP218]], double** [[TMP240]], align 4 -// CHECK11-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to double** -// CHECK11-NEXT: store double* [[TMP218]], double** [[TMP242]], align 4 -// CHECK11-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP243]], align 4 -// CHECK11-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK11-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK11-NEXT: [[SUB77:%.*]] = sub nsw i32 [[TMP247]], 0 -// CHECK11-NEXT: [[DIV78:%.*]] = sdiv i32 [[SUB77]], 1 -// CHECK11-NEXT: [[SUB79:%.*]] = sub nsw i32 [[DIV78]], 1 -// CHECK11-NEXT: store i32 [[SUB79]], i32* [[DOTCAPTURE_EXPR_76]], align 4 -// CHECK11-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_76]], align 4 -// CHECK11-NEXT: [[ADD80:%.*]] = add nsw i32 [[TMP248]], 1 -// CHECK11-NEXT: [[TMP249:%.*]] = zext i32 [[ADD80]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) -// CHECK11-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.24, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 -// CHECK11-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED81:%.*]], label [[OMP_OFFLOAD_CONT82:%.*]] -// CHECK11: omp_offload.failed81: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i32 [[TMP213]], i32 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT82]] -// CHECK11: omp_offload.cont82: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: ret i32 [[CALL]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 -// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] -// CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] -// CHECK11-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] -// CHECK11-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 -// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] -// CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] -// CHECK11-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] -// CHECK11-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 -// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] -// CHECK11-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK11: cond.true10: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END12:%.*]] -// CHECK11: cond.false11: -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END12]] -// CHECK11: cond.end12: -// CHECK11-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE10]] ], [ [[TMP30]], [[COND_FALSE11]] ] -// CHECK11-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] -// CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] -// CHECK11-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] -// CHECK11-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 -// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] -// CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] -// CHECK11-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] -// CHECK11-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 -// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK11: omp.dispatch.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp ugt i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK11: omp.dispatch.body: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] -// CHECK11-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] -// CHECK11-NEXT: [[TMP28:%.*]] = load double, double* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[TMP25]], [[TMP28]] -// CHECK11-NEXT: [[TMP29:%.*]] = load double*, double** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP29]], i32 [[TMP30]] -// CHECK11-NEXT: store double [[ADD9]], double* [[ARRAYIDX10]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK11: omp.dispatch.inc: -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] -// CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] -// CHECK11-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK11: omp.dispatch.end: -// CHECK11-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 -// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK11: omp.dispatch.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK11: omp.dispatch.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP21:%.*]] = load double*, double** [[TMP2]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP21]], i32 [[TMP22]] -// CHECK11-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP24:%.*]] = load double*, double** [[TMP3]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds double, double* [[TMP24]], i32 [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX5]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]] -// CHECK11-NEXT: [[TMP27:%.*]] = load double*, double** [[TMP1]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP27]], i32 [[TMP28]] -// CHECK11-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK11: omp.dispatch.inc: -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK11: omp.dispatch.end: -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 -// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**, i32)* @.omp_outlined..23 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK11: omp.dispatch.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 -// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK11: omp.dispatch.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[TMP22:%.*]] = load double*, double** [[TMP2]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP22]], i32 [[TMP23]] -// CHECK11-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[TMP25:%.*]] = load double*, double** [[TMP3]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP25]], i32 [[TMP26]] -// CHECK11-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX6]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]] -// CHECK11-NEXT: [[TMP28:%.*]] = load double*, double** [[TMP1]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP28]], i32 [[TMP29]] -// CHECK11-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK11: omp.dispatch.inc: -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK11: omp.dispatch.end: -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[B:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[C:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP7:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CH_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED16:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS17:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS18:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS19:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED29:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP33:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_34:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_35:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CH_CASTED42:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED43:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS44:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS45:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS46:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP47:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_48:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_49:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED56:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS57:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS58:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS59:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP60:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_62:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CH_CASTED69:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED70:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS71:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS72:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS73:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP74:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_76:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32** -// CHECK11-NEXT: store i32* [[TMP2]], i32** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32** -// CHECK11-NEXT: store i32* [[TMP2]], i32** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32** -// CHECK11-NEXT: store i32* [[TMP3]], i32** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32** -// CHECK11-NEXT: store i32* [[TMP3]], i32** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK11-NEXT: store i32* [[TMP4]], i32** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32** -// CHECK11-NEXT: store i32* [[TMP4]], i32** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP30]]) -// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42(i32 [[TMP1]], i32* [[TMP2]], i32* [[TMP3]], i32* [[TMP4]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK11-NEXT: [[TMP36:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK11-NEXT: [[TMP37:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP39]], align 4 -// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP41]], align 4 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32** -// CHECK11-NEXT: store i32* [[TMP35]], i32** [[TMP44]], align 4 -// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32** -// CHECK11-NEXT: store i32* [[TMP35]], i32** [[TMP46]], align 4 -// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP47]], align 4 -// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK11-NEXT: store i32* [[TMP36]], i32** [[TMP49]], align 4 -// CHECK11-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK11-NEXT: store i32* [[TMP36]], i32** [[TMP51]], align 4 -// CHECK11-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP52]], align 4 -// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32** -// CHECK11-NEXT: store i32* [[TMP37]], i32** [[TMP54]], align 4 -// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32** -// CHECK11-NEXT: store i32* [[TMP37]], i32** [[TMP56]], align 4 -// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP57]], align 4 -// CHECK11-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK11-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK11-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP61]], 0 -// CHECK11-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 -// CHECK11-NEXT: [[SUB12:%.*]] = sub nsw i32 [[DIV11]], 1 -// CHECK11-NEXT: store i32 [[SUB12]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP62]], 1 -// CHECK11-NEXT: [[TMP63:%.*]] = zext i32 [[ADD13]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) -// CHECK11-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.32, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.33, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 -// CHECK11-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] -// CHECK11: omp_offload.failed14: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51(i32 [[TMP34]], i32* [[TMP35]], i32* [[TMP36]], i32* [[TMP37]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT15]] -// CHECK11: omp_offload.cont15: -// CHECK11-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK11-NEXT: store i32 [[TMP66]], i32* [[CH_CASTED]], align 4 -// CHECK11-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH_CASTED]], align 4 -// CHECK11-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP68]], i32* [[N_CASTED16]], align 4 -// CHECK11-NEXT: [[TMP69:%.*]] = load i32, i32* [[N_CASTED16]], align 4 -// CHECK11-NEXT: [[TMP70:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK11-NEXT: [[TMP71:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK11-NEXT: [[TMP72:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK11-NEXT: store i32 [[TMP67]], i32* [[TMP74]], align 4 -// CHECK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* -// CHECK11-NEXT: store i32 [[TMP67]], i32* [[TMP76]], align 4 -// CHECK11-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP77]], align 4 -// CHECK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK11-NEXT: store i32 [[TMP69]], i32* [[TMP79]], align 4 -// CHECK11-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* -// CHECK11-NEXT: store i32 [[TMP69]], i32* [[TMP81]], align 4 -// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK11-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK11-NEXT: store i32* [[TMP70]], i32** [[TMP84]], align 4 -// CHECK11-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** -// CHECK11-NEXT: store i32* [[TMP70]], i32** [[TMP86]], align 4 -// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP87]], align 4 -// CHECK11-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK11-NEXT: store i32* [[TMP71]], i32** [[TMP89]], align 4 -// CHECK11-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** -// CHECK11-NEXT: store i32* [[TMP71]], i32** [[TMP91]], align 4 -// CHECK11-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP92]], align 4 -// CHECK11-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to i32** -// CHECK11-NEXT: store i32* [[TMP72]], i32** [[TMP94]], align 4 -// CHECK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32** -// CHECK11-NEXT: store i32* [[TMP72]], i32** [[TMP96]], align 4 -// CHECK11-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP97]], align 4 -// CHECK11-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK11-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK11-NEXT: [[SUB23:%.*]] = sub nsw i32 [[TMP101]], 0 -// CHECK11-NEXT: [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1 -// CHECK11-NEXT: [[SUB25:%.*]] = sub nsw i32 [[DIV24]], 1 -// CHECK11-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK11-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP102]], 1 -// CHECK11-NEXT: [[TMP103:%.*]] = zext i32 [[ADD26]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) -// CHECK11-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.36, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.37, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 -// CHECK11-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] -// CHECK11: omp_offload.failed27: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59(i32 [[TMP67]], i32 [[TMP69]], i32* [[TMP70]], i32* [[TMP71]], i32* [[TMP72]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT28]] -// CHECK11: omp_offload.cont28: -// CHECK11-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP106]], i32* [[N_CASTED29]], align 4 -// CHECK11-NEXT: [[TMP107:%.*]] = load i32, i32* [[N_CASTED29]], align 4 -// CHECK11-NEXT: [[TMP108:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK11-NEXT: [[TMP109:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK11-NEXT: [[TMP110:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK11-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* -// CHECK11-NEXT: store i32 [[TMP107]], i32* [[TMP112]], align 4 -// CHECK11-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* -// CHECK11-NEXT: store i32 [[TMP107]], i32* [[TMP114]], align 4 -// CHECK11-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP115]], align 4 -// CHECK11-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** -// CHECK11-NEXT: store i32* [[TMP108]], i32** [[TMP117]], align 4 -// CHECK11-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** -// CHECK11-NEXT: store i32* [[TMP108]], i32** [[TMP119]], align 4 -// CHECK11-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP120]], align 4 -// CHECK11-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** -// CHECK11-NEXT: store i32* [[TMP109]], i32** [[TMP122]], align 4 -// CHECK11-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32** -// CHECK11-NEXT: store i32* [[TMP109]], i32** [[TMP124]], align 4 -// CHECK11-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP125]], align 4 -// CHECK11-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32** -// CHECK11-NEXT: store i32* [[TMP110]], i32** [[TMP127]], align 4 -// CHECK11-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32** -// CHECK11-NEXT: store i32* [[TMP110]], i32** [[TMP129]], align 4 -// CHECK11-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP130]], align 4 -// CHECK11-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_34]], align 4 -// CHECK11-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_34]], align 4 -// CHECK11-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP134]], 0 -// CHECK11-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 -// CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i32 [[DIV37]], 1 -// CHECK11-NEXT: store i32 [[SUB38]], i32* [[DOTCAPTURE_EXPR_35]], align 4 -// CHECK11-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_35]], align 4 -// CHECK11-NEXT: [[ADD39:%.*]] = add nsw i32 [[TMP135]], 1 -// CHECK11-NEXT: [[TMP136:%.*]] = zext i32 [[ADD39]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) -// CHECK11-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.40, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.41, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 -// CHECK11-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED40:%.*]], label [[OMP_OFFLOAD_CONT41:%.*]] -// CHECK11: omp_offload.failed40: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67(i32 [[TMP107]], i32* [[TMP108]], i32* [[TMP109]], i32* [[TMP110]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT41]] -// CHECK11: omp_offload.cont41: -// CHECK11-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK11-NEXT: store i32 [[TMP139]], i32* [[CH_CASTED42]], align 4 -// CHECK11-NEXT: [[TMP140:%.*]] = load i32, i32* [[CH_CASTED42]], align 4 -// CHECK11-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP141]], i32* [[N_CASTED43]], align 4 -// CHECK11-NEXT: [[TMP142:%.*]] = load i32, i32* [[N_CASTED43]], align 4 -// CHECK11-NEXT: [[TMP143:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK11-NEXT: [[TMP144:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK11-NEXT: [[TMP145:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK11-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* -// CHECK11-NEXT: store i32 [[TMP140]], i32* [[TMP147]], align 4 -// CHECK11-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* -// CHECK11-NEXT: store i32 [[TMP140]], i32* [[TMP149]], align 4 -// CHECK11-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP150]], align 4 -// CHECK11-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i32* -// CHECK11-NEXT: store i32 [[TMP142]], i32* [[TMP152]], align 4 -// CHECK11-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i32* -// CHECK11-NEXT: store i32 [[TMP142]], i32* [[TMP154]], align 4 -// CHECK11-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP155]], align 4 -// CHECK11-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** -// CHECK11-NEXT: store i32* [[TMP143]], i32** [[TMP157]], align 4 -// CHECK11-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** -// CHECK11-NEXT: store i32* [[TMP143]], i32** [[TMP159]], align 4 -// CHECK11-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP160]], align 4 -// CHECK11-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32** -// CHECK11-NEXT: store i32* [[TMP144]], i32** [[TMP162]], align 4 -// CHECK11-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32** -// CHECK11-NEXT: store i32* [[TMP144]], i32** [[TMP164]], align 4 -// CHECK11-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP165]], align 4 -// CHECK11-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to i32** -// CHECK11-NEXT: store i32* [[TMP145]], i32** [[TMP167]], align 4 -// CHECK11-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to i32** -// CHECK11-NEXT: store i32* [[TMP145]], i32** [[TMP169]], align 4 -// CHECK11-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP170]], align 4 -// CHECK11-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_48]], align 4 -// CHECK11-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_48]], align 4 -// CHECK11-NEXT: [[SUB50:%.*]] = sub nsw i32 [[TMP174]], 0 -// CHECK11-NEXT: [[DIV51:%.*]] = sdiv i32 [[SUB50]], 1 -// CHECK11-NEXT: [[SUB52:%.*]] = sub nsw i32 [[DIV51]], 1 -// CHECK11-NEXT: store i32 [[SUB52]], i32* [[DOTCAPTURE_EXPR_49]], align 4 -// CHECK11-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_49]], align 4 -// CHECK11-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP175]], 1 -// CHECK11-NEXT: [[TMP176:%.*]] = zext i32 [[ADD53]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) -// CHECK11-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.44, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.45, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 -// CHECK11-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED54:%.*]], label [[OMP_OFFLOAD_CONT55:%.*]] -// CHECK11: omp_offload.failed54: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32 [[TMP140]], i32 [[TMP142]], i32* [[TMP143]], i32* [[TMP144]], i32* [[TMP145]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT55]] -// CHECK11: omp_offload.cont55: -// CHECK11-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP179]], i32* [[N_CASTED56]], align 4 -// CHECK11-NEXT: [[TMP180:%.*]] = load i32, i32* [[N_CASTED56]], align 4 -// CHECK11-NEXT: [[TMP181:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK11-NEXT: [[TMP182:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK11-NEXT: [[TMP183:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK11-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i32* -// CHECK11-NEXT: store i32 [[TMP180]], i32* [[TMP185]], align 4 -// CHECK11-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i32* -// CHECK11-NEXT: store i32 [[TMP180]], i32* [[TMP187]], align 4 -// CHECK11-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP188]], align 4 -// CHECK11-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to i32** -// CHECK11-NEXT: store i32* [[TMP181]], i32** [[TMP190]], align 4 -// CHECK11-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to i32** -// CHECK11-NEXT: store i32* [[TMP181]], i32** [[TMP192]], align 4 -// CHECK11-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP193]], align 4 -// CHECK11-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to i32** -// CHECK11-NEXT: store i32* [[TMP182]], i32** [[TMP195]], align 4 -// CHECK11-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to i32** -// CHECK11-NEXT: store i32* [[TMP182]], i32** [[TMP197]], align 4 -// CHECK11-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP198]], align 4 -// CHECK11-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to i32** -// CHECK11-NEXT: store i32* [[TMP183]], i32** [[TMP200]], align 4 -// CHECK11-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to i32** -// CHECK11-NEXT: store i32* [[TMP183]], i32** [[TMP202]], align 4 -// CHECK11-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP203]], align 4 -// CHECK11-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK11-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK11-NEXT: [[SUB63:%.*]] = sub nsw i32 [[TMP207]], 0 -// CHECK11-NEXT: [[DIV64:%.*]] = sdiv i32 [[SUB63]], 1 -// CHECK11-NEXT: [[SUB65:%.*]] = sub nsw i32 [[DIV64]], 1 -// CHECK11-NEXT: store i32 [[SUB65]], i32* [[DOTCAPTURE_EXPR_62]], align 4 -// CHECK11-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_62]], align 4 -// CHECK11-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP208]], 1 -// CHECK11-NEXT: [[TMP209:%.*]] = zext i32 [[ADD66]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) -// CHECK11-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.48, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.49, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 -// CHECK11-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED67:%.*]], label [[OMP_OFFLOAD_CONT68:%.*]] -// CHECK11: omp_offload.failed67: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83(i32 [[TMP180]], i32* [[TMP181]], i32* [[TMP182]], i32* [[TMP183]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT68]] -// CHECK11: omp_offload.cont68: -// CHECK11-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK11-NEXT: store i32 [[TMP212]], i32* [[CH_CASTED69]], align 4 -// CHECK11-NEXT: [[TMP213:%.*]] = load i32, i32* [[CH_CASTED69]], align 4 -// CHECK11-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP214]], i32* [[N_CASTED70]], align 4 -// CHECK11-NEXT: [[TMP215:%.*]] = load i32, i32* [[N_CASTED70]], align 4 -// CHECK11-NEXT: [[TMP216:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK11-NEXT: [[TMP217:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK11-NEXT: [[TMP218:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK11-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i32* -// CHECK11-NEXT: store i32 [[TMP213]], i32* [[TMP220]], align 4 -// CHECK11-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i32* -// CHECK11-NEXT: store i32 [[TMP213]], i32* [[TMP222]], align 4 -// CHECK11-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP223]], align 4 -// CHECK11-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i32* -// CHECK11-NEXT: store i32 [[TMP215]], i32* [[TMP225]], align 4 -// CHECK11-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i32* -// CHECK11-NEXT: store i32 [[TMP215]], i32* [[TMP227]], align 4 -// CHECK11-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP228]], align 4 -// CHECK11-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to i32** -// CHECK11-NEXT: store i32* [[TMP216]], i32** [[TMP230]], align 4 -// CHECK11-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to i32** -// CHECK11-NEXT: store i32* [[TMP216]], i32** [[TMP232]], align 4 -// CHECK11-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP233]], align 4 -// CHECK11-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to i32** -// CHECK11-NEXT: store i32* [[TMP217]], i32** [[TMP235]], align 4 -// CHECK11-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to i32** -// CHECK11-NEXT: store i32* [[TMP217]], i32** [[TMP237]], align 4 -// CHECK11-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP238]], align 4 -// CHECK11-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to i32** -// CHECK11-NEXT: store i32* [[TMP218]], i32** [[TMP240]], align 4 -// CHECK11-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to i32** -// CHECK11-NEXT: store i32* [[TMP218]], i32** [[TMP242]], align 4 -// CHECK11-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP243]], align 4 -// CHECK11-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK11-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK11-NEXT: [[SUB77:%.*]] = sub nsw i32 [[TMP247]], 0 -// CHECK11-NEXT: [[DIV78:%.*]] = sdiv i32 [[SUB77]], 1 -// CHECK11-NEXT: [[SUB79:%.*]] = sub nsw i32 [[DIV78]], 1 -// CHECK11-NEXT: store i32 [[SUB79]], i32* [[DOTCAPTURE_EXPR_76]], align 4 -// CHECK11-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_76]], align 4 -// CHECK11-NEXT: [[ADD80:%.*]] = add nsw i32 [[TMP248]], 1 -// CHECK11-NEXT: [[TMP249:%.*]] = zext i32 [[ADD80]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) -// CHECK11-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.52, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.53, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 -// CHECK11-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED81:%.*]], label [[OMP_OFFLOAD_CONT82:%.*]] -// CHECK11: omp_offload.failed81: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91(i32 [[TMP213]], i32 [[TMP215]], i32* [[TMP216]], i32* [[TMP217]], i32* [[TMP218]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT82]] -// CHECK11: omp_offload.cont82: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP21]], i32 2) -// CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK11-NEXT: br i1 [[TMP23]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK11: .cancel.exit: -// CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK11: .cancel.continue: -// CHECK11-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK11-NEXT: [[TMP30:%.*]] = load i32*, i32** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i32 [[TMP31]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: cancel.exit: -// CHECK11-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK11-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: br label [[CANCEL_CONT]] -// CHECK11: cancel.cont: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 -// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..31 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 -// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..34 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..35 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] -// CHECK11-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK11: cond.true10: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END12:%.*]] -// CHECK11: cond.false11: -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END12]] -// CHECK11: cond.end12: -// CHECK11-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE10]] ], [ [[TMP30]], [[COND_FALSE11]] ] -// CHECK11-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 -// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..38 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..39 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..42 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**, i32)* @.omp_outlined..43 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK11: omp.dispatch.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp ugt i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK11: omp.dispatch.body: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP28]] -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP29]], i32 [[TMP30]] -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX10]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK11: omp.dispatch.inc: -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] -// CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] -// CHECK11-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK11: omp.dispatch.end: -// CHECK11-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 -// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..46 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..47 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK11: omp.dispatch.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK11: omp.dispatch.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[TMP2]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i32 [[TMP22]] -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP3]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX5]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP26]] -// CHECK11-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP1]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX7]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK11: omp.dispatch.inc: -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK11: omp.dispatch.end: -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 -// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..50 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**, i32)* @.omp_outlined..51 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK11: omp.dispatch.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 -// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK11: omp.dispatch.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[TMP2]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP22]], i32 [[TMP23]] -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[TMP3]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP25]], i32 [[TMP26]] -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], [[TMP27]] -// CHECK11-NEXT: [[TMP28:%.*]] = load i32*, i32** [[TMP1]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP28]], i32 [[TMP29]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK11: omp.dispatch.inc: -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK11: omp.dispatch.end: -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[B:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[C:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP7:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[CH_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED16:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS17:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS18:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS19:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED29:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP33:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_34:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_35:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[CH_CASTED42:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED43:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS44:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS45:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS46:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP47:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_48:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_49:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED56:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS57:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS58:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS59:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP60:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_62:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[CH_CASTED69:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED70:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS71:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS72:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS73:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP74:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_76:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double*, double** [[A]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double*, double** [[B]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load double*, double** [[C]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to double** -// CHECK12-NEXT: store double* [[TMP2]], double** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK12-NEXT: store double* [[TMP2]], double** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double** -// CHECK12-NEXT: store double* [[TMP3]], double** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to double** -// CHECK12-NEXT: store double* [[TMP3]], double** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double** -// CHECK12-NEXT: store double* [[TMP4]], double** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double** -// CHECK12-NEXT: store double* [[TMP4]], double** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369(i32 [[TMP1]], double* [[TMP2]], double* [[TMP3]], double* [[TMP4]]) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = load double*, double** [[A]], align 4 -// CHECK12-NEXT: [[TMP36:%.*]] = load double*, double** [[B]], align 4 -// CHECK12-NEXT: [[TMP37:%.*]] = load double*, double** [[C]], align 4 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP39]], align 4 -// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP41]], align 4 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to double** -// CHECK12-NEXT: store double* [[TMP35]], double** [[TMP44]], align 4 -// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to double** -// CHECK12-NEXT: store double* [[TMP35]], double** [[TMP46]], align 4 -// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP47]], align 4 -// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** -// CHECK12-NEXT: store double* [[TMP36]], double** [[TMP49]], align 4 -// CHECK12-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** -// CHECK12-NEXT: store double* [[TMP36]], double** [[TMP51]], align 4 -// CHECK12-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP52]], align 4 -// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** -// CHECK12-NEXT: store double* [[TMP37]], double** [[TMP54]], align 4 -// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to double** -// CHECK12-NEXT: store double* [[TMP37]], double** [[TMP56]], align 4 -// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP57]], align 4 -// CHECK12-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK12-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK12-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP61]], 0 -// CHECK12-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 -// CHECK12-NEXT: [[SUB12:%.*]] = sub nsw i32 [[DIV11]], 1 -// CHECK12-NEXT: store i32 [[SUB12]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP62]], 1 -// CHECK12-NEXT: [[TMP63:%.*]] = zext i32 [[ADD13]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) -// CHECK12-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 -// CHECK12-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] -// CHECK12: omp_offload.failed14: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408(i32 [[TMP34]], double* [[TMP35]], double* [[TMP36]], double* [[TMP37]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT15]] -// CHECK12: omp_offload.cont15: -// CHECK12-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK12-NEXT: store i32 [[TMP66]], i32* [[CH_CASTED]], align 4 -// CHECK12-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH_CASTED]], align 4 -// CHECK12-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP68]], i32* [[N_CASTED16]], align 4 -// CHECK12-NEXT: [[TMP69:%.*]] = load i32, i32* [[N_CASTED16]], align 4 -// CHECK12-NEXT: [[TMP70:%.*]] = load double*, double** [[A]], align 4 -// CHECK12-NEXT: [[TMP71:%.*]] = load double*, double** [[B]], align 4 -// CHECK12-NEXT: [[TMP72:%.*]] = load double*, double** [[C]], align 4 -// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK12-NEXT: store i32 [[TMP67]], i32* [[TMP74]], align 4 -// CHECK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* -// CHECK12-NEXT: store i32 [[TMP67]], i32* [[TMP76]], align 4 -// CHECK12-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP77]], align 4 -// CHECK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK12-NEXT: store i32 [[TMP69]], i32* [[TMP79]], align 4 -// CHECK12-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* -// CHECK12-NEXT: store i32 [[TMP69]], i32* [[TMP81]], align 4 -// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK12-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to double** -// CHECK12-NEXT: store double* [[TMP70]], double** [[TMP84]], align 4 -// CHECK12-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to double** -// CHECK12-NEXT: store double* [[TMP70]], double** [[TMP86]], align 4 -// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP87]], align 4 -// CHECK12-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** -// CHECK12-NEXT: store double* [[TMP71]], double** [[TMP89]], align 4 -// CHECK12-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to double** -// CHECK12-NEXT: store double* [[TMP71]], double** [[TMP91]], align 4 -// CHECK12-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP92]], align 4 -// CHECK12-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** -// CHECK12-NEXT: store double* [[TMP72]], double** [[TMP94]], align 4 -// CHECK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to double** -// CHECK12-NEXT: store double* [[TMP72]], double** [[TMP96]], align 4 -// CHECK12-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP97]], align 4 -// CHECK12-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK12-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK12-NEXT: [[SUB23:%.*]] = sub nsw i32 [[TMP101]], 0 -// CHECK12-NEXT: [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1 -// CHECK12-NEXT: [[SUB25:%.*]] = sub nsw i32 [[DIV24]], 1 -// CHECK12-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK12-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK12-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP102]], 1 -// CHECK12-NEXT: [[TMP103:%.*]] = zext i32 [[ADD26]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) -// CHECK12-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 -// CHECK12-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] -// CHECK12: omp_offload.failed27: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447(i32 [[TMP67]], i32 [[TMP69]], double* [[TMP70]], double* [[TMP71]], double* [[TMP72]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT28]] -// CHECK12: omp_offload.cont28: -// CHECK12-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP106]], i32* [[N_CASTED29]], align 4 -// CHECK12-NEXT: [[TMP107:%.*]] = load i32, i32* [[N_CASTED29]], align 4 -// CHECK12-NEXT: [[TMP108:%.*]] = load double*, double** [[A]], align 4 -// CHECK12-NEXT: [[TMP109:%.*]] = load double*, double** [[B]], align 4 -// CHECK12-NEXT: [[TMP110:%.*]] = load double*, double** [[C]], align 4 -// CHECK12-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* -// CHECK12-NEXT: store i32 [[TMP107]], i32* [[TMP112]], align 4 -// CHECK12-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* -// CHECK12-NEXT: store i32 [[TMP107]], i32* [[TMP114]], align 4 -// CHECK12-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP115]], align 4 -// CHECK12-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to double** -// CHECK12-NEXT: store double* [[TMP108]], double** [[TMP117]], align 4 -// CHECK12-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to double** -// CHECK12-NEXT: store double* [[TMP108]], double** [[TMP119]], align 4 -// CHECK12-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP120]], align 4 -// CHECK12-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to double** -// CHECK12-NEXT: store double* [[TMP109]], double** [[TMP122]], align 4 -// CHECK12-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** -// CHECK12-NEXT: store double* [[TMP109]], double** [[TMP124]], align 4 -// CHECK12-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP125]], align 4 -// CHECK12-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** -// CHECK12-NEXT: store double* [[TMP110]], double** [[TMP127]], align 4 -// CHECK12-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** -// CHECK12-NEXT: store double* [[TMP110]], double** [[TMP129]], align 4 -// CHECK12-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP130]], align 4 -// CHECK12-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_34]], align 4 -// CHECK12-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_34]], align 4 -// CHECK12-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP134]], 0 -// CHECK12-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 -// CHECK12-NEXT: [[SUB38:%.*]] = sub nsw i32 [[DIV37]], 1 -// CHECK12-NEXT: store i32 [[SUB38]], i32* [[DOTCAPTURE_EXPR_35]], align 4 -// CHECK12-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_35]], align 4 -// CHECK12-NEXT: [[ADD39:%.*]] = add nsw i32 [[TMP135]], 1 -// CHECK12-NEXT: [[TMP136:%.*]] = zext i32 [[ADD39]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) -// CHECK12-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 -// CHECK12-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED40:%.*]], label [[OMP_OFFLOAD_CONT41:%.*]] -// CHECK12: omp_offload.failed40: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478(i32 [[TMP107]], double* [[TMP108]], double* [[TMP109]], double* [[TMP110]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT41]] -// CHECK12: omp_offload.cont41: -// CHECK12-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK12-NEXT: store i32 [[TMP139]], i32* [[CH_CASTED42]], align 4 -// CHECK12-NEXT: [[TMP140:%.*]] = load i32, i32* [[CH_CASTED42]], align 4 -// CHECK12-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP141]], i32* [[N_CASTED43]], align 4 -// CHECK12-NEXT: [[TMP142:%.*]] = load i32, i32* [[N_CASTED43]], align 4 -// CHECK12-NEXT: [[TMP143:%.*]] = load double*, double** [[A]], align 4 -// CHECK12-NEXT: [[TMP144:%.*]] = load double*, double** [[B]], align 4 -// CHECK12-NEXT: [[TMP145:%.*]] = load double*, double** [[C]], align 4 -// CHECK12-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* -// CHECK12-NEXT: store i32 [[TMP140]], i32* [[TMP147]], align 4 -// CHECK12-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* -// CHECK12-NEXT: store i32 [[TMP140]], i32* [[TMP149]], align 4 -// CHECK12-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP150]], align 4 -// CHECK12-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i32* -// CHECK12-NEXT: store i32 [[TMP142]], i32* [[TMP152]], align 4 -// CHECK12-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i32* -// CHECK12-NEXT: store i32 [[TMP142]], i32* [[TMP154]], align 4 -// CHECK12-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP155]], align 4 -// CHECK12-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to double** -// CHECK12-NEXT: store double* [[TMP143]], double** [[TMP157]], align 4 -// CHECK12-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to double** -// CHECK12-NEXT: store double* [[TMP143]], double** [[TMP159]], align 4 -// CHECK12-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP160]], align 4 -// CHECK12-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to double** -// CHECK12-NEXT: store double* [[TMP144]], double** [[TMP162]], align 4 -// CHECK12-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to double** -// CHECK12-NEXT: store double* [[TMP144]], double** [[TMP164]], align 4 -// CHECK12-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP165]], align 4 -// CHECK12-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to double** -// CHECK12-NEXT: store double* [[TMP145]], double** [[TMP167]], align 4 -// CHECK12-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to double** -// CHECK12-NEXT: store double* [[TMP145]], double** [[TMP169]], align 4 -// CHECK12-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP170]], align 4 -// CHECK12-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_48]], align 4 -// CHECK12-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_48]], align 4 -// CHECK12-NEXT: [[SUB50:%.*]] = sub nsw i32 [[TMP174]], 0 -// CHECK12-NEXT: [[DIV51:%.*]] = sdiv i32 [[SUB50]], 1 -// CHECK12-NEXT: [[SUB52:%.*]] = sub nsw i32 [[DIV51]], 1 -// CHECK12-NEXT: store i32 [[SUB52]], i32* [[DOTCAPTURE_EXPR_49]], align 4 -// CHECK12-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_49]], align 4 -// CHECK12-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP175]], 1 -// CHECK12-NEXT: [[TMP176:%.*]] = zext i32 [[ADD53]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) -// CHECK12-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 -// CHECK12-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED54:%.*]], label [[OMP_OFFLOAD_CONT55:%.*]] -// CHECK12: omp_offload.failed54: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506(i32 [[TMP140]], i32 [[TMP142]], double* [[TMP143]], double* [[TMP144]], double* [[TMP145]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT55]] -// CHECK12: omp_offload.cont55: -// CHECK12-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP179]], i32* [[N_CASTED56]], align 4 -// CHECK12-NEXT: [[TMP180:%.*]] = load i32, i32* [[N_CASTED56]], align 4 -// CHECK12-NEXT: [[TMP181:%.*]] = load double*, double** [[A]], align 4 -// CHECK12-NEXT: [[TMP182:%.*]] = load double*, double** [[B]], align 4 -// CHECK12-NEXT: [[TMP183:%.*]] = load double*, double** [[C]], align 4 -// CHECK12-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i32* -// CHECK12-NEXT: store i32 [[TMP180]], i32* [[TMP185]], align 4 -// CHECK12-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i32* -// CHECK12-NEXT: store i32 [[TMP180]], i32* [[TMP187]], align 4 -// CHECK12-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP188]], align 4 -// CHECK12-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to double** -// CHECK12-NEXT: store double* [[TMP181]], double** [[TMP190]], align 4 -// CHECK12-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to double** -// CHECK12-NEXT: store double* [[TMP181]], double** [[TMP192]], align 4 -// CHECK12-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP193]], align 4 -// CHECK12-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to double** -// CHECK12-NEXT: store double* [[TMP182]], double** [[TMP195]], align 4 -// CHECK12-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to double** -// CHECK12-NEXT: store double* [[TMP182]], double** [[TMP197]], align 4 -// CHECK12-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP198]], align 4 -// CHECK12-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to double** -// CHECK12-NEXT: store double* [[TMP183]], double** [[TMP200]], align 4 -// CHECK12-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to double** -// CHECK12-NEXT: store double* [[TMP183]], double** [[TMP202]], align 4 -// CHECK12-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP203]], align 4 -// CHECK12-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK12-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK12-NEXT: [[SUB63:%.*]] = sub nsw i32 [[TMP207]], 0 -// CHECK12-NEXT: [[DIV64:%.*]] = sdiv i32 [[SUB63]], 1 -// CHECK12-NEXT: [[SUB65:%.*]] = sub nsw i32 [[DIV64]], 1 -// CHECK12-NEXT: store i32 [[SUB65]], i32* [[DOTCAPTURE_EXPR_62]], align 4 -// CHECK12-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_62]], align 4 -// CHECK12-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP208]], 1 -// CHECK12-NEXT: [[TMP209:%.*]] = zext i32 [[ADD66]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) -// CHECK12-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 -// CHECK12-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED67:%.*]], label [[OMP_OFFLOAD_CONT68:%.*]] -// CHECK12: omp_offload.failed67: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536(i32 [[TMP180]], double* [[TMP181]], double* [[TMP182]], double* [[TMP183]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT68]] -// CHECK12: omp_offload.cont68: -// CHECK12-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK12-NEXT: store i32 [[TMP212]], i32* [[CH_CASTED69]], align 4 -// CHECK12-NEXT: [[TMP213:%.*]] = load i32, i32* [[CH_CASTED69]], align 4 -// CHECK12-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP214]], i32* [[N_CASTED70]], align 4 -// CHECK12-NEXT: [[TMP215:%.*]] = load i32, i32* [[N_CASTED70]], align 4 -// CHECK12-NEXT: [[TMP216:%.*]] = load double*, double** [[A]], align 4 -// CHECK12-NEXT: [[TMP217:%.*]] = load double*, double** [[B]], align 4 -// CHECK12-NEXT: [[TMP218:%.*]] = load double*, double** [[C]], align 4 -// CHECK12-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i32* -// CHECK12-NEXT: store i32 [[TMP213]], i32* [[TMP220]], align 4 -// CHECK12-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i32* -// CHECK12-NEXT: store i32 [[TMP213]], i32* [[TMP222]], align 4 -// CHECK12-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP223]], align 4 -// CHECK12-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i32* -// CHECK12-NEXT: store i32 [[TMP215]], i32* [[TMP225]], align 4 -// CHECK12-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i32* -// CHECK12-NEXT: store i32 [[TMP215]], i32* [[TMP227]], align 4 -// CHECK12-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP228]], align 4 -// CHECK12-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to double** -// CHECK12-NEXT: store double* [[TMP216]], double** [[TMP230]], align 4 -// CHECK12-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to double** -// CHECK12-NEXT: store double* [[TMP216]], double** [[TMP232]], align 4 -// CHECK12-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP233]], align 4 -// CHECK12-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to double** -// CHECK12-NEXT: store double* [[TMP217]], double** [[TMP235]], align 4 -// CHECK12-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to double** -// CHECK12-NEXT: store double* [[TMP217]], double** [[TMP237]], align 4 -// CHECK12-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP238]], align 4 -// CHECK12-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to double** -// CHECK12-NEXT: store double* [[TMP218]], double** [[TMP240]], align 4 -// CHECK12-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to double** -// CHECK12-NEXT: store double* [[TMP218]], double** [[TMP242]], align 4 -// CHECK12-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP243]], align 4 -// CHECK12-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK12-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK12-NEXT: [[SUB77:%.*]] = sub nsw i32 [[TMP247]], 0 -// CHECK12-NEXT: [[DIV78:%.*]] = sdiv i32 [[SUB77]], 1 -// CHECK12-NEXT: [[SUB79:%.*]] = sub nsw i32 [[DIV78]], 1 -// CHECK12-NEXT: store i32 [[SUB79]], i32* [[DOTCAPTURE_EXPR_76]], align 4 -// CHECK12-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_76]], align 4 -// CHECK12-NEXT: [[ADD80:%.*]] = add nsw i32 [[TMP248]], 1 -// CHECK12-NEXT: [[TMP249:%.*]] = zext i32 [[ADD80]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) -// CHECK12-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.24, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 -// CHECK12-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED81:%.*]], label [[OMP_OFFLOAD_CONT82:%.*]] -// CHECK12: omp_offload.failed81: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i32 [[TMP213]], i32 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT82]] -// CHECK12: omp_offload.cont82: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: ret i32 [[CALL]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 -// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] -// CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] -// CHECK12-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] -// CHECK12-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 -// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] -// CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] -// CHECK12-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] -// CHECK12-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 -// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] -// CHECK12-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK12: cond.true10: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END12:%.*]] -// CHECK12: cond.false11: -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END12]] -// CHECK12: cond.end12: -// CHECK12-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE10]] ], [ [[TMP30]], [[COND_FALSE11]] ] -// CHECK12-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] -// CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] -// CHECK12-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] -// CHECK12-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 -// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load double*, double** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP20]], i32 [[TMP21]] -// CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] -// CHECK12-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX6]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = fadd double [[TMP22]], [[TMP25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] -// CHECK12-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 -// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK12: omp.dispatch.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp ugt i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK12: omp.dispatch.body: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load double*, double** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP23]], i32 [[TMP24]] -// CHECK12-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load double*, double** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP26]], i32 [[TMP27]] -// CHECK12-NEXT: [[TMP28:%.*]] = load double, double* [[ARRAYIDX8]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = fadd double [[TMP25]], [[TMP28]] -// CHECK12-NEXT: [[TMP29:%.*]] = load double*, double** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP29]], i32 [[TMP30]] -// CHECK12-NEXT: store double [[ADD9]], double* [[ARRAYIDX10]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] -// CHECK12-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] -// CHECK12-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 -// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], double** [[TMP1]], double** [[TMP2]], double** [[TMP3]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK12: omp.dispatch.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK12: omp.dispatch.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP21:%.*]] = load double*, double** [[TMP2]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP21]], i32 [[TMP22]] -// CHECK12-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP24:%.*]] = load double*, double** [[TMP3]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds double, double* [[TMP24]], i32 [[TMP25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX5]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]] -// CHECK12-NEXT: [[TMP27:%.*]] = load double*, double** [[TMP1]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP27]], i32 [[TMP28]] -// CHECK12-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 -// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double* [[B]], double** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double* [[C]], double** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, double**, double**, double**)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], double** [[A_ADDR]], double** [[B_ADDR]], double** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, double**, double**, double**, i32)* @.omp_outlined..23 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], double** [[TMP2]], double** [[TMP3]], double** [[TMP4]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca double**, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store double** [[A]], double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store double** [[B]], double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store double** [[C]], double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load double**, double*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load double**, double*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load double**, double*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK12: omp.dispatch.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 -// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK12: omp.dispatch.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[TMP22:%.*]] = load double*, double** [[TMP2]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP22]], i32 [[TMP23]] -// CHECK12-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[TMP25:%.*]] = load double*, double** [[TMP3]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[TMP25]], i32 [[TMP26]] -// CHECK12-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX6]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]] -// CHECK12-NEXT: [[TMP28:%.*]] = load double*, double** [[TMP1]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP28]], i32 [[TMP29]] -// CHECK12-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[B:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[C:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP7:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[CH_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED16:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS17:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS18:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS19:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED29:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP33:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_34:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_35:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[CH_CASTED42:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED43:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS44:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS45:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS46:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP47:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_48:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_49:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED56:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS57:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS58:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS59:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP60:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_62:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[CH_CASTED69:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED70:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS71:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS72:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS73:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP74:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_76:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32** -// CHECK12-NEXT: store i32* [[TMP2]], i32** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32** -// CHECK12-NEXT: store i32* [[TMP2]], i32** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32** -// CHECK12-NEXT: store i32* [[TMP3]], i32** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32** -// CHECK12-NEXT: store i32* [[TMP3]], i32** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK12-NEXT: store i32* [[TMP4]], i32** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32** -// CHECK12-NEXT: store i32* [[TMP4]], i32** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP30]]) -// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42(i32 [[TMP1]], i32* [[TMP2]], i32* [[TMP3]], i32* [[TMP4]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK12-NEXT: [[TMP36:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK12-NEXT: [[TMP37:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP39]], align 4 -// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP41]], align 4 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32** -// CHECK12-NEXT: store i32* [[TMP35]], i32** [[TMP44]], align 4 -// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32** -// CHECK12-NEXT: store i32* [[TMP35]], i32** [[TMP46]], align 4 -// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP47]], align 4 -// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK12-NEXT: store i32* [[TMP36]], i32** [[TMP49]], align 4 -// CHECK12-NEXT: [[TMP50:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK12-NEXT: store i32* [[TMP36]], i32** [[TMP51]], align 4 -// CHECK12-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP52]], align 4 -// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32** -// CHECK12-NEXT: store i32* [[TMP37]], i32** [[TMP54]], align 4 -// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32** -// CHECK12-NEXT: store i32* [[TMP37]], i32** [[TMP56]], align 4 -// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP57]], align 4 -// CHECK12-NEXT: [[TMP58:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP59:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP60:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP60]], i32* [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK12-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK12-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP61]], 0 -// CHECK12-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 -// CHECK12-NEXT: [[SUB12:%.*]] = sub nsw i32 [[DIV11]], 1 -// CHECK12-NEXT: store i32 [[SUB12]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP62]], 1 -// CHECK12-NEXT: [[TMP63:%.*]] = zext i32 [[ADD13]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP63]]) -// CHECK12-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51.region_id, i32 4, i8** [[TMP58]], i8** [[TMP59]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.32, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.33, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 -// CHECK12-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] -// CHECK12: omp_offload.failed14: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51(i32 [[TMP34]], i32* [[TMP35]], i32* [[TMP36]], i32* [[TMP37]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT15]] -// CHECK12: omp_offload.cont15: -// CHECK12-NEXT: [[TMP66:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK12-NEXT: store i32 [[TMP66]], i32* [[CH_CASTED]], align 4 -// CHECK12-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH_CASTED]], align 4 -// CHECK12-NEXT: [[TMP68:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP68]], i32* [[N_CASTED16]], align 4 -// CHECK12-NEXT: [[TMP69:%.*]] = load i32, i32* [[N_CASTED16]], align 4 -// CHECK12-NEXT: [[TMP70:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK12-NEXT: [[TMP71:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK12-NEXT: [[TMP72:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK12-NEXT: store i32 [[TMP67]], i32* [[TMP74]], align 4 -// CHECK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* -// CHECK12-NEXT: store i32 [[TMP67]], i32* [[TMP76]], align 4 -// CHECK12-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP77]], align 4 -// CHECK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK12-NEXT: store i32 [[TMP69]], i32* [[TMP79]], align 4 -// CHECK12-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* -// CHECK12-NEXT: store i32 [[TMP69]], i32* [[TMP81]], align 4 -// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK12-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK12-NEXT: store i32* [[TMP70]], i32** [[TMP84]], align 4 -// CHECK12-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** -// CHECK12-NEXT: store i32* [[TMP70]], i32** [[TMP86]], align 4 -// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP87]], align 4 -// CHECK12-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK12-NEXT: store i32* [[TMP71]], i32** [[TMP89]], align 4 -// CHECK12-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** -// CHECK12-NEXT: store i32* [[TMP71]], i32** [[TMP91]], align 4 -// CHECK12-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP92]], align 4 -// CHECK12-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to i32** -// CHECK12-NEXT: store i32* [[TMP72]], i32** [[TMP94]], align 4 -// CHECK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32** -// CHECK12-NEXT: store i32* [[TMP72]], i32** [[TMP96]], align 4 -// CHECK12-NEXT: [[TMP97:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP97]], align 4 -// CHECK12-NEXT: [[TMP98:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP99:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP100:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP100]], i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK12-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 -// CHECK12-NEXT: [[SUB23:%.*]] = sub nsw i32 [[TMP101]], 0 -// CHECK12-NEXT: [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1 -// CHECK12-NEXT: [[SUB25:%.*]] = sub nsw i32 [[DIV24]], 1 -// CHECK12-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK12-NEXT: [[TMP102:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK12-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP102]], 1 -// CHECK12-NEXT: [[TMP103:%.*]] = zext i32 [[ADD26]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP103]]) -// CHECK12-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59.region_id, i32 5, i8** [[TMP98]], i8** [[TMP99]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.36, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.37, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0 -// CHECK12-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] -// CHECK12: omp_offload.failed27: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59(i32 [[TMP67]], i32 [[TMP69]], i32* [[TMP70]], i32* [[TMP71]], i32* [[TMP72]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT28]] -// CHECK12: omp_offload.cont28: -// CHECK12-NEXT: [[TMP106:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP106]], i32* [[N_CASTED29]], align 4 -// CHECK12-NEXT: [[TMP107:%.*]] = load i32, i32* [[N_CASTED29]], align 4 -// CHECK12-NEXT: [[TMP108:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK12-NEXT: [[TMP109:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK12-NEXT: [[TMP110:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK12-NEXT: [[TMP111:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* -// CHECK12-NEXT: store i32 [[TMP107]], i32* [[TMP112]], align 4 -// CHECK12-NEXT: [[TMP113:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* -// CHECK12-NEXT: store i32 [[TMP107]], i32* [[TMP114]], align 4 -// CHECK12-NEXT: [[TMP115:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP115]], align 4 -// CHECK12-NEXT: [[TMP116:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** -// CHECK12-NEXT: store i32* [[TMP108]], i32** [[TMP117]], align 4 -// CHECK12-NEXT: [[TMP118:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** -// CHECK12-NEXT: store i32* [[TMP108]], i32** [[TMP119]], align 4 -// CHECK12-NEXT: [[TMP120:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP120]], align 4 -// CHECK12-NEXT: [[TMP121:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** -// CHECK12-NEXT: store i32* [[TMP109]], i32** [[TMP122]], align 4 -// CHECK12-NEXT: [[TMP123:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32** -// CHECK12-NEXT: store i32* [[TMP109]], i32** [[TMP124]], align 4 -// CHECK12-NEXT: [[TMP125:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP125]], align 4 -// CHECK12-NEXT: [[TMP126:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32** -// CHECK12-NEXT: store i32* [[TMP110]], i32** [[TMP127]], align 4 -// CHECK12-NEXT: [[TMP128:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32** -// CHECK12-NEXT: store i32* [[TMP110]], i32** [[TMP129]], align 4 -// CHECK12-NEXT: [[TMP130:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP130]], align 4 -// CHECK12-NEXT: [[TMP131:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP132:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP133]], i32* [[DOTCAPTURE_EXPR_34]], align 4 -// CHECK12-NEXT: [[TMP134:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_34]], align 4 -// CHECK12-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP134]], 0 -// CHECK12-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 -// CHECK12-NEXT: [[SUB38:%.*]] = sub nsw i32 [[DIV37]], 1 -// CHECK12-NEXT: store i32 [[SUB38]], i32* [[DOTCAPTURE_EXPR_35]], align 4 -// CHECK12-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_35]], align 4 -// CHECK12-NEXT: [[ADD39:%.*]] = add nsw i32 [[TMP135]], 1 -// CHECK12-NEXT: [[TMP136:%.*]] = zext i32 [[ADD39]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP136]]) -// CHECK12-NEXT: [[TMP137:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67.region_id, i32 4, i8** [[TMP131]], i8** [[TMP132]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.40, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.41, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP138:%.*]] = icmp ne i32 [[TMP137]], 0 -// CHECK12-NEXT: br i1 [[TMP138]], label [[OMP_OFFLOAD_FAILED40:%.*]], label [[OMP_OFFLOAD_CONT41:%.*]] -// CHECK12: omp_offload.failed40: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67(i32 [[TMP107]], i32* [[TMP108]], i32* [[TMP109]], i32* [[TMP110]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT41]] -// CHECK12: omp_offload.cont41: -// CHECK12-NEXT: [[TMP139:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK12-NEXT: store i32 [[TMP139]], i32* [[CH_CASTED42]], align 4 -// CHECK12-NEXT: [[TMP140:%.*]] = load i32, i32* [[CH_CASTED42]], align 4 -// CHECK12-NEXT: [[TMP141:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP141]], i32* [[N_CASTED43]], align 4 -// CHECK12-NEXT: [[TMP142:%.*]] = load i32, i32* [[N_CASTED43]], align 4 -// CHECK12-NEXT: [[TMP143:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK12-NEXT: [[TMP144:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK12-NEXT: [[TMP145:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK12-NEXT: [[TMP146:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* -// CHECK12-NEXT: store i32 [[TMP140]], i32* [[TMP147]], align 4 -// CHECK12-NEXT: [[TMP148:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* -// CHECK12-NEXT: store i32 [[TMP140]], i32* [[TMP149]], align 4 -// CHECK12-NEXT: [[TMP150:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP150]], align 4 -// CHECK12-NEXT: [[TMP151:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP152:%.*]] = bitcast i8** [[TMP151]] to i32* -// CHECK12-NEXT: store i32 [[TMP142]], i32* [[TMP152]], align 4 -// CHECK12-NEXT: [[TMP153:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i32* -// CHECK12-NEXT: store i32 [[TMP142]], i32* [[TMP154]], align 4 -// CHECK12-NEXT: [[TMP155:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP155]], align 4 -// CHECK12-NEXT: [[TMP156:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** -// CHECK12-NEXT: store i32* [[TMP143]], i32** [[TMP157]], align 4 -// CHECK12-NEXT: [[TMP158:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** -// CHECK12-NEXT: store i32* [[TMP143]], i32** [[TMP159]], align 4 -// CHECK12-NEXT: [[TMP160:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP160]], align 4 -// CHECK12-NEXT: [[TMP161:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32** -// CHECK12-NEXT: store i32* [[TMP144]], i32** [[TMP162]], align 4 -// CHECK12-NEXT: [[TMP163:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32** -// CHECK12-NEXT: store i32* [[TMP144]], i32** [[TMP164]], align 4 -// CHECK12-NEXT: [[TMP165:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP165]], align 4 -// CHECK12-NEXT: [[TMP166:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP167:%.*]] = bitcast i8** [[TMP166]] to i32** -// CHECK12-NEXT: store i32* [[TMP145]], i32** [[TMP167]], align 4 -// CHECK12-NEXT: [[TMP168:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP169:%.*]] = bitcast i8** [[TMP168]] to i32** -// CHECK12-NEXT: store i32* [[TMP145]], i32** [[TMP169]], align 4 -// CHECK12-NEXT: [[TMP170:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS46]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP170]], align 4 -// CHECK12-NEXT: [[TMP171:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS44]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP172:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS45]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP173:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP173]], i32* [[DOTCAPTURE_EXPR_48]], align 4 -// CHECK12-NEXT: [[TMP174:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_48]], align 4 -// CHECK12-NEXT: [[SUB50:%.*]] = sub nsw i32 [[TMP174]], 0 -// CHECK12-NEXT: [[DIV51:%.*]] = sdiv i32 [[SUB50]], 1 -// CHECK12-NEXT: [[SUB52:%.*]] = sub nsw i32 [[DIV51]], 1 -// CHECK12-NEXT: store i32 [[SUB52]], i32* [[DOTCAPTURE_EXPR_49]], align 4 -// CHECK12-NEXT: [[TMP175:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_49]], align 4 -// CHECK12-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP175]], 1 -// CHECK12-NEXT: [[TMP176:%.*]] = zext i32 [[ADD53]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP176]]) -// CHECK12-NEXT: [[TMP177:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 5, i8** [[TMP171]], i8** [[TMP172]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.44, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.45, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP178:%.*]] = icmp ne i32 [[TMP177]], 0 -// CHECK12-NEXT: br i1 [[TMP178]], label [[OMP_OFFLOAD_FAILED54:%.*]], label [[OMP_OFFLOAD_CONT55:%.*]] -// CHECK12: omp_offload.failed54: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32 [[TMP140]], i32 [[TMP142]], i32* [[TMP143]], i32* [[TMP144]], i32* [[TMP145]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT55]] -// CHECK12: omp_offload.cont55: -// CHECK12-NEXT: [[TMP179:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP179]], i32* [[N_CASTED56]], align 4 -// CHECK12-NEXT: [[TMP180:%.*]] = load i32, i32* [[N_CASTED56]], align 4 -// CHECK12-NEXT: [[TMP181:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK12-NEXT: [[TMP182:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK12-NEXT: [[TMP183:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK12-NEXT: [[TMP184:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP185:%.*]] = bitcast i8** [[TMP184]] to i32* -// CHECK12-NEXT: store i32 [[TMP180]], i32* [[TMP185]], align 4 -// CHECK12-NEXT: [[TMP186:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP187:%.*]] = bitcast i8** [[TMP186]] to i32* -// CHECK12-NEXT: store i32 [[TMP180]], i32* [[TMP187]], align 4 -// CHECK12-NEXT: [[TMP188:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP188]], align 4 -// CHECK12-NEXT: [[TMP189:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP190:%.*]] = bitcast i8** [[TMP189]] to i32** -// CHECK12-NEXT: store i32* [[TMP181]], i32** [[TMP190]], align 4 -// CHECK12-NEXT: [[TMP191:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP192:%.*]] = bitcast i8** [[TMP191]] to i32** -// CHECK12-NEXT: store i32* [[TMP181]], i32** [[TMP192]], align 4 -// CHECK12-NEXT: [[TMP193:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP193]], align 4 -// CHECK12-NEXT: [[TMP194:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP195:%.*]] = bitcast i8** [[TMP194]] to i32** -// CHECK12-NEXT: store i32* [[TMP182]], i32** [[TMP195]], align 4 -// CHECK12-NEXT: [[TMP196:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP197:%.*]] = bitcast i8** [[TMP196]] to i32** -// CHECK12-NEXT: store i32* [[TMP182]], i32** [[TMP197]], align 4 -// CHECK12-NEXT: [[TMP198:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP198]], align 4 -// CHECK12-NEXT: [[TMP199:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to i32** -// CHECK12-NEXT: store i32* [[TMP183]], i32** [[TMP200]], align 4 -// CHECK12-NEXT: [[TMP201:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP202:%.*]] = bitcast i8** [[TMP201]] to i32** -// CHECK12-NEXT: store i32* [[TMP183]], i32** [[TMP202]], align 4 -// CHECK12-NEXT: [[TMP203:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS59]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP203]], align 4 -// CHECK12-NEXT: [[TMP204:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS57]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP205:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS58]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP206:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP206]], i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK12-NEXT: [[TMP207:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK12-NEXT: [[SUB63:%.*]] = sub nsw i32 [[TMP207]], 0 -// CHECK12-NEXT: [[DIV64:%.*]] = sdiv i32 [[SUB63]], 1 -// CHECK12-NEXT: [[SUB65:%.*]] = sub nsw i32 [[DIV64]], 1 -// CHECK12-NEXT: store i32 [[SUB65]], i32* [[DOTCAPTURE_EXPR_62]], align 4 -// CHECK12-NEXT: [[TMP208:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_62]], align 4 -// CHECK12-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP208]], 1 -// CHECK12-NEXT: [[TMP209:%.*]] = zext i32 [[ADD66]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP209]]) -// CHECK12-NEXT: [[TMP210:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83.region_id, i32 4, i8** [[TMP204]], i8** [[TMP205]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.48, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.49, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP211:%.*]] = icmp ne i32 [[TMP210]], 0 -// CHECK12-NEXT: br i1 [[TMP211]], label [[OMP_OFFLOAD_FAILED67:%.*]], label [[OMP_OFFLOAD_CONT68:%.*]] -// CHECK12: omp_offload.failed67: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83(i32 [[TMP180]], i32* [[TMP181]], i32* [[TMP182]], i32* [[TMP183]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT68]] -// CHECK12: omp_offload.cont68: -// CHECK12-NEXT: [[TMP212:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK12-NEXT: store i32 [[TMP212]], i32* [[CH_CASTED69]], align 4 -// CHECK12-NEXT: [[TMP213:%.*]] = load i32, i32* [[CH_CASTED69]], align 4 -// CHECK12-NEXT: [[TMP214:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP214]], i32* [[N_CASTED70]], align 4 -// CHECK12-NEXT: [[TMP215:%.*]] = load i32, i32* [[N_CASTED70]], align 4 -// CHECK12-NEXT: [[TMP216:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK12-NEXT: [[TMP217:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK12-NEXT: [[TMP218:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK12-NEXT: [[TMP219:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP220:%.*]] = bitcast i8** [[TMP219]] to i32* -// CHECK12-NEXT: store i32 [[TMP213]], i32* [[TMP220]], align 4 -// CHECK12-NEXT: [[TMP221:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP222:%.*]] = bitcast i8** [[TMP221]] to i32* -// CHECK12-NEXT: store i32 [[TMP213]], i32* [[TMP222]], align 4 -// CHECK12-NEXT: [[TMP223:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP223]], align 4 -// CHECK12-NEXT: [[TMP224:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP225:%.*]] = bitcast i8** [[TMP224]] to i32* -// CHECK12-NEXT: store i32 [[TMP215]], i32* [[TMP225]], align 4 -// CHECK12-NEXT: [[TMP226:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP227:%.*]] = bitcast i8** [[TMP226]] to i32* -// CHECK12-NEXT: store i32 [[TMP215]], i32* [[TMP227]], align 4 -// CHECK12-NEXT: [[TMP228:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP228]], align 4 -// CHECK12-NEXT: [[TMP229:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP230:%.*]] = bitcast i8** [[TMP229]] to i32** -// CHECK12-NEXT: store i32* [[TMP216]], i32** [[TMP230]], align 4 -// CHECK12-NEXT: [[TMP231:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP232:%.*]] = bitcast i8** [[TMP231]] to i32** -// CHECK12-NEXT: store i32* [[TMP216]], i32** [[TMP232]], align 4 -// CHECK12-NEXT: [[TMP233:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP233]], align 4 -// CHECK12-NEXT: [[TMP234:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP235:%.*]] = bitcast i8** [[TMP234]] to i32** -// CHECK12-NEXT: store i32* [[TMP217]], i32** [[TMP235]], align 4 -// CHECK12-NEXT: [[TMP236:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP237:%.*]] = bitcast i8** [[TMP236]] to i32** -// CHECK12-NEXT: store i32* [[TMP217]], i32** [[TMP237]], align 4 -// CHECK12-NEXT: [[TMP238:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP238]], align 4 -// CHECK12-NEXT: [[TMP239:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP240:%.*]] = bitcast i8** [[TMP239]] to i32** -// CHECK12-NEXT: store i32* [[TMP218]], i32** [[TMP240]], align 4 -// CHECK12-NEXT: [[TMP241:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP242:%.*]] = bitcast i8** [[TMP241]] to i32** -// CHECK12-NEXT: store i32* [[TMP218]], i32** [[TMP242]], align 4 -// CHECK12-NEXT: [[TMP243:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS73]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP243]], align 4 -// CHECK12-NEXT: [[TMP244:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS71]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP245:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS72]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP246:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP246]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK12-NEXT: [[TMP247:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK12-NEXT: [[SUB77:%.*]] = sub nsw i32 [[TMP247]], 0 -// CHECK12-NEXT: [[DIV78:%.*]] = sdiv i32 [[SUB77]], 1 -// CHECK12-NEXT: [[SUB79:%.*]] = sub nsw i32 [[DIV78]], 1 -// CHECK12-NEXT: store i32 [[SUB79]], i32* [[DOTCAPTURE_EXPR_76]], align 4 -// CHECK12-NEXT: [[TMP248:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_76]], align 4 -// CHECK12-NEXT: [[ADD80:%.*]] = add nsw i32 [[TMP248]], 1 -// CHECK12-NEXT: [[TMP249:%.*]] = zext i32 [[ADD80]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP249]]) -// CHECK12-NEXT: [[TMP250:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91.region_id, i32 5, i8** [[TMP244]], i8** [[TMP245]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.52, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.53, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP251:%.*]] = icmp ne i32 [[TMP250]], 0 -// CHECK12-NEXT: br i1 [[TMP251]], label [[OMP_OFFLOAD_FAILED81:%.*]], label [[OMP_OFFLOAD_CONT82:%.*]] -// CHECK12: omp_offload.failed81: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91(i32 [[TMP213]], i32 [[TMP215]], i32* [[TMP216]], i32* [[TMP217]], i32* [[TMP218]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT82]] -// CHECK12: omp_offload.cont82: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP21]], i32 2) -// CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK12-NEXT: br i1 [[TMP23]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK12: .cancel.exit: -// CHECK12-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK12: .cancel.continue: -// CHECK12-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK12-NEXT: [[TMP30:%.*]] = load i32*, i32** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i32 [[TMP31]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: cancel.exit: -// CHECK12-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK12-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: br label [[CANCEL_CONT]] -// CHECK12: cancel.cont: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 -// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..31 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 -// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..34 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..35 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] -// CHECK12-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK12: cond.true10: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END12:%.*]] -// CHECK12: cond.false11: -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END12]] -// CHECK12: cond.end12: -// CHECK12-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE10]] ], [ [[TMP30]], [[COND_FALSE11]] ] -// CHECK12-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 -// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..38 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..39 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..42 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**, i32)* @.omp_outlined..43 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK12: omp.dispatch.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp ugt i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK12: omp.dispatch.body: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP28]] -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP29]], i32 [[TMP30]] -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX10]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] -// CHECK12-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] -// CHECK12-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 -// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..46 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..47 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK12: omp.dispatch.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK12: omp.dispatch.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[TMP2]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i32 [[TMP22]] -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP3]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX5]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP26]] -// CHECK12-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP1]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX7]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 -// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..50 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**, i32)* @.omp_outlined..51 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK12: omp.dispatch.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 -// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK12: omp.dispatch.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32*, i32** [[TMP2]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP22]], i32 [[TMP23]] -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32*, i32** [[TMP3]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP25]], i32 [[TMP26]] -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], [[TMP27]] -// CHECK12-NEXT: [[TMP28:%.*]] = load i32*, i32** [[TMP1]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP28]], i32 [[TMP29]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[B:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I33:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I76:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP7:%.*]] = load double, double* [[ARRAYIDX2]], align 8 -// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[TMP4]], [[TMP7]] -// CHECK13-NEXT: [[TMP8:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[TMP8]], i64 [[IDXPROM3]] -// CHECK13-NEXT: store double [[ADD]], double* [[ARRAYIDX4]], align 8 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I5]], align 4 -// CHECK13-NEXT: br label [[FOR_COND6:%.*]] -// CHECK13: for.cond6: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body8: -// CHECK13-NEXT: [[TMP13:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP13]], i64 [[IDXPROM9]] -// CHECK13-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX10]], align 8 -// CHECK13-NEXT: [[TMP16:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP16]], i64 [[IDXPROM11]] -// CHECK13-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK13-NEXT: [[ADD13:%.*]] = fadd double [[TMP15]], [[TMP18]] -// CHECK13-NEXT: [[TMP19:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP19]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store double [[ADD13]], double* [[ARRAYIDX15]], align 8 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I5]], align 4 -// CHECK13-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20:%.*]] -// CHECK13: for.cond20: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK13-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END32:%.*]] -// CHECK13: for.body22: -// CHECK13-NEXT: [[TMP24:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK13-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds double, double* [[TMP24]], i64 [[IDXPROM23]] -// CHECK13-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX24]], align 8 -// CHECK13-NEXT: [[TMP27:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds double, double* [[TMP27]], i64 [[IDXPROM25]] -// CHECK13-NEXT: [[TMP29:%.*]] = load double, double* [[ARRAYIDX26]], align 8 -// CHECK13-NEXT: [[ADD27:%.*]] = fadd double [[TMP26]], [[TMP29]] -// CHECK13-NEXT: [[TMP30:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP31:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds double, double* [[TMP30]], i64 [[IDXPROM28]] -// CHECK13-NEXT: store double [[ADD27]], double* [[ARRAYIDX29]], align 8 -// CHECK13-NEXT: br label [[FOR_INC30:%.*]] -// CHECK13: for.inc30: -// CHECK13-NEXT: [[TMP32:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK13-NEXT: store i32 [[INC31]], i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end32: -// CHECK13-NEXT: store i32 0, i32* [[I33]], align 4 -// CHECK13-NEXT: br label [[FOR_COND34:%.*]] -// CHECK13: for.cond34: -// CHECK13-NEXT: [[TMP33:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP35:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK13-NEXT: br i1 [[CMP35]], label [[FOR_BODY36:%.*]], label [[FOR_END46:%.*]] -// CHECK13: for.body36: -// CHECK13-NEXT: [[TMP35:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP36:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP36]] to i64 -// CHECK13-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds double, double* [[TMP35]], i64 [[IDXPROM37]] -// CHECK13-NEXT: [[TMP37:%.*]] = load double, double* [[ARRAYIDX38]], align 8 -// CHECK13-NEXT: [[TMP38:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP39:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM39:%.*]] = sext i32 [[TMP39]] to i64 -// CHECK13-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds double, double* [[TMP38]], i64 [[IDXPROM39]] -// CHECK13-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX40]], align 8 -// CHECK13-NEXT: [[ADD41:%.*]] = fadd double [[TMP37]], [[TMP40]] -// CHECK13-NEXT: [[TMP41:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP42:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM42:%.*]] = sext i32 [[TMP42]] to i64 -// CHECK13-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds double, double* [[TMP41]], i64 [[IDXPROM42]] -// CHECK13-NEXT: store double [[ADD41]], double* [[ARRAYIDX43]], align 8 -// CHECK13-NEXT: br label [[FOR_INC44:%.*]] -// CHECK13: for.inc44: -// CHECK13-NEXT: [[TMP43:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK13-NEXT: store i32 [[INC45]], i32* [[I33]], align 4 -// CHECK13-NEXT: br label [[FOR_COND34]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end46: -// CHECK13-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK13-NEXT: br label [[FOR_COND48:%.*]] -// CHECK13: for.cond48: -// CHECK13-NEXT: [[TMP45:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK13-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END60:%.*]] -// CHECK13: for.body50: -// CHECK13-NEXT: [[TMP47:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP48:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM51:%.*]] = sext i32 [[TMP48]] to i64 -// CHECK13-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds double, double* [[TMP47]], i64 [[IDXPROM51]] -// CHECK13-NEXT: [[TMP49:%.*]] = load double, double* [[ARRAYIDX52]], align 8 -// CHECK13-NEXT: [[TMP50:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP51:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM53:%.*]] = sext i32 [[TMP51]] to i64 -// CHECK13-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds double, double* [[TMP50]], i64 [[IDXPROM53]] -// CHECK13-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX54]], align 8 -// CHECK13-NEXT: [[ADD55:%.*]] = fadd double [[TMP49]], [[TMP52]] -// CHECK13-NEXT: [[TMP53:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP54:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM56:%.*]] = sext i32 [[TMP54]] to i64 -// CHECK13-NEXT: [[ARRAYIDX57:%.*]] = getelementptr inbounds double, double* [[TMP53]], i64 [[IDXPROM56]] -// CHECK13-NEXT: store double [[ADD55]], double* [[ARRAYIDX57]], align 8 -// CHECK13-NEXT: br label [[FOR_INC58:%.*]] -// CHECK13: for.inc58: -// CHECK13-NEXT: [[TMP55:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK13-NEXT: store i32 [[INC59]], i32* [[I47]], align 4 -// CHECK13-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end60: -// CHECK13-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK13-NEXT: br label [[FOR_COND62:%.*]] -// CHECK13: for.cond62: -// CHECK13-NEXT: [[TMP56:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK13-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END74:%.*]] -// CHECK13: for.body64: -// CHECK13-NEXT: [[TMP58:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP59:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM65:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK13-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds double, double* [[TMP58]], i64 [[IDXPROM65]] -// CHECK13-NEXT: [[TMP60:%.*]] = load double, double* [[ARRAYIDX66]], align 8 -// CHECK13-NEXT: [[TMP61:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP62:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM67:%.*]] = sext i32 [[TMP62]] to i64 -// CHECK13-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds double, double* [[TMP61]], i64 [[IDXPROM67]] -// CHECK13-NEXT: [[TMP63:%.*]] = load double, double* [[ARRAYIDX68]], align 8 -// CHECK13-NEXT: [[ADD69:%.*]] = fadd double [[TMP60]], [[TMP63]] -// CHECK13-NEXT: [[TMP64:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP65:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM70:%.*]] = sext i32 [[TMP65]] to i64 -// CHECK13-NEXT: [[ARRAYIDX71:%.*]] = getelementptr inbounds double, double* [[TMP64]], i64 [[IDXPROM70]] -// CHECK13-NEXT: store double [[ADD69]], double* [[ARRAYIDX71]], align 8 -// CHECK13-NEXT: br label [[FOR_INC72:%.*]] -// CHECK13: for.inc72: -// CHECK13-NEXT: [[TMP66:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK13-NEXT: store i32 [[INC73]], i32* [[I61]], align 4 -// CHECK13-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end74: -// CHECK13-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I76]], align 4 -// CHECK13-NEXT: br label [[FOR_COND77:%.*]] -// CHECK13: for.cond77: -// CHECK13-NEXT: [[TMP68:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP78:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK13-NEXT: br i1 [[CMP78]], label [[FOR_BODY79:%.*]], label [[FOR_END89:%.*]] -// CHECK13: for.body79: -// CHECK13-NEXT: [[TMP70:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP71:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM80:%.*]] = sext i32 [[TMP71]] to i64 -// CHECK13-NEXT: [[ARRAYIDX81:%.*]] = getelementptr inbounds double, double* [[TMP70]], i64 [[IDXPROM80]] -// CHECK13-NEXT: [[TMP72:%.*]] = load double, double* [[ARRAYIDX81]], align 8 -// CHECK13-NEXT: [[TMP73:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP74:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM82:%.*]] = sext i32 [[TMP74]] to i64 -// CHECK13-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds double, double* [[TMP73]], i64 [[IDXPROM82]] -// CHECK13-NEXT: [[TMP75:%.*]] = load double, double* [[ARRAYIDX83]], align 8 -// CHECK13-NEXT: [[ADD84:%.*]] = fadd double [[TMP72]], [[TMP75]] -// CHECK13-NEXT: [[TMP76:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP77:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM85:%.*]] = sext i32 [[TMP77]] to i64 -// CHECK13-NEXT: [[ARRAYIDX86:%.*]] = getelementptr inbounds double, double* [[TMP76]], i64 [[IDXPROM85]] -// CHECK13-NEXT: store double [[ADD84]], double* [[ARRAYIDX86]], align 8 -// CHECK13-NEXT: br label [[FOR_INC87:%.*]] -// CHECK13: for.inc87: -// CHECK13-NEXT: [[TMP78:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[INC88:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK13-NEXT: store i32 [[INC88]], i32* [[I76]], align 4 -// CHECK13-NEXT: br label [[FOR_COND77]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK13: for.end89: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: ret i32 [[CALL]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[B:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I33:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I76:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX2]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP7]] -// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i64 [[IDXPROM3]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX4]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I5]], align 4 -// CHECK13-NEXT: br label [[FOR_COND6:%.*]] -// CHECK13: for.cond6: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body8: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i64 [[IDXPROM9]] -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX10]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i64 [[IDXPROM11]] -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP15]], [[TMP18]] -// CHECK13-NEXT: [[TMP19:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 [[ADD13]], i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I5]], align 4 -// CHECK13-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20:%.*]] -// CHECK13: for.cond20: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK13-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END32:%.*]] -// CHECK13: for.body22: -// CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK13-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM23]] -// CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX24]], align 4 -// CHECK13-NEXT: [[TMP27:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM25]] -// CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX26]], align 4 -// CHECK13-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK13-NEXT: [[TMP30:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP31:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i64 [[IDXPROM28]] -// CHECK13-NEXT: store i32 [[ADD27]], i32* [[ARRAYIDX29]], align 4 -// CHECK13-NEXT: br label [[FOR_INC30:%.*]] -// CHECK13: for.inc30: -// CHECK13-NEXT: [[TMP32:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK13-NEXT: store i32 [[INC31]], i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK13: for.end32: -// CHECK13-NEXT: store i32 0, i32* [[I33]], align 4 -// CHECK13-NEXT: br label [[FOR_COND34:%.*]] -// CHECK13: for.cond34: -// CHECK13-NEXT: [[TMP33:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP35:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK13-NEXT: br i1 [[CMP35]], label [[FOR_BODY36:%.*]], label [[FOR_END46:%.*]] -// CHECK13: for.body36: -// CHECK13-NEXT: [[TMP35:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP36:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP36]] to i64 -// CHECK13-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[TMP35]], i64 [[IDXPROM37]] -// CHECK13-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARRAYIDX38]], align 4 -// CHECK13-NEXT: [[TMP38:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP39:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM39:%.*]] = sext i32 [[TMP39]] to i64 -// CHECK13-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[TMP38]], i64 [[IDXPROM39]] -// CHECK13-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARRAYIDX40]], align 4 -// CHECK13-NEXT: [[ADD41:%.*]] = add nsw i32 [[TMP37]], [[TMP40]] -// CHECK13-NEXT: [[TMP41:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP42:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM42:%.*]] = sext i32 [[TMP42]] to i64 -// CHECK13-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds i32, i32* [[TMP41]], i64 [[IDXPROM42]] -// CHECK13-NEXT: store i32 [[ADD41]], i32* [[ARRAYIDX43]], align 4 -// CHECK13-NEXT: br label [[FOR_INC44:%.*]] -// CHECK13: for.inc44: -// CHECK13-NEXT: [[TMP43:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK13-NEXT: store i32 [[INC45]], i32* [[I33]], align 4 -// CHECK13-NEXT: br label [[FOR_COND34]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK13: for.end46: -// CHECK13-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK13-NEXT: br label [[FOR_COND48:%.*]] -// CHECK13: for.cond48: -// CHECK13-NEXT: [[TMP45:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK13-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END60:%.*]] -// CHECK13: for.body50: -// CHECK13-NEXT: [[TMP47:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP48:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM51:%.*]] = sext i32 [[TMP48]] to i64 -// CHECK13-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds i32, i32* [[TMP47]], i64 [[IDXPROM51]] -// CHECK13-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARRAYIDX52]], align 4 -// CHECK13-NEXT: [[TMP50:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP51:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM53:%.*]] = sext i32 [[TMP51]] to i64 -// CHECK13-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds i32, i32* [[TMP50]], i64 [[IDXPROM53]] -// CHECK13-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARRAYIDX54]], align 4 -// CHECK13-NEXT: [[ADD55:%.*]] = add nsw i32 [[TMP49]], [[TMP52]] -// CHECK13-NEXT: [[TMP53:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP54:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM56:%.*]] = sext i32 [[TMP54]] to i64 -// CHECK13-NEXT: [[ARRAYIDX57:%.*]] = getelementptr inbounds i32, i32* [[TMP53]], i64 [[IDXPROM56]] -// CHECK13-NEXT: store i32 [[ADD55]], i32* [[ARRAYIDX57]], align 4 -// CHECK13-NEXT: br label [[FOR_INC58:%.*]] -// CHECK13: for.inc58: -// CHECK13-NEXT: [[TMP55:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK13-NEXT: store i32 [[INC59]], i32* [[I47]], align 4 -// CHECK13-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK13: for.end60: -// CHECK13-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK13-NEXT: br label [[FOR_COND62:%.*]] -// CHECK13: for.cond62: -// CHECK13-NEXT: [[TMP56:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK13-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END74:%.*]] -// CHECK13: for.body64: -// CHECK13-NEXT: [[TMP58:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP59:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM65:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK13-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds i32, i32* [[TMP58]], i64 [[IDXPROM65]] -// CHECK13-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARRAYIDX66]], align 4 -// CHECK13-NEXT: [[TMP61:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP62:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM67:%.*]] = sext i32 [[TMP62]] to i64 -// CHECK13-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds i32, i32* [[TMP61]], i64 [[IDXPROM67]] -// CHECK13-NEXT: [[TMP63:%.*]] = load i32, i32* [[ARRAYIDX68]], align 4 -// CHECK13-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP60]], [[TMP63]] -// CHECK13-NEXT: [[TMP64:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP65:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM70:%.*]] = sext i32 [[TMP65]] to i64 -// CHECK13-NEXT: [[ARRAYIDX71:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i64 [[IDXPROM70]] -// CHECK13-NEXT: store i32 [[ADD69]], i32* [[ARRAYIDX71]], align 4 -// CHECK13-NEXT: br label [[FOR_INC72:%.*]] -// CHECK13: for.inc72: -// CHECK13-NEXT: [[TMP66:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK13-NEXT: store i32 [[INC73]], i32* [[I61]], align 4 -// CHECK13-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK13: for.end74: -// CHECK13-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I76]], align 4 -// CHECK13-NEXT: br label [[FOR_COND77:%.*]] -// CHECK13: for.cond77: -// CHECK13-NEXT: [[TMP68:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP78:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK13-NEXT: br i1 [[CMP78]], label [[FOR_BODY79:%.*]], label [[FOR_END89:%.*]] -// CHECK13: for.body79: -// CHECK13-NEXT: [[TMP70:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP71:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM80:%.*]] = sext i32 [[TMP71]] to i64 -// CHECK13-NEXT: [[ARRAYIDX81:%.*]] = getelementptr inbounds i32, i32* [[TMP70]], i64 [[IDXPROM80]] -// CHECK13-NEXT: [[TMP72:%.*]] = load i32, i32* [[ARRAYIDX81]], align 4 -// CHECK13-NEXT: [[TMP73:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP74:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM82:%.*]] = sext i32 [[TMP74]] to i64 -// CHECK13-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds i32, i32* [[TMP73]], i64 [[IDXPROM82]] -// CHECK13-NEXT: [[TMP75:%.*]] = load i32, i32* [[ARRAYIDX83]], align 4 -// CHECK13-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP72]], [[TMP75]] -// CHECK13-NEXT: [[TMP76:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP77:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM85:%.*]] = sext i32 [[TMP77]] to i64 -// CHECK13-NEXT: [[ARRAYIDX86:%.*]] = getelementptr inbounds i32, i32* [[TMP76]], i64 [[IDXPROM85]] -// CHECK13-NEXT: store i32 [[ADD84]], i32* [[ARRAYIDX86]], align 4 -// CHECK13-NEXT: br label [[FOR_INC87:%.*]] -// CHECK13: for.inc87: -// CHECK13-NEXT: [[TMP78:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[INC88:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK13-NEXT: store i32 [[INC88]], i32* [[I76]], align 4 -// CHECK13-NEXT: br label [[FOR_COND77]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK13: for.end89: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[B:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I33:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I76:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP7:%.*]] = load double, double* [[ARRAYIDX2]], align 8 -// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[TMP4]], [[TMP7]] -// CHECK14-NEXT: [[TMP8:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[TMP8]], i64 [[IDXPROM3]] -// CHECK14-NEXT: store double [[ADD]], double* [[ARRAYIDX4]], align 8 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I5]], align 4 -// CHECK14-NEXT: br label [[FOR_COND6:%.*]] -// CHECK14: for.cond6: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body8: -// CHECK14-NEXT: [[TMP13:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP13]], i64 [[IDXPROM9]] -// CHECK14-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX10]], align 8 -// CHECK14-NEXT: [[TMP16:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP16]], i64 [[IDXPROM11]] -// CHECK14-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK14-NEXT: [[ADD13:%.*]] = fadd double [[TMP15]], [[TMP18]] -// CHECK14-NEXT: [[TMP19:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP19]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store double [[ADD13]], double* [[ARRAYIDX15]], align 8 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I5]], align 4 -// CHECK14-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20:%.*]] -// CHECK14: for.cond20: -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK14-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END32:%.*]] -// CHECK14: for.body22: -// CHECK14-NEXT: [[TMP24:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK14-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds double, double* [[TMP24]], i64 [[IDXPROM23]] -// CHECK14-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX24]], align 8 -// CHECK14-NEXT: [[TMP27:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK14-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds double, double* [[TMP27]], i64 [[IDXPROM25]] -// CHECK14-NEXT: [[TMP29:%.*]] = load double, double* [[ARRAYIDX26]], align 8 -// CHECK14-NEXT: [[ADD27:%.*]] = fadd double [[TMP26]], [[TMP29]] -// CHECK14-NEXT: [[TMP30:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP31:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK14-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds double, double* [[TMP30]], i64 [[IDXPROM28]] -// CHECK14-NEXT: store double [[ADD27]], double* [[ARRAYIDX29]], align 8 -// CHECK14-NEXT: br label [[FOR_INC30:%.*]] -// CHECK14: for.inc30: -// CHECK14-NEXT: [[TMP32:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK14-NEXT: store i32 [[INC31]], i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end32: -// CHECK14-NEXT: store i32 0, i32* [[I33]], align 4 -// CHECK14-NEXT: br label [[FOR_COND34:%.*]] -// CHECK14: for.cond34: -// CHECK14-NEXT: [[TMP33:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP35:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK14-NEXT: br i1 [[CMP35]], label [[FOR_BODY36:%.*]], label [[FOR_END46:%.*]] -// CHECK14: for.body36: -// CHECK14-NEXT: [[TMP35:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP36:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP36]] to i64 -// CHECK14-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds double, double* [[TMP35]], i64 [[IDXPROM37]] -// CHECK14-NEXT: [[TMP37:%.*]] = load double, double* [[ARRAYIDX38]], align 8 -// CHECK14-NEXT: [[TMP38:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP39:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM39:%.*]] = sext i32 [[TMP39]] to i64 -// CHECK14-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds double, double* [[TMP38]], i64 [[IDXPROM39]] -// CHECK14-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX40]], align 8 -// CHECK14-NEXT: [[ADD41:%.*]] = fadd double [[TMP37]], [[TMP40]] -// CHECK14-NEXT: [[TMP41:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP42:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM42:%.*]] = sext i32 [[TMP42]] to i64 -// CHECK14-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds double, double* [[TMP41]], i64 [[IDXPROM42]] -// CHECK14-NEXT: store double [[ADD41]], double* [[ARRAYIDX43]], align 8 -// CHECK14-NEXT: br label [[FOR_INC44:%.*]] -// CHECK14: for.inc44: -// CHECK14-NEXT: [[TMP43:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK14-NEXT: store i32 [[INC45]], i32* [[I33]], align 4 -// CHECK14-NEXT: br label [[FOR_COND34]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end46: -// CHECK14-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK14-NEXT: br label [[FOR_COND48:%.*]] -// CHECK14: for.cond48: -// CHECK14-NEXT: [[TMP45:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK14-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END60:%.*]] -// CHECK14: for.body50: -// CHECK14-NEXT: [[TMP47:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP48:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM51:%.*]] = sext i32 [[TMP48]] to i64 -// CHECK14-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds double, double* [[TMP47]], i64 [[IDXPROM51]] -// CHECK14-NEXT: [[TMP49:%.*]] = load double, double* [[ARRAYIDX52]], align 8 -// CHECK14-NEXT: [[TMP50:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP51:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM53:%.*]] = sext i32 [[TMP51]] to i64 -// CHECK14-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds double, double* [[TMP50]], i64 [[IDXPROM53]] -// CHECK14-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX54]], align 8 -// CHECK14-NEXT: [[ADD55:%.*]] = fadd double [[TMP49]], [[TMP52]] -// CHECK14-NEXT: [[TMP53:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP54:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM56:%.*]] = sext i32 [[TMP54]] to i64 -// CHECK14-NEXT: [[ARRAYIDX57:%.*]] = getelementptr inbounds double, double* [[TMP53]], i64 [[IDXPROM56]] -// CHECK14-NEXT: store double [[ADD55]], double* [[ARRAYIDX57]], align 8 -// CHECK14-NEXT: br label [[FOR_INC58:%.*]] -// CHECK14: for.inc58: -// CHECK14-NEXT: [[TMP55:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK14-NEXT: store i32 [[INC59]], i32* [[I47]], align 4 -// CHECK14-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end60: -// CHECK14-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK14-NEXT: br label [[FOR_COND62:%.*]] -// CHECK14: for.cond62: -// CHECK14-NEXT: [[TMP56:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK14-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END74:%.*]] -// CHECK14: for.body64: -// CHECK14-NEXT: [[TMP58:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP59:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM65:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK14-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds double, double* [[TMP58]], i64 [[IDXPROM65]] -// CHECK14-NEXT: [[TMP60:%.*]] = load double, double* [[ARRAYIDX66]], align 8 -// CHECK14-NEXT: [[TMP61:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP62:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM67:%.*]] = sext i32 [[TMP62]] to i64 -// CHECK14-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds double, double* [[TMP61]], i64 [[IDXPROM67]] -// CHECK14-NEXT: [[TMP63:%.*]] = load double, double* [[ARRAYIDX68]], align 8 -// CHECK14-NEXT: [[ADD69:%.*]] = fadd double [[TMP60]], [[TMP63]] -// CHECK14-NEXT: [[TMP64:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP65:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM70:%.*]] = sext i32 [[TMP65]] to i64 -// CHECK14-NEXT: [[ARRAYIDX71:%.*]] = getelementptr inbounds double, double* [[TMP64]], i64 [[IDXPROM70]] -// CHECK14-NEXT: store double [[ADD69]], double* [[ARRAYIDX71]], align 8 -// CHECK14-NEXT: br label [[FOR_INC72:%.*]] -// CHECK14: for.inc72: -// CHECK14-NEXT: [[TMP66:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK14-NEXT: store i32 [[INC73]], i32* [[I61]], align 4 -// CHECK14-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end74: -// CHECK14-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I76]], align 4 -// CHECK14-NEXT: br label [[FOR_COND77:%.*]] -// CHECK14: for.cond77: -// CHECK14-NEXT: [[TMP68:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP78:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK14-NEXT: br i1 [[CMP78]], label [[FOR_BODY79:%.*]], label [[FOR_END89:%.*]] -// CHECK14: for.body79: -// CHECK14-NEXT: [[TMP70:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP71:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM80:%.*]] = sext i32 [[TMP71]] to i64 -// CHECK14-NEXT: [[ARRAYIDX81:%.*]] = getelementptr inbounds double, double* [[TMP70]], i64 [[IDXPROM80]] -// CHECK14-NEXT: [[TMP72:%.*]] = load double, double* [[ARRAYIDX81]], align 8 -// CHECK14-NEXT: [[TMP73:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP74:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM82:%.*]] = sext i32 [[TMP74]] to i64 -// CHECK14-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds double, double* [[TMP73]], i64 [[IDXPROM82]] -// CHECK14-NEXT: [[TMP75:%.*]] = load double, double* [[ARRAYIDX83]], align 8 -// CHECK14-NEXT: [[ADD84:%.*]] = fadd double [[TMP72]], [[TMP75]] -// CHECK14-NEXT: [[TMP76:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP77:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM85:%.*]] = sext i32 [[TMP77]] to i64 -// CHECK14-NEXT: [[ARRAYIDX86:%.*]] = getelementptr inbounds double, double* [[TMP76]], i64 [[IDXPROM85]] -// CHECK14-NEXT: store double [[ADD84]], double* [[ARRAYIDX86]], align 8 -// CHECK14-NEXT: br label [[FOR_INC87:%.*]] -// CHECK14: for.inc87: -// CHECK14-NEXT: [[TMP78:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[INC88:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK14-NEXT: store i32 [[INC88]], i32* [[I76]], align 4 -// CHECK14-NEXT: br label [[FOR_COND77]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK14: for.end89: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: ret i32 [[CALL]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[B:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I33:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I76:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX2]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP7]] -// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i64 [[IDXPROM3]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX4]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I5]], align 4 -// CHECK14-NEXT: br label [[FOR_COND6:%.*]] -// CHECK14: for.cond6: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body8: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i64 [[IDXPROM9]] -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX10]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i64 [[IDXPROM11]] -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP15]], [[TMP18]] -// CHECK14-NEXT: [[TMP19:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 [[ADD13]], i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I5]], align 4 -// CHECK14-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20:%.*]] -// CHECK14: for.cond20: -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK14-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END32:%.*]] -// CHECK14: for.body22: -// CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK14-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM23]] -// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX24]], align 4 -// CHECK14-NEXT: [[TMP27:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK14-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM25]] -// CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX26]], align 4 -// CHECK14-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK14-NEXT: [[TMP30:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP31:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK14-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i64 [[IDXPROM28]] -// CHECK14-NEXT: store i32 [[ADD27]], i32* [[ARRAYIDX29]], align 4 -// CHECK14-NEXT: br label [[FOR_INC30:%.*]] -// CHECK14: for.inc30: -// CHECK14-NEXT: [[TMP32:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK14-NEXT: store i32 [[INC31]], i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK14: for.end32: -// CHECK14-NEXT: store i32 0, i32* [[I33]], align 4 -// CHECK14-NEXT: br label [[FOR_COND34:%.*]] -// CHECK14: for.cond34: -// CHECK14-NEXT: [[TMP33:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP35:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK14-NEXT: br i1 [[CMP35]], label [[FOR_BODY36:%.*]], label [[FOR_END46:%.*]] -// CHECK14: for.body36: -// CHECK14-NEXT: [[TMP35:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP36:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP36]] to i64 -// CHECK14-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[TMP35]], i64 [[IDXPROM37]] -// CHECK14-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARRAYIDX38]], align 4 -// CHECK14-NEXT: [[TMP38:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP39:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM39:%.*]] = sext i32 [[TMP39]] to i64 -// CHECK14-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[TMP38]], i64 [[IDXPROM39]] -// CHECK14-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARRAYIDX40]], align 4 -// CHECK14-NEXT: [[ADD41:%.*]] = add nsw i32 [[TMP37]], [[TMP40]] -// CHECK14-NEXT: [[TMP41:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP42:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM42:%.*]] = sext i32 [[TMP42]] to i64 -// CHECK14-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds i32, i32* [[TMP41]], i64 [[IDXPROM42]] -// CHECK14-NEXT: store i32 [[ADD41]], i32* [[ARRAYIDX43]], align 4 -// CHECK14-NEXT: br label [[FOR_INC44:%.*]] -// CHECK14: for.inc44: -// CHECK14-NEXT: [[TMP43:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK14-NEXT: store i32 [[INC45]], i32* [[I33]], align 4 -// CHECK14-NEXT: br label [[FOR_COND34]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK14: for.end46: -// CHECK14-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK14-NEXT: br label [[FOR_COND48:%.*]] -// CHECK14: for.cond48: -// CHECK14-NEXT: [[TMP45:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK14-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END60:%.*]] -// CHECK14: for.body50: -// CHECK14-NEXT: [[TMP47:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP48:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM51:%.*]] = sext i32 [[TMP48]] to i64 -// CHECK14-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds i32, i32* [[TMP47]], i64 [[IDXPROM51]] -// CHECK14-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARRAYIDX52]], align 4 -// CHECK14-NEXT: [[TMP50:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP51:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM53:%.*]] = sext i32 [[TMP51]] to i64 -// CHECK14-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds i32, i32* [[TMP50]], i64 [[IDXPROM53]] -// CHECK14-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARRAYIDX54]], align 4 -// CHECK14-NEXT: [[ADD55:%.*]] = add nsw i32 [[TMP49]], [[TMP52]] -// CHECK14-NEXT: [[TMP53:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP54:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM56:%.*]] = sext i32 [[TMP54]] to i64 -// CHECK14-NEXT: [[ARRAYIDX57:%.*]] = getelementptr inbounds i32, i32* [[TMP53]], i64 [[IDXPROM56]] -// CHECK14-NEXT: store i32 [[ADD55]], i32* [[ARRAYIDX57]], align 4 -// CHECK14-NEXT: br label [[FOR_INC58:%.*]] -// CHECK14: for.inc58: -// CHECK14-NEXT: [[TMP55:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK14-NEXT: store i32 [[INC59]], i32* [[I47]], align 4 -// CHECK14-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK14: for.end60: -// CHECK14-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK14-NEXT: br label [[FOR_COND62:%.*]] -// CHECK14: for.cond62: -// CHECK14-NEXT: [[TMP56:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK14-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END74:%.*]] -// CHECK14: for.body64: -// CHECK14-NEXT: [[TMP58:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP59:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM65:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK14-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds i32, i32* [[TMP58]], i64 [[IDXPROM65]] -// CHECK14-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARRAYIDX66]], align 4 -// CHECK14-NEXT: [[TMP61:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP62:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM67:%.*]] = sext i32 [[TMP62]] to i64 -// CHECK14-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds i32, i32* [[TMP61]], i64 [[IDXPROM67]] -// CHECK14-NEXT: [[TMP63:%.*]] = load i32, i32* [[ARRAYIDX68]], align 4 -// CHECK14-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP60]], [[TMP63]] -// CHECK14-NEXT: [[TMP64:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP65:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM70:%.*]] = sext i32 [[TMP65]] to i64 -// CHECK14-NEXT: [[ARRAYIDX71:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i64 [[IDXPROM70]] -// CHECK14-NEXT: store i32 [[ADD69]], i32* [[ARRAYIDX71]], align 4 -// CHECK14-NEXT: br label [[FOR_INC72:%.*]] -// CHECK14: for.inc72: -// CHECK14-NEXT: [[TMP66:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK14-NEXT: store i32 [[INC73]], i32* [[I61]], align 4 -// CHECK14-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK14: for.end74: -// CHECK14-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I76]], align 4 -// CHECK14-NEXT: br label [[FOR_COND77:%.*]] -// CHECK14: for.cond77: -// CHECK14-NEXT: [[TMP68:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP78:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK14-NEXT: br i1 [[CMP78]], label [[FOR_BODY79:%.*]], label [[FOR_END89:%.*]] -// CHECK14: for.body79: -// CHECK14-NEXT: [[TMP70:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP71:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM80:%.*]] = sext i32 [[TMP71]] to i64 -// CHECK14-NEXT: [[ARRAYIDX81:%.*]] = getelementptr inbounds i32, i32* [[TMP70]], i64 [[IDXPROM80]] -// CHECK14-NEXT: [[TMP72:%.*]] = load i32, i32* [[ARRAYIDX81]], align 4 -// CHECK14-NEXT: [[TMP73:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP74:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM82:%.*]] = sext i32 [[TMP74]] to i64 -// CHECK14-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds i32, i32* [[TMP73]], i64 [[IDXPROM82]] -// CHECK14-NEXT: [[TMP75:%.*]] = load i32, i32* [[ARRAYIDX83]], align 4 -// CHECK14-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP72]], [[TMP75]] -// CHECK14-NEXT: [[TMP76:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP77:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM85:%.*]] = sext i32 [[TMP77]] to i64 -// CHECK14-NEXT: [[ARRAYIDX86:%.*]] = getelementptr inbounds i32, i32* [[TMP76]], i64 [[IDXPROM85]] -// CHECK14-NEXT: store i32 [[ADD84]], i32* [[ARRAYIDX86]], align 4 -// CHECK14-NEXT: br label [[FOR_INC87:%.*]] -// CHECK14: for.inc87: -// CHECK14-NEXT: [[TMP78:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[INC88:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK14-NEXT: store i32 [[INC88]], i32* [[I76]], align 4 -// CHECK14-NEXT: br label [[FOR_COND77]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK14: for.end89: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I59:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 [[TMP3]] -// CHECK15-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 [[TMP6]] -// CHECK15-NEXT: [[TMP7:%.*]] = load double, double* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = fadd double [[TMP4]], [[TMP7]] -// CHECK15-NEXT: [[TMP8:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP8]], i32 [[TMP9]] -// CHECK15-NEXT: store double [[ADD]], double* [[ARRAYIDX2]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4:%.*]] -// CHECK15: for.cond4: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END13:%.*]] -// CHECK15: for.body6: -// CHECK15-NEXT: [[TMP13:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP13]], i32 [[TMP14]] -// CHECK15-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX7]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP16]], i32 [[TMP17]] -// CHECK15-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX8]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = fadd double [[TMP15]], [[TMP18]] -// CHECK15-NEXT: [[TMP19:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP19]], i32 [[TMP20]] -// CHECK15-NEXT: store double [[ADD9]], double* [[ARRAYIDX10]], align 4 -// CHECK15-NEXT: br label [[FOR_INC11:%.*]] -// CHECK15: for.inc11: -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK15-NEXT: store i32 [[INC12]], i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end13: -// CHECK15-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK15-NEXT: br label [[FOR_COND15:%.*]] -// CHECK15: for.cond15: -// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK15-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK15: for.body17: -// CHECK15-NEXT: [[TMP24:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[TMP24]], i32 [[TMP25]] -// CHECK15-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX18]], align 4 -// CHECK15-NEXT: [[TMP27:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP27]], i32 [[TMP28]] -// CHECK15-NEXT: [[TMP29:%.*]] = load double, double* [[ARRAYIDX19]], align 4 -// CHECK15-NEXT: [[ADD20:%.*]] = fadd double [[TMP26]], [[TMP29]] -// CHECK15-NEXT: [[TMP30:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP31:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[TMP30]], i32 [[TMP31]] -// CHECK15-NEXT: store double [[ADD20]], double* [[ARRAYIDX21]], align 4 -// CHECK15-NEXT: br label [[FOR_INC22:%.*]] -// CHECK15: for.inc22: -// CHECK15-NEXT: [[TMP32:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK15-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK15-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end24: -// CHECK15-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK15-NEXT: br label [[FOR_COND26:%.*]] -// CHECK15: for.cond26: -// CHECK15-NEXT: [[TMP33:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK15-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK15: for.body28: -// CHECK15-NEXT: [[TMP35:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP36:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds double, double* [[TMP35]], i32 [[TMP36]] -// CHECK15-NEXT: [[TMP37:%.*]] = load double, double* [[ARRAYIDX29]], align 4 -// CHECK15-NEXT: [[TMP38:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP39:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds double, double* [[TMP38]], i32 [[TMP39]] -// CHECK15-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX30]], align 4 -// CHECK15-NEXT: [[ADD31:%.*]] = fadd double [[TMP37]], [[TMP40]] -// CHECK15-NEXT: [[TMP41:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP42:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds double, double* [[TMP41]], i32 [[TMP42]] -// CHECK15-NEXT: store double [[ADD31]], double* [[ARRAYIDX32]], align 4 -// CHECK15-NEXT: br label [[FOR_INC33:%.*]] -// CHECK15: for.inc33: -// CHECK15-NEXT: [[TMP43:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK15-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK15-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end35: -// CHECK15-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK15-NEXT: br label [[FOR_COND37:%.*]] -// CHECK15: for.cond37: -// CHECK15-NEXT: [[TMP45:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK15-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK15: for.body39: -// CHECK15-NEXT: [[TMP47:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP48:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds double, double* [[TMP47]], i32 [[TMP48]] -// CHECK15-NEXT: [[TMP49:%.*]] = load double, double* [[ARRAYIDX40]], align 4 -// CHECK15-NEXT: [[TMP50:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP51:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds double, double* [[TMP50]], i32 [[TMP51]] -// CHECK15-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX41]], align 4 -// CHECK15-NEXT: [[ADD42:%.*]] = fadd double [[TMP49]], [[TMP52]] -// CHECK15-NEXT: [[TMP53:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP54:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds double, double* [[TMP53]], i32 [[TMP54]] -// CHECK15-NEXT: store double [[ADD42]], double* [[ARRAYIDX43]], align 4 -// CHECK15-NEXT: br label [[FOR_INC44:%.*]] -// CHECK15: for.inc44: -// CHECK15-NEXT: [[TMP55:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK15-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK15-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end46: -// CHECK15-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK15-NEXT: br label [[FOR_COND48:%.*]] -// CHECK15: for.cond48: -// CHECK15-NEXT: [[TMP56:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK15-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END57:%.*]] -// CHECK15: for.body50: -// CHECK15-NEXT: [[TMP58:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP59:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX51:%.*]] = getelementptr inbounds double, double* [[TMP58]], i32 [[TMP59]] -// CHECK15-NEXT: [[TMP60:%.*]] = load double, double* [[ARRAYIDX51]], align 4 -// CHECK15-NEXT: [[TMP61:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP62:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds double, double* [[TMP61]], i32 [[TMP62]] -// CHECK15-NEXT: [[TMP63:%.*]] = load double, double* [[ARRAYIDX52]], align 4 -// CHECK15-NEXT: [[ADD53:%.*]] = fadd double [[TMP60]], [[TMP63]] -// CHECK15-NEXT: [[TMP64:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP65:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds double, double* [[TMP64]], i32 [[TMP65]] -// CHECK15-NEXT: store double [[ADD53]], double* [[ARRAYIDX54]], align 4 -// CHECK15-NEXT: br label [[FOR_INC55:%.*]] -// CHECK15: for.inc55: -// CHECK15-NEXT: [[TMP66:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[INC56:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK15-NEXT: store i32 [[INC56]], i32* [[I47]], align 4 -// CHECK15-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end57: -// CHECK15-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I59]], align 4 -// CHECK15-NEXT: br label [[FOR_COND60:%.*]] -// CHECK15: for.cond60: -// CHECK15-NEXT: [[TMP68:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP61:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK15-NEXT: br i1 [[CMP61]], label [[FOR_BODY62:%.*]], label [[FOR_END69:%.*]] -// CHECK15: for.body62: -// CHECK15-NEXT: [[TMP70:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP71:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX63:%.*]] = getelementptr inbounds double, double* [[TMP70]], i32 [[TMP71]] -// CHECK15-NEXT: [[TMP72:%.*]] = load double, double* [[ARRAYIDX63]], align 4 -// CHECK15-NEXT: [[TMP73:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP74:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds double, double* [[TMP73]], i32 [[TMP74]] -// CHECK15-NEXT: [[TMP75:%.*]] = load double, double* [[ARRAYIDX64]], align 4 -// CHECK15-NEXT: [[ADD65:%.*]] = fadd double [[TMP72]], [[TMP75]] -// CHECK15-NEXT: [[TMP76:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP77:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds double, double* [[TMP76]], i32 [[TMP77]] -// CHECK15-NEXT: store double [[ADD65]], double* [[ARRAYIDX66]], align 4 -// CHECK15-NEXT: br label [[FOR_INC67:%.*]] -// CHECK15: for.inc67: -// CHECK15-NEXT: [[TMP78:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[INC68:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK15-NEXT: store i32 [[INC68]], i32* [[I59]], align 4 -// CHECK15-NEXT: br label [[FOR_COND60]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end69: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: ret i32 [[CALL]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I59:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP3]] -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i32 [[TMP6]] -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP7]] -// CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i32 [[TMP9]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX2]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4:%.*]] -// CHECK15: for.cond4: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END13:%.*]] -// CHECK15: for.body6: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i32 [[TMP14]] -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i32 [[TMP17]] -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], [[TMP18]] -// CHECK15-NEXT: [[TMP19:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i32 [[TMP20]] -// CHECK15-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX10]], align 4 -// CHECK15-NEXT: br label [[FOR_INC11:%.*]] -// CHECK15: for.inc11: -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK15-NEXT: store i32 [[INC12]], i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK15: for.end13: -// CHECK15-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK15-NEXT: br label [[FOR_COND15:%.*]] -// CHECK15: for.cond15: -// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK15-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK15: for.body17: -// CHECK15-NEXT: [[TMP24:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] -// CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX18]], align 4 -// CHECK15-NEXT: [[TMP27:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] -// CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX19]], align 4 -// CHECK15-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK15-NEXT: [[TMP30:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP31:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i32 [[TMP31]] -// CHECK15-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX21]], align 4 -// CHECK15-NEXT: br label [[FOR_INC22:%.*]] -// CHECK15: for.inc22: -// CHECK15-NEXT: [[TMP32:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK15-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK15-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK15: for.end24: -// CHECK15-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK15-NEXT: br label [[FOR_COND26:%.*]] -// CHECK15: for.cond26: -// CHECK15-NEXT: [[TMP33:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK15-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK15: for.body28: -// CHECK15-NEXT: [[TMP35:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP36:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[TMP35]], i32 [[TMP36]] -// CHECK15-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARRAYIDX29]], align 4 -// CHECK15-NEXT: [[TMP38:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP39:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[TMP38]], i32 [[TMP39]] -// CHECK15-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARRAYIDX30]], align 4 -// CHECK15-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP37]], [[TMP40]] -// CHECK15-NEXT: [[TMP41:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP42:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds i32, i32* [[TMP41]], i32 [[TMP42]] -// CHECK15-NEXT: store i32 [[ADD31]], i32* [[ARRAYIDX32]], align 4 -// CHECK15-NEXT: br label [[FOR_INC33:%.*]] -// CHECK15: for.inc33: -// CHECK15-NEXT: [[TMP43:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK15-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK15-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK15: for.end35: -// CHECK15-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK15-NEXT: br label [[FOR_COND37:%.*]] -// CHECK15: for.cond37: -// CHECK15-NEXT: [[TMP45:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK15-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK15: for.body39: -// CHECK15-NEXT: [[TMP47:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP48:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[TMP47]], i32 [[TMP48]] -// CHECK15-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARRAYIDX40]], align 4 -// CHECK15-NEXT: [[TMP50:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP51:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds i32, i32* [[TMP50]], i32 [[TMP51]] -// CHECK15-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARRAYIDX41]], align 4 -// CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP49]], [[TMP52]] -// CHECK15-NEXT: [[TMP53:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP54:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds i32, i32* [[TMP53]], i32 [[TMP54]] -// CHECK15-NEXT: store i32 [[ADD42]], i32* [[ARRAYIDX43]], align 4 -// CHECK15-NEXT: br label [[FOR_INC44:%.*]] -// CHECK15: for.inc44: -// CHECK15-NEXT: [[TMP55:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK15-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK15-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK15: for.end46: -// CHECK15-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK15-NEXT: br label [[FOR_COND48:%.*]] -// CHECK15: for.cond48: -// CHECK15-NEXT: [[TMP56:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK15-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END57:%.*]] -// CHECK15: for.body50: -// CHECK15-NEXT: [[TMP58:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP59:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX51:%.*]] = getelementptr inbounds i32, i32* [[TMP58]], i32 [[TMP59]] -// CHECK15-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARRAYIDX51]], align 4 -// CHECK15-NEXT: [[TMP61:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP62:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds i32, i32* [[TMP61]], i32 [[TMP62]] -// CHECK15-NEXT: [[TMP63:%.*]] = load i32, i32* [[ARRAYIDX52]], align 4 -// CHECK15-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP60]], [[TMP63]] -// CHECK15-NEXT: [[TMP64:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP65:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 [[TMP65]] -// CHECK15-NEXT: store i32 [[ADD53]], i32* [[ARRAYIDX54]], align 4 -// CHECK15-NEXT: br label [[FOR_INC55:%.*]] -// CHECK15: for.inc55: -// CHECK15-NEXT: [[TMP66:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[INC56:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK15-NEXT: store i32 [[INC56]], i32* [[I47]], align 4 -// CHECK15-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK15: for.end57: -// CHECK15-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I59]], align 4 -// CHECK15-NEXT: br label [[FOR_COND60:%.*]] -// CHECK15: for.cond60: -// CHECK15-NEXT: [[TMP68:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP61:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK15-NEXT: br i1 [[CMP61]], label [[FOR_BODY62:%.*]], label [[FOR_END69:%.*]] -// CHECK15: for.body62: -// CHECK15-NEXT: [[TMP70:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP71:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX63:%.*]] = getelementptr inbounds i32, i32* [[TMP70]], i32 [[TMP71]] -// CHECK15-NEXT: [[TMP72:%.*]] = load i32, i32* [[ARRAYIDX63]], align 4 -// CHECK15-NEXT: [[TMP73:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP74:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds i32, i32* [[TMP73]], i32 [[TMP74]] -// CHECK15-NEXT: [[TMP75:%.*]] = load i32, i32* [[ARRAYIDX64]], align 4 -// CHECK15-NEXT: [[ADD65:%.*]] = add nsw i32 [[TMP72]], [[TMP75]] -// CHECK15-NEXT: [[TMP76:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP77:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds i32, i32* [[TMP76]], i32 [[TMP77]] -// CHECK15-NEXT: store i32 [[ADD65]], i32* [[ARRAYIDX66]], align 4 -// CHECK15-NEXT: br label [[FOR_INC67:%.*]] -// CHECK15: for.inc67: -// CHECK15-NEXT: [[TMP78:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[INC68:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK15-NEXT: store i32 [[INC68]], i32* [[I59]], align 4 -// CHECK15-NEXT: br label [[FOR_COND60]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK15: for.end69: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I59:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 [[TMP3]] -// CHECK16-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 [[TMP6]] -// CHECK16-NEXT: [[TMP7:%.*]] = load double, double* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = fadd double [[TMP4]], [[TMP7]] -// CHECK16-NEXT: [[TMP8:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP8]], i32 [[TMP9]] -// CHECK16-NEXT: store double [[ADD]], double* [[ARRAYIDX2]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4:%.*]] -// CHECK16: for.cond4: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END13:%.*]] -// CHECK16: for.body6: -// CHECK16-NEXT: [[TMP13:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP13]], i32 [[TMP14]] -// CHECK16-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX7]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP16]], i32 [[TMP17]] -// CHECK16-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX8]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = fadd double [[TMP15]], [[TMP18]] -// CHECK16-NEXT: [[TMP19:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP19]], i32 [[TMP20]] -// CHECK16-NEXT: store double [[ADD9]], double* [[ARRAYIDX10]], align 4 -// CHECK16-NEXT: br label [[FOR_INC11:%.*]] -// CHECK16: for.inc11: -// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK16-NEXT: store i32 [[INC12]], i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end13: -// CHECK16-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK16-NEXT: br label [[FOR_COND15:%.*]] -// CHECK16: for.cond15: -// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK16-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK16: for.body17: -// CHECK16-NEXT: [[TMP24:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP25:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[TMP24]], i32 [[TMP25]] -// CHECK16-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX18]], align 4 -// CHECK16-NEXT: [[TMP27:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP27]], i32 [[TMP28]] -// CHECK16-NEXT: [[TMP29:%.*]] = load double, double* [[ARRAYIDX19]], align 4 -// CHECK16-NEXT: [[ADD20:%.*]] = fadd double [[TMP26]], [[TMP29]] -// CHECK16-NEXT: [[TMP30:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP31:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[TMP30]], i32 [[TMP31]] -// CHECK16-NEXT: store double [[ADD20]], double* [[ARRAYIDX21]], align 4 -// CHECK16-NEXT: br label [[FOR_INC22:%.*]] -// CHECK16: for.inc22: -// CHECK16-NEXT: [[TMP32:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK16-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK16-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end24: -// CHECK16-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK16-NEXT: br label [[FOR_COND26:%.*]] -// CHECK16: for.cond26: -// CHECK16-NEXT: [[TMP33:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK16-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK16: for.body28: -// CHECK16-NEXT: [[TMP35:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP36:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds double, double* [[TMP35]], i32 [[TMP36]] -// CHECK16-NEXT: [[TMP37:%.*]] = load double, double* [[ARRAYIDX29]], align 4 -// CHECK16-NEXT: [[TMP38:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP39:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds double, double* [[TMP38]], i32 [[TMP39]] -// CHECK16-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX30]], align 4 -// CHECK16-NEXT: [[ADD31:%.*]] = fadd double [[TMP37]], [[TMP40]] -// CHECK16-NEXT: [[TMP41:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP42:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds double, double* [[TMP41]], i32 [[TMP42]] -// CHECK16-NEXT: store double [[ADD31]], double* [[ARRAYIDX32]], align 4 -// CHECK16-NEXT: br label [[FOR_INC33:%.*]] -// CHECK16: for.inc33: -// CHECK16-NEXT: [[TMP43:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK16-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK16-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end35: -// CHECK16-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK16-NEXT: br label [[FOR_COND37:%.*]] -// CHECK16: for.cond37: -// CHECK16-NEXT: [[TMP45:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK16-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK16: for.body39: -// CHECK16-NEXT: [[TMP47:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP48:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds double, double* [[TMP47]], i32 [[TMP48]] -// CHECK16-NEXT: [[TMP49:%.*]] = load double, double* [[ARRAYIDX40]], align 4 -// CHECK16-NEXT: [[TMP50:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP51:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds double, double* [[TMP50]], i32 [[TMP51]] -// CHECK16-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX41]], align 4 -// CHECK16-NEXT: [[ADD42:%.*]] = fadd double [[TMP49]], [[TMP52]] -// CHECK16-NEXT: [[TMP53:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP54:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds double, double* [[TMP53]], i32 [[TMP54]] -// CHECK16-NEXT: store double [[ADD42]], double* [[ARRAYIDX43]], align 4 -// CHECK16-NEXT: br label [[FOR_INC44:%.*]] -// CHECK16: for.inc44: -// CHECK16-NEXT: [[TMP55:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK16-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK16-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end46: -// CHECK16-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK16-NEXT: br label [[FOR_COND48:%.*]] -// CHECK16: for.cond48: -// CHECK16-NEXT: [[TMP56:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK16-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END57:%.*]] -// CHECK16: for.body50: -// CHECK16-NEXT: [[TMP58:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP59:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX51:%.*]] = getelementptr inbounds double, double* [[TMP58]], i32 [[TMP59]] -// CHECK16-NEXT: [[TMP60:%.*]] = load double, double* [[ARRAYIDX51]], align 4 -// CHECK16-NEXT: [[TMP61:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP62:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds double, double* [[TMP61]], i32 [[TMP62]] -// CHECK16-NEXT: [[TMP63:%.*]] = load double, double* [[ARRAYIDX52]], align 4 -// CHECK16-NEXT: [[ADD53:%.*]] = fadd double [[TMP60]], [[TMP63]] -// CHECK16-NEXT: [[TMP64:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP65:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds double, double* [[TMP64]], i32 [[TMP65]] -// CHECK16-NEXT: store double [[ADD53]], double* [[ARRAYIDX54]], align 4 -// CHECK16-NEXT: br label [[FOR_INC55:%.*]] -// CHECK16: for.inc55: -// CHECK16-NEXT: [[TMP66:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[INC56:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK16-NEXT: store i32 [[INC56]], i32* [[I47]], align 4 -// CHECK16-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end57: -// CHECK16-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I59]], align 4 -// CHECK16-NEXT: br label [[FOR_COND60:%.*]] -// CHECK16: for.cond60: -// CHECK16-NEXT: [[TMP68:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP61:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK16-NEXT: br i1 [[CMP61]], label [[FOR_BODY62:%.*]], label [[FOR_END69:%.*]] -// CHECK16: for.body62: -// CHECK16-NEXT: [[TMP70:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP71:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX63:%.*]] = getelementptr inbounds double, double* [[TMP70]], i32 [[TMP71]] -// CHECK16-NEXT: [[TMP72:%.*]] = load double, double* [[ARRAYIDX63]], align 4 -// CHECK16-NEXT: [[TMP73:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP74:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds double, double* [[TMP73]], i32 [[TMP74]] -// CHECK16-NEXT: [[TMP75:%.*]] = load double, double* [[ARRAYIDX64]], align 4 -// CHECK16-NEXT: [[ADD65:%.*]] = fadd double [[TMP72]], [[TMP75]] -// CHECK16-NEXT: [[TMP76:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP77:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds double, double* [[TMP76]], i32 [[TMP77]] -// CHECK16-NEXT: store double [[ADD65]], double* [[ARRAYIDX66]], align 4 -// CHECK16-NEXT: br label [[FOR_INC67:%.*]] -// CHECK16: for.inc67: -// CHECK16-NEXT: [[TMP78:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[INC68:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK16-NEXT: store i32 [[INC68]], i32* [[I59]], align 4 -// CHECK16-NEXT: br label [[FOR_COND60]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end69: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: ret i32 [[CALL]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I59:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP3]] -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i32 [[TMP6]] -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP7]] -// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i32 [[TMP9]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX2]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4:%.*]] -// CHECK16: for.cond4: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END13:%.*]] -// CHECK16: for.body6: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i32 [[TMP14]] -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i32 [[TMP17]] -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], [[TMP18]] -// CHECK16-NEXT: [[TMP19:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i32 [[TMP20]] -// CHECK16-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX10]], align 4 -// CHECK16-NEXT: br label [[FOR_INC11:%.*]] -// CHECK16: for.inc11: -// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK16-NEXT: store i32 [[INC12]], i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK16: for.end13: -// CHECK16-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK16-NEXT: br label [[FOR_COND15:%.*]] -// CHECK16: for.cond15: -// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK16-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK16: for.body17: -// CHECK16-NEXT: [[TMP24:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP25:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] -// CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX18]], align 4 -// CHECK16-NEXT: [[TMP27:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] -// CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX19]], align 4 -// CHECK16-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK16-NEXT: [[TMP30:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP31:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i32 [[TMP31]] -// CHECK16-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX21]], align 4 -// CHECK16-NEXT: br label [[FOR_INC22:%.*]] -// CHECK16: for.inc22: -// CHECK16-NEXT: [[TMP32:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK16-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK16-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK16: for.end24: -// CHECK16-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK16-NEXT: br label [[FOR_COND26:%.*]] -// CHECK16: for.cond26: -// CHECK16-NEXT: [[TMP33:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK16-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK16: for.body28: -// CHECK16-NEXT: [[TMP35:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP36:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[TMP35]], i32 [[TMP36]] -// CHECK16-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARRAYIDX29]], align 4 -// CHECK16-NEXT: [[TMP38:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP39:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[TMP38]], i32 [[TMP39]] -// CHECK16-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARRAYIDX30]], align 4 -// CHECK16-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP37]], [[TMP40]] -// CHECK16-NEXT: [[TMP41:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP42:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds i32, i32* [[TMP41]], i32 [[TMP42]] -// CHECK16-NEXT: store i32 [[ADD31]], i32* [[ARRAYIDX32]], align 4 -// CHECK16-NEXT: br label [[FOR_INC33:%.*]] -// CHECK16: for.inc33: -// CHECK16-NEXT: [[TMP43:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK16-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK16-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK16: for.end35: -// CHECK16-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK16-NEXT: br label [[FOR_COND37:%.*]] -// CHECK16: for.cond37: -// CHECK16-NEXT: [[TMP45:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK16-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK16: for.body39: -// CHECK16-NEXT: [[TMP47:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP48:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[TMP47]], i32 [[TMP48]] -// CHECK16-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARRAYIDX40]], align 4 -// CHECK16-NEXT: [[TMP50:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP51:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds i32, i32* [[TMP50]], i32 [[TMP51]] -// CHECK16-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARRAYIDX41]], align 4 -// CHECK16-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP49]], [[TMP52]] -// CHECK16-NEXT: [[TMP53:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP54:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds i32, i32* [[TMP53]], i32 [[TMP54]] -// CHECK16-NEXT: store i32 [[ADD42]], i32* [[ARRAYIDX43]], align 4 -// CHECK16-NEXT: br label [[FOR_INC44:%.*]] -// CHECK16: for.inc44: -// CHECK16-NEXT: [[TMP55:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK16-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK16-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK16: for.end46: -// CHECK16-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK16-NEXT: br label [[FOR_COND48:%.*]] -// CHECK16: for.cond48: -// CHECK16-NEXT: [[TMP56:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK16-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END57:%.*]] -// CHECK16: for.body50: -// CHECK16-NEXT: [[TMP58:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP59:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX51:%.*]] = getelementptr inbounds i32, i32* [[TMP58]], i32 [[TMP59]] -// CHECK16-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARRAYIDX51]], align 4 -// CHECK16-NEXT: [[TMP61:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP62:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds i32, i32* [[TMP61]], i32 [[TMP62]] -// CHECK16-NEXT: [[TMP63:%.*]] = load i32, i32* [[ARRAYIDX52]], align 4 -// CHECK16-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP60]], [[TMP63]] -// CHECK16-NEXT: [[TMP64:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP65:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 [[TMP65]] -// CHECK16-NEXT: store i32 [[ADD53]], i32* [[ARRAYIDX54]], align 4 -// CHECK16-NEXT: br label [[FOR_INC55:%.*]] -// CHECK16: for.inc55: -// CHECK16-NEXT: [[TMP66:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[INC56:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK16-NEXT: store i32 [[INC56]], i32* [[I47]], align 4 -// CHECK16-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK16: for.end57: -// CHECK16-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I59]], align 4 -// CHECK16-NEXT: br label [[FOR_COND60:%.*]] -// CHECK16: for.cond60: -// CHECK16-NEXT: [[TMP68:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP61:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK16-NEXT: br i1 [[CMP61]], label [[FOR_BODY62:%.*]], label [[FOR_END69:%.*]] -// CHECK16: for.body62: -// CHECK16-NEXT: [[TMP70:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP71:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX63:%.*]] = getelementptr inbounds i32, i32* [[TMP70]], i32 [[TMP71]] -// CHECK16-NEXT: [[TMP72:%.*]] = load i32, i32* [[ARRAYIDX63]], align 4 -// CHECK16-NEXT: [[TMP73:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP74:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds i32, i32* [[TMP73]], i32 [[TMP74]] -// CHECK16-NEXT: [[TMP75:%.*]] = load i32, i32* [[ARRAYIDX64]], align 4 -// CHECK16-NEXT: [[ADD65:%.*]] = add nsw i32 [[TMP72]], [[TMP75]] -// CHECK16-NEXT: [[TMP76:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP77:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds i32, i32* [[TMP76]], i32 [[TMP77]] -// CHECK16-NEXT: store i32 [[ADD65]], i32* [[ARRAYIDX66]], align 4 -// CHECK16-NEXT: br label [[FOR_INC67:%.*]] -// CHECK16: for.inc67: -// CHECK16-NEXT: [[TMP78:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[INC68:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK16-NEXT: store i32 [[INC68]], i32* [[I59]], align 4 -// CHECK16-NEXT: br label [[FOR_COND60]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK16: for.end69: -// CHECK16-NEXT: ret i32 0 +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 +// CHECK8-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..27 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP21]], i32 2) +// CHECK8-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK8-NEXT: br i1 [[TMP23]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK8: .cancel.exit: +// CHECK8-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK8: .cancel.continue: +// CHECK8-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] +// CHECK8-NEXT: [[TMP30:%.*]] = load i32*, i32** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i32 [[TMP31]] +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP32]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: cancel.exit: +// CHECK8-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK8-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: br label [[CANCEL_CONT]] +// CHECK8: cancel.cont: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 +// CHECK8-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..31 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..31 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 +// CHECK8-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..34 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..34 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP9]]) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..35 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] +// CHECK8-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK8: cond.true10: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END12:%.*]] +// CHECK8: cond.false11: +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END12]] +// CHECK8: cond.end12: +// CHECK8-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE10]] ], [ [[TMP30]], [[COND_FALSE11]] ] +// CHECK8-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..35 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 +// CHECK8-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..38 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..38 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..39 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..39 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 [[TMP21]] +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 +// CHECK8-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..42 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..42 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**, i32)* @.omp_outlined..43 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..43 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp ugt i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP23]], i32 [[TMP24]] +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP26]], i32 [[TMP27]] +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP28]] +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP29]], i32 [[TMP30]] +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX10]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK8-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] +// CHECK8-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] +// CHECK8-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP36]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP37]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 +// CHECK8-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..46 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..46 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**)* @.omp_outlined..47 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32** [[TMP1]], i32** [[TMP2]], i32** [[TMP3]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..47 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK8-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 1) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[TMP2]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i32 [[TMP22]] +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32*, i32** [[TMP3]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX5]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP26]] +// CHECK8-NEXT: [[TMP27:%.*]] = load i32*, i32** [[TMP1]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX7]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 +// CHECK8-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[CH]], i32* [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32**, i32**, i32**)* @.omp_outlined..50 to void (i32*, i32*, ...)*), i32* [[CH_ADDR]], i32* [[N_ADDR]], i32** [[A_ADDR]], i32** [[B_ADDR]], i32** [[C_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..50 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[CH_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[CH]], i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[CH_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: store i32 [[TMP21]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32**, i32**, i32**, i32)* @.omp_outlined..51 to void (i32*, i32*, ...)*), i32 [[TMP19]], i32 [[TMP20]], i32* [[TMP1]], i32** [[TMP2]], i32** [[TMP3]], i32** [[TMP4]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..51 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[A]], i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[B]], i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32**, i32*** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK8-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32*, i32** [[TMP2]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP22]], i32 [[TMP23]] +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[TMP3]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP25]], i32 [[TMP26]] +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], [[TMP27]] +// CHECK8-NEXT: [[TMP28:%.*]] = load i32*, i32** [[TMP1]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP28]], i32 [[TMP29]] +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp @@ -7,24 +7,24 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1309,16 +1309,936 @@ // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK5-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done3: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP39]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done6: +// CHECK5-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK5-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] +// CHECK5-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = zext i32 [[TMP26]] to i64 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[SVAR9]], align 4 +// CHECK5-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP31]], i32* [[CONV11]], align 4 +// CHECK5-NEXT: [[TMP32:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP25]], i64 [[TMP27]], [2 x i32]* [[VEC4]], i64 [[TMP29]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP30]], i64 [[TMP32]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done13: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR8:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP9:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8* +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE7:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE7]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done7: +// CHECK5-NEXT: [[TMP11:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR8]] to i8* +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP11]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) +// CHECK5-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK5-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]] +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR8]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done15: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP32]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done6: +// CHECK5-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* +// CHECK5-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK5-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP23]], i64 [[TMP25]], [2 x i32]* [[VEC4]], i64 [[TMP27]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP28]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done11: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done6: +// CHECK5-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) +// CHECK5-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done14: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -1326,17 +2246,937 @@ // CHECK6-NEXT: entry: // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK6-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done3: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP39]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done6: +// CHECK6-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK6-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] +// CHECK6-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = zext i32 [[TMP26]] to i64 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[SVAR9]], align 4 +// CHECK6-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP31]], i32* [[CONV11]], align 4 +// CHECK6-NEXT: [[TMP32:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP25]], i64 [[TMP27]], [2 x i32]* [[VEC4]], i64 [[TMP29]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP30]], i64 [[TMP32]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done13: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR8:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP9:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8* +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE7:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE7]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done7: +// CHECK6-NEXT: [[TMP11:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR8]] to i8* +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP11]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) +// CHECK6-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK6-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]] +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR8]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done15: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK6-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP32]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done6: +// CHECK6-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* +// CHECK6-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK6-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP23]], i64 [[TMP25]], [2 x i32]* [[VEC4]], i64 [[TMP27]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP28]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done11: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done6: +// CHECK6-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) +// CHECK6-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done14: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main @@ -1345,16 +3185,912 @@ // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK7-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP39]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done6: +// CHECK7-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK7-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: store i32 [[TMP26]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[SVAR9]], align 4 +// CHECK7-NEXT: store i32 [[TMP29]], i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP24]], i32 [[TMP25]], [2 x i32]* [[VEC4]], i32 [[TMP27]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP28]], i32 [[TMP30]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done12: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done4: +// CHECK7-NEXT: [[TMP11:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR5]] to i8* +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP11]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) +// CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] +// CHECK7-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX8]] to i8* +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done11: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP32]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done6: +// CHECK7-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK7-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK7-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: store i32 [[TMP24]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP23]], [2 x i32]* [[VEC4]], i32 [[TMP25]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP26]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done11: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done4: +// CHECK7-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) +// CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] +// CHECK7-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP25]] +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done11: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main @@ -1362,83 +4098,81 @@ // CHECK8-NEXT: entry: // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 8 +// CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store double* [[G]], double** [[G1]], align 8 +// CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK8-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK8-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 // CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 // CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 // CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 // CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 // CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 // CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK8-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK8-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 // CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 // CHECK8-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK8-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK8-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 4 // CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK8-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 // CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK8-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK8-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP33]], align 4 // CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) @@ -1446,21 +4180,21 @@ // CHECK8-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 // CHECK8-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK8: omp_offload.failed: -// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK8: omp_offload.cont: -// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP39]] @@ -1469,9 +4203,9 @@ // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // @@ -1479,53 +4213,51 @@ // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK8-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -1536,26 +4268,26 @@ // CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 // CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 // CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK8-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK8-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK8-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 @@ -1564,10 +4296,10 @@ // CHECK8-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* // CHECK8-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 8, i1 false) +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 8, i1 false) // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK8: omp.arraycpy.body: @@ -1575,20 +4307,20 @@ // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK8-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK8: omp.arraycpy.done6: -// CHECK8-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 +// CHECK8-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 // CHECK8-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK8-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK8-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK8-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK8-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 -// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 @@ -1614,120 +4346,112 @@ // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: // CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK8-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 -// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK8-NEXT: [[TMP27:%.*]] = zext i32 [[TMP26]] to i64 -// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK8-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4 -// CHECK8-NEXT: [[TMP29:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK8-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 -// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[SVAR9]], align 4 -// CHECK8-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK8-NEXT: store i32 [[TMP31]], i32* [[CONV11]], align 4 -// CHECK8-NEXT: [[TMP32:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP25]], i64 [[TMP27]], [2 x i32]* [[VEC4]], i64 [[TMP29]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP30]], i64 [[TMP32]]) +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: store i32 [[TMP26]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[SVAR9]], align 4 +// CHECK8-NEXT: store i32 [[TMP29]], i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP24]], i32 [[TMP25]], [2 x i32]* [[VEC4]], i32 [[TMP27]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP28]], i32 [[TMP30]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] // CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: -// CHECK8-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK8-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 +// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done13: +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done12: // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR8:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK8-NEXT: [[_TMP9:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK8-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP3]] to i32 -// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK8-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK8-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK8-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8* +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* // CHECK8-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE7:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK8: omp.arraycpy.body: // CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE7]], label [[OMP_ARRAYCPY_BODY]] -// CHECK8: omp.arraycpy.done7: -// CHECK8-NEXT: [[TMP11:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR8]] to i8* +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done4: +// CHECK8-NEXT: [[TMP11:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK8-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP11]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) -// CHECK8-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) +// CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 @@ -1747,8 +4471,8 @@ // CHECK8: omp.inner.for.cond: // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8: omp.inner.for.cond.cleanup: // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: @@ -1756,52 +4480,50 @@ // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] // CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 +// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]] -// CHECK8-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX8]] to i8* // CHECK8-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: // CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK8-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: -// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR8]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done15: +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done11: // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // @@ -1814,63 +4536,62 @@ // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK8-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK8-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 // CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 // CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 // CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 // CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 // CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 4 // CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 // CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK8-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 // CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK8-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 4 // CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1878,16 +4599,16 @@ // CHECK8-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK8-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK8: omp_offload.failed: -// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK8: omp_offload.cont: // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] @@ -1900,9 +4621,9 @@ // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4 // CHECK8-NEXT: ret void @@ -1911,11 +4632,11 @@ // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 // CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4 @@ -1925,68 +4646,67 @@ // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK8-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -1997,22 +4717,22 @@ // CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 // CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 @@ -2021,10 +4741,10 @@ // CHECK8-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* // CHECK8-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false) +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 8, i1 false) // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK8: omp.arraycpy.body: @@ -2032,18 +4752,18 @@ // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK8-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK8: omp.arraycpy.done6: -// CHECK8-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 +// CHECK8-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 // CHECK8-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* // CHECK8-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) -// CHECK8-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 -// CHECK8-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK8-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 @@ -2069,35 +4789,32 @@ // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK8-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 -// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK8-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 -// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK8-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4 -// CHECK8-NEXT: [[TMP27:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK8-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP23]], i64 [[TMP25]], [2 x i32]* [[VEC4]], i64 [[TMP27]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP28]]) +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: store i32 [[TMP24]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP23]], [2 x i32]* [[VEC4]], i32 [[TMP25]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP26]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] // CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: -// CHECK8-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 -// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] @@ -2106,76 +4823,73 @@ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 -// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK8-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK8-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 -// CHECK8-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* // CHECK8-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK8: omp.arraycpy.body: // CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK8: omp.arraycpy.done6: -// CHECK8-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done4: +// CHECK8-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* // CHECK8-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) -// CHECK8-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) +// CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 @@ -2195,8 +4909,8 @@ // CHECK8: omp.inner.for.cond: // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK8-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8: omp.inner.for.cond.cleanup: // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: @@ -2204,52 +4918,50 @@ // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] // CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK8-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP25]] +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK8-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: // CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK8-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: -// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done14: +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done11: // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // @@ -2257,22 +4969,22 @@ // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: store i32 0, i32* [[F]], align 4 // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 @@ -2282,9 +4994,9 @@ // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: ret void // // @@ -2294,3885 +5006,3 @@ // CHECK8-NEXT: call void @__tgt_register_requires(i64 1) // CHECK8-NEXT: ret void // -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP39]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done6: -// CHECK9-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK9-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] -// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = zext i32 [[TMP26]] to i64 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[SVAR9]], align 4 -// CHECK9-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP31]], i32* [[CONV11]], align 4 -// CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP25]], i64 [[TMP27]], [2 x i32]* [[VEC4]], i64 [[TMP29]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP30]], i64 [[TMP32]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done13: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR8:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP9:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP3]] to i32 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8* -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE7:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE7]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done7: -// CHECK9-NEXT: [[TMP11:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR8]] to i8* -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP11]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) -// CHECK9-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]] -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR8]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done15: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP32]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done6: -// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* -// CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) -// CHECK9-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP23]], i64 [[TMP25]], [2 x i32]* [[VEC4]], i64 [[TMP27]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP28]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done11: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done6: -// CHECK9-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) -// CHECK9-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done14: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK10-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP39]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK10-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK10-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done6: -// CHECK10-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) -// CHECK10-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] -// CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP26]], i32* [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[SVAR9]], align 4 -// CHECK10-NEXT: store i32 [[TMP29]], i32* [[SVAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP24]], i32 [[TMP25]], [2 x i32]* [[VEC4]], i32 [[TMP27]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP28]], i32 [[TMP30]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done12: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK10-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK10-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done4: -// CHECK10-NEXT: [[TMP11:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR5]] to i8* -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP11]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) -// CHECK10-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP25]] -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX8]] to i8* -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done11: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP32]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK10-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done6: -// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* -// CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) -// CHECK10-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP24]], i32* [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP23]], [2 x i32]* [[VEC4]], i32 [[TMP25]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP26]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done11: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK10-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK10-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done4: -// CHECK10-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) -// CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP25]] -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done11: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP39]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done6: -// CHECK11-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) -// CHECK11-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: store i32 [[TMP26]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[SVAR9]], align 4 -// CHECK11-NEXT: store i32 [[TMP29]], i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP24]], i32 [[TMP25]], [2 x i32]* [[VEC4]], i32 [[TMP27]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP28]], i32 [[TMP30]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done12: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK11-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done4: -// CHECK11-NEXT: [[TMP11:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR5]] to i8* -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP11]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) -// CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] -// CHECK11-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX8]] to i8* -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done11: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP32]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done6: -// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) -// CHECK11-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] -// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: store i32 [[TMP24]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP23]], [2 x i32]* [[VEC4]], i32 [[TMP25]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP26]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done11: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK11-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done4: -// CHECK11-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) -// CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP16]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] -// CHECK11-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP25]] -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done11: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK12-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK12-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done5: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP14]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK12-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK12-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done5: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP14]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK14-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK14-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// diff --git a/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp @@ -3,32 +3,32 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2717,303 +2717,2595 @@ // CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47() #[[ATTR2:[0-9]+]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 +// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z9gtid_testv() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: () #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK3-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK3-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK3-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK3: omp_offload.failed5: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK3: omp_offload.cont6: +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) +// CHECK3-NEXT: ret i32 [[CALL]] +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn4v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn5v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 +// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK3-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn6v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK3-NEXT: ret i32 [[CALL]] +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK3-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK3-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK3-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK3: omp_offload.failed5: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75(i64 [[TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK3: omp_offload.cont6: +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn1v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn2v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 +// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK3-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn3v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: ret i32 0 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK3-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK3-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47() #[[ATTR2:[0-9]+]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 +// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z9gtid_testv() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: () #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK4-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK4-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK4-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK4-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK4: omp_offload.failed5: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK4: omp_offload.cont6: +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) +// CHECK4-NEXT: ret i32 [[CALL]] +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn4v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn5v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 +// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK4-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn6v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK4-NEXT: ret i32 [[CALL]] +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK4-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK4-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK4-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK4-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK4: omp_offload.failed5: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75(i64 [[TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK4: omp_offload.cont6: +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn1v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn2v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 +// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK4-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn3v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: ret i32 0 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK4-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK4-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv @@ -5613,6093 +7905,2593 @@ // CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47() #[[ATTR2:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK7: omp_offload.failed2: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK7: omp_offload.cont3: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 +// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z9gtid_testv() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end7: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK7: omp_offload.failed2: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK7: omp_offload.cont3: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK7-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK7: omp_offload.failed5: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP5]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK7: omp_offload.cont6: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) +// CHECK7-NEXT: ret i32 [[CALL]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn4v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn5v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 +// CHECK7-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.else: +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK7-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn6v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK7: omp_offload.failed2: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK7: omp_offload.cont3: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK7-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK7: omp_offload.failed5: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75(i64 [[TMP5]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK7: omp_offload.cont6: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn1v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn2v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 +// CHECK7-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.else: +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK7-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn3v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47() #[[ATTR2:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK8: omp_offload.failed2: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK8: omp_offload.cont3: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 +// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z9gtid_testv() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end7: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK8: omp_offload.failed2: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK8: omp_offload.cont3: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK8-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK8: omp_offload.failed5: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP5]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK8: omp_offload.cont6: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) +// CHECK8-NEXT: ret i32 [[CALL]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn4v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn5v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 +// CHECK8-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.else: +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK8-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn6v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK8: omp_offload.failed2: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK8: omp_offload.cont3: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK8-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK8: omp_offload.failed5: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75(i64 [[TMP5]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK8: omp_offload.cont6: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn1v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn2v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 +// CHECK8-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.else: +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK8-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn3v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: ret i32 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47() #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK9: omp_offload.failed2: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK9: omp_offload.cont3: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 -// CHECK9-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z9gtid_testv() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK9: omp_offload.failed2: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK9: omp_offload.cont3: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK9-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK9: omp_offload.failed5: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP5]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK9: omp_offload.cont6: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn4v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn5v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK9-NEXT: br label [[OMP_IF_END]] -// CHECK9: omp_if.end: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn6v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK9: omp_offload.failed2: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK9: omp_offload.cont3: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK9-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK9: omp_offload.failed5: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75(i64 [[TMP5]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK9: omp_offload.cont6: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn1v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn2v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK9-NEXT: br label [[OMP_IF_END]] -// CHECK9: omp_if.end: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn3v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47() #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK10: omp_offload.failed2: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK10: omp_offload.cont3: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 -// CHECK10-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z9gtid_testv() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK10: omp_offload.failed2: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK10: omp_offload.cont3: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK10-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK10: omp_offload.failed5: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP5]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK10: omp_offload.cont6: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn4v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn5v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK10-NEXT: br label [[OMP_IF_END]] -// CHECK10: omp_if.end: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn6v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK10-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK10: omp_offload.failed2: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK10: omp_offload.cont3: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK10-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK10: omp_offload.failed5: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75(i64 [[TMP5]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK10: omp_offload.cont6: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn1v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn2v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK10-NEXT: br label [[OMP_IF_END]] -// CHECK10: omp_if.end: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn3v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z9gtid_testv() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn4v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn5v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn6v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK11-NEXT: ret i32 [[CALL]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK11-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn1v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn2v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn3v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z9gtid_testv() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn4v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn5v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn6v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK12-NEXT: ret i32 [[CALL]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK12-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn1v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn2v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn3v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47() #[[ATTR2:[0-9]+]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK13: omp_offload.failed2: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK13: omp_offload.cont3: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 -// CHECK13-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z9gtid_testv() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK13: omp_offload.failed2: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK13: omp_offload.cont3: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK13-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK13-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK13-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK13-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK13: omp_offload.failed5: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP5]]) #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK13: omp_offload.cont6: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) -// CHECK13-NEXT: ret i32 [[CALL]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn4v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn5v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK13: omp_if.then: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK13: omp_if.else: -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK13-NEXT: br label [[OMP_IF_END]] -// CHECK13: omp_if.end: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn6v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK13-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK13: omp_offload.failed2: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK13: omp_offload.cont3: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK13-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK13-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK13-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK13-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK13: omp_offload.failed5: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75(i64 [[TMP5]]) #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK13: omp_offload.cont6: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn1v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn2v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK13: omp_if.then: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK13: omp_if.else: -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK13-NEXT: br label [[OMP_IF_END]] -// CHECK13: omp_if.end: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn3v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK13-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47() #[[ATTR2:[0-9]+]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK14: omp_offload.failed2: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK14: omp_offload.cont3: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 -// CHECK14-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z9gtid_testv() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK14: omp_offload.failed2: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK14: omp_offload.cont3: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK14-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK14-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK14-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK14-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK14: omp_offload.failed5: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP5]]) #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK14: omp_offload.cont6: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) -// CHECK14-NEXT: ret i32 [[CALL]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn4v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn5v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK14: omp_if.then: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK14: omp_if.else: -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK14-NEXT: br label [[OMP_IF_END]] -// CHECK14: omp_if.end: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn6v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK14-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK14: omp_offload.failed2: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK14: omp_offload.cont3: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK14-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK14-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK14-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK14-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK14: omp_offload.failed5: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75(i64 [[TMP5]]) #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK14: omp_offload.cont6: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn1v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn2v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[ARG]], i32** [[ARG_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARG_ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK14: omp_if.then: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK14: omp_if.else: -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) -// CHECK14-NEXT: br label [[OMP_IF_END]] -// CHECK14: omp_if.end: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn3v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK14-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z9gtid_testv() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn4v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn5v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn6v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK15-NEXT: ret i32 [[CALL]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK15-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn1v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn2v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn3v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z9gtid_testv() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn4v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn5v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn6v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK16-NEXT: ret i32 [[CALL]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK16-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn1v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn2v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn3v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: ret i32 0 +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp @@ -6,26 +6,26 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1294,16 +1294,1003 @@ // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK5-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done3: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP39]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK5-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN10]], [[TMP29]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done11: +// CHECK5-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP6]] to i8* +// CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) +// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK5-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done13: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK5-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP31]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done14: +// CHECK5-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* +// CHECK5-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) +// CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK5-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done16: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP32]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK5-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK5-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: store i32 [[TMP24]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done10: +// CHECK5-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done12: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK5-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP30]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done13: +// CHECK5-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* +// CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done15: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -1312,16 +2299,1003 @@ // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK6-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done3: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP39]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK6-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN10]], [[TMP29]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done11: +// CHECK6-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP6]] to i8* +// CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK6-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done13: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK6-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP31]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done14: +// CHECK6-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* +// CHECK6-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) +// CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK6-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done16: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK6-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP32]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK6-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK6-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: store i32 [[TMP24]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done10: +// CHECK6-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done12: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK6-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP30]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done13: +// CHECK6-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* +// CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done15: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main @@ -1330,16 +3304,985 @@ // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK7-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP39]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK7-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK7-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: store i32 [[TMP23]], i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN10]], [[TMP27]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done11: +// CHECK7-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP6]] to i8* +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK7-NEXT: store i32 [[TMP33]], i32* [[TMP4]], align 4 +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done13: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK7-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP31]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done12: +// CHECK7-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* +// CHECK7-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) +// CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK7-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done14: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP32]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK7-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK7-NEXT: store i32 [[TMP22]], i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP26]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done10: +// CHECK7-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* +// CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done12: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] +// CHECK7-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP30]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done11: +// CHECK7-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* +// CHECK7-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done13: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main @@ -1348,5118 +4291,983 @@ // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP39]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN10]], [[TMP29]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done11: -// CHECK9-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK9-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) -// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK9-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done13: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK9-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP31]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done14: -// CHECK9-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK9-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK9-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done16: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP32]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK9-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: store i32 [[TMP24]], i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done10: -// CHECK9-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done12: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK9-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP30]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done13: -// CHECK9-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK9-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done15: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK10-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP39]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK10-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP25]], i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN10]], [[TMP29]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done11: -// CHECK10-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK10-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) -// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK10-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done13: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK10-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP31]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done14: -// CHECK10-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK10-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK10-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done16: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP32]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK10-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP24]], i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done10: -// CHECK10-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done12: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK10-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP30]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done13: -// CHECK10-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK10-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done15: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP39]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK11-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK11-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: store i32 [[TMP23]], i32* [[TMP0]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN10]], [[TMP27]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done11: -// CHECK11-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK11-NEXT: store i32 [[TMP33]], i32* [[TMP4]], align 4 -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done13: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK11-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP31]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done12: -// CHECK11-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK11-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) -// CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK11-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done14: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP32]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK11-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK11-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK11-NEXT: store i32 [[TMP22]], i32* [[TMP0]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP26]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done10: -// CHECK11-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* -// CHECK11-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done12: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] -// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK11-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP30]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done11: -// CHECK11-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK11-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done13: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK12-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP39]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK12-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK12-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK12-NEXT: store i32 [[TMP23]], i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN10]], [[TMP27]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done11: -// CHECK12-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK12-NEXT: store i32 [[TMP33]], i32* [[TMP4]], align 4 -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done13: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK12-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP31]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done12: -// CHECK12-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK12-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) -// CHECK12-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK12-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done14: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK12-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP32]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK12-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK12-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK12-NEXT: store i32 [[TMP22]], i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP26]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done10: -// CHECK12-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* -// CHECK12-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done12: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] -// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK12-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP30]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done11: -// CHECK12-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK12-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done13: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done6: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done6: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done5: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done5: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK8-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP39]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK8-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK8-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: store i32 [[TMP23]], i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN10]], [[TMP27]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done11: +// CHECK8-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP6]] to i8* +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK8-NEXT: store i32 [[TMP33]], i32* [[TMP4]], align 4 +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done13: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK8-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP31]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done12: +// CHECK8-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* +// CHECK8-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) +// CHECK8-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK8-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done14: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK8-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP32]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK8-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK8-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK8-NEXT: store i32 [[TMP22]], i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP26]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done10: +// CHECK8-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* +// CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done12: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] +// CHECK8-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK8-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP30]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done11: +// CHECK8-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* +// CHECK8-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done13: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp @@ -3,33 +3,33 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2345,30 +2345,25 @@ // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I2:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) // CHECK3-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK3: invoke.cont: // CHECK3-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont1: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: lpad: // CHECK3-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } // CHECK3-NEXT: cleanup @@ -2376,52 +2371,51 @@ // CHECK3-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK3-NEXT: br label [[EH_RESUME:%.*]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3:%.*]] -// CHECK3: for.cond3: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK3-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK3: for.body5: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont6: -// CHECK3-NEXT: br label [[FOR_INC7:%.*]] -// CHECK3: for.inc7: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end9: -// CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK3-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK3-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK3: invoke.cont10: -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK3-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK3-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK3: invoke.cont12: -// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK3-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP8]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* +// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 +// CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK3-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK3-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK3-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP6]]) #[[ATTR6]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 +// CHECK3-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 +// CHECK3-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() +// CHECK3-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] +// CHECK3: invoke.cont5: +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] +// CHECK3-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() +// CHECK3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] +// CHECK3: invoke.cont7: +// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] +// CHECK3-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK3-NEXT: ret i32 [[TMP17]] // CHECK3: eh.resume: // CHECK3-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 // CHECK3-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 // CHECK3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK3-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK3-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK3-NEXT: unreachable +// CHECK3-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 +// CHECK3-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El @@ -2450,121 +2444,375 @@ // CHECK3-NEXT: ret i8 [[CONV]] // // -// CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK3-NEXT: unreachable +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 +// CHECK3-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK3-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: invoke void @_Z3foov() // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK3: invoke.cont: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont5: -// CHECK3-NEXT: br label [[FOR_INC6:%.*]] -// CHECK3: for.inc6: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end8: -// CHECK3-NEXT: ret i32 0 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void // CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } // CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10:[0-9]+]] // CHECK3-NEXT: unreachable // // -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK3-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] +// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] +// CHECK3-NEXT: unreachable +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 +// CHECK3-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i8* [[CONV]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 +// CHECK3-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: invoke void @_Z3foov() // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK3: invoke.cont: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont5: -// CHECK3-NEXT: br label [[FOR_INC6:%.*]] -// CHECK3: for.inc6: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end8: -// CHECK3-NEXT: ret i32 0 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void // CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } // CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] // CHECK3-NEXT: unreachable // // +// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv +// CHECK3-SAME: () #[[ATTR7:[0-9]+]] comdat { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv +// CHECK3-SAME: () #[[ATTR7]] comdat { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: ret i32 0 +// +// // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2577,8 +2825,626 @@ // CHECK3-NEXT: ret void // // +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 +// CHECK3-SAME: () #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// CHECK3: terminate.lpad: +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK3-NEXT: unreachable +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 +// CHECK3-SAME: () #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// CHECK3: terminate.lpad: +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK3-NEXT: unreachable +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 +// CHECK3-SAME: () #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// CHECK3: terminate.lpad: +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK3-NEXT: unreachable +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 +// CHECK3-SAME: () #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 +// CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] +// CHECK3: invoke.cont2: +// CHECK3-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: lpad: +// CHECK3-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 +// CHECK3-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 +// CHECK3-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 +// CHECK3-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK3-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// CHECK3: terminate.lpad: +// CHECK3-NEXT: [[TMP17:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP18:%.*]] = extractvalue { i8*, i32 } [[TMP17]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP18]]) #[[ATTR10]] +// CHECK3-NEXT: unreachable +// CHECK3: terminate.handler: +// CHECK3-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] +// CHECK3-NEXT: unreachable +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// CHECK3: terminate.lpad: +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK3-NEXT: unreachable +// +// // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2586,6 +3452,13 @@ // CHECK3-NEXT: ret void // // +// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK3-SAME: () #[[ATTR9:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK3-NEXT: ret void +// +// // CHECK4-LABEL: define {{[^@]+}}@main // CHECK4-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK4-NEXT: entry: @@ -2594,30 +3467,25 @@ // CHECK4-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK4-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I2:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) // CHECK4-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK4: invoke.cont: // CHECK4-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont1: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: lpad: // CHECK4-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } // CHECK4-NEXT: cleanup @@ -2625,52 +3493,51 @@ // CHECK4-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK4-NEXT: br label [[EH_RESUME:%.*]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3:%.*]] -// CHECK4: for.cond3: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK4-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK4: for.body5: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont6: -// CHECK4-NEXT: br label [[FOR_INC7:%.*]] -// CHECK4: for.inc7: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end9: -// CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK4-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK4-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK4: invoke.cont10: -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK4-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK4-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK4: invoke.cont12: -// CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK4-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP8]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* +// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 +// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK4-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK4-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK4-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP6]]) #[[ATTR6]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 +// CHECK4-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 +// CHECK4-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() +// CHECK4-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] +// CHECK4: invoke.cont5: +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] +// CHECK4-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() +// CHECK4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] +// CHECK4: invoke.cont7: +// CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] +// CHECK4-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK4-NEXT: ret i32 [[TMP17]] // CHECK4: eh.resume: // CHECK4-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 // CHECK4-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 // CHECK4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK4-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK4-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK4-NEXT: unreachable +// CHECK4-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 +// CHECK4-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1El @@ -2699,121 +3566,375 @@ // CHECK4-NEXT: ret i8 [[CONV]] // // -// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK4-NEXT: unreachable +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 +// CHECK4-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void // // -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK4-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: invoke void @_Z3foov() // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK4: invoke.cont: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont5: -// CHECK4-NEXT: br label [[FOR_INC6:%.*]] -// CHECK4: for.inc6: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end8: -// CHECK4-NEXT: ret i32 0 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void // CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } // CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10:[0-9]+]] // CHECK4-NEXT: unreachable // // -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK4-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] +// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] +// CHECK4-NEXT: unreachable +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 +// CHECK4-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i8* [[CONV]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 +// CHECK4-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: invoke void @_Z3foov() // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK4: invoke.cont: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont5: -// CHECK4-NEXT: br label [[FOR_INC6:%.*]] -// CHECK4: for.inc6: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end8: -// CHECK4-NEXT: ret i32 0 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void // CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } // CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] // CHECK4-NEXT: unreachable // // +// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv +// CHECK4-SAME: () #[[ATTR7:[0-9]+]] comdat { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv +// CHECK4-SAME: () #[[ATTR7]] comdat { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: ret i32 0 +// +// // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2826,71 +3947,696 @@ // CHECK4-NEXT: ret void // // -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 +// CHECK4-SAME: () #[[ATTR3]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK5-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK5-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK5-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] -// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK5: lpad: -// CHECK5-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: cleanup -// CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK5-NEXT: br label [[EH_RESUME:%.*]] -// CHECK5: omp_offload.cont: -// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* -// CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 -// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK5-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK5-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK5: omp_offload.failed2: +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: invoke void @_Z3foov() +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// CHECK4: terminate.lpad: +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK4-NEXT: unreachable +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 +// CHECK4-SAME: () #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: invoke void @_Z3foov() +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// CHECK4: terminate.lpad: +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK4-NEXT: unreachable +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 +// CHECK4-SAME: () #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: invoke void @_Z3foov() +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// CHECK4: terminate.lpad: +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK4-NEXT: unreachable +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 +// CHECK4-SAME: () #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 +// CHECK4-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] +// CHECK4: invoke.cont2: +// CHECK4-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: lpad: +// CHECK4-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 +// CHECK4-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 +// CHECK4-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK4-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// CHECK4: terminate.lpad: +// CHECK4-NEXT: [[TMP17:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP18:%.*]] = extractvalue { i8*, i32 } [[TMP17]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP18]]) #[[ATTR10]] +// CHECK4-NEXT: unreachable +// CHECK4: terminate.handler: +// CHECK4-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] +// CHECK4-NEXT: unreachable +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: invoke void @_Z3foov() +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// CHECK4: terminate.lpad: +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK4-NEXT: unreachable +// +// +// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev +// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK4-SAME: () #[[ATTR9:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK4-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 +// CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) +// CHECK5-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK5: invoke.cont: +// CHECK5-NEXT: store i8 [[CALL]], i8* [[A]], align 1 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK5-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: lpad: +// CHECK5-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } +// CHECK5-NEXT: cleanup +// CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 +// CHECK5-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] +// CHECK5-NEXT: br label [[EH_RESUME:%.*]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* +// CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK5-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK5-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK5: omp_offload.failed2: // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP6]]) #[[ATTR6]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK5: omp_offload.cont3: @@ -3323,6 +5069,15 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 // CHECK5-SAME: () #[[ATTR3]] { // CHECK5-NEXT: entry: @@ -3818,7 +5573,7 @@ // CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) // CHECK5-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK5: invoke.cont2: // CHECK5-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 @@ -3941,15 +5696,6 @@ // CHECK5-NEXT: unreachable // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK5-SAME: () #[[ATTR9:[0-9]+]] { // CHECK5-NEXT: entry: @@ -3973,7 +5719,7 @@ // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK6-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) +// CHECK6-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -4445,6 +6191,15 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 // CHECK6-SAME: () #[[ATTR3]] { // CHECK6-NEXT: entry: @@ -4940,7 +6695,7 @@ // CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: -// CHECK6-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) // CHECK6-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK6: invoke.cont2: // CHECK6-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 @@ -5063,15 +6818,6 @@ // CHECK6-NEXT: unreachable // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// // CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK6-SAME: () #[[ATTR9:[0-9]+]] { // CHECK6-NEXT: entry: @@ -5087,30 +6833,25 @@ // CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK7-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK7-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK7-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) +// CHECK7-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) // CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK7: invoke.cont: // CHECK7-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont1: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: lpad: // CHECK7-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } // CHECK7-NEXT: cleanup @@ -5118,52 +6859,51 @@ // CHECK7-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK7-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] +// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK7-NEXT: br label [[EH_RESUME:%.*]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont6: -// CHECK7-NEXT: br label [[FOR_INC7:%.*]] -// CHECK7: for.inc7: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end9: -// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK7-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK7-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK7: invoke.cont10: -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK7-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK7-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK7: invoke.cont12: -// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK7-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* +// CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 +// CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK7-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK7-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK7-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK7: omp_offload.failed2: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP6]]) #[[ATTR6]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK7: omp_offload.cont3: +// CHECK7-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 +// CHECK7-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 +// CHECK7-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() +// CHECK7-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] +// CHECK7: invoke.cont5: +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] +// CHECK7-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() +// CHECK7-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] +// CHECK7: invoke.cont7: +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP17]] // CHECK7: eh.resume: // CHECK7-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 // CHECK7-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 // CHECK7-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK7-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK7-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK7-NEXT: unreachable +// CHECK7-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 +// CHECK7-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SC1El @@ -5192,121 +6932,375 @@ // CHECK7-NEXT: ret i8 [[CONV]] // // -// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK7-NEXT: unreachable +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 +// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: invoke void @_Z3foov() // CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK7: invoke.cont: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont5: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void // CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK7-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } // CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] +// CHECK7-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10:[0-9]+]] // CHECK7-NEXT: unreachable // // -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK7-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] +// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] +// CHECK7-NEXT: unreachable +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 +// CHECK7-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i8* [[CONV]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 +// CHECK7-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: invoke void @_Z3foov() // CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK7: invoke.cont: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont5: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void // CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK7-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } // CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] +// CHECK7-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] // CHECK7-NEXT: unreachable // // +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv +// CHECK7-SAME: () #[[ATTR7:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK7: omp_offload.failed2: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK7: omp_offload.cont3: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv +// CHECK7-SAME: () #[[ATTR7]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK7: omp_offload.failed2: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK7: omp_offload.cont3: +// CHECK7-NEXT: ret i32 0 +// +// // CHECK7-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR7]] +// CHECK7-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -5319,8 +7313,626 @@ // CHECK7-NEXT: ret void // // +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 +// CHECK7-SAME: () #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: invoke void @_Z3foov() +// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK7: invoke.cont: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// CHECK7: terminate.lpad: +// CHECK7-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK7-NEXT: catch i8* null +// CHECK7-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK7-NEXT: unreachable +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 +// CHECK7-SAME: () #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: invoke void @_Z3foov() +// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK7: invoke.cont: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// CHECK7: terminate.lpad: +// CHECK7-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK7-NEXT: catch i8* null +// CHECK7-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK7-NEXT: unreachable +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 +// CHECK7-SAME: () #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: invoke void @_Z3foov() +// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK7: invoke.cont: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// CHECK7: terminate.lpad: +// CHECK7-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK7-NEXT: catch i8* null +// CHECK7-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK7-NEXT: unreachable +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 +// CHECK7-SAME: () #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 +// CHECK7-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK7-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK7: invoke.cont: +// CHECK7-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK7-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] +// CHECK7: invoke.cont2: +// CHECK7-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: lpad: +// CHECK7-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } +// CHECK7-NEXT: catch i8* null +// CHECK7-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 +// CHECK7-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 +// CHECK7-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK7-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// CHECK7: terminate.lpad: +// CHECK7-NEXT: [[TMP17:%.*]] = landingpad { i8*, i32 } +// CHECK7-NEXT: catch i8* null +// CHECK7-NEXT: [[TMP18:%.*]] = extractvalue { i8*, i32 } [[TMP17]], 0 +// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP18]]) #[[ATTR10]] +// CHECK7-NEXT: unreachable +// CHECK7: terminate.handler: +// CHECK7-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] +// CHECK7-NEXT: unreachable +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: invoke void @_Z3foov() +// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK7: invoke.cont: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// CHECK7: terminate.lpad: +// CHECK7-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK7-NEXT: catch i8* null +// CHECK7-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK7-NEXT: unreachable +// +// // CHECK7-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5328,6 +7940,13 @@ // CHECK7-NEXT: ret void // // +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR9:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void +// +// // CHECK8-LABEL: define {{[^@]+}}@main // CHECK8-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK8-NEXT: entry: @@ -5336,30 +7955,25 @@ // CHECK8-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK8-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK8-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK8-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) +// CHECK8-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) // CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK8: invoke.cont: // CHECK8-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont1: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK8: lpad: // CHECK8-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } // CHECK8-NEXT: cleanup @@ -5367,52 +7981,51 @@ // CHECK8-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK8-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] +// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK8-NEXT: br label [[EH_RESUME:%.*]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont6: -// CHECK8-NEXT: br label [[FOR_INC7:%.*]] -// CHECK8: for.inc7: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end9: -// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK8-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK8-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK8-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK8: invoke.cont10: -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK8-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK8-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK8: invoke.cont12: -// CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK8-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* +// CHECK8-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 +// CHECK8-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK8-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK8-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK8-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK8: omp_offload.failed2: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP6]]) #[[ATTR6]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK8: omp_offload.cont3: +// CHECK8-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 +// CHECK8-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 +// CHECK8-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() +// CHECK8-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] +// CHECK8: invoke.cont5: +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] +// CHECK8-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() +// CHECK8-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] +// CHECK8: invoke.cont7: +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP17]] // CHECK8: eh.resume: // CHECK8-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 // CHECK8-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 // CHECK8-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK8-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK8-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK8-NEXT: unreachable +// CHECK8-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 +// CHECK8-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SC1El @@ -5441,121 +8054,375 @@ // CHECK8-NEXT: ret i8 [[CONV]] // // -// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK8-NEXT: unreachable +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 +// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: invoke void @_Z3foov() // CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK8: invoke.cont: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont5: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: ret i32 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void // CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK8-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } // CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] +// CHECK8-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10:[0-9]+]] // CHECK8-NEXT: unreachable // // -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK8-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate +// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] +// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] +// CHECK8-NEXT: unreachable +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 +// CHECK8-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i8* [[CONV]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 +// CHECK8-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: invoke void @_Z3foov() // CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK8: invoke.cont: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont5: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: ret i32 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void // CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK8-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } // CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] +// CHECK8-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] // CHECK8-NEXT: unreachable // // +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv +// CHECK8-SAME: () #[[ATTR7:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK8: omp_offload.failed2: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK8: omp_offload.cont3: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv +// CHECK8-SAME: () #[[ATTR7]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK8: omp_offload.failed2: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK8: omp_offload.cont3: +// CHECK8-NEXT: ret i32 0 +// +// // CHECK8-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR7]] +// CHECK8-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -5568,8 +8435,626 @@ // CHECK8-NEXT: ret void // // +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 +// CHECK8-SAME: () #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: invoke void @_Z3foov() +// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK8: invoke.cont: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// CHECK8: terminate.lpad: +// CHECK8-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK8-NEXT: catch i8* null +// CHECK8-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK8-NEXT: unreachable +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 +// CHECK8-SAME: () #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: invoke void @_Z3foov() +// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK8: invoke.cont: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// CHECK8: terminate.lpad: +// CHECK8-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK8-NEXT: catch i8* null +// CHECK8-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK8-NEXT: unreachable +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 +// CHECK8-SAME: () #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: invoke void @_Z3foov() +// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK8: invoke.cont: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// CHECK8: terminate.lpad: +// CHECK8-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK8-NEXT: catch i8* null +// CHECK8-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK8-NEXT: unreachable +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 +// CHECK8-SAME: () #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 +// CHECK8-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK8-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK8: invoke.cont: +// CHECK8-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK8-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] +// CHECK8: invoke.cont2: +// CHECK8-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: lpad: +// CHECK8-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } +// CHECK8-NEXT: catch i8* null +// CHECK8-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 +// CHECK8-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 +// CHECK8-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK8-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// CHECK8: terminate.lpad: +// CHECK8-NEXT: [[TMP17:%.*]] = landingpad { i8*, i32 } +// CHECK8-NEXT: catch i8* null +// CHECK8-NEXT: [[TMP18:%.*]] = extractvalue { i8*, i32 } [[TMP17]], 0 +// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP18]]) #[[ATTR10]] +// CHECK8-NEXT: unreachable +// CHECK8: terminate.handler: +// CHECK8-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] +// CHECK8-NEXT: unreachable +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: invoke void @_Z3foov() +// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK8: invoke.cont: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// CHECK8: terminate.lpad: +// CHECK8-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK8-NEXT: catch i8* null +// CHECK8-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] +// CHECK8-NEXT: unreachable +// +// // CHECK8-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5577,5486 +9062,9 @@ // CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK9-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK9-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: lpad: -// CHECK9-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: cleanup -// CHECK9-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK9-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK9-NEXT: br label [[EH_RESUME:%.*]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* -// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK9-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK9: omp_offload.failed2: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP6]]) #[[ATTR6]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK9: omp_offload.cont3: -// CHECK9-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 -// CHECK9-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK9-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK9-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] -// CHECK9: invoke.cont5: -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK9-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK9-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] -// CHECK9: invoke.cont7: -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP17]] -// CHECK9: eh.resume: -// CHECK9-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK9-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK9-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK9-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK9-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_Z8mayThrowv() -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK9-NEXT: ret i8 [[CONV]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null -// CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10:[0-9]+]] -// CHECK9-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK9-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] -// CHECK9-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i8* [[CONV]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 -// CHECK9-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null -// CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK9-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK9-SAME: () #[[ATTR7:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK9: omp_offload.failed2: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK9: omp_offload.cont3: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK9-SAME: () #[[ATTR7]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK9: omp_offload.failed2: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK9: omp_offload.cont3: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 -// CHECK9-SAME: () #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null -// CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK9-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 -// CHECK9-SAME: () #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null -// CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK9-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 -// CHECK9-SAME: () #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null -// CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK9-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 -// CHECK9-SAME: () #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK9-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK9-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] -// CHECK9: invoke.cont2: -// CHECK9-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: lpad: -// CHECK9-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null -// CHECK9-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK9-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK9-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP17:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null -// CHECK9-NEXT: [[TMP18:%.*]] = extractvalue { i8*, i32 } [[TMP17]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP18]]) #[[ATTR10]] -// CHECK9-NEXT: unreachable -// CHECK9: terminate.handler: -// CHECK9-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] -// CHECK9-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null -// CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK9-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR9:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK10-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK10-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK10: invoke.cont: -// CHECK10-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: lpad: -// CHECK10-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK10-NEXT: cleanup -// CHECK10-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK10-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK10-NEXT: br label [[EH_RESUME:%.*]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* -// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK10-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK10: omp_offload.failed2: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP6]]) #[[ATTR6]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK10: omp_offload.cont3: -// CHECK10-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 -// CHECK10-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK10-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK10-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] -// CHECK10: invoke.cont5: -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK10-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK10-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] -// CHECK10: invoke.cont7: -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP17]] -// CHECK10: eh.resume: -// CHECK10-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK10-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK10-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK10-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK10-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_Z8mayThrowv() -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK10-NEXT: ret i8 [[CONV]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK10: invoke.cont: -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// CHECK10: terminate.lpad: -// CHECK10-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK10-NEXT: catch i8* null -// CHECK10-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10:[0-9]+]] -// CHECK10-NEXT: unreachable -// -// -// CHECK10-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK10-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] -// CHECK10-NEXT: unreachable -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i8* [[CONV]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 -// CHECK10-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK10: invoke.cont: -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// CHECK10: terminate.lpad: -// CHECK10-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK10-NEXT: catch i8* null -// CHECK10-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK10-NEXT: unreachable -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK10-SAME: () #[[ATTR7:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK10: omp_offload.failed2: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK10: omp_offload.cont3: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK10-SAME: () #[[ATTR7]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK10: omp_offload.failed2: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK10: omp_offload.cont3: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 -// CHECK10-SAME: () #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK10: invoke.cont: -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// CHECK10: terminate.lpad: -// CHECK10-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK10-NEXT: catch i8* null -// CHECK10-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK10-NEXT: unreachable -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 -// CHECK10-SAME: () #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK10: invoke.cont: -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// CHECK10: terminate.lpad: -// CHECK10-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK10-NEXT: catch i8* null -// CHECK10-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK10-NEXT: unreachable -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 -// CHECK10-SAME: () #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK10: invoke.cont: -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// CHECK10: terminate.lpad: -// CHECK10-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK10-NEXT: catch i8* null -// CHECK10-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK10-NEXT: unreachable -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 -// CHECK10-SAME: () #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK10-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK10: invoke.cont: -// CHECK10-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK10-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] -// CHECK10: invoke.cont2: -// CHECK10-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: lpad: -// CHECK10-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK10-NEXT: catch i8* null -// CHECK10-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK10-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK10-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// CHECK10: terminate.lpad: -// CHECK10-NEXT: [[TMP17:%.*]] = landingpad { i8*, i32 } -// CHECK10-NEXT: catch i8* null -// CHECK10-NEXT: [[TMP18:%.*]] = extractvalue { i8*, i32 } [[TMP17]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP18]]) #[[ATTR10]] -// CHECK10-NEXT: unreachable -// CHECK10: terminate.handler: -// CHECK10-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] -// CHECK10-NEXT: unreachable -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK10: invoke.cont: -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// CHECK10: terminate.lpad: -// CHECK10-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK10-NEXT: catch i8* null -// CHECK10-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK10-NEXT: unreachable -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR9:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK11-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK11-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK11-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK11: invoke.cont: -// CHECK11-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK11: invoke.cont1: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: lpad: -// CHECK11-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK11-NEXT: cleanup -// CHECK11-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK11-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK11-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK11-NEXT: br label [[EH_RESUME:%.*]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3:%.*]] -// CHECK11: for.cond3: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK11-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK11: for.body5: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK11: invoke.cont6: -// CHECK11-NEXT: br label [[FOR_INC7:%.*]] -// CHECK11: for.inc7: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end9: -// CHECK11-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK11-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK11-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK11: invoke.cont10: -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK11-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK11-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK11: invoke.cont12: -// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK11-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP8]] -// CHECK11: eh.resume: -// CHECK11-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK11-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK11-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK11-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK11-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK11: terminate.lpad: -// CHECK11-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK11-NEXT: catch i8* null -// CHECK11-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK11-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK11-NEXT: unreachable -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_Z8mayThrowv() -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK11-NEXT: ret i8 [[CONV]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK11-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK11-NEXT: unreachable -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK11: invoke.cont: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK11: invoke.cont5: -// CHECK11-NEXT: br label [[FOR_INC6:%.*]] -// CHECK11: for.inc6: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK11: for.end8: -// CHECK11-NEXT: ret i32 0 -// CHECK11: terminate.lpad: -// CHECK11-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK11-NEXT: catch i8* null -// CHECK11-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK11-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK11-NEXT: unreachable -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK11-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK11: invoke.cont: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK11: invoke.cont5: -// CHECK11-NEXT: br label [[FOR_INC6:%.*]] -// CHECK11: for.inc6: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK11: for.end8: -// CHECK11-NEXT: ret i32 0 -// CHECK11: terminate.lpad: -// CHECK11-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK11-NEXT: catch i8* null -// CHECK11-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK11-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK11-NEXT: unreachable -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK12-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK12-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK12-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK12: invoke.cont: -// CHECK12-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK12: invoke.cont1: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: lpad: -// CHECK12-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK12-NEXT: cleanup -// CHECK12-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK12-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK12-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK12-NEXT: br label [[EH_RESUME:%.*]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3:%.*]] -// CHECK12: for.cond3: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK12-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK12: for.body5: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK12: invoke.cont6: -// CHECK12-NEXT: br label [[FOR_INC7:%.*]] -// CHECK12: for.inc7: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end9: -// CHECK12-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK12-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK12-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK12: invoke.cont10: -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK12-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK12-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK12: invoke.cont12: -// CHECK12-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK12-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP8]] -// CHECK12: eh.resume: -// CHECK12-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK12-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK12-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK12-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK12-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK12: terminate.lpad: -// CHECK12-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK12-NEXT: catch i8* null -// CHECK12-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK12-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK12-NEXT: unreachable -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_Z8mayThrowv() -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK12-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK12-NEXT: ret i8 [[CONV]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK12-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK12-NEXT: unreachable -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK12: invoke.cont: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK12: invoke.cont5: -// CHECK12-NEXT: br label [[FOR_INC6:%.*]] -// CHECK12: for.inc6: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK12: for.end8: -// CHECK12-NEXT: ret i32 0 -// CHECK12: terminate.lpad: -// CHECK12-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK12-NEXT: catch i8* null -// CHECK12-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK12-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK12-NEXT: unreachable -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK12-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK12: invoke.cont: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK12: invoke.cont5: -// CHECK12-NEXT: br label [[FOR_INC6:%.*]] -// CHECK12: for.inc6: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK12: for.end8: -// CHECK12-NEXT: ret i32 0 -// CHECK12: terminate.lpad: -// CHECK12-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK12-NEXT: catch i8* null -// CHECK12-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK12-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK12-NEXT: unreachable -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK13-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK13-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK13: invoke.cont: -// CHECK13-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: lpad: -// CHECK13-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK13-NEXT: cleanup -// CHECK13-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK13-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK13-NEXT: br label [[EH_RESUME:%.*]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* -// CHECK13-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 -// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK13-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK13-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK13-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK13-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK13: omp_offload.failed2: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP6]]) #[[ATTR6]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK13: omp_offload.cont3: -// CHECK13-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 -// CHECK13-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK13-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK13-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] -// CHECK13: invoke.cont5: -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK13-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK13-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] -// CHECK13: invoke.cont7: -// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] -// CHECK13-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP17]] -// CHECK13: eh.resume: -// CHECK13-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK13-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK13-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK13-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK13-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_Z8mayThrowv() -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK13-NEXT: ret i8 [[CONV]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK13: invoke.cont: -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// CHECK13: terminate.lpad: -// CHECK13-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK13-NEXT: catch i8* null -// CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10:[0-9]+]] -// CHECK13-NEXT: unreachable -// -// -// CHECK13-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK13-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK13-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] -// CHECK13-NEXT: unreachable -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK13-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i8* [[CONV]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 -// CHECK13-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK13: invoke.cont: -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// CHECK13: terminate.lpad: -// CHECK13-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK13-NEXT: catch i8* null -// CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK13-NEXT: unreachable -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK13-SAME: () #[[ATTR7:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK13: omp_offload.failed2: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK13: omp_offload.cont3: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK13-SAME: () #[[ATTR7]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK13: omp_offload.failed2: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK13: omp_offload.cont3: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 -// CHECK13-SAME: () #[[ATTR3]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK13: invoke.cont: -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// CHECK13: terminate.lpad: -// CHECK13-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK13-NEXT: catch i8* null -// CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK13-NEXT: unreachable -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 -// CHECK13-SAME: () #[[ATTR3]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK13: invoke.cont: -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// CHECK13: terminate.lpad: -// CHECK13-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK13-NEXT: catch i8* null -// CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK13-NEXT: unreachable -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 -// CHECK13-SAME: () #[[ATTR3]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK13: invoke.cont: -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// CHECK13: terminate.lpad: -// CHECK13-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK13-NEXT: catch i8* null -// CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK13-NEXT: unreachable -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 -// CHECK13-SAME: () #[[ATTR3]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK13-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK13: invoke.cont: -// CHECK13-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK13-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] -// CHECK13: invoke.cont2: -// CHECK13-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: lpad: -// CHECK13-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK13-NEXT: catch i8* null -// CHECK13-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK13-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 -// CHECK13-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK13-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// CHECK13: terminate.lpad: -// CHECK13-NEXT: [[TMP17:%.*]] = landingpad { i8*, i32 } -// CHECK13-NEXT: catch i8* null -// CHECK13-NEXT: [[TMP18:%.*]] = extractvalue { i8*, i32 } [[TMP17]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP18]]) #[[ATTR10]] -// CHECK13-NEXT: unreachable -// CHECK13: terminate.handler: -// CHECK13-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] -// CHECK13-NEXT: unreachable -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK13: invoke.cont: -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// CHECK13: terminate.lpad: -// CHECK13-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK13-NEXT: catch i8* null -// CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK13-NEXT: unreachable -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK13-SAME: () #[[ATTR9:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK14-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK14-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK14: invoke.cont: -// CHECK14-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: lpad: -// CHECK14-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK14-NEXT: cleanup -// CHECK14-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK14-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK14-NEXT: br label [[EH_RESUME:%.*]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* -// CHECK14-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 -// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK14-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK14-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK14-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK14-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK14-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK14: omp_offload.failed2: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP6]]) #[[ATTR6]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK14: omp_offload.cont3: -// CHECK14-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 -// CHECK14-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK14-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK14-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] -// CHECK14: invoke.cont5: -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK14-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK14-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] -// CHECK14: invoke.cont7: -// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] -// CHECK14-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP17]] -// CHECK14: eh.resume: -// CHECK14-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK14-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK14-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK14-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK14-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_Z8mayThrowv() -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK14-NEXT: ret i8 [[CONV]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK14: invoke.cont: -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// CHECK14: terminate.lpad: -// CHECK14-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK14-NEXT: catch i8* null -// CHECK14-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10:[0-9]+]] -// CHECK14-NEXT: unreachable -// -// -// CHECK14-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK14-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK14-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] -// CHECK14-NEXT: unreachable -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK14-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i8* [[CONV]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 -// CHECK14-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK14: invoke.cont: -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// CHECK14: terminate.lpad: -// CHECK14-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK14-NEXT: catch i8* null -// CHECK14-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK14-NEXT: unreachable -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK14-SAME: () #[[ATTR7:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK14: omp_offload.failed2: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK14: omp_offload.cont3: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK14-SAME: () #[[ATTR7]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK14: omp_offload.failed2: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK14: omp_offload.cont3: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 -// CHECK14-SAME: () #[[ATTR3]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK14: invoke.cont: -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// CHECK14: terminate.lpad: -// CHECK14-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK14-NEXT: catch i8* null -// CHECK14-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK14-NEXT: unreachable -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 -// CHECK14-SAME: () #[[ATTR3]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK14: invoke.cont: -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// CHECK14: terminate.lpad: -// CHECK14-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK14-NEXT: catch i8* null -// CHECK14-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK14-NEXT: unreachable -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 -// CHECK14-SAME: () #[[ATTR3]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK14: invoke.cont: -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// CHECK14: terminate.lpad: -// CHECK14-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK14-NEXT: catch i8* null -// CHECK14-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK14-NEXT: unreachable -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 -// CHECK14-SAME: () #[[ATTR3]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK14-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK14: invoke.cont: -// CHECK14-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK14-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] -// CHECK14: invoke.cont2: -// CHECK14-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: lpad: -// CHECK14-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK14-NEXT: catch i8* null -// CHECK14-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK14-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 -// CHECK14-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK14-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// CHECK14: terminate.lpad: -// CHECK14-NEXT: [[TMP17:%.*]] = landingpad { i8*, i32 } -// CHECK14-NEXT: catch i8* null -// CHECK14-NEXT: [[TMP18:%.*]] = extractvalue { i8*, i32 } [[TMP17]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP18]]) #[[ATTR10]] -// CHECK14-NEXT: unreachable -// CHECK14: terminate.handler: -// CHECK14-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] -// CHECK14-NEXT: unreachable -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK14: invoke.cont: -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// CHECK14: terminate.lpad: -// CHECK14-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK14-NEXT: catch i8* null -// CHECK14-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR10]] -// CHECK14-NEXT: unreachable -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK14-SAME: () #[[ATTR9:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK15-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK15-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK15-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK15-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK15: invoke.cont: -// CHECK15-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK15: invoke.cont1: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: lpad: -// CHECK15-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK15-NEXT: cleanup -// CHECK15-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK15-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK15-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK15-NEXT: br label [[EH_RESUME:%.*]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3:%.*]] -// CHECK15: for.cond3: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK15-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK15: for.body5: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK15: invoke.cont6: -// CHECK15-NEXT: br label [[FOR_INC7:%.*]] -// CHECK15: for.inc7: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end9: -// CHECK15-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK15-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK15-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK15-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK15: invoke.cont10: -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK15-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK15-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK15: invoke.cont12: -// CHECK15-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK15-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// CHECK15: eh.resume: -// CHECK15-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK15-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK15-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK15-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK15-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK15: terminate.lpad: -// CHECK15-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK15-NEXT: catch i8* null -// CHECK15-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK15-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK15-NEXT: unreachable -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: call void @_Z8mayThrowv() -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK15-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK15-NEXT: ret i8 [[CONV]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK15-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK15-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK15-NEXT: unreachable -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK15-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK15: invoke.cont: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK15: invoke.cont5: -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: ret i32 0 -// CHECK15: terminate.lpad: -// CHECK15-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK15-NEXT: catch i8* null -// CHECK15-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK15-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK15-NEXT: unreachable -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK15-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK15: invoke.cont: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK15: invoke.cont5: -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: ret i32 0 -// CHECK15: terminate.lpad: -// CHECK15-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK15-NEXT: catch i8* null -// CHECK15-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK15-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK15-NEXT: unreachable -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK15-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK16-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK16-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK16-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK16: invoke.cont: -// CHECK16-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK16: invoke.cont1: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: lpad: -// CHECK16-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK16-NEXT: cleanup -// CHECK16-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK16-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK16-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK16-NEXT: br label [[EH_RESUME:%.*]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3:%.*]] -// CHECK16: for.cond3: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK16-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK16: for.body5: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK16: invoke.cont6: -// CHECK16-NEXT: br label [[FOR_INC7:%.*]] -// CHECK16: for.inc7: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end9: -// CHECK16-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK16-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK16-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK16-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK16: invoke.cont10: -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK16-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK16-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK16: invoke.cont12: -// CHECK16-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK16-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// CHECK16: eh.resume: -// CHECK16-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK16-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK16-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK16-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK16-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK16: terminate.lpad: -// CHECK16-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK16-NEXT: catch i8* null -// CHECK16-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK16-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK16-NEXT: unreachable -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK16-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: call void @_Z8mayThrowv() -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK16-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK16-NEXT: ret i8 [[CONV]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK16-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK16-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK16-NEXT: unreachable -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK16-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK16: invoke.cont: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK16: invoke.cont5: -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: ret i32 0 -// CHECK16: terminate.lpad: -// CHECK16-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK16-NEXT: catch i8* null -// CHECK16-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK16-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK16-NEXT: unreachable -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK16-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK16: invoke.cont: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK16: invoke.cont5: -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: ret i32 0 -// CHECK16: terminate.lpad: -// CHECK16-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK16-NEXT: catch i8* null -// CHECK16-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK16-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK16-NEXT: unreachable -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK16-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR9:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp @@ -6,26 +6,26 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -889,11 +889,670 @@ // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK5-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP4]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95 +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done5: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP3]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP3]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK5-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done9: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK5-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP4]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK5-SAME: () #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done5: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK5-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done9: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -902,11 +1561,670 @@ // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK6-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP4]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95 +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done5: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP3]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP3]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK6-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done9: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK6-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP4]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK6-SAME: () #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done5: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK6-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done9: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main @@ -915,11 +2233,658 @@ // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK7-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP4]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95 +// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done5: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done7: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK7-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP4]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK7-SAME: () #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done5: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done7: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main @@ -928,3937 +2893,656 @@ // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK9-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP4]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95 -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done5: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP3]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP3]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] -// CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done9: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK9-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP4]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: () #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done5: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] -// CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done9: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK10-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP4]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95 -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done5: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP3]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP3]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] -// CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done9: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK10-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP4]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: () #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done5: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] -// CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done9: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK11-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP4]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95 -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done5: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done7: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK11-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP4]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: () #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done5: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done7: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK12-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP4]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95 -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done5: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done7: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK12-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP4]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: () #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done5: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done7: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done8: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK13: arraydestroy.body10: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK13: arraydestroy.done14: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP11]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done8: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK13: arraydestroy.body10: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK13: arraydestroy.done14: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP11]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done8: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK14: arraydestroy.body10: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK14: arraydestroy.done14: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP11]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done8: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK14: arraydestroy.body10: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK14: arraydestroy.done14: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP11]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK15: arraydestroy.body9: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK15: arraydestroy.done13: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP11]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK15: arraydestroy.body9: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK15: arraydestroy.done13: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP11]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK16: arraydestroy.body9: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK16: arraydestroy.done13: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP11]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK16: arraydestroy.body9: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK16: arraydestroy.done13: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP11]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK8-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP4]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95 +// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done5: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done7: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK8-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP4]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK8-SAME: () #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done5: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done7: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp @@ -5,9 +5,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -978,123 +978,3 @@ // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret i32 0 -// diff --git a/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1273,62 +1273,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG23:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG23]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG24:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG25:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG27:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG29:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG31:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG31]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG31]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG32:![0-9]+]], !llvm.loop [[LOOP33:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG36]] -// diff --git a/clang/test/OpenMP/distribute_private_codegen.cpp b/clang/test/OpenMP/distribute_private_codegen.cpp --- a/clang/test/OpenMP/distribute_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_private_codegen.cpp @@ -6,26 +6,26 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -564,11 +564,539 @@ // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK5-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK5-NEXT: br i1 [[TMP4]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK5: omp_offload.failed3: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK5: omp_offload.cont4: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done5: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP6]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done8: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 +// CHECK5-SAME: () #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK5-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP4]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK5-SAME: () #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done8: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -577,11 +1105,539 @@ // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK6-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP3:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK6-NEXT: br i1 [[TMP4]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK6: omp_offload.failed3: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK6: omp_offload.cont4: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done5: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP6]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done8: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 +// CHECK6-SAME: () #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK6-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP4]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK6-SAME: () #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done8: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main @@ -590,11 +1646,535 @@ // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK7-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP3:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK7-NEXT: br i1 [[TMP4]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK7: omp_offload.failed3: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK7: omp_offload.cont4: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done5: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP6]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 +// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done7: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 +// CHECK7-SAME: () #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK7-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP4]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK7-SAME: () #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done7: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main @@ -603,3493 +2183,533 @@ // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK9-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK9-NEXT: br i1 [[TMP4]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK9: omp_offload.failed3: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK9: omp_offload.cont4: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done5: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP6]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done8: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK9-SAME: () #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK9-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP4]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: () #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done8: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK10-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP3:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK10-NEXT: br i1 [[TMP4]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK10: omp_offload.failed3: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK10: omp_offload.cont4: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done5: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP6]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done8: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK10-SAME: () #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK10-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP4]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: () #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done8: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK11-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK11-NEXT: br i1 [[TMP4]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK11: omp_offload.failed3: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK11: omp_offload.cont4: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done5: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP6]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done7: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK11-SAME: () #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK11-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP4]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: () #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done7: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK12-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK12-NEXT: br i1 [[TMP4]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK12: omp_offload.failed3: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK12: omp_offload.cont4: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done5: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP6]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done7: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK12-SAME: () #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK12-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP4]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: () #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done7: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done8: -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END16:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: br label [[FOR_INC14:%.*]] -// CHECK13: for.inc14: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC15]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end16: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] -// CHECK13: arraydestroy.body18: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END16]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] -// CHECK13: arraydestroy.done22: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP13]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done8: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK13: arraydestroy.body10: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK13: arraydestroy.done14: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP11]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done8: -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END16:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: br label [[FOR_INC14:%.*]] -// CHECK14: for.inc14: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC15]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end16: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] -// CHECK14: arraydestroy.body18: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END16]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] -// CHECK14: arraydestroy.done22: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done8: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK14: arraydestroy.body10: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK14: arraydestroy.done14: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP11]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END15:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: br label [[FOR_INC13:%.*]] -// CHECK15: for.inc13: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC14]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end15: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] -// CHECK15: arraydestroy.body17: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] -// CHECK15: arraydestroy.done21: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK15: arraydestroy.body9: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK15: arraydestroy.done13: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP11]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END15:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: br label [[FOR_INC13:%.*]] -// CHECK16: for.inc13: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC14]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end15: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] -// CHECK16: arraydestroy.body17: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] -// CHECK16: arraydestroy.done21: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK16: arraydestroy.body9: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK16: arraydestroy.done13: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP11]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK8-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP3:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK8-NEXT: br i1 [[TMP4]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK8: omp_offload.failed3: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK8: omp_offload.cont4: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done5: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP6]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 +// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done7: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 +// CHECK8-SAME: () #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK8-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP4]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK8-SAME: () #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done7: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/for_firstprivate_codegen.cpp b/clang/test/OpenMP/for_firstprivate_codegen.cpp --- a/clang/test/OpenMP/for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/for_firstprivate_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1848,961 +1848,3 @@ // CHECK4-NEXT: call void @__cxx_global_var_init.2() // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP11]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP12]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP11]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP12]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** @g1, align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store i32 1, i32* @g, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store volatile i32 1, i32* [[TMP2]], align 4 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP3:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store volatile i32 [[TMP3]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP4]], i32** [[BLOCK_CAPTURED2]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[BLOCK_CAPTURED3]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP6]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP9:%.*]] = load i8*, i8** [[TMP7]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP10]](i8* [[TMP8]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: store i32 2, i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/for_lastprivate_codegen.cpp b/clang/test/OpenMP/for_lastprivate_codegen.cpp --- a/clang/test/OpenMP/for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/for_lastprivate_codegen.cpp @@ -10,16 +10,16 @@ // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -7858,3411 +7858,3 @@ // CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]]) // CHECK8-NEXT: ret void // -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK9-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[ARRAYIDX2]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK9-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK9-NEXT: br label [[FOR_COND4:%.*]] -// CHECK9: for.cond4: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 2 -// CHECK9-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END10:%.*]] -// CHECK9: for.body6: -// CHECK9-NEXT: [[TMP9:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: [[INC7:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK9-NEXT: store double [[INC7]], double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: br label [[FOR_INC8:%.*]] -// CHECK9: for.inc8: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK9-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[INC9]], i32* [[I3]], align 4 -// CHECK9-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK9: for.end10: -// CHECK9-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK9-NEXT: br label [[FOR_COND12:%.*]] -// CHECK9: for.cond12: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK9-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK9-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END18:%.*]] -// CHECK9: for.body14: -// CHECK9-NEXT: [[TMP12:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: [[INC15:%.*]] = fadd double [[TMP12]], 1.000000e+00 -// CHECK9-NEXT: store double [[INC15]], double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: br label [[FOR_INC16:%.*]] -// CHECK9: for.inc16: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK9-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[INC17]], i32* [[I11]], align 4 -// CHECK9-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end18: -// CHECK9-NEXT: store i8 0, i8* @cnt, align 1 -// CHECK9-NEXT: br label [[FOR_COND19:%.*]] -// CHECK9: for.cond19: -// CHECK9-NEXT: [[TMP14:%.*]] = load i8, i8* @cnt, align 1 -// CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK9-NEXT: [[CMP20:%.*]] = icmp slt i32 [[CONV]], 2 -// CHECK9-NEXT: br i1 [[CMP20]], label [[FOR_BODY21:%.*]], label [[FOR_END25:%.*]] -// CHECK9: for.body21: -// CHECK9-NEXT: [[TMP15:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: [[INC22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK9-NEXT: store double [[INC22]], double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: store float 0.000000e+00, float* @f, align 4 -// CHECK9-NEXT: br label [[FOR_INC23:%.*]] -// CHECK9: for.inc23: -// CHECK9-NEXT: [[TMP16:%.*]] = load i8, i8* @cnt, align 1 -// CHECK9-NEXT: [[INC24:%.*]] = add i8 [[TMP16]], 1 -// CHECK9-NEXT: store i8 [[INC24]], i8* @cnt, align 1 -// CHECK9-NEXT: br label [[FOR_COND19]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK9: for.end25: -// CHECK9-NEXT: [[CALL26:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL26]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done27: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP18]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK9-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP6]]) -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done4: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP10]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK9-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A11:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK9-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK9-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK9-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK9-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK9-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK9-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK9-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK9-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK9-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK9-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK9-NEXT: store i32 [[DEC]], i32* [[B5]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK9-NEXT: store i32 [[INC10]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[A12]], i32** [[A11]], align 8 -// CHECK9-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A13]], align 8 -// CHECK9-NEXT: br label [[FOR_COND14:%.*]] -// CHECK9: for.cond14: -// CHECK9-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[A15]], align 8 -// CHECK9-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP12]], 2 -// CHECK9-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END29:%.*]] -// CHECK9: for.body17: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A11]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK9-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[INC18]], i32* [[TMP13]], align 4 -// CHECK9-NEXT: [[B19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK9-NEXT: [[BF_LOAD20:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK9-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD20]], 4 -// CHECK9-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK9-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK9-NEXT: [[DEC21:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK9-NEXT: [[TMP15:%.*]] = trunc i32 [[DEC21]] to i8 -// CHECK9-NEXT: [[BF_LOAD22:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK9-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP15]], 15 -// CHECK9-NEXT: [[BF_CLEAR23:%.*]] = and i8 [[BF_LOAD22]], -16 -// CHECK9-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR23]], [[BF_VALUE]] -// CHECK9-NEXT: store i8 [[BF_SET]], i8* [[B19]], align 8 -// CHECK9-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK9-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK9-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK9-NEXT: [[C24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C24]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP17]], 1 -// CHECK9-NEXT: store i32 [[DIV25]], i32* [[TMP16]], align 4 -// CHECK9-NEXT: br label [[FOR_INC26:%.*]] -// CHECK9: for.inc26: -// CHECK9-NEXT: [[A27:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[A27]], align 8 -// CHECK9-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: store i32 [[INC28]], i32* [[A27]], align 8 -// CHECK9-NEXT: br label [[FOR_COND14]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK9: for.end29: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK9-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK9-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A5:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK9-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK9-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[A6]], i32** [[A5]], align 8 -// CHECK9-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A7]], align 4 -// CHECK9-NEXT: br label [[FOR_COND8:%.*]] -// CHECK9: for.cond8: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP6]], 2 -// CHECK9-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END14:%.*]] -// CHECK9: for.body10: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: [[INC11:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC11]], i32* [[TMP7]], align 4 -// CHECK9-NEXT: br label [[FOR_INC12:%.*]] -// CHECK9: for.inc12: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK9-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[INC13]], i32* [[TMP9]], align 4 -// CHECK9-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK9: for.end14: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK10-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[ARRAYIDX2]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK10-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK10-NEXT: br label [[FOR_COND4:%.*]] -// CHECK10: for.cond4: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 2 -// CHECK10-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END10:%.*]] -// CHECK10: for.body6: -// CHECK10-NEXT: [[TMP9:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: [[INC7:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK10-NEXT: store double [[INC7]], double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: br label [[FOR_INC8:%.*]] -// CHECK10: for.inc8: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK10-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[INC9]], i32* [[I3]], align 4 -// CHECK10-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK10: for.end10: -// CHECK10-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK10-NEXT: br label [[FOR_COND12:%.*]] -// CHECK10: for.cond12: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK10-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK10-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END18:%.*]] -// CHECK10: for.body14: -// CHECK10-NEXT: [[TMP12:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: [[INC15:%.*]] = fadd double [[TMP12]], 1.000000e+00 -// CHECK10-NEXT: store double [[INC15]], double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: br label [[FOR_INC16:%.*]] -// CHECK10: for.inc16: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK10-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[INC17]], i32* [[I11]], align 4 -// CHECK10-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end18: -// CHECK10-NEXT: store i8 0, i8* @cnt, align 1 -// CHECK10-NEXT: br label [[FOR_COND19:%.*]] -// CHECK10: for.cond19: -// CHECK10-NEXT: [[TMP14:%.*]] = load i8, i8* @cnt, align 1 -// CHECK10-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK10-NEXT: [[CMP20:%.*]] = icmp slt i32 [[CONV]], 2 -// CHECK10-NEXT: br i1 [[CMP20]], label [[FOR_BODY21:%.*]], label [[FOR_END25:%.*]] -// CHECK10: for.body21: -// CHECK10-NEXT: [[TMP15:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: [[INC22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK10-NEXT: store double [[INC22]], double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: store float 0.000000e+00, float* @f, align 4 -// CHECK10-NEXT: br label [[FOR_INC23:%.*]] -// CHECK10: for.inc23: -// CHECK10-NEXT: [[TMP16:%.*]] = load i8, i8* @cnt, align 1 -// CHECK10-NEXT: [[INC24:%.*]] = add i8 [[TMP16]], 1 -// CHECK10-NEXT: store i8 [[INC24]], i8* @cnt, align 1 -// CHECK10-NEXT: br label [[FOR_COND19]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK10: for.end25: -// CHECK10-NEXT: [[CALL26:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL26]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done27: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP18]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK10-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP6]]) -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done4: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP10]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK10-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A11:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK10-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK10-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK10-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK10-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK10-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK10-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK10-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK10-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK10-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK10-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK10-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK10-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK10-NEXT: store i32 [[DEC]], i32* [[B5]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: store i32 [[INC10]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[A12]], i32** [[A11]], align 8 -// CHECK10-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A13]], align 8 -// CHECK10-NEXT: br label [[FOR_COND14:%.*]] -// CHECK10: for.cond14: -// CHECK10-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[A15]], align 8 -// CHECK10-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP12]], 2 -// CHECK10-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END29:%.*]] -// CHECK10: for.body17: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A11]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK10-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[INC18]], i32* [[TMP13]], align 4 -// CHECK10-NEXT: [[B19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK10-NEXT: [[BF_LOAD20:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK10-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD20]], 4 -// CHECK10-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK10-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK10-NEXT: [[DEC21:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK10-NEXT: [[TMP15:%.*]] = trunc i32 [[DEC21]] to i8 -// CHECK10-NEXT: [[BF_LOAD22:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK10-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP15]], 15 -// CHECK10-NEXT: [[BF_CLEAR23:%.*]] = and i8 [[BF_LOAD22]], -16 -// CHECK10-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR23]], [[BF_VALUE]] -// CHECK10-NEXT: store i8 [[BF_SET]], i8* [[B19]], align 8 -// CHECK10-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK10-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK10-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK10-NEXT: [[C24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C24]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK10-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP17]], 1 -// CHECK10-NEXT: store i32 [[DIV25]], i32* [[TMP16]], align 4 -// CHECK10-NEXT: br label [[FOR_INC26:%.*]] -// CHECK10: for.inc26: -// CHECK10-NEXT: [[A27:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[A27]], align 8 -// CHECK10-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: store i32 [[INC28]], i32* [[A27]], align 8 -// CHECK10-NEXT: br label [[FOR_COND14]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK10: for.end29: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK10-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK10-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A5:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK10-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK10-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[A6]], i32** [[A5]], align 8 -// CHECK10-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A7]], align 4 -// CHECK10-NEXT: br label [[FOR_COND8:%.*]] -// CHECK10: for.cond8: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP6]], 2 -// CHECK10-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END14:%.*]] -// CHECK10: for.body10: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: [[INC11:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC11]], i32* [[TMP7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC12:%.*]] -// CHECK10: for.inc12: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK10-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[INC13]], i32* [[TMP9]], align 4 -// CHECK10-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK10: for.end14: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK11-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK11-NEXT: [[A10:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[REF_TMP17:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK11-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK11-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK11-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK11-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK11-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK11-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK11-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK11-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP6]], align 8 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK11-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK11-NEXT: store i32* [[B5]], i32** [[TMP9]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK11-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK11-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(32) [[REF_TMP]]) -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: [[A11:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32* [[A11]], i32** [[A10]], align 8 -// CHECK11-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[A12]], align 8 -// CHECK11-NEXT: br label [[FOR_COND13:%.*]] -// CHECK11: for.cond13: -// CHECK11-NEXT: [[A14:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[A14]], align 8 -// CHECK11-NEXT: [[CMP15:%.*]] = icmp slt i32 [[TMP13]], 2 -// CHECK11-NEXT: br i1 [[CMP15]], label [[FOR_BODY16:%.*]], label [[FOR_END21:%.*]] -// CHECK11: for.body16: -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP17]], i32 0, i32 0 -// CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP14]], align 8 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP17]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[A10]], align 8 -// CHECK11-NEXT: store i32* [[TMP16]], i32** [[TMP15]], align 8 -// CHECK11-NEXT: call void @_ZZN2SSC1ERiENKUlvE0_clEv(%class.anon.1* nonnull dereferenceable(16) [[REF_TMP17]]) -// CHECK11-NEXT: br label [[FOR_INC18:%.*]] -// CHECK11: for.inc18: -// CHECK11-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[A19]], align 8 -// CHECK11-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK11-NEXT: store i32 [[INC20]], i32* [[A19]], align 8 -// CHECK11-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK11: for.end21: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK11-SAME: (%class.anon.0* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK11-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK11-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK11-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK11-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK11-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP19]], 2 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: store i32 [[INC5]], i32* [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK11-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP22]], -1 -// CHECK11-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP24]], 1 -// CHECK11-NEXT: store i32 [[DIV7]], i32* [[TMP23]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP25]], 1 -// CHECK11-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE0_clEv -// CHECK11-SAME: (%class.anon.1* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR2]] align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %class.anon.1*, %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1:%.*]], %class.anon.1* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP4]], -1 -// CHECK11-NEXT: store i32 [[DEC]], i32* [[TMP3]], align 4 -// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 2 -// CHECK11-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK11-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD]], 4 -// CHECK11-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK11-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[BF_CAST]], 1 -// CHECK11-NEXT: [[TMP5:%.*]] = trunc i32 [[INC]] to i8 -// CHECK11-NEXT: [[BF_LOAD2:%.*]] = load i8, i8* [[B]], align 8 -// CHECK11-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP5]], 15 -// CHECK11-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD2]], -16 -// CHECK11-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], [[BF_VALUE]] -// CHECK11-NEXT: store i8 [[BF_SET]], i8* [[B]], align 8 -// CHECK11-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK11-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK11-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 2 -// CHECK11-NEXT: store i32 [[MUL]], i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK11-NEXT: store i32* [[TMP9]], i32** [[TMP]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK11-NEXT: store i32* [[TMP10]], i32** [[_TMP4]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[B3]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK11-NEXT: store i32 [[INC5]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK11-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP14]], -1 -// CHECK11-NEXT: store i32 [[DEC6]], i32* [[B3]], align 4 -// CHECK11-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP16]], 1 -// CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP15]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK11-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK11-NEXT: store i32 [[INC8]], i32* [[B3]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, align 128 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** @g1, align 8 -// CHECK12-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: store i32 1, i32* @g, align 128 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store volatile i32 1, i32* [[TMP2]], align 4 -// CHECK12-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: store i32 1, i32* @g, align 128 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store volatile i32 1, i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK12-NEXT: store volatile i32 [[TMP4]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED2]], align 32 -// CHECK12-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED3]], align 8 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP7]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP8]], align 8 -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP11]](i8* [[TMP9]]) -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>*, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR1]], align 32 -// CHECK12-NEXT: store i32 1, i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK12-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK12-NEXT: [[A12:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[BLOCK19:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, align 8 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK12-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK12-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK12-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK12-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK12-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK12-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK12-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK12-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK12-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK12-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK12-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK12-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[TMP6]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED10:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[BLOCK_CAPTURED10]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED11:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK12-NEXT: store i32* [[TMP8]], i32** [[BLOCK_CAPTURED11]], align 8 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP9]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP12:%.*]] = load i8*, i8** [[TMP10]], align 8 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8* [[TMP12]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP13]](i8* [[TMP11]]) -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32* [[A13]], i32** [[A12]], align 8 -// CHECK12-NEXT: [[A14:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[A14]], align 8 -// CHECK12-NEXT: br label [[FOR_COND15:%.*]] -// CHECK12: for.cond15: -// CHECK12-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[A16]], align 8 -// CHECK12-NEXT: [[CMP17:%.*]] = icmp slt i32 [[TMP15]], 2 -// CHECK12-NEXT: br i1 [[CMP17]], label [[FOR_BODY18:%.*]], label [[FOR_END31:%.*]] -// CHECK12: for.body18: -// CHECK12-NEXT: [[BLOCK_ISA20:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA20]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS21:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS21]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED22:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED22]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE23:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE23]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR24:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR24]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS_ADDR25:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 5 -// CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR25]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED26:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32*, i32** [[A12]], align 8 -// CHECK12-NEXT: store i32* [[TMP16]], i32** [[BLOCK_CAPTURED26]], align 8 -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL27:%.*]] = bitcast void ()* [[TMP17]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC]], %struct.__block_literal_generic* [[BLOCK_LITERAL27]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL27]] to i8* -// CHECK12-NEXT: [[TMP20:%.*]] = load i8*, i8** [[TMP18]], align 8 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8* [[TMP20]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP21]](i8* [[TMP19]]) -// CHECK12-NEXT: br label [[FOR_INC28:%.*]] -// CHECK12: for.inc28: -// CHECK12-NEXT: [[A29:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[A29]], align 8 -// CHECK12-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK12-NEXT: store i32 [[INC30]], i32* [[A29]], align 8 -// CHECK12-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK12: for.end31: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK12-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK12-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 -// CHECK12-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[TMP7]], i32** [[_TMP7]], align 8 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP6]], align 8 -// CHECK12-NEXT: store i32* [[TMP8]], i32** [[_TMP8]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP9]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: store i32 [[INC9]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK12-NEXT: [[DEC10:%.*]] = add nsw i32 [[TMP12]], -1 -// CHECK12-NEXT: store i32 [[DEC10]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[DIV11:%.*]] = sdiv i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[DIV11]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: store i32 [[INC12]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke_2 -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[C4:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS]], i32 0, i32 2 -// CHECK12-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK12-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD]], 4 -// CHECK12-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK12-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK12-NEXT: [[TMP2:%.*]] = trunc i32 [[DEC]] to i8 -// CHECK12-NEXT: [[BF_LOAD1:%.*]] = load i8, i8* [[B]], align 8 -// CHECK12-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP2]], 15 -// CHECK12-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD1]], -16 -// CHECK12-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], [[BF_VALUE]] -// CHECK12-NEXT: store i8 [[BF_SET]], i8* [[B]], align 8 -// CHECK12-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK12-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK12-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK12-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK12-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[TMP6]], i32** [[_TMP3]], align 8 -// CHECK12-NEXT: [[C5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK12-NEXT: store i32* [[TMP7]], i32** [[C4]], align 8 -// CHECK12-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[TMP8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK12-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[INC8]], i32* [[TMP11]], align 4 -// CHECK12-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 2 -// CHECK12-NEXT: [[BF_LOAD10:%.*]] = load i8, i8* [[B9]], align 8 -// CHECK12-NEXT: [[BF_SHL11:%.*]] = shl i8 [[BF_LOAD10]], 4 -// CHECK12-NEXT: [[BF_ASHR12:%.*]] = ashr i8 [[BF_SHL11]], 4 -// CHECK12-NEXT: [[BF_CAST13:%.*]] = sext i8 [[BF_ASHR12]] to i32 -// CHECK12-NEXT: [[DEC14:%.*]] = add nsw i32 [[BF_CAST13]], -1 -// CHECK12-NEXT: [[TMP13:%.*]] = trunc i32 [[DEC14]] to i8 -// CHECK12-NEXT: [[BF_LOAD15:%.*]] = load i8, i8* [[B9]], align 8 -// CHECK12-NEXT: [[BF_VALUE16:%.*]] = and i8 [[TMP13]], 15 -// CHECK12-NEXT: [[BF_CLEAR17:%.*]] = and i8 [[BF_LOAD15]], -16 -// CHECK12-NEXT: [[BF_SET18:%.*]] = or i8 [[BF_CLEAR17]], [[BF_VALUE16]] -// CHECK12-NEXT: store i8 [[BF_SET18]], i8* [[B9]], align 8 -// CHECK12-NEXT: [[BF_RESULT_SHL19:%.*]] = shl i8 [[BF_VALUE16]], 4 -// CHECK12-NEXT: [[BF_RESULT_ASHR20:%.*]] = ashr i8 [[BF_RESULT_SHL19]], 4 -// CHECK12-NEXT: [[BF_RESULT_CAST21:%.*]] = sext i8 [[BF_RESULT_ASHR20]] to i32 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32*, i32** [[C4]], align 8 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK12-NEXT: [[DIV22:%.*]] = sdiv i32 [[TMP15]], 1 -// CHECK12-NEXT: store i32 [[DIV22]], i32* [[TMP14]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[C23:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C23]], align 8 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK12-NEXT: [[INC24:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK12-NEXT: store i32 [[INC24]], i32* [[TMP16]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK13-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[ARRAYIDX2]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK13-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK13-NEXT: br label [[FOR_COND4:%.*]] -// CHECK13: for.cond4: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK13-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 2 -// CHECK13-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END10:%.*]] -// CHECK13: for.body6: -// CHECK13-NEXT: [[TMP9:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: [[INC7:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC7]], double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: br label [[FOR_INC8:%.*]] -// CHECK13: for.inc8: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK13-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC9]], i32* [[I3]], align 4 -// CHECK13-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end10: -// CHECK13-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK13-NEXT: br label [[FOR_COND12:%.*]] -// CHECK13: for.cond12: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK13-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK13-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body14: -// CHECK13-NEXT: [[TMP12:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: [[INC15:%.*]] = fadd double [[TMP12]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC15]], double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I11]], align 4 -// CHECK13-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: store i8 0, i8* @cnt, align 1 -// CHECK13-NEXT: br label [[FOR_COND19:%.*]] -// CHECK13: for.cond19: -// CHECK13-NEXT: [[TMP14:%.*]] = load i8, i8* @cnt, align 1 -// CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK13-NEXT: [[CMP20:%.*]] = icmp slt i32 [[CONV]], 2 -// CHECK13-NEXT: br i1 [[CMP20]], label [[FOR_BODY21:%.*]], label [[FOR_END25:%.*]] -// CHECK13: for.body21: -// CHECK13-NEXT: [[TMP15:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: [[INC22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC22]], double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: store float 0.000000e+00, float* @f, align 4 -// CHECK13-NEXT: br label [[FOR_INC23:%.*]] -// CHECK13: for.inc23: -// CHECK13-NEXT: [[TMP16:%.*]] = load i8, i8* @cnt, align 1 -// CHECK13-NEXT: [[INC24:%.*]] = add i8 [[TMP16]], 1 -// CHECK13-NEXT: store i8 [[INC24]], i8* @cnt, align 1 -// CHECK13-NEXT: br label [[FOR_COND19]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end25: -// CHECK13-NEXT: [[CALL26:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL26]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done27: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK13-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK13-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP6]]) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done4: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP10]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK13-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK13-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A11:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK13-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK13-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK13-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK13-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK13-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK13-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK13-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK13-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK13-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK13-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK13-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK13-NEXT: store i32 [[DEC]], i32* [[B5]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC10]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A12]], i32** [[A11]], align 8 -// CHECK13-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A13]], align 8 -// CHECK13-NEXT: br label [[FOR_COND14:%.*]] -// CHECK13: for.cond14: -// CHECK13-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[A15]], align 8 -// CHECK13-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP12]], 2 -// CHECK13-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END29:%.*]] -// CHECK13: for.body17: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A11]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK13-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[INC18]], i32* [[TMP13]], align 4 -// CHECK13-NEXT: [[B19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK13-NEXT: [[BF_LOAD20:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK13-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD20]], 4 -// CHECK13-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK13-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK13-NEXT: [[DEC21:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK13-NEXT: [[TMP15:%.*]] = trunc i32 [[DEC21]] to i8 -// CHECK13-NEXT: [[BF_LOAD22:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK13-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP15]], 15 -// CHECK13-NEXT: [[BF_CLEAR23:%.*]] = and i8 [[BF_LOAD22]], -16 -// CHECK13-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR23]], [[BF_VALUE]] -// CHECK13-NEXT: store i8 [[BF_SET]], i8* [[B19]], align 8 -// CHECK13-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK13-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK13-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK13-NEXT: [[C24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C24]], align 8 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK13-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP17]], 1 -// CHECK13-NEXT: store i32 [[DIV25]], i32* [[TMP16]], align 4 -// CHECK13-NEXT: br label [[FOR_INC26:%.*]] -// CHECK13: for.inc26: -// CHECK13-NEXT: [[A27:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[A27]], align 8 -// CHECK13-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK13-NEXT: store i32 [[INC28]], i32* [[A27]], align 8 -// CHECK13-NEXT: br label [[FOR_COND14]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK13: for.end29: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK13-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK13-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A5:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK13-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A6]], i32** [[A5]], align 8 -// CHECK13-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A7]], align 4 -// CHECK13-NEXT: br label [[FOR_COND8:%.*]] -// CHECK13: for.cond8: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK13-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP6]], 2 -// CHECK13-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END14:%.*]] -// CHECK13: for.body10: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK13-NEXT: [[INC11:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC11]], i32* [[TMP7]], align 4 -// CHECK13-NEXT: br label [[FOR_INC12:%.*]] -// CHECK13: for.inc12: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK13-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC13]], i32* [[TMP9]], align 4 -// CHECK13-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK13: for.end14: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK14-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[ARRAYIDX2]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK14-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK14-NEXT: br label [[FOR_COND4:%.*]] -// CHECK14: for.cond4: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK14-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 2 -// CHECK14-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END10:%.*]] -// CHECK14: for.body6: -// CHECK14-NEXT: [[TMP9:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: [[INC7:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC7]], double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: br label [[FOR_INC8:%.*]] -// CHECK14: for.inc8: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK14-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC9]], i32* [[I3]], align 4 -// CHECK14-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end10: -// CHECK14-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK14-NEXT: br label [[FOR_COND12:%.*]] -// CHECK14: for.cond12: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK14-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK14-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body14: -// CHECK14-NEXT: [[TMP12:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: [[INC15:%.*]] = fadd double [[TMP12]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC15]], double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I11]], align 4 -// CHECK14-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: store i8 0, i8* @cnt, align 1 -// CHECK14-NEXT: br label [[FOR_COND19:%.*]] -// CHECK14: for.cond19: -// CHECK14-NEXT: [[TMP14:%.*]] = load i8, i8* @cnt, align 1 -// CHECK14-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK14-NEXT: [[CMP20:%.*]] = icmp slt i32 [[CONV]], 2 -// CHECK14-NEXT: br i1 [[CMP20]], label [[FOR_BODY21:%.*]], label [[FOR_END25:%.*]] -// CHECK14: for.body21: -// CHECK14-NEXT: [[TMP15:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: [[INC22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC22]], double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: store float 0.000000e+00, float* @f, align 4 -// CHECK14-NEXT: br label [[FOR_INC23:%.*]] -// CHECK14: for.inc23: -// CHECK14-NEXT: [[TMP16:%.*]] = load i8, i8* @cnt, align 1 -// CHECK14-NEXT: [[INC24:%.*]] = add i8 [[TMP16]], 1 -// CHECK14-NEXT: store i8 [[INC24]], i8* @cnt, align 1 -// CHECK14-NEXT: br label [[FOR_COND19]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end25: -// CHECK14-NEXT: [[CALL26:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL26]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done27: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK14-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK14-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP6]]) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP10]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK14-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK14-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A11:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK14-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK14-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK14-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK14-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK14-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK14-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK14-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK14-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK14-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK14-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK14-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK14-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK14-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK14-NEXT: store i32 [[DEC]], i32* [[B5]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC10]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A12]], i32** [[A11]], align 8 -// CHECK14-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A13]], align 8 -// CHECK14-NEXT: br label [[FOR_COND14:%.*]] -// CHECK14: for.cond14: -// CHECK14-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[A15]], align 8 -// CHECK14-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP12]], 2 -// CHECK14-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END29:%.*]] -// CHECK14: for.body17: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A11]], align 8 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK14-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[INC18]], i32* [[TMP13]], align 4 -// CHECK14-NEXT: [[B19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK14-NEXT: [[BF_LOAD20:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK14-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD20]], 4 -// CHECK14-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK14-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK14-NEXT: [[DEC21:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK14-NEXT: [[TMP15:%.*]] = trunc i32 [[DEC21]] to i8 -// CHECK14-NEXT: [[BF_LOAD22:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK14-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP15]], 15 -// CHECK14-NEXT: [[BF_CLEAR23:%.*]] = and i8 [[BF_LOAD22]], -16 -// CHECK14-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR23]], [[BF_VALUE]] -// CHECK14-NEXT: store i8 [[BF_SET]], i8* [[B19]], align 8 -// CHECK14-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK14-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK14-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK14-NEXT: [[C24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK14-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C24]], align 8 -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK14-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP17]], 1 -// CHECK14-NEXT: store i32 [[DIV25]], i32* [[TMP16]], align 4 -// CHECK14-NEXT: br label [[FOR_INC26:%.*]] -// CHECK14: for.inc26: -// CHECK14-NEXT: [[A27:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[A27]], align 8 -// CHECK14-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK14-NEXT: store i32 [[INC28]], i32* [[A27]], align 8 -// CHECK14-NEXT: br label [[FOR_COND14]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK14: for.end29: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK14-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK14-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A5:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK14-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A6]], i32** [[A5]], align 8 -// CHECK14-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A7]], align 4 -// CHECK14-NEXT: br label [[FOR_COND8:%.*]] -// CHECK14: for.cond8: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK14-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP6]], 2 -// CHECK14-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END14:%.*]] -// CHECK14: for.body10: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK14-NEXT: [[INC11:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC11]], i32* [[TMP7]], align 4 -// CHECK14-NEXT: br label [[FOR_INC12:%.*]] -// CHECK14: for.inc12: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK14-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC13]], i32* [[TMP9]], align 4 -// CHECK14-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK14: for.end14: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK15-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK15-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK15-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK15-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK15-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK15-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK15-NEXT: [[A10:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[REF_TMP17:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK15-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK15-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK15-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK15-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK15-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK15-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK15-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK15-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK15-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK15-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK15-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP6]], align 8 -// CHECK15-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK15-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK15-NEXT: store i32* [[B5]], i32** [[TMP9]], align 8 -// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK15-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK15-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(32) [[REF_TMP]]) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[A11:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32* [[A11]], i32** [[A10]], align 8 -// CHECK15-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A12]], align 8 -// CHECK15-NEXT: br label [[FOR_COND13:%.*]] -// CHECK15: for.cond13: -// CHECK15-NEXT: [[A14:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[A14]], align 8 -// CHECK15-NEXT: [[CMP15:%.*]] = icmp slt i32 [[TMP13]], 2 -// CHECK15-NEXT: br i1 [[CMP15]], label [[FOR_BODY16:%.*]], label [[FOR_END21:%.*]] -// CHECK15: for.body16: -// CHECK15-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP17]], i32 0, i32 0 -// CHECK15-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP14]], align 8 -// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP17]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32*, i32** [[A10]], align 8 -// CHECK15-NEXT: store i32* [[TMP16]], i32** [[TMP15]], align 8 -// CHECK15-NEXT: call void @_ZZN2SSC1ERiENKUlvE0_clEv(%class.anon.1* nonnull dereferenceable(16) [[REF_TMP17]]) -// CHECK15-NEXT: br label [[FOR_INC18:%.*]] -// CHECK15: for.inc18: -// CHECK15-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[A19]], align 8 -// CHECK15-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK15-NEXT: store i32 [[INC20]], i32* [[A19]], align 8 -// CHECK15-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end21: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK15-SAME: (%class.anon.0* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK15-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK15-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK15-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK15-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK15-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP19]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK15-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK15-NEXT: store i32 [[INC5]], i32* [[TMP20]], align 4 -// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK15-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP22]], -1 -// CHECK15-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4 -// CHECK15-NEXT: [[TMP23:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK15-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP24]], 1 -// CHECK15-NEXT: store i32 [[DIV7]], i32* [[TMP23]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP25]], 1 -// CHECK15-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE0_clEv -// CHECK15-SAME: (%class.anon.1* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR2]] align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %class.anon.1*, %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1:%.*]], %class.anon.1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP4]], -1 -// CHECK15-NEXT: store i32 [[DEC]], i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 2 -// CHECK15-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK15-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD]], 4 -// CHECK15-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK15-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[BF_CAST]], 1 -// CHECK15-NEXT: [[TMP5:%.*]] = trunc i32 [[INC]] to i8 -// CHECK15-NEXT: [[BF_LOAD2:%.*]] = load i8, i8* [[B]], align 8 -// CHECK15-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP5]], 15 -// CHECK15-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD2]], -16 -// CHECK15-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], [[BF_VALUE]] -// CHECK15-NEXT: store i8 [[BF_SET]], i8* [[B]], align 8 -// CHECK15-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK15-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK15-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK15-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 2 -// CHECK15-NEXT: store i32 [[MUL]], i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK15-NEXT: store i32* [[TMP9]], i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK15-NEXT: store i32* [[TMP10]], i32** [[_TMP4]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[B3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK15-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK15-NEXT: store i32 [[INC5]], i32* [[TMP12]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK15-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP14]], -1 -// CHECK15-NEXT: store i32 [[DEC6]], i32* [[B3]], align 4 -// CHECK15-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP15:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP16]], 1 -// CHECK15-NEXT: store i32 [[DIV]], i32* [[TMP15]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK15-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK15-NEXT: store i32 [[INC8]], i32* [[B3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK16-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK16-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK16-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, align 128 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** @g1, align 8 -// CHECK16-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 1, i32* @g, align 128 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store volatile i32 1, i32* [[TMP2]], align 4 -// CHECK16-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: store i32 1, i32* @g, align 128 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store volatile i32 1, i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: store volatile i32 [[TMP4]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK16-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED2]], align 32 -// CHECK16-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED3]], align 8 -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP7]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP8]], align 8 -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP11]](i8* [[TMP9]]) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>*, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR1]], align 32 -// CHECK16-NEXT: store i32 1, i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK16-SAME: (%struct.SS* nonnull dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK16-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK16-NEXT: [[A12:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[BLOCK19:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, align 8 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK16-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK16-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK16-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK16-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK16-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK16-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK16-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK16-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK16-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK16-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK16-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK16-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32* [[TMP6]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED10:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK16-NEXT: store i32 [[TMP7]], i32* [[BLOCK_CAPTURED10]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED11:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK16-NEXT: store i32* [[TMP8]], i32** [[BLOCK_CAPTURED11]], align 8 -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP9]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP12:%.*]] = load i8*, i8** [[TMP10]], align 8 -// CHECK16-NEXT: [[TMP13:%.*]] = bitcast i8* [[TMP12]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP13]](i8* [[TMP11]]) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32* [[A13]], i32** [[A12]], align 8 -// CHECK16-NEXT: [[A14:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A14]], align 8 -// CHECK16-NEXT: br label [[FOR_COND15:%.*]] -// CHECK16: for.cond15: -// CHECK16-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[A16]], align 8 -// CHECK16-NEXT: [[CMP17:%.*]] = icmp slt i32 [[TMP15]], 2 -// CHECK16-NEXT: br i1 [[CMP17]], label [[FOR_BODY18:%.*]], label [[FOR_END31:%.*]] -// CHECK16: for.body18: -// CHECK16-NEXT: [[BLOCK_ISA20:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA20]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS21:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS21]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED22:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED22]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE23:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE23]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR24:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR24]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS_ADDR25:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 5 -// CHECK16-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR25]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED26:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32*, i32** [[A12]], align 8 -// CHECK16-NEXT: store i32* [[TMP16]], i32** [[BLOCK_CAPTURED26]], align 8 -// CHECK16-NEXT: [[TMP17:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL27:%.*]] = bitcast void ()* [[TMP17]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC]], %struct.__block_literal_generic* [[BLOCK_LITERAL27]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP19:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL27]] to i8* -// CHECK16-NEXT: [[TMP20:%.*]] = load i8*, i8** [[TMP18]], align 8 -// CHECK16-NEXT: [[TMP21:%.*]] = bitcast i8* [[TMP20]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP21]](i8* [[TMP19]]) -// CHECK16-NEXT: br label [[FOR_INC28:%.*]] -// CHECK16: for.inc28: -// CHECK16-NEXT: [[A29:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[A29]], align 8 -// CHECK16-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK16-NEXT: store i32 [[INC30]], i32* [[A29]], align 8 -// CHECK16-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end31: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK16-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK16-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK16-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 -// CHECK16-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32* [[TMP7]], i32** [[_TMP7]], align 8 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP6]], align 8 -// CHECK16-NEXT: store i32* [[TMP8]], i32** [[_TMP8]], align 8 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP9]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK16-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC9]], i32* [[TMP10]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK16-NEXT: [[DEC10:%.*]] = add nsw i32 [[TMP12]], -1 -// CHECK16-NEXT: store i32 [[DEC10]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK16-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK16-NEXT: [[DIV11:%.*]] = sdiv i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[DIV11]], i32* [[TMP13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK16-NEXT: store i32 [[INC12]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke_2 -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[C4:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS]], i32 0, i32 2 -// CHECK16-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK16-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD]], 4 -// CHECK16-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK16-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK16-NEXT: [[DEC:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK16-NEXT: [[TMP2:%.*]] = trunc i32 [[DEC]] to i8 -// CHECK16-NEXT: [[BF_LOAD1:%.*]] = load i8, i8* [[B]], align 8 -// CHECK16-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP2]], 15 -// CHECK16-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD1]], -16 -// CHECK16-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], [[BF_VALUE]] -// CHECK16-NEXT: store i8 [[BF_SET]], i8* [[B]], align 8 -// CHECK16-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK16-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK16-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK16-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK16-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32* [[TMP6]], i32** [[_TMP3]], align 8 -// CHECK16-NEXT: [[C5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK16-NEXT: store i32* [[TMP7]], i32** [[C4]], align 8 -// CHECK16-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK16-NEXT: store i32 0, i32* [[TMP8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK16-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC8]], i32* [[TMP11]], align 4 -// CHECK16-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 2 -// CHECK16-NEXT: [[BF_LOAD10:%.*]] = load i8, i8* [[B9]], align 8 -// CHECK16-NEXT: [[BF_SHL11:%.*]] = shl i8 [[BF_LOAD10]], 4 -// CHECK16-NEXT: [[BF_ASHR12:%.*]] = ashr i8 [[BF_SHL11]], 4 -// CHECK16-NEXT: [[BF_CAST13:%.*]] = sext i8 [[BF_ASHR12]] to i32 -// CHECK16-NEXT: [[DEC14:%.*]] = add nsw i32 [[BF_CAST13]], -1 -// CHECK16-NEXT: [[TMP13:%.*]] = trunc i32 [[DEC14]] to i8 -// CHECK16-NEXT: [[BF_LOAD15:%.*]] = load i8, i8* [[B9]], align 8 -// CHECK16-NEXT: [[BF_VALUE16:%.*]] = and i8 [[TMP13]], 15 -// CHECK16-NEXT: [[BF_CLEAR17:%.*]] = and i8 [[BF_LOAD15]], -16 -// CHECK16-NEXT: [[BF_SET18:%.*]] = or i8 [[BF_CLEAR17]], [[BF_VALUE16]] -// CHECK16-NEXT: store i8 [[BF_SET18]], i8* [[B9]], align 8 -// CHECK16-NEXT: [[BF_RESULT_SHL19:%.*]] = shl i8 [[BF_VALUE16]], 4 -// CHECK16-NEXT: [[BF_RESULT_ASHR20:%.*]] = ashr i8 [[BF_RESULT_SHL19]], 4 -// CHECK16-NEXT: [[BF_RESULT_CAST21:%.*]] = sext i8 [[BF_RESULT_ASHR20]] to i32 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32*, i32** [[C4]], align 8 -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK16-NEXT: [[DIV22:%.*]] = sdiv i32 [[TMP15]], 1 -// CHECK16-NEXT: store i32 [[DIV22]], i32* [[TMP14]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[C23:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C23]], align 8 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK16-NEXT: [[INC24:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK16-NEXT: store i32 [[INC24]], i32* [[TMP16]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// diff --git a/clang/test/OpenMP/for_linear_codegen.cpp b/clang/test/OpenMP/for_linear_codegen.cpp --- a/clang/test/OpenMP/for_linear_codegen.cpp +++ b/clang/test/OpenMP/for_linear_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -2570,980 +2570,3 @@ // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[PVAR:%.*]] = alloca float*, align 8 -// CHECK5-NEXT: [[LVAR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 -// CHECK5-NEXT: store float* [[F]], float** [[PVAR]], align 8 -// CHECK5-NEXT: store i64 0, i64* [[LVAR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[PVAR]], align 8 -// CHECK5-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3 -// CHECK5-NEXT: store float* [[ADD_PTR]], float** [[PVAR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[LVAR]], align 8 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP2]], 3 -// CHECK5-NEXT: store i64 [[ADD]], i64* [[LVAR]], align 8 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3:[0-9]+]] -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP4]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK5-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[LVAR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 -// CHECK5-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[F1]], i32** [[LVAR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[LVAR]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32* [[TMP1]], i32** [[_TMP2]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[PVAR]], align 8 -// CHECK5-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 1 -// CHECK5-NEXT: store i32* [[INCDEC_PTR]], i32** [[PVAR]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP4]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK5-NEXT: store i32 [[INC3]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK5-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK5-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK5-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK5-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK5-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK5-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK5-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[PVAR:%.*]] = alloca float*, align 8 -// CHECK6-NEXT: [[LVAR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 -// CHECK6-NEXT: store float* [[F]], float** [[PVAR]], align 8 -// CHECK6-NEXT: store i64 0, i64* [[LVAR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[PVAR]], align 8 -// CHECK6-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3 -// CHECK6-NEXT: store float* [[ADD_PTR]], float** [[PVAR]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[LVAR]], align 8 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP2]], 3 -// CHECK6-NEXT: store i64 [[ADD]], i64* [[LVAR]], align 8 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3:[0-9]+]] -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP4]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK6-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[LVAR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 -// CHECK6-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[F1]], i32** [[LVAR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[LVAR]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32* [[TMP1]], i32** [[_TMP2]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[PVAR]], align 8 -// CHECK6-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 1 -// CHECK6-NEXT: store i32* [[INCDEC_PTR]], i32** [[PVAR]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP4]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[INC3]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK6-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK6-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK6-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK6-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK6-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK6-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK6-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK6-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK7-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK7-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B4]], i32** [[TMP8]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK7-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 8 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(32) [[REF_TMP]]) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK7-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK7-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK7-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP19]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK7-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK7-NEXT: store i32 [[INC5]], i32* [[TMP20]], align 4 -// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP22]], -1 -// CHECK7-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK7-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP24]], 1 -// CHECK7-NEXT: store i32 [[DIV7]], i32* [[TMP23]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP25]], 1 -// CHECK7-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK2:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** @g1, align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 5 -// CHECK8-NEXT: store i32 [[ADD]], i32* @g, align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load volatile i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 5 -// CHECK8-NEXT: store volatile i32 [[ADD1]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: store i32 1, i32* @g, align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store volatile i32 5, i32* [[TMP5]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP6:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store volatile i32 [[TMP6]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED3]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP12]](i8* [[TMP10]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: store i32 2, i32* [[TMP0]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK8-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK8-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK8-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED8]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED9:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK8-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED9]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP12]](i8* [[TMP10]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 -// CHECK8-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP7]], i32** [[_TMP7]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP6]], align 8 -// CHECK8-NEXT: store i32* [[TMP8]], i32** [[_TMP8]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP9]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[TMP10]], align 4 -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK8-NEXT: [[DEC10:%.*]] = add nsw i32 [[TMP12]], -1 -// CHECK8-NEXT: store i32 [[DEC10]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK8-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK8-NEXT: [[DIV11:%.*]] = sdiv i32 [[TMP14]], 1 -// CHECK8-NEXT: store i32 [[DIV11]], i32* [[TMP13]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK8-NEXT: store i32 [[INC12]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/for_private_codegen.cpp b/clang/test/OpenMP/for_private_codegen.cpp --- a/clang/test/OpenMP/for_private_codegen.cpp +++ b/clang/test/OpenMP/for_private_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1326,773 +1326,3 @@ // CHECK4-NEXT: store float 9.000000e+00, float* [[BLOCK_CAPTURE_ADDR3]], align 4 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done8: -// CHECK5-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK5-NEXT: br label [[FOR_COND11:%.*]] -// CHECK5: for.cond11: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK5-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK5-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END16:%.*]] -// CHECK5: for.body13: -// CHECK5-NEXT: br label [[FOR_INC14:%.*]] -// CHECK5: for.inc14: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK5-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK5-NEXT: store i32 [[INC15]], i32* [[I10]], align 4 -// CHECK5-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end16: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] -// CHECK5: arraydestroy.body18: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END16]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] -// CHECK5: arraydestroy.done22: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP13]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done8: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK5: arraydestroy.body10: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK5: arraydestroy.done14: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP11]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done8: -// CHECK6-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK6-NEXT: br label [[FOR_COND11:%.*]] -// CHECK6: for.cond11: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK6-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK6-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END16:%.*]] -// CHECK6: for.body13: -// CHECK6-NEXT: br label [[FOR_INC14:%.*]] -// CHECK6: for.inc14: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK6-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK6-NEXT: store i32 [[INC15]], i32* [[I10]], align 4 -// CHECK6-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end16: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] -// CHECK6: arraydestroy.body18: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END16]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] -// CHECK6: arraydestroy.done22: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP13]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done8: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK6: arraydestroy.body10: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK6: arraydestroy.done14: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP11]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SFVAR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store double* [[G1]], double** [[TMP]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store double 1.000000e+00, double* [[G]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store volatile double 1.000000e+00, double* [[TMP1]], align 8 -// CHECK8-NEXT: store i32 2, i32* [[SVAR]], align 4 -// CHECK8-NEXT: store float 3.000000e+00, float* [[SFVAR]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP2:%.*]] = load volatile double, double* [[G]], align 8 -// CHECK8-NEXT: store volatile double [[TMP2]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP3:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store double* [[TMP3]], double** [[BLOCK_CAPTURED2]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[SVAR]], align 4 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[BLOCK_CAPTURED3]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load float, float* [[SFVAR]], align 4 -// CHECK8-NEXT: store float [[TMP5]], float* [[BLOCK_CAPTURED4]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP6]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP9:%.*]] = load i8*, i8** [[TMP7]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP10]](i8* [[TMP8]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load double*, double** [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: store double 2.000000e+00, double* [[TMP0]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: store float 9.000000e+00, float* [[BLOCK_CAPTURE_ADDR3]], align 4 -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/for_reduction_codegen.cpp b/clang/test/OpenMP/for_reduction_codegen.cpp --- a/clang/test/OpenMP/for_reduction_codegen.cpp +++ b/clang/test/OpenMP/for_reduction_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -8832,1436 +8832,3 @@ // CHECK4-NEXT: store double [[ADD2]], double* [[TMP17]], align 8 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [4 x %struct.S], align 16 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[ARRS:%.*]] = alloca [10 x [4 x %struct.S]], align 16 -// CHECK5-NEXT: [[VAR2:%.*]] = alloca %struct.S**, align 8 -// CHECK5-NEXT: [[VVAR2:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK5-NEXT: [[VAR3:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[_TMP10:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I54:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I68:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I75:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP82:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[_TMP83:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[I84:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP91:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[_TMP92:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[I93:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP100:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[_TMP101:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[I102:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP109:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[_TMP110:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[I111:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT1]], float 3.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT1]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT2]], float 4.000000e+00) -// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], [10 x [4 x %struct.S]]* [[ARRS]], i32 0, i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 40 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[CALL:%.*]] = call %struct.S** @_Z3foov() -// CHECK5-NEXT: store %struct.S** [[CALL]], %struct.S*** [[VAR2]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[VVAR2]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 5 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] -// CHECK5: arrayctor.loop5: -// CHECK5-NEXT: [[ARRAYCTOR_CUR6:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYCTOR_NEXT7:%.*]], [[ARRAYCTOR_LOOP5]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR6]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT7]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR6]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE8:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT7]], [[ARRAYCTOR_END4]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] -// CHECK5: arrayctor.cont9: -// CHECK5-NEXT: store [4 x %struct.S]* [[S_ARR]], [4 x %struct.S]** [[VAR3]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[_TMP10]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP10]], align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM11]] -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 1 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX13]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[TMP13:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP13]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP14:%.*]] = mul nuw i64 10, [[TMP12]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP14]], align 16 -// CHECK5-NEXT: store i64 [[TMP12]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK5-NEXT: br label [[FOR_COND15:%.*]] -// CHECK5: for.cond15: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK5-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP15]], 10 -// CHECK5-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK5: for.body17: -// CHECK5-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP16]] -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK5-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX18]], i64 [[IDXPROM19]] -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX20]], align 4 -// CHECK5-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK5-NEXT: store i32 [[INC21]], i32* [[ARRAYIDX20]], align 4 -// CHECK5-NEXT: br label [[FOR_INC22:%.*]] -// CHECK5: for.inc22: -// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK5-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK5-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK5-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end24: -// CHECK5-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK5-NEXT: br label [[FOR_COND26:%.*]] -// CHECK5: for.cond26: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK5-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP20]], 10 -// CHECK5-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK5: for.body28: -// CHECK5-NEXT: [[TMP21:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK5-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP21]] -// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK5-NEXT: [[IDXPROM30:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK5-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX29]], i64 [[IDXPROM30]] -// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX31]], align 4 -// CHECK5-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK5-NEXT: store i32 [[INC32]], i32* [[ARRAYIDX31]], align 4 -// CHECK5-NEXT: br label [[FOR_INC33:%.*]] -// CHECK5: for.inc33: -// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK5-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK5-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK5-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end35: -// CHECK5-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK5-NEXT: br label [[FOR_COND37:%.*]] -// CHECK5: for.cond37: -// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK5-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP25]], 10 -// CHECK5-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK5: for.body39: -// CHECK5-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK5-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP26]] -// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK5-NEXT: [[IDXPROM41:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK5-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX40]], i64 [[IDXPROM41]] -// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX42]], align 4 -// CHECK5-NEXT: [[INC43:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK5-NEXT: store i32 [[INC43]], i32* [[ARRAYIDX42]], align 4 -// CHECK5-NEXT: br label [[FOR_INC44:%.*]] -// CHECK5: for.inc44: -// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK5-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK5-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK5-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK5: for.end46: -// CHECK5-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK5-NEXT: br label [[FOR_COND48:%.*]] -// CHECK5: for.cond48: -// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK5-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP30]], 10 -// CHECK5-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END53:%.*]] -// CHECK5: for.body50: -// CHECK5-NEXT: br label [[FOR_INC51:%.*]] -// CHECK5: for.inc51: -// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK5-NEXT: [[INC52:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK5-NEXT: store i32 [[INC52]], i32* [[I47]], align 4 -// CHECK5-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK5: for.end53: -// CHECK5-NEXT: store i32 0, i32* [[I54]], align 4 -// CHECK5-NEXT: br label [[FOR_COND55:%.*]] -// CHECK5: for.cond55: -// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[I54]], align 4 -// CHECK5-NEXT: [[CMP56:%.*]] = icmp slt i32 [[TMP32]], 10 -// CHECK5-NEXT: br i1 [[CMP56]], label [[FOR_BODY57:%.*]], label [[FOR_END60:%.*]] -// CHECK5: for.body57: -// CHECK5-NEXT: br label [[FOR_INC58:%.*]] -// CHECK5: for.inc58: -// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[I54]], align 4 -// CHECK5-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP33]], 1 -// CHECK5-NEXT: store i32 [[INC59]], i32* [[I54]], align 4 -// CHECK5-NEXT: br label [[FOR_COND55]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK5: for.end60: -// CHECK5-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK5-NEXT: br label [[FOR_COND62:%.*]] -// CHECK5: for.cond62: -// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK5-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP34]], 10 -// CHECK5-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END67:%.*]] -// CHECK5: for.body64: -// CHECK5-NEXT: br label [[FOR_INC65:%.*]] -// CHECK5: for.inc65: -// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK5-NEXT: [[INC66:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK5-NEXT: store i32 [[INC66]], i32* [[I61]], align 4 -// CHECK5-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK5: for.end67: -// CHECK5-NEXT: store i32 0, i32* [[I68]], align 4 -// CHECK5-NEXT: br label [[FOR_COND69:%.*]] -// CHECK5: for.cond69: -// CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[I68]], align 4 -// CHECK5-NEXT: [[CMP70:%.*]] = icmp slt i32 [[TMP36]], 10 -// CHECK5-NEXT: br i1 [[CMP70]], label [[FOR_BODY71:%.*]], label [[FOR_END74:%.*]] -// CHECK5: for.body71: -// CHECK5-NEXT: br label [[FOR_INC72:%.*]] -// CHECK5: for.inc72: -// CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[I68]], align 4 -// CHECK5-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP37]], 1 -// CHECK5-NEXT: store i32 [[INC73]], i32* [[I68]], align 4 -// CHECK5-NEXT: br label [[FOR_COND69]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK5: for.end74: -// CHECK5-NEXT: store i32 0, i32* [[I75]], align 4 -// CHECK5-NEXT: br label [[FOR_COND76:%.*]] -// CHECK5: for.cond76: -// CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[I75]], align 4 -// CHECK5-NEXT: [[CMP77:%.*]] = icmp slt i32 [[TMP38]], 10 -// CHECK5-NEXT: br i1 [[CMP77]], label [[FOR_BODY78:%.*]], label [[FOR_END81:%.*]] -// CHECK5: for.body78: -// CHECK5-NEXT: br label [[FOR_INC79:%.*]] -// CHECK5: for.inc79: -// CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[I75]], align 4 -// CHECK5-NEXT: [[INC80:%.*]] = add nsw i32 [[TMP39]], 1 -// CHECK5-NEXT: store i32 [[INC80]], i32* [[I75]], align 4 -// CHECK5-NEXT: br label [[FOR_COND76]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK5: for.end81: -// CHECK5-NEXT: [[TMP40:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP40]], [4 x %struct.S]** [[_TMP82]], align 8 -// CHECK5-NEXT: [[TMP41:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP82]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP41]], [4 x %struct.S]** [[_TMP83]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I84]], align 4 -// CHECK5-NEXT: br label [[FOR_COND85:%.*]] -// CHECK5: for.cond85: -// CHECK5-NEXT: [[TMP42:%.*]] = load i32, i32* [[I84]], align 4 -// CHECK5-NEXT: [[CMP86:%.*]] = icmp slt i32 [[TMP42]], 10 -// CHECK5-NEXT: br i1 [[CMP86]], label [[FOR_BODY87:%.*]], label [[FOR_END90:%.*]] -// CHECK5: for.body87: -// CHECK5-NEXT: br label [[FOR_INC88:%.*]] -// CHECK5: for.inc88: -// CHECK5-NEXT: [[TMP43:%.*]] = load i32, i32* [[I84]], align 4 -// CHECK5-NEXT: [[INC89:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK5-NEXT: store i32 [[INC89]], i32* [[I84]], align 4 -// CHECK5-NEXT: br label [[FOR_COND85]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK5: for.end90: -// CHECK5-NEXT: [[TMP44:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP44]], [4 x %struct.S]** [[_TMP91]], align 8 -// CHECK5-NEXT: [[TMP45:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP91]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP45]], [4 x %struct.S]** [[_TMP92]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I93]], align 4 -// CHECK5-NEXT: br label [[FOR_COND94:%.*]] -// CHECK5: for.cond94: -// CHECK5-NEXT: [[TMP46:%.*]] = load i32, i32* [[I93]], align 4 -// CHECK5-NEXT: [[CMP95:%.*]] = icmp slt i32 [[TMP46]], 10 -// CHECK5-NEXT: br i1 [[CMP95]], label [[FOR_BODY96:%.*]], label [[FOR_END99:%.*]] -// CHECK5: for.body96: -// CHECK5-NEXT: br label [[FOR_INC97:%.*]] -// CHECK5: for.inc97: -// CHECK5-NEXT: [[TMP47:%.*]] = load i32, i32* [[I93]], align 4 -// CHECK5-NEXT: [[INC98:%.*]] = add nsw i32 [[TMP47]], 1 -// CHECK5-NEXT: store i32 [[INC98]], i32* [[I93]], align 4 -// CHECK5-NEXT: br label [[FOR_COND94]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK5: for.end99: -// CHECK5-NEXT: [[TMP48:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP48]], [4 x %struct.S]** [[_TMP100]], align 8 -// CHECK5-NEXT: [[TMP49:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP100]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP49]], [4 x %struct.S]** [[_TMP101]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I102]], align 4 -// CHECK5-NEXT: br label [[FOR_COND103:%.*]] -// CHECK5: for.cond103: -// CHECK5-NEXT: [[TMP50:%.*]] = load i32, i32* [[I102]], align 4 -// CHECK5-NEXT: [[CMP104:%.*]] = icmp slt i32 [[TMP50]], 10 -// CHECK5-NEXT: br i1 [[CMP104]], label [[FOR_BODY105:%.*]], label [[FOR_END108:%.*]] -// CHECK5: for.body105: -// CHECK5-NEXT: br label [[FOR_INC106:%.*]] -// CHECK5: for.inc106: -// CHECK5-NEXT: [[TMP51:%.*]] = load i32, i32* [[I102]], align 4 -// CHECK5-NEXT: [[INC107:%.*]] = add nsw i32 [[TMP51]], 1 -// CHECK5-NEXT: store i32 [[INC107]], i32* [[I102]], align 4 -// CHECK5-NEXT: br label [[FOR_COND103]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK5: for.end108: -// CHECK5-NEXT: [[TMP52:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP52]], [4 x %struct.S]** [[_TMP109]], align 8 -// CHECK5-NEXT: [[TMP53:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP109]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP53]], [4 x %struct.S]** [[_TMP110]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I111]], align 4 -// CHECK5-NEXT: br label [[FOR_COND112:%.*]] -// CHECK5: for.cond112: -// CHECK5-NEXT: [[TMP54:%.*]] = load i32, i32* [[I111]], align 4 -// CHECK5-NEXT: [[CMP113:%.*]] = icmp slt i32 [[TMP54]], 10 -// CHECK5-NEXT: br i1 [[CMP113]], label [[FOR_BODY114:%.*]], label [[FOR_END117:%.*]] -// CHECK5: for.body114: -// CHECK5-NEXT: br label [[FOR_INC115:%.*]] -// CHECK5: for.inc115: -// CHECK5-NEXT: [[TMP55:%.*]] = load i32, i32* [[I111]], align 4 -// CHECK5-NEXT: [[INC116:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK5-NEXT: store i32 [[INC116]], i32* [[I111]], align 4 -// CHECK5-NEXT: br label [[FOR_COND112]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK5: for.end117: -// CHECK5-NEXT: [[CALL118:%.*]] = call i32 @_Z5tmainIiLi42EET_v() -// CHECK5-NEXT: store i32 [[CALL118]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP56:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP56]]) -// CHECK5-NEXT: [[ARRAY_BEGIN119:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[VVAR2]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN119]], i64 5 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP57]], [[FOR_END117]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6:[0-9]+]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN119]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE120:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done120: -// CHECK5-NEXT: [[ARRAY_BEGIN121:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], [10 x [4 x %struct.S]]* [[ARRS]], i32 0, i32 0, i32 0 -// CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN121]], i64 40 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY122:%.*]] -// CHECK5: arraydestroy.body122: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST123:%.*]] = phi %struct.S* [ [[TMP58]], [[ARRAYDESTROY_DONE120]] ], [ [[ARRAYDESTROY_ELEMENT124:%.*]], [[ARRAYDESTROY_BODY122]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT124]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST123]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT124]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE125:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT124]], [[ARRAY_BEGIN121]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE125]], label [[ARRAYDESTROY_DONE126:%.*]], label [[ARRAYDESTROY_BODY122]] -// CHECK5: arraydestroy.done126: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAY_BEGIN127:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN127]], i64 4 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY128:%.*]] -// CHECK5: arraydestroy.body128: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST129:%.*]] = phi %struct.S* [ [[TMP59]], [[ARRAYDESTROY_DONE126]] ], [ [[ARRAYDESTROY_ELEMENT130:%.*]], [[ARRAYDESTROY_BODY128]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT130]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST129]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT130]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE131:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT130]], [[ARRAY_BEGIN127]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE131]], label [[ARRAYDESTROY_DONE132:%.*]], label [[ARRAYDESTROY_BODY128]] -// CHECK5: arraydestroy.done132: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR6]] -// CHECK5-NEXT: [[TMP60:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP60]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[ARR:%.*]] = alloca [42 x %struct.S.0], align 16 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP4:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP5:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP17:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP18:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiLi42EET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S.0], [42 x %struct.S.0]* [[ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 42 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP11]], %struct.S.0** [[_TMP4]], align 8 -// CHECK5-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP4]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP12]], %struct.S.0** [[_TMP5]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK5-NEXT: br label [[FOR_COND7:%.*]] -// CHECK5: for.cond7: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP13]], 2 -// CHECK5-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END16:%.*]] -// CHECK5: for.body9: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM10]] -// CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX11]], align 4 -// CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP5]], align 8 -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM12]] -// CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX13]] to i8* -// CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC14:%.*]] -// CHECK5: for.inc14: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK5-NEXT: store i32 [[INC15]], i32* [[I6]], align 4 -// CHECK5-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK5: for.end16: -// CHECK5-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP21]], %struct.S.0** [[_TMP17]], align 8 -// CHECK5-NEXT: [[TMP22:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP17]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP22]], %struct.S.0** [[_TMP18]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK5-NEXT: br label [[FOR_COND20:%.*]] -// CHECK5: for.cond20: -// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP23]], 2 -// CHECK5-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK5: for.body22: -// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK5-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM23]] -// CHECK5-NEXT: store i32 [[TMP24]], i32* [[ARRAYIDX24]], align 4 -// CHECK5-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP18]], align 8 -// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK5-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM25]] -// CHECK5-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[ARRAYIDX26]] to i8* -// CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[TMP26]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC27:%.*]] -// CHECK5: for.inc27: -// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK5-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK5-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP18:![0-9]+]] -// CHECK5: for.end29: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN30:%.*]] = getelementptr inbounds [42 x %struct.S.0], [42 x %struct.S.0]* [[ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN30]], i64 42 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[FOR_END29]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN30]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE31:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done31: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN32]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY33:%.*]] -// CHECK5: arraydestroy.body33: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST34:%.*]] = phi %struct.S.0* [ [[TMP32]], [[ARRAYDESTROY_DONE31]] ], [ [[ARRAYDESTROY_ELEMENT35:%.*]], [[ARRAYDESTROY_BODY33]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT35]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST34]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT35]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE36:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT35]], [[ARRAY_BEGIN32]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE36]], label [[ARRAYDESTROY_DONE37:%.*]], label [[ARRAYDESTROY_BODY33]] -// CHECK5: arraydestroy.done37: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR6]] -// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP33]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[CONV:%.*]] = fptrunc double [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK5-NEXT: [[CONV2:%.*]] = fptrunc double [[ADD]] to float -// CHECK5-NEXT: store float [[CONV2]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK5-NEXT: [[CONV2:%.*]] = fptosi double [[ADD]] to i32 -// CHECK5-NEXT: store i32 [[CONV2]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [4 x %struct.S], align 16 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[ARRS:%.*]] = alloca [10 x [4 x %struct.S]], align 16 -// CHECK6-NEXT: [[VAR2:%.*]] = alloca %struct.S**, align 8 -// CHECK6-NEXT: [[VVAR2:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK6-NEXT: [[VAR3:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[_TMP10:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I54:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I68:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I75:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP82:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[_TMP83:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[I84:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP91:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[_TMP92:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[I93:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP100:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[_TMP101:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[I102:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP109:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[_TMP110:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[I111:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT1]], float 3.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT1]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT2]], float 4.000000e+00) -// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], [10 x [4 x %struct.S]]* [[ARRS]], i32 0, i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 40 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: [[CALL:%.*]] = call %struct.S** @_Z3foov() -// CHECK6-NEXT: store %struct.S** [[CALL]], %struct.S*** [[VAR2]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[VVAR2]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 5 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] -// CHECK6: arrayctor.loop5: -// CHECK6-NEXT: [[ARRAYCTOR_CUR6:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYCTOR_NEXT7:%.*]], [[ARRAYCTOR_LOOP5]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR6]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT7]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR6]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE8:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT7]], [[ARRAYCTOR_END4]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] -// CHECK6: arrayctor.cont9: -// CHECK6-NEXT: store [4 x %struct.S]* [[S_ARR]], [4 x %struct.S]** [[VAR3]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[_TMP10]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP10]], align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM11]] -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 1 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX13]], align 4 -// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK6-NEXT: [[TMP13:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP13]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP14:%.*]] = mul nuw i64 10, [[TMP12]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP14]], align 16 -// CHECK6-NEXT: store i64 [[TMP12]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK6-NEXT: br label [[FOR_COND15:%.*]] -// CHECK6: for.cond15: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK6-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP15]], 10 -// CHECK6-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK6: for.body17: -// CHECK6-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP16]] -// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK6-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK6-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX18]], i64 [[IDXPROM19]] -// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX20]], align 4 -// CHECK6-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK6-NEXT: store i32 [[INC21]], i32* [[ARRAYIDX20]], align 4 -// CHECK6-NEXT: br label [[FOR_INC22:%.*]] -// CHECK6: for.inc22: -// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK6-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK6-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK6-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end24: -// CHECK6-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK6-NEXT: br label [[FOR_COND26:%.*]] -// CHECK6: for.cond26: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK6-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP20]], 10 -// CHECK6-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK6: for.body28: -// CHECK6-NEXT: [[TMP21:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK6-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP21]] -// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK6-NEXT: [[IDXPROM30:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK6-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX29]], i64 [[IDXPROM30]] -// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX31]], align 4 -// CHECK6-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK6-NEXT: store i32 [[INC32]], i32* [[ARRAYIDX31]], align 4 -// CHECK6-NEXT: br label [[FOR_INC33:%.*]] -// CHECK6: for.inc33: -// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK6-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK6-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK6-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end35: -// CHECK6-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK6-NEXT: br label [[FOR_COND37:%.*]] -// CHECK6: for.cond37: -// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK6-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP25]], 10 -// CHECK6-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK6: for.body39: -// CHECK6-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK6-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP26]] -// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK6-NEXT: [[IDXPROM41:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK6-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX40]], i64 [[IDXPROM41]] -// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX42]], align 4 -// CHECK6-NEXT: [[INC43:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK6-NEXT: store i32 [[INC43]], i32* [[ARRAYIDX42]], align 4 -// CHECK6-NEXT: br label [[FOR_INC44:%.*]] -// CHECK6: for.inc44: -// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK6-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK6-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK6-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK6: for.end46: -// CHECK6-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK6-NEXT: br label [[FOR_COND48:%.*]] -// CHECK6: for.cond48: -// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK6-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP30]], 10 -// CHECK6-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END53:%.*]] -// CHECK6: for.body50: -// CHECK6-NEXT: br label [[FOR_INC51:%.*]] -// CHECK6: for.inc51: -// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK6-NEXT: [[INC52:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK6-NEXT: store i32 [[INC52]], i32* [[I47]], align 4 -// CHECK6-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK6: for.end53: -// CHECK6-NEXT: store i32 0, i32* [[I54]], align 4 -// CHECK6-NEXT: br label [[FOR_COND55:%.*]] -// CHECK6: for.cond55: -// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[I54]], align 4 -// CHECK6-NEXT: [[CMP56:%.*]] = icmp slt i32 [[TMP32]], 10 -// CHECK6-NEXT: br i1 [[CMP56]], label [[FOR_BODY57:%.*]], label [[FOR_END60:%.*]] -// CHECK6: for.body57: -// CHECK6-NEXT: br label [[FOR_INC58:%.*]] -// CHECK6: for.inc58: -// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[I54]], align 4 -// CHECK6-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP33]], 1 -// CHECK6-NEXT: store i32 [[INC59]], i32* [[I54]], align 4 -// CHECK6-NEXT: br label [[FOR_COND55]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK6: for.end60: -// CHECK6-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK6-NEXT: br label [[FOR_COND62:%.*]] -// CHECK6: for.cond62: -// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK6-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP34]], 10 -// CHECK6-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END67:%.*]] -// CHECK6: for.body64: -// CHECK6-NEXT: br label [[FOR_INC65:%.*]] -// CHECK6: for.inc65: -// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK6-NEXT: [[INC66:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK6-NEXT: store i32 [[INC66]], i32* [[I61]], align 4 -// CHECK6-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK6: for.end67: -// CHECK6-NEXT: store i32 0, i32* [[I68]], align 4 -// CHECK6-NEXT: br label [[FOR_COND69:%.*]] -// CHECK6: for.cond69: -// CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[I68]], align 4 -// CHECK6-NEXT: [[CMP70:%.*]] = icmp slt i32 [[TMP36]], 10 -// CHECK6-NEXT: br i1 [[CMP70]], label [[FOR_BODY71:%.*]], label [[FOR_END74:%.*]] -// CHECK6: for.body71: -// CHECK6-NEXT: br label [[FOR_INC72:%.*]] -// CHECK6: for.inc72: -// CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[I68]], align 4 -// CHECK6-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP37]], 1 -// CHECK6-NEXT: store i32 [[INC73]], i32* [[I68]], align 4 -// CHECK6-NEXT: br label [[FOR_COND69]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK6: for.end74: -// CHECK6-NEXT: store i32 0, i32* [[I75]], align 4 -// CHECK6-NEXT: br label [[FOR_COND76:%.*]] -// CHECK6: for.cond76: -// CHECK6-NEXT: [[TMP38:%.*]] = load i32, i32* [[I75]], align 4 -// CHECK6-NEXT: [[CMP77:%.*]] = icmp slt i32 [[TMP38]], 10 -// CHECK6-NEXT: br i1 [[CMP77]], label [[FOR_BODY78:%.*]], label [[FOR_END81:%.*]] -// CHECK6: for.body78: -// CHECK6-NEXT: br label [[FOR_INC79:%.*]] -// CHECK6: for.inc79: -// CHECK6-NEXT: [[TMP39:%.*]] = load i32, i32* [[I75]], align 4 -// CHECK6-NEXT: [[INC80:%.*]] = add nsw i32 [[TMP39]], 1 -// CHECK6-NEXT: store i32 [[INC80]], i32* [[I75]], align 4 -// CHECK6-NEXT: br label [[FOR_COND76]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK6: for.end81: -// CHECK6-NEXT: [[TMP40:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP40]], [4 x %struct.S]** [[_TMP82]], align 8 -// CHECK6-NEXT: [[TMP41:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP82]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP41]], [4 x %struct.S]** [[_TMP83]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I84]], align 4 -// CHECK6-NEXT: br label [[FOR_COND85:%.*]] -// CHECK6: for.cond85: -// CHECK6-NEXT: [[TMP42:%.*]] = load i32, i32* [[I84]], align 4 -// CHECK6-NEXT: [[CMP86:%.*]] = icmp slt i32 [[TMP42]], 10 -// CHECK6-NEXT: br i1 [[CMP86]], label [[FOR_BODY87:%.*]], label [[FOR_END90:%.*]] -// CHECK6: for.body87: -// CHECK6-NEXT: br label [[FOR_INC88:%.*]] -// CHECK6: for.inc88: -// CHECK6-NEXT: [[TMP43:%.*]] = load i32, i32* [[I84]], align 4 -// CHECK6-NEXT: [[INC89:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK6-NEXT: store i32 [[INC89]], i32* [[I84]], align 4 -// CHECK6-NEXT: br label [[FOR_COND85]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK6: for.end90: -// CHECK6-NEXT: [[TMP44:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP44]], [4 x %struct.S]** [[_TMP91]], align 8 -// CHECK6-NEXT: [[TMP45:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP91]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP45]], [4 x %struct.S]** [[_TMP92]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I93]], align 4 -// CHECK6-NEXT: br label [[FOR_COND94:%.*]] -// CHECK6: for.cond94: -// CHECK6-NEXT: [[TMP46:%.*]] = load i32, i32* [[I93]], align 4 -// CHECK6-NEXT: [[CMP95:%.*]] = icmp slt i32 [[TMP46]], 10 -// CHECK6-NEXT: br i1 [[CMP95]], label [[FOR_BODY96:%.*]], label [[FOR_END99:%.*]] -// CHECK6: for.body96: -// CHECK6-NEXT: br label [[FOR_INC97:%.*]] -// CHECK6: for.inc97: -// CHECK6-NEXT: [[TMP47:%.*]] = load i32, i32* [[I93]], align 4 -// CHECK6-NEXT: [[INC98:%.*]] = add nsw i32 [[TMP47]], 1 -// CHECK6-NEXT: store i32 [[INC98]], i32* [[I93]], align 4 -// CHECK6-NEXT: br label [[FOR_COND94]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK6: for.end99: -// CHECK6-NEXT: [[TMP48:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP48]], [4 x %struct.S]** [[_TMP100]], align 8 -// CHECK6-NEXT: [[TMP49:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP100]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP49]], [4 x %struct.S]** [[_TMP101]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I102]], align 4 -// CHECK6-NEXT: br label [[FOR_COND103:%.*]] -// CHECK6: for.cond103: -// CHECK6-NEXT: [[TMP50:%.*]] = load i32, i32* [[I102]], align 4 -// CHECK6-NEXT: [[CMP104:%.*]] = icmp slt i32 [[TMP50]], 10 -// CHECK6-NEXT: br i1 [[CMP104]], label [[FOR_BODY105:%.*]], label [[FOR_END108:%.*]] -// CHECK6: for.body105: -// CHECK6-NEXT: br label [[FOR_INC106:%.*]] -// CHECK6: for.inc106: -// CHECK6-NEXT: [[TMP51:%.*]] = load i32, i32* [[I102]], align 4 -// CHECK6-NEXT: [[INC107:%.*]] = add nsw i32 [[TMP51]], 1 -// CHECK6-NEXT: store i32 [[INC107]], i32* [[I102]], align 4 -// CHECK6-NEXT: br label [[FOR_COND103]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK6: for.end108: -// CHECK6-NEXT: [[TMP52:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP52]], [4 x %struct.S]** [[_TMP109]], align 8 -// CHECK6-NEXT: [[TMP53:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP109]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP53]], [4 x %struct.S]** [[_TMP110]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I111]], align 4 -// CHECK6-NEXT: br label [[FOR_COND112:%.*]] -// CHECK6: for.cond112: -// CHECK6-NEXT: [[TMP54:%.*]] = load i32, i32* [[I111]], align 4 -// CHECK6-NEXT: [[CMP113:%.*]] = icmp slt i32 [[TMP54]], 10 -// CHECK6-NEXT: br i1 [[CMP113]], label [[FOR_BODY114:%.*]], label [[FOR_END117:%.*]] -// CHECK6: for.body114: -// CHECK6-NEXT: br label [[FOR_INC115:%.*]] -// CHECK6: for.inc115: -// CHECK6-NEXT: [[TMP55:%.*]] = load i32, i32* [[I111]], align 4 -// CHECK6-NEXT: [[INC116:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK6-NEXT: store i32 [[INC116]], i32* [[I111]], align 4 -// CHECK6-NEXT: br label [[FOR_COND112]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK6: for.end117: -// CHECK6-NEXT: [[CALL118:%.*]] = call i32 @_Z5tmainIiLi42EET_v() -// CHECK6-NEXT: store i32 [[CALL118]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[TMP56:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP56]]) -// CHECK6-NEXT: [[ARRAY_BEGIN119:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[VVAR2]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN119]], i64 5 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP57]], [[FOR_END117]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6:[0-9]+]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN119]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE120:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done120: -// CHECK6-NEXT: [[ARRAY_BEGIN121:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], [10 x [4 x %struct.S]]* [[ARRS]], i32 0, i32 0, i32 0 -// CHECK6-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN121]], i64 40 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY122:%.*]] -// CHECK6: arraydestroy.body122: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST123:%.*]] = phi %struct.S* [ [[TMP58]], [[ARRAYDESTROY_DONE120]] ], [ [[ARRAYDESTROY_ELEMENT124:%.*]], [[ARRAYDESTROY_BODY122]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT124]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST123]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT124]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE125:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT124]], [[ARRAY_BEGIN121]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE125]], label [[ARRAYDESTROY_DONE126:%.*]], label [[ARRAYDESTROY_BODY122]] -// CHECK6: arraydestroy.done126: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAY_BEGIN127:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN127]], i64 4 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY128:%.*]] -// CHECK6: arraydestroy.body128: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST129:%.*]] = phi %struct.S* [ [[TMP59]], [[ARRAYDESTROY_DONE126]] ], [ [[ARRAYDESTROY_ELEMENT130:%.*]], [[ARRAYDESTROY_BODY128]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT130]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST129]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT130]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE131:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT130]], [[ARRAY_BEGIN127]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE131]], label [[ARRAYDESTROY_DONE132:%.*]], label [[ARRAYDESTROY_BODY128]] -// CHECK6: arraydestroy.done132: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR6]] -// CHECK6-NEXT: [[TMP60:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP60]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[ARR:%.*]] = alloca [42 x %struct.S.0], align 16 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP4:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP5:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP17:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP18:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiLi42EET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S.0], [42 x %struct.S.0]* [[ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 42 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP11]], %struct.S.0** [[_TMP4]], align 8 -// CHECK6-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP4]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP12]], %struct.S.0** [[_TMP5]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK6-NEXT: br label [[FOR_COND7:%.*]] -// CHECK6: for.cond7: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP13]], 2 -// CHECK6-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END16:%.*]] -// CHECK6: for.body9: -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM10]] -// CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX11]], align 4 -// CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP5]], align 8 -// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM12]] -// CHECK6-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX13]] to i8* -// CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC14:%.*]] -// CHECK6: for.inc14: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK6-NEXT: store i32 [[INC15]], i32* [[I6]], align 4 -// CHECK6-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK6: for.end16: -// CHECK6-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP21]], %struct.S.0** [[_TMP17]], align 8 -// CHECK6-NEXT: [[TMP22:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP17]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP22]], %struct.S.0** [[_TMP18]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK6-NEXT: br label [[FOR_COND20:%.*]] -// CHECK6: for.cond20: -// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP23]], 2 -// CHECK6-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK6: for.body22: -// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK6-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM23]] -// CHECK6-NEXT: store i32 [[TMP24]], i32* [[ARRAYIDX24]], align 4 -// CHECK6-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP18]], align 8 -// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK6-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM25]] -// CHECK6-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[ARRAYIDX26]] to i8* -// CHECK6-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[TMP26]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC27:%.*]] -// CHECK6: for.inc27: -// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK6-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK6-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP18:![0-9]+]] -// CHECK6: for.end29: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN30:%.*]] = getelementptr inbounds [42 x %struct.S.0], [42 x %struct.S.0]* [[ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN30]], i64 42 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[FOR_END29]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN30]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE31:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done31: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN32]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY33:%.*]] -// CHECK6: arraydestroy.body33: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST34:%.*]] = phi %struct.S.0* [ [[TMP32]], [[ARRAYDESTROY_DONE31]] ], [ [[ARRAYDESTROY_ELEMENT35:%.*]], [[ARRAYDESTROY_BODY33]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT35]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST34]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT35]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE36:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT35]], [[ARRAY_BEGIN32]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE36]], label [[ARRAYDESTROY_DONE37:%.*]], label [[ARRAYDESTROY_BODY33]] -// CHECK6: arraydestroy.done37: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR6]] -// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP33]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[CONV:%.*]] = fptrunc double [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK6-NEXT: [[CONV2:%.*]] = fptrunc double [[ADD]] to float -// CHECK6-NEXT: store float [[CONV2]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i32 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK6-NEXT: [[CONV2:%.*]] = fptosi double [[ADD]] to i32 -// CHECK6-NEXT: store i32 [[CONV2]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load double*, double** @g1, align 8 -// CHECK8-NEXT: store double* [[TMP0]], double** [[TMP]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store double 1.000000e+00, double* @g, align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store volatile double 1.000000e+00, double* [[TMP2]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP3:%.*]] = load volatile double, double* @g, align 8 -// CHECK8-NEXT: store volatile double [[TMP3]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP4:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store double* [[TMP4]], double** [[BLOCK_CAPTURED2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP5]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP8:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP8]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP9]](i8* [[TMP7]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load double*, double** [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: store double 2.000000e+00, double* [[TMP0]], align 8 -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/for_reduction_task_codegen.cpp b/clang/test/OpenMP/for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1091,62 +1091,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG23:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG23]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG24:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG25:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG27:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG29:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG31:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG31]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG31]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG32:![0-9]+]], !llvm.loop [[LOOP33:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG36]] -// diff --git a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp --- a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1393,227 +1393,3 @@ // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK3-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK3: arrayctor.loop: -// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK3: arrayctor.cont: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK3-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 5 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CONV]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK3: arraydestroy.done3: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP10]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK4-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK4: arrayctor.loop: -// CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK4: arrayctor.cont: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 5 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CONV]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK4: arraydestroy.body: -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK4: arraydestroy.done3: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP10]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: ret void -// diff --git a/clang/test/OpenMP/openmp_win_codegen.cpp b/clang/test/OpenMP/openmp_win_codegen.cpp --- a/clang/test/OpenMP/openmp_win_codegen.cpp +++ b/clang/test/OpenMP/openmp_win_codegen.cpp @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-pc-windows-msvc18.0.0 -std=c++11 -fms-compatibility-version=18 -fms-extensions -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-pc-windows-msvc18.0.0 -std=c++11 -fms-compatibility-version=18 -fms-extensions -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-pc-windows-msvc18.0.0 -std=c++11 -fms-compatibility-version=18 -fms-extensions -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics @@ -155,32 +155,3 @@ // CHECK1-NEXT: store i32 [[TMP12]], i32* [[TMP8]], align 4 // CHECK1-NEXT: ret void // -// -// CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @"?main@Test@@SAXXZ"() -// CHECK2-NEXT: invoke void @"?foo@@YAXXZ"() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[CATCH_DISPATCH:%.*]] -// CHECK2: catch.dispatch: -// CHECK2-NEXT: [[TMP0:%.*]] = catchswitch within none [label %catch] unwind label [[TERMINATE:%.*]] -// CHECK2: catch: -// CHECK2-NEXT: [[TMP1:%.*]] = catchpad within [[TMP0]] [%rtti.TypeDescriptor2* @"??_R0H@8", i32 0, i32* %t] -// CHECK2-NEXT: invoke void @"?bar@@YAXXZ"() [ "funclet"(token [[TMP1]]) ] -// CHECK2-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE]] -// CHECK2: invoke.cont1: -// CHECK2-NEXT: catchret from [[TMP1]] to label [[CATCHRET_DEST:%.*]] -// CHECK2: catchret.dest: -// CHECK2-NEXT: br label [[TRY_CONT:%.*]] -// CHECK2: try.cont: -// CHECK2-NEXT: ret i32 0 -// CHECK2: invoke.cont: -// CHECK2-NEXT: br label [[TRY_CONT]] -// CHECK2: terminate: -// CHECK2-NEXT: [[TMP2:%.*]] = cleanuppad within none [] -// CHECK2-NEXT: call void @"?terminate@@YAXXZ"() #[[ATTR3:[0-9]+]] [ "funclet"(token [[TMP2]]) ] -// CHECK2-NEXT: unreachable -// diff --git a/clang/test/OpenMP/parallel_codegen.cpp b/clang/test/OpenMP/parallel_codegen.cpp --- a/clang/test/OpenMP/parallel_codegen.cpp +++ b/clang/test/OpenMP/parallel_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -gno-column-info -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -958,493 +958,3 @@ // CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG71:![0-9]+]] // CHECK4-NEXT: ret void, !dbg [[DBG71]] // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK2:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]]) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX1]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK2]], align 8 -// CHECK5-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP1]], align 16 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 -// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 -// CHECK5-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP6]]) -// CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK5: invoke.cont5: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[GLOBAL]], align 4 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1 -// CHECK5-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK2]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4 -// CHECK5-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP9]]) -// CHECK5-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK5: invoke.cont8: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* @global, align 4 -// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK5-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX9]], align 4 -// CHECK5-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP11]]) -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP13]] -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK5-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK5-SAME: (i8** [[ARGC:%.*]]) #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK5-NEXT: [[VAR:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP0]], i64 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[ARRAYIDX1]], align 1 -// CHECK5-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 -// CHECK5-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8 -// CHECK5-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP4]]) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: [[TMP5:%.*]] = load double*, double** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = mul nsw i64 0, [[TMP3]] -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[TMP6]] -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX2]], i64 0 -// CHECK5-NEXT: ret i32 0 -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP7:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP8:%.*]] = extractvalue { i8*, i32 } [[TMP7]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP8]]) #[[ATTR4]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK5-SAME: (i8** [[ARGC:%.*]]) #[[ATTR2]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK5-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG11:![0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK2:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META17:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18:![0-9]+]] -// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META19:![0-9]+]], metadata !DIExpression()), !dbg [[DBG20:![0-9]+]] -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4, !dbg [[DBG21:![0-9]+]] -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG22:![0-9]+]] -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG22]] -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG22]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG22]] -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG22]] -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25:![0-9]+]] -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG30:![0-9]+]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG31:![0-9]+]] -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !dbg [[DBG31]] -// CHECK6-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]]) -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG33:![0-9]+]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG34:![0-9]+]] -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG35:![0-9]+]] -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i32* [[GLOBAL]], metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39:![0-9]+]] -// CHECK6-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG40:![0-9]+]] -// CHECK6-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK2]], align 8, !dbg [[DBG40]] -// CHECK6-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG40]] -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8, !dbg [[DBG40]] -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR1]], metadata [[META41:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39]] -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA3]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39]] -// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1, !dbg [[DBG43:![0-9]+]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4, !dbg [[DBG43]] -// CHECK6-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP6]]) -// CHECK6-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG45:![0-9]+]] -// CHECK6: invoke.cont5: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[GLOBAL]], align 4, !dbg [[DBG46:![0-9]+]] -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1, !dbg [[DBG47:![0-9]+]] -// CHECK6-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX6]], align 4, !dbg [[DBG48:![0-9]+]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK2]], align 8, !dbg [[DBG49:![0-9]+]] -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]), !dbg [[DBG49]] -// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG50:![0-9]+]] -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4, !dbg [[DBG50]] -// CHECK6-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP9]]) -// CHECK6-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG53:![0-9]+]] -// CHECK6: invoke.cont8: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG54:![0-9]+]] -// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG55:![0-9]+]] -// CHECK6-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX9]], align 4, !dbg [[DBG56:![0-9]+]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8, !dbg [[DBG57:![0-9]+]] -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP11]]), !dbg [[DBG58:![0-9]+]] -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4, !dbg [[DBG59:![0-9]+]] -// CHECK6-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG60:![0-9]+]] -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]), !dbg [[DBG60]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG60]] -// CHECK6-NEXT: ret i32 [[TMP13]], !dbg [[DBG60]] -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null, !dbg [[DBG33]] -// CHECK6-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0, !dbg [[DBG33]] -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]], !dbg [[DBG33]] -// CHECK6-NEXT: unreachable, !dbg [[DBG33]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK6-SAME: (i32 [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat !dbg [[DBG61:![0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]] -// CHECK6-NEXT: ret void, !dbg [[DBG68:![0-9]+]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK6-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK6-SAME: (i8** [[ARGC:%.*]]) #[[ATTR3]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG69:![0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK6-NEXT: [[VAR:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META74:![0-9]+]], metadata !DIExpression()), !dbg [[DBG75:![0-9]+]] -// CHECK6-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8, !dbg [[DBG76:![0-9]+]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP0]], i64 0, !dbg [[DBG76]] -// CHECK6-NEXT: [[TMP1:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8, !dbg [[DBG76]] -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i64 0, !dbg [[DBG76]] -// CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[ARRAYIDX1]], align 1, !dbg [[DBG76]] -// CHECK6-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64, !dbg [[DBG77:![0-9]+]] -// CHECK6-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8, !dbg [[DBG78:![0-9]+]] -// CHECK6-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP4]]) -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG81:![0-9]+]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata double** [[VAR]], metadata [[META82:![0-9]+]], metadata !DIExpression()), !dbg [[DBG89:![0-9]+]] -// CHECK6-NEXT: [[TMP5:%.*]] = load double*, double** [[VAR]], align 8, !dbg [[DBG90:![0-9]+]] -// CHECK6-NEXT: [[TMP6:%.*]] = mul nsw i64 0, [[TMP3]], !dbg [[DBG90]] -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[TMP6]], !dbg [[DBG90]] -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX2]], i64 0, !dbg [[DBG90]] -// CHECK6-NEXT: ret i32 0, !dbg [[DBG91:![0-9]+]] -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP7:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null, !dbg [[DBG81]] -// CHECK6-NEXT: [[TMP8:%.*]] = extractvalue { i8*, i32 } [[TMP7]], 0, !dbg [[DBG81]] -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP8]]) #[[ATTR5]], !dbg [[DBG81]] -// CHECK6-NEXT: unreachable, !dbg [[DBG81]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK6-SAME: (i8** [[ARGC:%.*]]) #[[ATTR3]] comdat !dbg [[DBG92:![0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK6-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META95:![0-9]+]], metadata !DIExpression()), !dbg [[DBG96:![0-9]+]] -// CHECK6-NEXT: ret void, !dbg [[DBG97:![0-9]+]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK2:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 -// CHECK7-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX1]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK2]], align 8 -// CHECK7-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP1]], align 16 -// CHECK7-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP6]]) -// CHECK7-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont5: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[GLOBAL]], align 4 -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1 -// CHECK7-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK2]], align 8 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP9]]) -// CHECK7-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont8: -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* @global, align 4 -// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK7-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX9]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP11]]) -// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP13]] -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR4:[0-9]+]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK7-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK7-SAME: (i8** [[ARGC:%.*]]) #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK7-NEXT: [[VAR:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP0]], i64 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i64 0 -// CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[ARRAYIDX1]], align 1 -// CHECK7-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 -// CHECK7-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8 -// CHECK7-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP4]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: [[TMP5:%.*]] = load double*, double** [[VAR]], align 8 -// CHECK7-NEXT: [[TMP6:%.*]] = mul nsw i64 0, [[TMP3]] -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[TMP6]] -// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX2]], i64 0 -// CHECK7-NEXT: ret i32 0 -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP7:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP8:%.*]] = extractvalue { i8*, i32 } [[TMP7]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP8]]) #[[ATTR4]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK7-SAME: (i8** [[ARGC:%.*]]) #[[ATTR2]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK7-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG11:![0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK2:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META17:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18:![0-9]+]] -// CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META19:![0-9]+]], metadata !DIExpression()), !dbg [[DBG20:![0-9]+]] -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4, !dbg [[DBG21:![0-9]+]] -// CHECK8-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG22:![0-9]+]] -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG22]] -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG22]] -// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG22]] -// CHECK8-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG22]] -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25:![0-9]+]] -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG30:![0-9]+]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG31:![0-9]+]] -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !dbg [[DBG31]] -// CHECK8-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG33:![0-9]+]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG34:![0-9]+]] -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG35:![0-9]+]] -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i32* [[GLOBAL]], metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39:![0-9]+]] -// CHECK8-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG40:![0-9]+]] -// CHECK8-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK2]], align 8, !dbg [[DBG40]] -// CHECK8-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG40]] -// CHECK8-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8, !dbg [[DBG40]] -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR1]], metadata [[META41:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39]] -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA3]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39]] -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1, !dbg [[DBG43:![0-9]+]] -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4, !dbg [[DBG43]] -// CHECK8-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP6]]) -// CHECK8-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG45:![0-9]+]] -// CHECK8: invoke.cont5: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[GLOBAL]], align 4, !dbg [[DBG46:![0-9]+]] -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1, !dbg [[DBG47:![0-9]+]] -// CHECK8-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX6]], align 4, !dbg [[DBG48:![0-9]+]] -// CHECK8-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK2]], align 8, !dbg [[DBG49:![0-9]+]] -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]), !dbg [[DBG49]] -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG50:![0-9]+]] -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4, !dbg [[DBG50]] -// CHECK8-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP9]]) -// CHECK8-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG53:![0-9]+]] -// CHECK8: invoke.cont8: -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG54:![0-9]+]] -// CHECK8-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG55:![0-9]+]] -// CHECK8-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX9]], align 4, !dbg [[DBG56:![0-9]+]] -// CHECK8-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8, !dbg [[DBG57:![0-9]+]] -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP11]]), !dbg [[DBG58:![0-9]+]] -// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4, !dbg [[DBG59:![0-9]+]] -// CHECK8-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG60:![0-9]+]] -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]), !dbg [[DBG60]] -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG60]] -// CHECK8-NEXT: ret i32 [[TMP13]], !dbg [[DBG60]] -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null, !dbg [[DBG33]] -// CHECK8-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0, !dbg [[DBG33]] -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]], !dbg [[DBG33]] -// CHECK8-NEXT: unreachable, !dbg [[DBG33]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK8-SAME: (i32 [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat !dbg [[DBG61:![0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]] -// CHECK8-NEXT: ret void, !dbg [[DBG68:![0-9]+]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK8-SAME: (i8** [[ARGC:%.*]]) #[[ATTR3]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG69:![0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK8-NEXT: [[VAR:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META74:![0-9]+]], metadata !DIExpression()), !dbg [[DBG75:![0-9]+]] -// CHECK8-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8, !dbg [[DBG76:![0-9]+]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP0]], i64 0, !dbg [[DBG76]] -// CHECK8-NEXT: [[TMP1:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8, !dbg [[DBG76]] -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i64 0, !dbg [[DBG76]] -// CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[ARRAYIDX1]], align 1, !dbg [[DBG76]] -// CHECK8-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64, !dbg [[DBG77:![0-9]+]] -// CHECK8-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8, !dbg [[DBG78:![0-9]+]] -// CHECK8-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP4]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG81:![0-9]+]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata double** [[VAR]], metadata [[META82:![0-9]+]], metadata !DIExpression()), !dbg [[DBG89:![0-9]+]] -// CHECK8-NEXT: [[TMP5:%.*]] = load double*, double** [[VAR]], align 8, !dbg [[DBG90:![0-9]+]] -// CHECK8-NEXT: [[TMP6:%.*]] = mul nsw i64 0, [[TMP3]], !dbg [[DBG90]] -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[TMP6]], !dbg [[DBG90]] -// CHECK8-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX2]], i64 0, !dbg [[DBG90]] -// CHECK8-NEXT: ret i32 0, !dbg [[DBG91:![0-9]+]] -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP7:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null, !dbg [[DBG81]] -// CHECK8-NEXT: [[TMP8:%.*]] = extractvalue { i8*, i32 } [[TMP7]], 0, !dbg [[DBG81]] -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP8]]) #[[ATTR5]], !dbg [[DBG81]] -// CHECK8-NEXT: unreachable, !dbg [[DBG81]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK8-SAME: (i8** [[ARGC:%.*]]) #[[ATTR3]] comdat !dbg [[DBG92:![0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK8-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META95:![0-9]+]], metadata !DIExpression()), !dbg [[DBG96:![0-9]+]] -// CHECK8-NEXT: ret void, !dbg [[DBG97:![0-9]+]] -// diff --git a/clang/test/OpenMP/parallel_copyin_codegen.cpp b/clang/test/OpenMP/parallel_copyin_codegen.cpp --- a/clang/test/OpenMP/parallel_copyin_codegen.cpp +++ b/clang/test/OpenMP/parallel_copyin_codegen.cpp @@ -6,27 +6,27 @@ // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -DNESTED -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -DNESTED -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #if !defined(ARRAY) && !defined(NESTED) #ifndef HEADER @@ -1672,45 +1672,33 @@ // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) // CHECK6-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] -// CHECK6-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE5s_arr, align 1 // CHECK6-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK6-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK6: init.check: -// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK6: init: // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK6-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]] +// CHECK6-NEXT: store i8 1, i8* @_ZGVZ4mainE5s_arr, align 1 // CHECK6-NEXT: br label [[INIT_END]] // CHECK6: init.end: -// CHECK6-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8 -// CHECK6-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK6-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] +// CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* @_ZGVZ4mainE3var, align 1 +// CHECK6-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 +// CHECK6-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] // CHECK6: init.check2: -// CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK6-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK6: init4: // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK6-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK6-NEXT: br label [[INIT_END5]] -// CHECK6: init.end5: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK6-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK6-NEXT: [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL7]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] +// CHECK6-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR4]] +// CHECK6-NEXT: store i8 1, i8* @_ZGVZ4mainE3var, align 1 +// CHECK6-NEXT: br label [[INIT_END3]] +// CHECK6: init.end3: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var, [2 x i32]* @_ZZ4mainE3vec, [2 x %struct.S]* @_ZZ4mainE5s_arr, %struct.S* @_ZZ4mainE3var) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var) +// CHECK6-NEXT: [[CALL4:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL4]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP4]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev @@ -1740,7 +1728,7 @@ // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK6-NEXT: ret void // // @@ -1758,7 +1746,7 @@ // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1766,13 +1754,90 @@ // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ4mainE5t_var to i64) +// CHECK6-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK6: copyin.not.master: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* @_ZZ4mainE5t_var, align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i8* align 4 [[TMP7]], i64 8, i1 false) +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* +// CHECK6-NEXT: br i1 icmp eq (%struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), %struct.S* getelementptr ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2) +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done1: +// CHECK6-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) @_ZZ4mainE3var, %struct.S* nonnull align 4 dereferenceable(4) [[TMP3]]) +// CHECK6-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK6: copyin.not.master.end: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK6-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP10]]) +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 +// CHECK6-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 +// CHECK6-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ4mainE5t_var to i64) +// CHECK6-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK6: copyin.not.master: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* @_ZZ4mainE5t_var, align 4 +// CHECK6-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK6: copyin.not.master.end: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK6-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 +// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK6-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v // CHECK6-SAME: () #[[ATTR2]] comdat { // CHECK6-NEXT: entry: @@ -1781,38 +1846,29 @@ // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) // CHECK6-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] -// CHECK6-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 // CHECK6-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK6-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] // CHECK6: init.check: -// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK6: init: // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) -// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK6-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor.2, i8* null, i8* @__dso_handle) #[[ATTR4]] +// CHECK6-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 // CHECK6-NEXT: br label [[INIT_END]] // CHECK6: init.end: -// CHECK6-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8 -// CHECK6-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK6-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] +// CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 +// CHECK6-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 +// CHECK6-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] // CHECK6: init.check2: -// CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK6-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK6: init4: // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) -// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK6-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK6-NEXT: br label [[INIT_END5]] -// CHECK6: init.end5: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK6-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK6-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK6-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR4]] +// CHECK6-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 +// CHECK6-NEXT: br label [[INIT_END3]] +// CHECK6: init.end3: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var, [2 x i32]* @_ZZ5tmainIiET_vE3vec, [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, %struct.S.0* @_ZZ5tmainIiET_vE3var) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var) +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK6-NEXT: ret i32 0 // // @@ -1882,7 +1938,7 @@ // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK6-NEXT: ret void // // @@ -1899,8 +1955,8 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1 -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.2 +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1908,13 +1964,87 @@ // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64) +// CHECK6-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK6: copyin.not.master: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK6-NEXT: store i32 [[TMP6]], i32* @_ZZ5tmainIiET_vE5t_var, align 128 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i8* align 128 [[TMP7]], i64 8, i1 false) +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK6-NEXT: br i1 icmp eq (%struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), %struct.S.0* getelementptr ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S_0]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2) +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done1: +// CHECK6-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) @_ZZ5tmainIiET_vE3var, %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]]) +// CHECK6-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK6: copyin.not.master.end: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK6-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 +// CHECK6-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 +// CHECK6-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64) +// CHECK6-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK6: copyin.not.master: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK6-NEXT: store i32 [[TMP3]], i32* @_ZZ5tmainIiET_vE5t_var, align 128 +// CHECK6-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK6: copyin.not.master.end: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK6-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: @@ -1952,6 +2082,11 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZTW1g +// CHECK6-SAME: () #[[ATTR8:[0-9]+]] comdat { +// CHECK6-NEXT: ret i32* @g +// +// // CHECK7-LABEL: define {{[^@]+}}@main // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: @@ -1962,45 +2097,33 @@ // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) // CHECK7-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] -// CHECK7-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE5s_arr, align 1 // CHECK7-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK7-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK7: init.check: -// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK7-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK7: init: // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK7-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] +// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]] +// CHECK7-NEXT: store i8 1, i8* @_ZGVZ4mainE5s_arr, align 1 // CHECK7-NEXT: br label [[INIT_END]] // CHECK7: init.end: -// CHECK7-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8 -// CHECK7-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK7-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] +// CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* @_ZGVZ4mainE3var, align 1 +// CHECK7-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] // CHECK7: init.check2: -// CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK7-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK7-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK7: init4: // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK7-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK7-NEXT: br label [[INIT_END5]] -// CHECK7: init.end5: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK7-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK7-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK7-NEXT: [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: store i32 [[CALL7]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] +// CHECK7-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR4]] +// CHECK7-NEXT: store i8 1, i8* @_ZGVZ4mainE3var, align 1 +// CHECK7-NEXT: br label [[INIT_END3]] +// CHECK7: init.end3: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var, [2 x i32]* @_ZZ4mainE3vec, [2 x %struct.S]* @_ZZ4mainE5s_arr, %struct.S* @_ZZ4mainE3var) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var) +// CHECK7-NEXT: [[CALL4:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL4]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP4]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev @@ -2030,7 +2153,7 @@ // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // @@ -2048,7 +2171,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2056,13 +2179,90 @@ // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: // CHECK7-NEXT: ret void // // +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK7-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ4mainE5t_var to i64) +// CHECK7-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK7: copyin.not.master: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* @_ZZ4mainE5t_var, align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i8* align 4 [[TMP7]], i64 8, i1 false) +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* +// CHECK7-NEXT: br i1 icmp eq (%struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), %struct.S* getelementptr ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2) +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done1: +// CHECK7-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) @_ZZ4mainE3var, %struct.S* nonnull align 4 dereferenceable(4) [[TMP3]]) +// CHECK7-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK7: copyin.not.master.end: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP10]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 +// CHECK7-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 +// CHECK7-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK7-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ4mainE5t_var to i64) +// CHECK7-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK7: copyin.not.master: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* @_ZZ4mainE5t_var, align 4 +// CHECK7-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK7: copyin.not.master.end: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 +// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK7-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 +// CHECK7-NEXT: ret void +// +// // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v // CHECK7-SAME: () #[[ATTR2]] comdat { // CHECK7-NEXT: entry: @@ -2071,38 +2271,29 @@ // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) // CHECK7-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] -// CHECK7-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 // CHECK7-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK7-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] // CHECK7: init.check: -// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK7-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK7: init: // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) -// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK7-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] +// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor.2, i8* null, i8* @__dso_handle) #[[ATTR4]] +// CHECK7-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 // CHECK7-NEXT: br label [[INIT_END]] // CHECK7: init.end: -// CHECK7-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8 -// CHECK7-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK7-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] +// CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 +// CHECK7-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] // CHECK7: init.check2: -// CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK7-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK7-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK7: init4: // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) -// CHECK7-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK7-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK7-NEXT: br label [[INIT_END5]] -// CHECK7: init.end5: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK7-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK7-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK7-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR4]] +// CHECK7-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 +// CHECK7-NEXT: br label [[INIT_END3]] +// CHECK7: init.end3: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var, [2 x i32]* @_ZZ5tmainIiET_vE3vec, [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, %struct.S.0* @_ZZ5tmainIiET_vE3var) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK7-NEXT: ret i32 0 // // @@ -2172,7 +2363,7 @@ // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // @@ -2189,8 +2380,8 @@ // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1 -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.2 +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2198,13 +2389,87 @@ // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: // CHECK7-NEXT: ret void // // +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK7-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64) +// CHECK7-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK7: copyin.not.master: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK7-NEXT: store i32 [[TMP6]], i32* @_ZZ5tmainIiET_vE5t_var, align 128 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i8* align 128 [[TMP7]], i64 8, i1 false) +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK7-NEXT: br i1 icmp eq (%struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), %struct.S.0* getelementptr ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S_0]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2) +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done1: +// CHECK7-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) @_ZZ5tmainIiET_vE3var, %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]]) +// CHECK7-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK7: copyin.not.master.end: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 +// CHECK7-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 +// CHECK7-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK7-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64) +// CHECK7-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK7: copyin.not.master: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK7-NEXT: store i32 [[TMP3]], i32* @_ZZ5tmainIiET_vE5t_var, align 128 +// CHECK7-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK7: copyin.not.master.end: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK7-NEXT: ret void +// +// // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: @@ -2242,6 +2507,11 @@ // CHECK7-NEXT: ret void // // +// CHECK7-LABEL: define {{[^@]+}}@_ZTW1g +// CHECK7-SAME: () #[[ATTR8:[0-9]+]] comdat { +// CHECK7-NEXT: ret i32* @g +// +// // CHECK8-LABEL: define {{[^@]+}}@main // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: @@ -2252,6 +2522,38 @@ // CHECK8-NEXT: ret i32 0 // // +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 1 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK8-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @g to i64) +// CHECK8-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK8: copyin.not.master: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK8-NEXT: store volatile i32 [[TMP3]], i32* @g, align 128 +// CHECK8-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK8: copyin.not.master.end: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) +// CHECK8-NEXT: store volatile i32 1, i32* @g, align 128 +// CHECK8-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZTW1g +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: ret i32* @g +// +// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: @@ -2271,14 +2573,39 @@ // CHECK9-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 // CHECK9-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* // CHECK9-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @g) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @g to i64) +// CHECK9-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK9: copyin.not.master: +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK9-NEXT: store volatile i32 [[TMP3]], i32* @g, align 128 +// CHECK9-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK9: copyin.not.master.end: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) // CHECK9-NEXT: store volatile i32 1, i32* @g, align 128 -// CHECK9-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK9-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*)) +// CHECK9-NEXT: [[TMP6:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to void (i8*)* +// CHECK9-NEXT: call void [[TMP7]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*)) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@__main_block_invoke_2 +// CHECK9-LABEL: define {{[^@]+}}@g_block_invoke // CHECK9-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 @@ -2290,34 +2617,36 @@ // CHECK9-NEXT: ret void // // +// CHECK9-LABEL: define {{[^@]+}}@_ZTW1g +// CHECK9-SAME: () #[[ATTR6:[0-9]+]] comdat { +// CHECK9-NEXT: ret i32* @g +// +// // CHECK10-LABEL: define {{[^@]+}}@_Z10array_funcv // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ10array_funcvE1s to i8*) acquire, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ10array_funcvE1s, align 1 // CHECK10-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK10-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK10: init.check: -// CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1:[0-9]+]] -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK10: init: // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT_CHECK]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2) // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR1]] -// CHECK10-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1]] +// CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3:[0-9]+]] +// CHECK10-NEXT: store i8 1, i8* @_ZGVZ10array_funcvE1s, align 1 // CHECK10-NEXT: br label [[INIT_END]] // CHECK10: init.end: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, [2 x %struct.St]*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* @_ZZ10array_funcvE1a, [2 x %struct.St]* @_ZZ10array_funcvE1s) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -2327,7 +2656,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section ".text.startup" { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2335,7 +2664,7 @@ // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] +// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -2343,17 +2672,66 @@ // // // CHECK10-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR1]] +// CHECK10-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK10-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], [2 x %struct.St]* nonnull align 4 dereferenceable(16) [[S:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca [2 x %struct.St]*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store [2 x %struct.St]* [[S]], [2 x %struct.St]** [[S_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.St]*, [2 x %struct.St]** [[S_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = ptrtoint [2 x i32]* [[TMP0]] to i64 +// CHECK10-NEXT: [[TMP3:%.*]] = icmp ne i64 [[TMP2]], ptrtoint ([2 x i32]* @_ZZ10array_funcvE1a to i64) +// CHECK10-NEXT: br i1 [[TMP3]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK10: copyin.not.master: +// CHECK10-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x i32]* @_ZZ10array_funcvE1a to i8*), i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.St]* [[TMP1]] to %struct.St* +// CHECK10-NEXT: br i1 icmp eq (%struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), %struct.St* getelementptr ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK10: omp.arraycpy.body: +// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.St* [ [[TMP5]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK10-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(8) %struct.St* @_ZN2StaSERKS_(%struct.St* nonnull dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.St* nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.St* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2) +// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] +// CHECK10: omp.arraycpy.done1: +// CHECK10-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK10: copyin.not.master.end: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2StaSERKS_ +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store %struct.St* [[TMP0]], %struct.St** [[DOTADDR]], align 8 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: ret %struct.St* [[THIS1]] +// +// // CHECK10-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -2366,7 +2744,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -2374,1881 +2752,79 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) -// CHECK11-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE5s_arr, align 1 -// CHECK11-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK11: init.check: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]] -// CHECK11-NEXT: store i8 1, i8* @_ZGVZ4mainE5s_arr, align 1 -// CHECK11-NEXT: br label [[INIT_END]] -// CHECK11: init.end: -// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* @_ZGVZ4mainE3var, align 1 -// CHECK11-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] -// CHECK11: init.check2: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR4]] -// CHECK11-NEXT: store i8 1, i8* @_ZGVZ4mainE3var, align 1 -// CHECK11-NEXT: br label [[INIT_END3]] -// CHECK11: init.end3: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var, [2 x i32]* @_ZZ4mainE3vec, [2 x %struct.S]* @_ZZ4mainE5s_arr, %struct.S* @_ZZ4mainE3var) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var) -// CHECK11-NEXT: [[CALL4:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL4]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP4]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret %struct.S* [[THIS1]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init +// CHECK11-SAME: () #[[ATTR0:[0-9]+]] section ".text.startup" { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z6t_initv() +// CHECK11-NEXT: store i32 [[CALL]], i32* @t, align 4 // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" { +// CHECK11-LABEL: define {{[^@]+}}@_Z3foov +// CHECK11-SAME: () #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK11-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ4mainE5t_var to i64) -// CHECK11-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK11: copyin.not.master: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i8* align 4 [[TMP7]], i64 8, i1 false) -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* -// CHECK11-NEXT: br i1 icmp eq (%struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), %struct.S* getelementptr ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2) -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done1: -// CHECK11-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) @_ZZ4mainE3var, %struct.S* nonnull align 4 dereferenceable(4) [[TMP3]]) -// CHECK11-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK11: copyin.not.master.end: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP10]]) -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK11-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK11-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) +// CHECK11-NEXT: [[TMP0:%.*]] = call i32* @_ZTW1t() +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ4mainE5t_var to i64) -// CHECK11-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK11: copyin.not.master: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK11-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK11: copyin.not.master.end: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR2]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) -// CHECK11-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 -// CHECK11-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] -// CHECK11: init.check: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) -// CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor.2, i8* null, i8* @__dso_handle) #[[ATTR4]] -// CHECK11-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 -// CHECK11-NEXT: br label [[INIT_END]] -// CHECK11: init.end: -// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 -// CHECK11-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] -// CHECK11: init.check2: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) -// CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR4]] -// CHECK11-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 -// CHECK11-NEXT: br label [[INIT_END3]] -// CHECK11: init.end3: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var, [2 x i32]* @_ZZ5tmainIiET_vE3vec, [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, %struct.S.0* @_ZZ5tmainIiET_vE3var) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret %struct.S.0* [[THIS1]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.2 -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK11-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64) -// CHECK11-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK11: copyin.not.master: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK11-NEXT: store i32 [[TMP6]], i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i8* align 128 [[TMP7]], i64 8, i1 false) -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK11-NEXT: br i1 icmp eq (%struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), %struct.S.0* getelementptr ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S_0]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2) -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done1: -// CHECK11-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) @_ZZ5tmainIiET_vE3var, %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]]) -// CHECK11-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK11: copyin.not.master.end: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK11-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK11-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[T_ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64) -// CHECK11-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK11-NEXT: store i32* [[T]], i32** [[T_ADDR]], align 8 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_ADDR]], align 8 +// CHECK11-NEXT: [[TMP1:%.*]] = call i32* @_ZTW1t() +// CHECK11-NEXT: [[TMP2:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK11-NEXT: [[TMP3:%.*]] = ptrtoint i32* [[TMP1]] to i64 +// CHECK11-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]] +// CHECK11-NEXT: br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] // CHECK11: copyin.not.master: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK11-NEXT: store i32 [[TMP3]], i32* @_ZZ5tmainIiET_vE5t_var, align 128 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP1]], align 4 // CHECK11-NEXT: br label [[COPYIN_NOT_MASTER_END]] // CHECK11: copyin.not.master.end: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]]) +// CHECK11-NEXT: [[TMP8:%.*]] = call i32* @_ZTW1t() +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP8]], align 4 // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void +// CHECK11-LABEL: define {{[^@]+}}@_ZTW1t +// CHECK11-SAME: () #[[ATTR4:[0-9]+]] comdat { +// CHECK11-NEXT: call void @_ZTH1t() +// CHECK11-NEXT: ret i32* @t // // -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-LABEL: define {{[^@]+}}@__tls_init +// CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* @__tls_guard, align 1 +// CHECK11-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 +// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF4:![0-9]+]] +// CHECK11: init: +// CHECK11-NEXT: store i8 1, i8* @__tls_guard, align 1 +// CHECK11-NEXT: call void @__cxx_global_var_init() +// CHECK11-NEXT: br label [[EXIT]] +// CHECK11: exit: // CHECK11-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@_ZTW1g -// CHECK11-SAME: () #[[ATTR8:[0-9]+]] comdat { -// CHECK11-NEXT: ret i32* @g -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) -// CHECK12-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE5s_arr, align 1 -// CHECK12-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK12: init.check: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]] -// CHECK12-NEXT: store i8 1, i8* @_ZGVZ4mainE5s_arr, align 1 -// CHECK12-NEXT: br label [[INIT_END]] -// CHECK12: init.end: -// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* @_ZGVZ4mainE3var, align 1 -// CHECK12-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] -// CHECK12: init.check2: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR4]] -// CHECK12-NEXT: store i8 1, i8* @_ZGVZ4mainE3var, align 1 -// CHECK12-NEXT: br label [[INIT_END3]] -// CHECK12: init.end3: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var, [2 x i32]* @_ZZ4mainE3vec, [2 x %struct.S]* @_ZZ4mainE5s_arr, %struct.S* @_ZZ4mainE3var) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var) -// CHECK12-NEXT: [[CALL4:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL4]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP4]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret %struct.S* [[THIS1]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK12-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ4mainE5t_var to i64) -// CHECK12-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK12: copyin.not.master: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i8* align 4 [[TMP7]], i64 8, i1 false) -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* -// CHECK12-NEXT: br i1 icmp eq (%struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), %struct.S* getelementptr ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2) -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done1: -// CHECK12-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) @_ZZ4mainE3var, %struct.S* nonnull align 4 dereferenceable(4) [[TMP3]]) -// CHECK12-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK12: copyin.not.master.end: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP10]]) -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK12-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK12-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ4mainE5t_var to i64) -// CHECK12-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK12: copyin.not.master: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK12-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK12: copyin.not.master.end: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR2]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) -// CHECK12-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 -// CHECK12-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] -// CHECK12: init.check: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) -// CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor.2, i8* null, i8* @__dso_handle) #[[ATTR4]] -// CHECK12-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 -// CHECK12-NEXT: br label [[INIT_END]] -// CHECK12: init.end: -// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 -// CHECK12-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] -// CHECK12: init.check2: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) -// CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR4]] -// CHECK12-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 -// CHECK12-NEXT: br label [[INIT_END3]] -// CHECK12: init.end3: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var, [2 x i32]* @_ZZ5tmainIiET_vE3vec, [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, %struct.S.0* @_ZZ5tmainIiET_vE3var) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret %struct.S.0* [[THIS1]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.2 -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK12-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64) -// CHECK12-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK12: copyin.not.master: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK12-NEXT: store i32 [[TMP6]], i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i8* align 128 [[TMP7]], i64 8, i1 false) -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK12-NEXT: br i1 icmp eq (%struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), %struct.S.0* getelementptr ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S_0]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2) -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done1: -// CHECK12-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) @_ZZ5tmainIiET_vE3var, %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]]) -// CHECK12-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK12: copyin.not.master.end: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK12-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK12-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64) -// CHECK12-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK12: copyin.not.master: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK12-NEXT: store i32 [[TMP3]], i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK12-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK12: copyin.not.master.end: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZTW1g -// CHECK12-SAME: () #[[ATTR8:[0-9]+]] comdat { -// CHECK12-NEXT: ret i32* @g -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 1 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @g to i64) -// CHECK13-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK13: copyin.not.master: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK13-NEXT: store volatile i32 [[TMP3]], i32* @g, align 128 -// CHECK13-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK13: copyin.not.master.end: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK13-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) -// CHECK13-NEXT: store volatile i32 1, i32* @g, align 128 -// CHECK13-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZTW1g -// CHECK13-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK13-NEXT: ret i32* @g -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK14-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK14-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK14-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK14-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK14-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @g) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @g to i64) -// CHECK14-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK14: copyin.not.master: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK14-NEXT: store volatile i32 [[TMP3]], i32* @g, align 128 -// CHECK14-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK14: copyin.not.master.end: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK14-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) -// CHECK14-NEXT: store volatile i32 1, i32* @g, align 128 -// CHECK14-NEXT: [[TMP6:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to void (i8*)* -// CHECK14-NEXT: call void [[TMP7]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@g_block_invoke -// CHECK14-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK14-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK14-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK14-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK14-NEXT: store volatile i32 2, i32* @g, align 128 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZTW1g -// CHECK14-SAME: () #[[ATTR6:[0-9]+]] comdat { -// CHECK14-NEXT: ret i32* @g -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z10array_funcv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ10array_funcvE1s, align 1 -// CHECK15-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK15-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK15: init.check: -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT_CHECK]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2) -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3:[0-9]+]] -// CHECK15-NEXT: store i8 1, i8* @_ZGVZ10array_funcvE1s, align 1 -// CHECK15-NEXT: br label [[INIT_END]] -// CHECK15: init.end: -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, [2 x %struct.St]*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* @_ZZ10array_funcvE1a, [2 x %struct.St]* @_ZZ10array_funcvE1s) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK15-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK15-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section ".text.startup" { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK15-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0) -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done1: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK15-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR3]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], [2 x %struct.St]* nonnull align 4 dereferenceable(16) [[S:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK15-NEXT: [[S_ADDR:%.*]] = alloca [2 x %struct.St]*, align 8 -// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK15-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 -// CHECK15-NEXT: store [2 x %struct.St]* [[S]], [2 x %struct.St]** [[S_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 -// CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.St]*, [2 x %struct.St]** [[S_ADDR]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = ptrtoint [2 x i32]* [[TMP0]] to i64 -// CHECK15-NEXT: [[TMP3:%.*]] = icmp ne i64 [[TMP2]], ptrtoint ([2 x i32]* @_ZZ10array_funcvE1a to i64) -// CHECK15-NEXT: br i1 [[TMP3]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK15: copyin.not.master: -// CHECK15-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x i32]* @_ZZ10array_funcvE1a to i8*), i8* align 4 [[TMP4]], i64 8, i1 false) -// CHECK15-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.St]* [[TMP1]] to %struct.St* -// CHECK15-NEXT: br i1 icmp eq (%struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), %struct.St* getelementptr ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK15: omp.arraycpy.body: -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.St* [ [[TMP5]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(8) %struct.St* @_ZN2StaSERKS_(%struct.St* nonnull dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.St* nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) -// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.St* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2) -// CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] -// CHECK15: omp.arraycpy.done1: -// CHECK15-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK15: copyin.not.master.end: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK15-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2StaSERKS_ -// CHECK15-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK15-NEXT: [[DOTADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store %struct.St* [[TMP0]], %struct.St** [[DOTADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: ret %struct.St* [[THIS1]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK15-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK15-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] section ".text.startup" { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z6t_initv() -// CHECK16-NEXT: store i32 [[CALL]], i32* @t, align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3foov -// CHECK16-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK16-NEXT: [[TMP0:%.*]] = call i32* @_ZTW1t() -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T:%.*]]) #[[ATTR3]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[T_ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK16-NEXT: store i32* [[T]], i32** [[T_ADDR]], align 8 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_ADDR]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = call i32* @_ZTW1t() -// CHECK16-NEXT: [[TMP2:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK16-NEXT: [[TMP3:%.*]] = ptrtoint i32* [[TMP1]] to i64 -// CHECK16-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK16: copyin.not.master: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[TMP1]], align 4 -// CHECK16-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK16: copyin.not.master.end: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK16-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]]) -// CHECK16-NEXT: [[TMP8:%.*]] = call i32* @_ZTW1t() -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP8]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZTW1t -// CHECK16-SAME: () #[[ATTR4:[0-9]+]] comdat { -// CHECK16-NEXT: call void @_ZTH1t() -// CHECK16-NEXT: ret i32* @t -// -// -// CHECK16-LABEL: define {{[^@]+}}@__tls_init -// CHECK16-SAME: () #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[TMP0:%.*]] = load i8, i8* @__tls_guard, align 1 -// CHECK16-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK16-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF4:![0-9]+]] -// CHECK16: init: -// CHECK16-NEXT: store i8 1, i8* @__tls_guard, align 1 -// CHECK16-NEXT: call void @__cxx_global_var_init() -// CHECK16-NEXT: br label [[EXIT]] -// CHECK16: exit: -// CHECK16-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@main -// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK17-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK17-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) -// CHECK17-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK17-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8 -// CHECK17-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK17-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK17: init.check: -// CHECK17-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK17: init: -// CHECK17-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK17-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK17-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK17-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK17-NEXT: br label [[INIT_END]] -// CHECK17: init.end: -// CHECK17-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8 -// CHECK17-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK17-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK17: init.check2: -// CHECK17-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK17-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK17: init4: -// CHECK17-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) -// CHECK17-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK17-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK17-NEXT: br label [[INIT_END5]] -// CHECK17: init.end5: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK17-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK17-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK17-NEXT: [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK17-NEXT: store i32 [[CALL7]], i32* [[RETVAL]], align 4 -// CHECK17-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK17-NEXT: ret i32 [[TMP8]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK17-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK17-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: ret %struct.S* [[THIS1]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK17-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK17-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK17-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK17-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK17-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK17: arraydestroy.body: -// CHECK17-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK17-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK17-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK17-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) -// CHECK17-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK17: arraydestroy.done1: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK17-SAME: () #[[ATTR2]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK17-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK17-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) -// CHECK17-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK17-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] -// CHECK17-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8 -// CHECK17-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK17-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] -// CHECK17: init.check: -// CHECK17-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK17: init: -// CHECK17-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) -// CHECK17-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) -// CHECK17-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK17-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK17-NEXT: br label [[INIT_END]] -// CHECK17: init.end: -// CHECK17-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8 -// CHECK17-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK17-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK17: init.check2: -// CHECK17-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK17-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK17: init4: -// CHECK17-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) -// CHECK17-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK17-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK17-NEXT: br label [[INIT_END5]] -// CHECK17: init.end5: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK17-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK17-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) -// CHECK17-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK17-NEXT: ret i32 0 -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK17-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK17-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK17-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK17-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK17-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK17-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK17-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK17-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: ret %struct.S.0* [[THIS1]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK17-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK17-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK17-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1 -// CHECK17-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK17-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK17: arraydestroy.body: -// CHECK17-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK17-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK17-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK17-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) -// CHECK17-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK17: arraydestroy.done1: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK17-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK17-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK17-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK18-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) -// CHECK18-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] -// CHECK18-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8 -// CHECK18-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK18-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK18: init.check: -// CHECK18-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK18: init: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK18-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK18-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK18-NEXT: br label [[INIT_END]] -// CHECK18: init.end: -// CHECK18-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8 -// CHECK18-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK18-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK18: init.check2: -// CHECK18-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK18-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK18: init4: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) -// CHECK18-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK18-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK18-NEXT: br label [[INIT_END5]] -// CHECK18: init.end5: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK18-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK18-NEXT: [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK18-NEXT: store i32 [[CALL7]], i32* [[RETVAL]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: ret i32 [[TMP8]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret %struct.S* [[THIS1]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done1: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK18-SAME: () #[[ATTR2]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK18-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) -// CHECK18-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] -// CHECK18-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8 -// CHECK18-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK18-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] -// CHECK18: init.check: -// CHECK18-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK18: init: -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) -// CHECK18-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK18-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK18-NEXT: br label [[INIT_END]] -// CHECK18: init.end: -// CHECK18-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8 -// CHECK18-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK18-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK18: init.check2: -// CHECK18-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK18-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK18: init4: -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) -// CHECK18-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK18-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK18-NEXT: br label [[INIT_END5]] -// CHECK18: init.end5: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK18-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK18-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK18-NEXT: ret i32 0 -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK18-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK18-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK18-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret %struct.S.0* [[THIS1]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1 -// CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done1: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK19-NEXT: ret i32 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK20-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK20-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK20-NEXT: ret i32 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK20-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK20-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK20-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK20-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK20-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK20-NEXT: store volatile i32 1, i32* @g, align 128 -// CHECK20-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK20-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK20-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK20-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK20-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK20-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK20-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK20-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK20-NEXT: store volatile i32 2, i32* @g, align 128 -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z10array_funcv -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ10array_funcvE1s to i8*) acquire, align 8 -// CHECK21-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK21-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK21: init.check: -// CHECK21-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1:[0-9]+]] -// CHECK21-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK21-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK21: init: -// CHECK21-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK21: arrayctor.loop: -// CHECK21-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK21-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[ARRAYCTOR_CUR]]) -// CHECK21-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1 -// CHECK21-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2) -// CHECK21-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK21: arrayctor.cont: -// CHECK21-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR1]] -// CHECK21-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1]] -// CHECK21-NEXT: br label [[INIT_END]] -// CHECK21: init.end: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK21-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK21-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK21-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0) -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done1: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK21-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR1]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK21-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK21-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK21-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: ret void -// diff --git a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp --- a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp @@ -5,27 +5,27 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK18 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef ARRAY #ifndef HEADER @@ -2161,71 +2161,79 @@ // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK5-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP6]]) // CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done4: // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP8]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // @@ -2233,18 +2241,154 @@ // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK5-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done4: +// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) +// CHECK5-NEXT: store i32 2, i32* [[CONV1]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done9: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK5-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK5-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*)) +// CHECK5-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32* +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8* +// CHECK5-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*)) +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -2257,72 +2401,57 @@ // CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[T_VAR]]) // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done1: // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP2]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[C7:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[_TMP10:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[C7:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[A]], align 8 // CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 // CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 // CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 // CHECK5-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 // CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 // CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 4 +// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 // CHECK5-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 // CHECK5-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 // CHECK5-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 @@ -2330,29 +2459,77 @@ // CHECK5-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 // CHECK5-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 // CHECK5-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 -// CHECK5-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 +// CHECK5-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 // CHECK5-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK5-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK5-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 4 -// CHECK5-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 -// CHECK5-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4 +// CHECK5-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 +// CHECK5-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 +// CHECK5-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 +// CHECK5-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 +// CHECK5-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK5-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 +// CHECK5-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* +// CHECK5-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) +// CHECK5-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK5-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 4 +// CHECK5-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 // CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP11]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 // CHECK5-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 // CHECK5-NEXT: ret void // @@ -2360,9 +2537,9 @@ // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float @@ -2370,23 +2547,14 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: ret void -// -// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 @@ -2396,12 +2564,63 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK5-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK5-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK5-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // @@ -2409,9 +2628,9 @@ // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev // CHECK5-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 // CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // @@ -2419,32 +2638,131 @@ // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 +// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK5-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK5-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done4: +// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) +// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 +// CHECK5-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 +// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done9: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 @@ -2454,18 +2772,40 @@ // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev // CHECK5-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 // CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 +// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i64 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK5-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 @@ -2475,11 +2815,11 @@ // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 @@ -2488,12 +2828,31 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: ret void // // @@ -2501,71 +2860,79 @@ // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK6-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP6]]) // CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done4: // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP8]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // @@ -2573,18 +2940,154 @@ // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK6-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK6-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done4: +// CHECK6-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK6-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) +// CHECK6-NEXT: store i32 2, i32* [[CONV1]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done9: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK6-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK6-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK6-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK6-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*)) +// CHECK6-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8* +// CHECK6-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*)) +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -2597,72 +3100,57 @@ // CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[T_VAR]]) // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done1: // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP2]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[C7:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[_TMP10:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[C7:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[A]], align 8 // CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 // CHECK6-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 // CHECK6-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 // CHECK6-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 // CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 // CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 4 +// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 // CHECK6-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 // CHECK6-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 // CHECK6-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 @@ -2670,29 +3158,77 @@ // CHECK6-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 // CHECK6-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 // CHECK6-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 -// CHECK6-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 +// CHECK6-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 // CHECK6-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK6-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK6-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 4 -// CHECK6-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 -// CHECK6-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 4 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4 +// CHECK6-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 +// CHECK6-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 +// CHECK6-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 +// CHECK6-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 +// CHECK6-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK6-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 +// CHECK6-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* +// CHECK6-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) +// CHECK6-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK6-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 4 +// CHECK6-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 // CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK6-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP11]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 // CHECK6-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 // CHECK6-NEXT: ret void // @@ -2700,9 +3236,9 @@ // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float @@ -2710,23 +3246,14 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: ret void -// -// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 @@ -2736,12 +3263,63 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK6-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK6-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK6-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK6-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK6-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // @@ -2749,9 +3327,9 @@ // CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev // CHECK6-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 // CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // @@ -2759,32 +3337,131 @@ // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 +// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK6-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK6-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK6-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done4: +// CHECK6-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) +// CHECK6-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 +// CHECK6-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 +// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done9: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 @@ -2794,18 +3471,40 @@ // CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev // CHECK6-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 // CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 +// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i64 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK6-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 @@ -2815,11 +3514,11 @@ // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 @@ -2828,12 +3527,31 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: ret void // // @@ -2841,56 +3559,55 @@ // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 +// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(4) [[REF_TMP]]) +// CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 +// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[A2:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C7:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[_TMP10:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[C7:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[A]], align 8 // CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 // CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 // CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 // CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 // CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 +// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 // CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32* [[A3]], i32** [[A2]], align 4 +// CHECK7-NEXT: store i32* [[A3]], i32** [[A2]], align 8 // CHECK7-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 // CHECK7-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 // CHECK7-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 @@ -2898,74 +3615,188 @@ // CHECK7-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 // CHECK7-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 // CHECK7-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 -// CHECK7-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 +// CHECK7-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 // CHECK7-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 4 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 -// CHECK7-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 4 +// CHECK7-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 +// CHECK7-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 +// CHECK7-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 +// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 +// CHECK7-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* +// CHECK7-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 +// CHECK7-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK7-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 +// CHECK7-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* +// CHECK7-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) +// CHECK7-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP5]], align 4 +// CHECK7-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP5]], align 8 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK7-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK7-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 8 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B4]], i32** [[TMP8]], align 4 +// CHECK7-NEXT: store i32* [[CONV1]], i32** [[TMP8]], align 8 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP10]], align 4 -// CHECK7-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 4 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(16) [[REF_TMP]]) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK7-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 8 +// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(32) [[REF_TMP]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK7-SAME: (%class.anon.0* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 4 -// CHECK7-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 4 -// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 4 -// CHECK7-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 4 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK7-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK7-NEXT: store i32 [[INC3]], i32* [[TMP17]], align 4 -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[DEC4:%.*]] = add nsw i32 [[TMP19]], -1 -// CHECK7-NEXT: store i32 [[DEC4]], i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP2]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP17]], i32* [[CONV2]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP19]], align 8 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP21]], 1 -// CHECK7-NEXT: store i32 [[DIV5]], i32* [[TMP20]], align 4 +// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i64* [[C_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP21]], i32* [[CONV3]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i64, i64* [[C_CASTED]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* +// CHECK7-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK7-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 +// CHECK7-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 +// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[G1:%.*]] = alloca i32, align 128 +// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 +// CHECK7-NEXT: store i32 1, i32* [[G1]], align 128 +// CHECK7-NEXT: store i32 2, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 +// CHECK7-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 +// CHECK7-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 +// CHECK7-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull dereferenceable(16) [[REF_TMP]]) // CHECK7-NEXT: ret void // // @@ -2973,126 +3804,149 @@ // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 4 +// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 +// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 4 +// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 // CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4 +// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 // CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 // CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 // CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 4 +// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 // CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 4 +// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 // CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* // CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* // CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 // CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* // CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) // CHECK8-NEXT: ret i32 0 // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 +// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke // CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, align 128 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 +// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 +// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 +// CHECK8-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 // CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 1, i32* @g, align 128 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 +// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @g, i64 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[G1:%.*]] = alloca i32, align 128 +// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, align 128 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 +// CHECK8-NEXT: store i32 1, i32* [[G1]], align 128 +// CHECK8-NEXT: store i32 2, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 0 // CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 8 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 4 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 16 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) +// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 1 +// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 +// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 2 +// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 +// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 3 +// CHECK8-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 16 +// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 4 +// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 +// CHECK8-NEXT: [[TMP2:%.*]] = load volatile i32, i32* [[G1]], align 128 +// CHECK8-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 128 +// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[BLOCK_CAPTURED2]], align 32 +// CHECK8-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]] to void ()* +// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic* +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* +// CHECK8-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)* +// CHECK8-NEXT: call void [[TMP8]](i8* [[TMP6]]) // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 +// CHECK8-LABEL: define {{[^@]+}}@g_block_invoke // CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>*, align 4 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>** [[BLOCK_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 +// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 +// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>*, align 8 +// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 +// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* +// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>** [[BLOCK_ADDR]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 // CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 +// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 +// CHECK8-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR1]], align 32 // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[A2:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C7:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[_TMP10:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[C7:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[A]], align 8 // CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 // CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 // CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 // CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 // CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 +// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 // CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32* [[A3]], i32** [[A2]], align 4 +// CHECK8-NEXT: store i32* [[A3]], i32** [[A2]], align 8 // CHECK8-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 // CHECK8-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 // CHECK8-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 @@ -3100,3379 +3954,371 @@ // CHECK8-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 // CHECK8-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 // CHECK8-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 -// CHECK8-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 +// CHECK8-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 // CHECK8-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK8-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 4 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 -// CHECK8-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 4 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 2 +// CHECK8-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 +// CHECK8-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 +// CHECK8-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 +// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 +// CHECK8-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* +// CHECK8-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 +// CHECK8-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK8-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 +// CHECK8-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* +// CHECK8-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) +// CHECK8-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 +// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 +// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 +// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 +// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 +// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 // CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 4 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED12:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK8-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED12]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED13:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP10]], align 4 -// CHECK8-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED13]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]] to void ()* +// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 +// CHECK8-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 +// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 +// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.4 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 +// CHECK8-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK8-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED7]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK8-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED8]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* // CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 8 // CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* // CHECK8-NEXT: call void [[TMP12]](i8* [[TMP10]]) // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke +// CHECK8-LABEL: define {{[^@]+}}@g_block_invoke_2 // CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>*, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[_TMP6:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>** [[BLOCK_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 4 +// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 +// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 +// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* +// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 +// CHECK8-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 +// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 4 +// CHECK8-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 // CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 4 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 4 -// CHECK8-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[TMP7]], align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 4 -// CHECK8-NEXT: [[DEC8:%.*]] = add nsw i32 [[TMP9]], -1 -// CHECK8-NEXT: store i32 [[DEC8]], i32* [[BLOCK_CAPTURE_ADDR4]], align 4 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP6]], align 4 +// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 +// CHECK8-NEXT: [[CONV5:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR6:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR6]], align 8 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK8-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[DIV9]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[CONV7:%.*]] = bitcast i64* [[C_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP11]], i32* [[CONV7]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[C_CASTED]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SS* [[THIS]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP12]]) // CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) -// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP6]]) -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done4: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP8]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* +// CHECK8-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK8-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 +// CHECK8-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 +// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe +// CHECK9-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK9-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] +// CHECK9-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, x86_fp80*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP8]], i32* [[N_ADDR]], i64 [[TMP1]], x86_fp80* [[TMP9]], float* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]]) +// CHECK9-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK9-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK9-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done4: -// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) -// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done9: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK9-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK9-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK9-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 +// CHECK9-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) +// CHECK9-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 +// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) +// CHECK9-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe +// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK9-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] +// CHECK9-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, x86_fp80*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], x86_fp80* [[TMP9]], %struct.St* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i32* [[N_ADDR]], %struct.St* [[TMP10]]) +// CHECK9-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*)) -// CHECK9-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32* -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8* -// CHECK9-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[T_VAR]]) -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP2]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK9-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK9-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK9-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK9-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK9-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK9-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK9-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK9-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK9-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK9-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK9-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK9-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK9-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK9-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 -// CHECK9-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 -// CHECK9-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 -// CHECK9-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 -// CHECK9-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* -// CHECK9-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) -// CHECK9-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK9-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 -// CHECK9-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK9-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK9-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 -// CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done4: -// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) -// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK9-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done9: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK9-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK9-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i64 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK9-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 8 +// CHECK9-NEXT: [[TMP8:%.*]] = add nuw i64 [[TMP7]], 127 +// CHECK9-NEXT: [[TMP9:%.*]] = udiv i64 [[TMP8]], 128 +// CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 128 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK9-NEXT: [[DOTVLA2__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP12]], i64 [[TMP10]], i8* inttoptr (i64 8 to i8*)) +// CHECK9-NEXT: [[DOTVLA2__ADDR:%.*]] = bitcast i8* [[DOTVLA2__VOID_ADDR]] to double* +// CHECK9-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK9-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast double* [[DOTVLA2__ADDR]] to i8* +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast double* [[TMP4]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP15]], i8* align 128 [[TMP16]], i64 [[TMP14]], i1 false) +// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: store i32 [[TMP17]], i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP17]] to double +// CHECK9-NEXT: [[TMP18:%.*]] = mul nsw i64 1, [[TMP3]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[DOTVLA2__ADDR]], i64 [[TMP18]] +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP19]], 1 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 +// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] +// CHECK9-NEXT: store double [[CONV]], double* [[ARRAYIDX7]], align 8 +// CHECK9-NEXT: [[CONV8:%.*]] = fpext double [[CONV]] to x86_fp80 +// CHECK9-NEXT: [[TMP20:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[B9]], align 4 +// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP20]], i64 [[IDXPROM10]] +// CHECK9-NEXT: store x86_fp80 [[CONV8]], x86_fp80* [[ARRAYIDX11]], align 16 +// CHECK9-NEXT: [[TMP22:%.*]] = bitcast double* [[DOTVLA2__ADDR]] to i8* +// CHECK9-NEXT: call void @__kmpc_free(i32 [[TMP12]], i8* [[TMP22]], i8* inttoptr (i64 8 to i8*)) // CHECK9-NEXT: ret void // -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) -// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP6]]) -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done4: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP8]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK10-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done4: -// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) -// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) -// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done9: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*)) -// CHECK10-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32* -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8* -// CHECK10-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[T_VAR]]) -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP2]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK10-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK10-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK10-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK10-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK10-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK10-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK10-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK10-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK10-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK10-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK10-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK10-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK10-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK10-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK10-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 -// CHECK10-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 -// CHECK10-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 -// CHECK10-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 -// CHECK10-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* -// CHECK10-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) -// CHECK10-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK10-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK10-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 -// CHECK10-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK10-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK10-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 -// CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done4: -// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) -// CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) -// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK10-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done9: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK10-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i64 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK11-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK11-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK11-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK11-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK11-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK11-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK11-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK11-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK11-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK11-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK11-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 -// CHECK11-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 -// CHECK11-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* -// CHECK11-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK11-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 -// CHECK11-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* -// CHECK11-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) -// CHECK11-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP5]], align 8 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK11-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 8 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK11-NEXT: store i32* [[CONV1]], i32** [[TMP8]], align 8 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK11-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 8 -// CHECK11-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(32) [[REF_TMP]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK11-SAME: (%class.anon.0* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK11-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[CONV]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK11-NEXT: store i32 [[TMP17]], i32* [[CONV2]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP19]], align 8 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[C_CASTED]] to i32* -// CHECK11-NEXT: store i32 [[TMP21]], i32* [[CONV3]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[C_CASTED]], align 8 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* -// CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK11-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK11-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca i32, align 128 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 -// CHECK11-NEXT: store i32 1, i32* [[G1]], align 128 -// CHECK11-NEXT: store i32 2, i32* [[CONV]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 -// CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 -// CHECK11-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @g, i64 [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca i32, align 128 -// CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, align 128 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 -// CHECK12-NEXT: store i32 1, i32* [[G1]], align 128 -// CHECK12-NEXT: store i32 2, i32* [[CONV]], align 8 -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: [[TMP2:%.*]] = load volatile i32, i32* [[G1]], align 128 -// CHECK12-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[BLOCK_CAPTURED2]], align 32 -// CHECK12-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 8 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP8]](i8* [[TMP6]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@g_block_invoke -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>*, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR1]], align 32 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK12-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK12-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK12-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK12-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK12-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK12-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK12-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK12-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK12-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK12-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK12-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK12-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK12-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK12-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK12-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 -// CHECK12-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 -// CHECK12-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 -// CHECK12-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* -// CHECK12-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 -// CHECK12-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 -// CHECK12-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* -// CHECK12-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) -// CHECK12-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.4 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED7]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK12-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED8]], align 8 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP12]](i8* [[TMP10]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@g_block_invoke_2 -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK12-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK12-NEXT: [[CONV5:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR6:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR6]], align 8 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[CONV7:%.*]] = bitcast i64* [[C_CASTED]] to i32* -// CHECK12-NEXT: store i32 [[TMP11]], i32* [[CONV7]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[C_CASTED]], align 8 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SS* [[THIS]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP12]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* -// CHECK12-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK12-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done2: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK13-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done2: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK13-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK13-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK13-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK13-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK13-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK13-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK13-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK13-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK13-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK13-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK13-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK13-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK13-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK13-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK13-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK13-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK13-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK13-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK13-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP11]], align 8 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 -// CHECK13-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK13-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK13-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK13-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK13-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK13-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done2: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK14-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done2: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK14-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK14-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK14-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK14-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK14-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK14-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK14-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK14-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK14-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK14-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK14-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK14-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK14-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK14-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK14-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK14-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK14-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK14-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK14-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK14-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP11]], align 8 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 -// CHECK14-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK14-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK14-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK14-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK14-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK14-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK14-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK15-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK15-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK15-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK15-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK15-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 8 -// CHECK15-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK15-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK15-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK15-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK15-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK15-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK15-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK15-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK15-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK15-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK15-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK15-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK15-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK15-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK15-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 8 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK15-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP5]], align 8 -// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK15-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 8 -// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK15-NEXT: store i32* [[B4]], i32** [[TMP8]], align 8 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK15-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 8 -// CHECK15-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(32) [[REF_TMP]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK15-SAME: (%class.anon.0* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK15-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK15-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK15-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK15-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK15-NEXT: store i32 [[INC3]], i32* [[TMP17]], align 4 -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK15-NEXT: [[DEC4:%.*]] = add nsw i32 [[TMP19]], -1 -// CHECK15-NEXT: store i32 [[DEC4]], i32* [[TMP14]], align 4 -// CHECK15-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK15-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP21]], 1 -// CHECK15-NEXT: store i32 [[DIV5]], i32* [[TMP20]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK16-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK16-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK16-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK16-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, align 128 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store i32 1, i32* @g, align 128 -// CHECK16-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK16-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 32 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>*, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR1]], align 32 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK16-SAME: (%struct.SS* nonnull dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK16-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK16-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK16-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK16-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK16-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK16-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK16-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK16-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK16-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK16-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK16-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK16-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK16-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK16-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK16-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK16-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK16-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 8 -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED12:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED12]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED13:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK16-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED13]], align 8 -// CHECK16-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK16-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP12]](i8* [[TMP10]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK16-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK16-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK16-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 -// CHECK16-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[TMP7]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK16-NEXT: [[DEC8:%.*]] = add nsw i32 [[TMP9]], -1 -// CHECK16-NEXT: store i32 [[DEC8]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP6]], align 8 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK16-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[DIV9]], i32* [[TMP10]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe -// CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, x86_fp80*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP8]], i32* [[N_ADDR]], i64 [[TMP1]], x86_fp80* [[TMP9]], float* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]]) -// CHECK17-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 -// CHECK17-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) -// CHECK17-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 -// CHECK17-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) -// CHECK17-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe -// CHECK17-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, x86_fp80*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], x86_fp80* [[TMP9]], %struct.St* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i32* [[N_ADDR]], %struct.St* [[TMP10]]) -// CHECK17-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 8 -// CHECK17-NEXT: [[TMP8:%.*]] = add nuw i64 [[TMP7]], 127 -// CHECK17-NEXT: [[TMP9:%.*]] = udiv i64 [[TMP8]], 128 -// CHECK17-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 128 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK17-NEXT: [[DOTVLA2__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP12]], i64 [[TMP10]], i8* inttoptr (i64 8 to i8*)) -// CHECK17-NEXT: [[DOTVLA2__ADDR:%.*]] = bitcast i8* [[DOTVLA2__VOID_ADDR]] to double* -// CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast double* [[DOTVLA2__ADDR]] to i8* -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast double* [[TMP4]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP15]], i8* align 128 [[TMP16]], i64 [[TMP14]], i1 false) -// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 -// CHECK17-NEXT: store i32 [[TMP17]], i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP17]] to double -// CHECK17-NEXT: [[TMP18:%.*]] = mul nsw i64 1, [[TMP3]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[DOTVLA2__ADDR]], i64 [[TMP18]] -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP19]], 1 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 -// CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] -// CHECK17-NEXT: store double [[CONV]], double* [[ARRAYIDX7]], align 8 -// CHECK17-NEXT: [[CONV8:%.*]] = fpext double [[CONV]] to x86_fp80 -// CHECK17-NEXT: [[TMP20:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[B9]], align 4 -// CHECK17-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK17-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP20]], i64 [[IDXPROM10]] -// CHECK17-NEXT: store x86_fp80 [[CONV8]], x86_fp80* [[ARRAYIDX11]], align 16 -// CHECK17-NEXT: [[TMP22:%.*]] = bitcast double* [[DOTVLA2__ADDR]] to i8* -// CHECK17-NEXT: call void @__kmpc_free(i32 [[TMP12]], i8* [[TMP22]], i8* inttoptr (i64 8 to i8*)) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe -// CHECK18-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK18-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP8]], i64 0 -// CHECK18-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP9]], i32 [[TMP10]], x86_fp80* [[TMP11]]) -// CHECK18-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe -// CHECK18-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK18-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 -// CHECK18-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[B2]], align 4 -// CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: store i32 [[TMP9]], i32* [[A3]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double -// CHECK18-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i64 [[TMP10]] -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], 1 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 -// CHECK18-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] -// CHECK18-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to x86_fp80 -// CHECK18-NEXT: [[TMP12:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[B6]], align 4 -// CHECK18-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP12]], i64 [[IDXPROM7]] -// CHECK18-NEXT: store x86_fp80 [[CONV5]], x86_fp80* [[ARRAYIDX8]], align 16 -// CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK18-NEXT: ret void -// diff --git a/clang/test/OpenMP/parallel_for_codegen.cpp b/clang/test/OpenMP/parallel_for_codegen.cpp --- a/clang/test/OpenMP/parallel_for_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_codegen.cpp @@ -11,19 +11,19 @@ // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -gno-column-info -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -O1 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -O1 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -O1 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" /// The RUN using flags "-triple x86_64-apple-darwin10 -O1 -fopenmp-simd" generates different IR when there is no X86 backend. // REQUIRES: x86-registered-target @@ -6507,2897 +6507,860 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z17with_var_schedulev +// CHECK7-LABEL: define {{[^@]+}}@_Z9incrementv // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[A1:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store double 5.000000e+00, double* [[A]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 -// CHECK7-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 -// CHECK7-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i64 1, i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[CONV2:%.*]] = uitofp i64 [[TMP1]] to double -// CHECK7-NEXT: [[TMP2:%.*]] = load double, double* [[A1]], align 8 -// CHECK7-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP2]] -// CHECK7-NEXT: [[CMP:%.*]] = fcmp olt double [[CONV2]], [[ADD]] -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[INC:%.*]] = add i64 [[TMP3]], 1 -// CHECK7-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) +// CHECK7-NEXT: ret i32 0 // // -// CHECK7-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv +// CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i64 131071, i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] -// CHECK7-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 -// CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 5, [[MUL]] +// CHECK7-NEXT: store i32 [[SUB]], i32* [[J]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret i32 0 // // -// CHECK7-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@_Z16range_for_singlev +// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i64 131071, i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] -// CHECK7-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 -// CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end: +// CHECK7-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* +// CHECK7-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[Y:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[X]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[Y]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK7-NEXT: store i8 [[CONV]], i8* [[I]], align 1 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: store i32 11, i32* [[X]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] -// CHECK7-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] -// CHECK7-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK7-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] -// CHECK7-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] -// CHECK7-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[X]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 -// CHECK7-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end13: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 +// CHECK7-NEXT: [[__END1:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[__BEGIN15:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[A:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 +// CHECK7-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 +// CHECK7-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 +// CHECK7-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 +// CHECK7-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 +// CHECK7-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 +// CHECK7-NEXT: store i32* [[ARRAYDECAY1]], i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__END1]], align 8 +// CHECK7-NEXT: store i32* [[TMP3]], i32** [[DOTCAPTURE_EXPR_2]], align 8 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK7-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP4]] to i64 +// CHECK7-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP5]] to i64 +// CHECK7-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] +// CHECK7-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 +// CHECK7-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1 +// CHECK7-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK7-NEXT: store i32* [[TMP6]], i32** [[__BEGIN1]], align 8 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 +// CHECK7-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK7-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP20]], 1 +// CHECK7-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[MUL]] +// CHECK7-NEXT: store i32* [[ADD_PTR8]], i32** [[__BEGIN15]], align 8 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[__BEGIN15]], align 8 +// CHECK7-NEXT: store i32* [[TMP21]], i32** [[A]], align 8 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP23]], 1 +// CHECK7-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv +// CHECK7-SAME: () #[[ATTR3]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[X]], align 4 -// CHECK7-NEXT: store i8 48, i8* [[I]], align 1 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: store i32 -10, i32* [[X]], align 4 -// CHECK7-NEXT: br label [[FOR_COND1:%.*]] -// CHECK7: for.cond1: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 -// CHECK7-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK7-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body3: -// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] -// CHECK7-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] -// CHECK7-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] -// CHECK7-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[X]], align 4 -// CHECK7-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC11:%.*]] -// CHECK7: for.inc11: -// CHECK7-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 -// CHECK7-NEXT: store i8 [[INC12]], i8* [[I]], align 1 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK7: for.end13: +// CHECK7-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* +// CHECK7-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z3foov -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_Z8mayThrowv() -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK7-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: [[SAVED_STACK1:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 -// CHECK7-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK1]], align 8 -// CHECK7-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP1]], align 16 -// CHECK7-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 -// CHECK7-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP4]], 2147483647 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[CONV]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP7]] to float -// CHECK7-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]] -// CHECK7-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM5:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM5]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK7-NEXT: [[ADD7:%.*]] = fadd float [[TMP10]], [[ADD4]] -// CHECK7-NEXT: store float [[ADD7]], float* [[ARRAYIDX6]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 127 -// CHECK7-NEXT: store i32 [[ADD8]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK1]], align 8 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK7-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 +// CHECK7-NEXT: [[__END1:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 +// CHECK7-NEXT: [[__END2:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[__BEGIN119:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[__BEGIN220:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[A:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 +// CHECK7-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 +// CHECK7-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 +// CHECK7-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 +// CHECK7-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 +// CHECK7-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE2]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 +// CHECK7-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 +// CHECK7-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY2]], i64 10 +// CHECK7-NEXT: store i32* [[ADD_PTR3]], i32** [[__END2]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 +// CHECK7-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 +// CHECK7-NEXT: store i32* [[ARRAYDECAY4]], i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 +// CHECK7-NEXT: store i32* [[TMP4]], i32** [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 +// CHECK7-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP5]], i64 0, i64 0 +// CHECK7-NEXT: store i32* [[ARRAYDECAY7]], i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[__END2]], align 8 +// CHECK7-NEXT: store i32* [[TMP6]], i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK7-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP7]] to i64 +// CHECK7-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP8]] to i64 +// CHECK7-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] +// CHECK7-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK7-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint i32* [[TMP9]] to i64 +// CHECK7-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint i32* [[TMP10]] to i64 +// CHECK7-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]] +// CHECK7-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4 +// CHECK7-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1 +// CHECK7-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1 +// CHECK7-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]] +// CHECK7-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_9]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK7-NEXT: store i32* [[TMP11]], i32** [[__BEGIN1]], align 8 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK7-NEXT: store i32* [[TMP12]], i32** [[__BEGIN2]], align 8 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP13]], [[TMP14]] +// CHECK7-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: land.lhs.true: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK7-NEXT: [[CMP18:%.*]] = icmp ult i32* [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 +// CHECK7-NEXT: store i64 [[TMP17]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 +// CHECK7-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]] +// CHECK7-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP24]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] +// CHECK7-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK7-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK7-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint i32* [[TMP29]] to i64 +// CHECK7-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint i32* [[TMP30]] to i64 +// CHECK7-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]] +// CHECK7-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4 +// CHECK7-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1 +// CHECK7-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1 +// CHECK7-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1 +// CHECK7-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]] +// CHECK7-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP28]], [[MUL30]] +// CHECK7-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1 +// CHECK7-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[MUL32]] +// CHECK7-NEXT: store i32* [[ADD_PTR33]], i32** [[__BEGIN119]], align 8 +// CHECK7-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK7-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK7-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK7-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint i32* [[TMP34]] to i64 +// CHECK7-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint i32* [[TMP35]] to i64 +// CHECK7-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]] +// CHECK7-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4 +// CHECK7-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1 +// CHECK7-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1 +// CHECK7-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1 +// CHECK7-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]] +// CHECK7-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP33]], [[MUL41]] +// CHECK7-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK7-NEXT: [[TMP37:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK7-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint i32* [[TMP36]] to i64 +// CHECK7-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint i32* [[TMP37]] to i64 +// CHECK7-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]] +// CHECK7-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4 +// CHECK7-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1 +// CHECK7-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1 +// CHECK7-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1 +// CHECK7-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]] +// CHECK7-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]] +// CHECK7-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP32]], [[MUL51]] +// CHECK7-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1 +// CHECK7-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, i32* [[TMP31]], i64 [[MUL53]] +// CHECK7-NEXT: store i32* [[ADD_PTR54]], i32** [[__BEGIN220]], align 8 +// CHECK7-NEXT: [[TMP38:%.*]] = load i32*, i32** [[__BEGIN119]], align 8 +// CHECK7-NEXT: store i32* [[TMP38]], i32** [[A]], align 8 +// CHECK7-NEXT: [[TMP39:%.*]] = load i32*, i32** [[__BEGIN220]], align 8 +// CHECK7-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP39]], align 4 +// CHECK7-NEXT: store i32 [[TMP40]], i32* [[B]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = load i32, i32* [[B]], align 4 +// CHECK7-NEXT: [[TMP42:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK7-NEXT: store i32 [[TMP41]], i32* [[TMP42]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP43:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP43]], 1 +// CHECK7-NEXT: store i64 [[ADD55]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP45]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: // CHECK7-NEXT: ret void -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]] -// CHECK7-NEXT: unreachable -// // -// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK7-NEXT: unreachable // -// -// CHECK8-LABEL: define {{[^@]+}}@_Z17with_var_schedulev +// CHECK8-LABEL: define {{[^@]+}}@_Z9incrementv // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[A1:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store double 5.000000e+00, double* [[A]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 -// CHECK8-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 -// CHECK8-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i64 1, i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[CONV2:%.*]] = uitofp i64 [[TMP1]] to double -// CHECK8-NEXT: [[TMP2:%.*]] = load double, double* [[A1]], align 8 -// CHECK8-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP2]] -// CHECK8-NEXT: [[CMP:%.*]] = fcmp olt double [[CONV2]], [[ADD]] -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[INC:%.*]] = add i64 [[TMP3]], 1 -// CHECK8-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) +// CHECK8-NEXT: ret i32 0 // // -// CHECK8-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv +// CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i64 131071, i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] -// CHECK8-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 -// CHECK8-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 5, [[MUL]] +// CHECK8-NEXT: store i32 [[SUB]], i32* [[J]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret i32 0 // // -// CHECK8-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@_Z16range_for_singlev +// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i64 131071, i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] -// CHECK8-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 -// CHECK8-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end: +// CHECK8-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* +// CHECK8-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[Y:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[X]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[Y]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK8-NEXT: store i8 [[CONV]], i8* [[I]], align 1 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store i32 11, i32* [[X]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] -// CHECK8-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 -// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] -// CHECK8-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK8-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] -// CHECK8-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] -// CHECK8-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 -// CHECK8-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[X]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 -// CHECK8-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end13: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 +// CHECK8-NEXT: [[__END1:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[__BEGIN15:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[A:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 +// CHECK8-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 +// CHECK8-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 +// CHECK8-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 +// CHECK8-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 +// CHECK8-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 +// CHECK8-NEXT: store i32* [[ARRAYDECAY1]], i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__END1]], align 8 +// CHECK8-NEXT: store i32* [[TMP3]], i32** [[DOTCAPTURE_EXPR_2]], align 8 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK8-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP4]] to i64 +// CHECK8-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP5]] to i64 +// CHECK8-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] +// CHECK8-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 +// CHECK8-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1 +// CHECK8-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK8-NEXT: store i32* [[TMP6]], i32** [[__BEGIN1]], align 8 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 +// CHECK8-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK8-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP20]], 1 +// CHECK8-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[MUL]] +// CHECK8-NEXT: store i32* [[ADD_PTR8]], i32** [[__BEGIN15]], align 8 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[__BEGIN15]], align 8 +// CHECK8-NEXT: store i32* [[TMP21]], i32** [[A]], align 8 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP23]], 1 +// CHECK8-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv +// CHECK8-SAME: () #[[ATTR3]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[X]], align 4 -// CHECK8-NEXT: store i8 48, i8* [[I]], align 1 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store i32 -10, i32* [[X]], align 4 -// CHECK8-NEXT: br label [[FOR_COND1:%.*]] -// CHECK8: for.cond1: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 -// CHECK8-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK8-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body3: -// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] -// CHECK8-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] -// CHECK8-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] -// CHECK8-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[X]], align 4 -// CHECK8-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC11:%.*]] -// CHECK8: for.inc11: -// CHECK8-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 -// CHECK8-NEXT: store i8 [[INC12]], i8* [[I]], align 1 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK8: for.end13: +// CHECK8-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* +// CHECK8-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z3foov -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_Z8mayThrowv() -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK8-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[SAVED_STACK1:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 -// CHECK8-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK1]], align 8 -// CHECK8-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP1]], align 16 -// CHECK8-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 -// CHECK8-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP4]], 2147483647 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[CONV]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP7]] to float -// CHECK8-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]] -// CHECK8-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM5:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM5]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK8-NEXT: [[ADD7:%.*]] = fadd float [[TMP10]], [[ADD4]] -// CHECK8-NEXT: store float [[ADD7]], float* [[ARRAYIDX6]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 127 -// CHECK8-NEXT: store i32 [[ADD8]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK1]], align 8 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK8-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 +// CHECK8-NEXT: [[__END1:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 +// CHECK8-NEXT: [[__END2:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[__BEGIN119:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[__BEGIN220:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[A:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 +// CHECK8-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 +// CHECK8-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 +// CHECK8-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 +// CHECK8-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 +// CHECK8-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE2]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 +// CHECK8-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 +// CHECK8-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY2]], i64 10 +// CHECK8-NEXT: store i32* [[ADD_PTR3]], i32** [[__END2]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 +// CHECK8-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 +// CHECK8-NEXT: store i32* [[ARRAYDECAY4]], i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 +// CHECK8-NEXT: store i32* [[TMP4]], i32** [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 +// CHECK8-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP5]], i64 0, i64 0 +// CHECK8-NEXT: store i32* [[ARRAYDECAY7]], i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[__END2]], align 8 +// CHECK8-NEXT: store i32* [[TMP6]], i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK8-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP7]] to i64 +// CHECK8-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP8]] to i64 +// CHECK8-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] +// CHECK8-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK8-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint i32* [[TMP9]] to i64 +// CHECK8-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint i32* [[TMP10]] to i64 +// CHECK8-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]] +// CHECK8-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4 +// CHECK8-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1 +// CHECK8-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1 +// CHECK8-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]] +// CHECK8-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_9]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK8-NEXT: store i32* [[TMP11]], i32** [[__BEGIN1]], align 8 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK8-NEXT: store i32* [[TMP12]], i32** [[__BEGIN2]], align 8 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP13]], [[TMP14]] +// CHECK8-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: land.lhs.true: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK8-NEXT: [[CMP18:%.*]] = icmp ult i32* [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 +// CHECK8-NEXT: store i64 [[TMP17]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 +// CHECK8-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]] +// CHECK8-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP24]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] +// CHECK8-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 +// CHECK8-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK8-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint i32* [[TMP29]] to i64 +// CHECK8-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint i32* [[TMP30]] to i64 +// CHECK8-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]] +// CHECK8-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4 +// CHECK8-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1 +// CHECK8-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1 +// CHECK8-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1 +// CHECK8-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]] +// CHECK8-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP28]], [[MUL30]] +// CHECK8-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1 +// CHECK8-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[MUL32]] +// CHECK8-NEXT: store i32* [[ADD_PTR33]], i32** [[__BEGIN119]], align 8 +// CHECK8-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK8-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK8-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK8-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint i32* [[TMP34]] to i64 +// CHECK8-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint i32* [[TMP35]] to i64 +// CHECK8-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]] +// CHECK8-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4 +// CHECK8-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1 +// CHECK8-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1 +// CHECK8-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1 +// CHECK8-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]] +// CHECK8-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP33]], [[MUL41]] +// CHECK8-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 +// CHECK8-NEXT: [[TMP37:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK8-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint i32* [[TMP36]] to i64 +// CHECK8-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint i32* [[TMP37]] to i64 +// CHECK8-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]] +// CHECK8-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4 +// CHECK8-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1 +// CHECK8-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1 +// CHECK8-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1 +// CHECK8-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]] +// CHECK8-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]] +// CHECK8-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP32]], [[MUL51]] +// CHECK8-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1 +// CHECK8-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, i32* [[TMP31]], i64 [[MUL53]] +// CHECK8-NEXT: store i32* [[ADD_PTR54]], i32** [[__BEGIN220]], align 8 +// CHECK8-NEXT: [[TMP38:%.*]] = load i32*, i32** [[__BEGIN119]], align 8 +// CHECK8-NEXT: store i32* [[TMP38]], i32** [[A]], align 8 +// CHECK8-NEXT: [[TMP39:%.*]] = load i32*, i32** [[__BEGIN220]], align 8 +// CHECK8-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP39]], align 4 +// CHECK8-NEXT: store i32 [[TMP40]], i32* [[B]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = load i32, i32* [[B]], align 4 +// CHECK8-NEXT: [[TMP42:%.*]] = load i32*, i32** [[A]], align 8 +// CHECK8-NEXT: store i32 [[TMP41]], i32* [[TMP42]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP43:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP43]], 1 +// CHECK8-NEXT: store i64 [[ADD55]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP45]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: // CHECK8-NEXT: ret void -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK8-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z17with_var_schedulev -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[A1:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store double 5.000000e+00, double* [[A]], align 8, !dbg [[DBG9:![0-9]+]] -// CHECK9-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8, !dbg [[DBG10:![0-9]+]] -// CHECK9-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8, !dbg [[DBG10]] -// CHECK9-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11:![0-9]+]] -// CHECK9-NEXT: store i64 1, i64* [[I]], align 8, !dbg [[DBG12:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG13:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG14:![0-9]+]] -// CHECK9-NEXT: [[CONV2:%.*]] = uitofp i64 [[TMP1]] to double, !dbg [[DBG14]] -// CHECK9-NEXT: [[TMP2:%.*]] = load double, double* [[A1]], align 8, !dbg [[DBG15:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP2]], !dbg [[DBG16:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = fcmp olt double [[CONV2]], [[ADD]], !dbg [[DBG17:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG18:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG19:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG20:![0-9]+]] -// CHECK9-NEXT: [[INC:%.*]] = add i64 [[TMP3]], 1, !dbg [[DBG20]] -// CHECK9-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG20]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG18]], !llvm.loop [[LOOP21:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG23:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG24:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 33, i32* [[I]], align 4, !dbg [[DBG25:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG26:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000, !dbg [[DBG28:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG29:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG30:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG31:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64, !dbg [[DBG30]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]], !dbg [[DBG30]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG30]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG32:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG33:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64, !dbg [[DBG32]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]], !dbg [[DBG32]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG32]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG34:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG35:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG35]] -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]], !dbg [[DBG35]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG35]] -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG37:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG38:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG39:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG38]] -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]], !dbg [[DBG38]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !dbg [[DBG40:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG41:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG42:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7, !dbg [[DBG42]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG42]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG29]], !llvm.loop [[LOOP43:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG44:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG45:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 32000000, i32* [[I]], align 4, !dbg [[DBG46:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG47:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG48:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33, !dbg [[DBG49:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG50:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG51:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG52:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64, !dbg [[DBG51]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]], !dbg [[DBG51]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG51]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG53:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG54:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64, !dbg [[DBG53]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]], !dbg [[DBG53]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG53]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG55:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG56:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG57:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG56]] -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]], !dbg [[DBG56]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG56]] -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG58:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG59:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG60:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG59]] -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]], !dbg [[DBG59]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !dbg [[DBG61:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG62:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG63:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7, !dbg [[DBG63]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG63]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG50]], !llvm.loop [[LOOP64:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG65:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG66:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 131071, i32* [[I]], align 4, !dbg [[DBG67:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG68:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG69:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647, !dbg [[DBG70:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG71:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG72:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG73:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64, !dbg [[DBG72]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]], !dbg [[DBG72]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG72]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG74:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG75:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64, !dbg [[DBG74]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]], !dbg [[DBG74]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG74]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG76:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG77:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG78:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64, !dbg [[DBG77]] -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]], !dbg [[DBG77]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG77]] -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG79:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG80:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG81:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64, !dbg [[DBG80]] -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]], !dbg [[DBG80]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !dbg [[DBG82:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG83:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG84:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127, !dbg [[DBG84]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG84]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG71]], !llvm.loop [[LOOP85:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG86:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG87:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i64 131071, i64* [[I]], align 8, !dbg [[DBG88:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG89:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG90:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647, !dbg [[DBG91:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG92:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG93:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG94:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]], !dbg [[DBG93]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG93]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG95:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG96:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]], !dbg [[DBG95]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !dbg [[DBG95]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG97:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG98:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG99:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]], !dbg [[DBG98]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG98]] -// CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG100:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG101:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG102:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]], !dbg [[DBG101]] -// CHECK9-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4, !dbg [[DBG103:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG104:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG105:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127, !dbg [[DBG105]] -// CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !dbg [[DBG105]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP106:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG107:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG108:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i64 131071, i64* [[I]], align 8, !dbg [[DBG109:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG110:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG111:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647, !dbg [[DBG112:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG113:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG114:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG115:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]], !dbg [[DBG114]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG114]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG116:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG117:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]], !dbg [[DBG116]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !dbg [[DBG116]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG118:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG119:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG120:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]], !dbg [[DBG119]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG119]] -// CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG121:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG122:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG123:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]], !dbg [[DBG122]] -// CHECK9-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4, !dbg [[DBG124:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG125:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG126:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127, !dbg [[DBG126]] -// CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !dbg [[DBG126]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG113]], !llvm.loop [[LOOP127:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG128:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG129:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[Y:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG130:![0-9]+]] -// CHECK9-NEXT: store i32 0, i32* [[Y]], align 4, !dbg [[DBG131:![0-9]+]] -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4, !dbg [[DBG132:![0-9]+]] -// CHECK9-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8, !dbg [[DBG132]] -// CHECK9-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !dbg [[DBG133:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG134:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG135:![0-9]+]] -// CHECK9-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32, !dbg [[DBG135]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57, !dbg [[DBG136:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]], !dbg [[DBG137:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: store i32 11, i32* [[X]], align 4, !dbg [[DBG138:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND2:%.*]], !dbg [[DBG139:![0-9]+]] -// CHECK9: for.cond2: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG140:![0-9]+]] -// CHECK9-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0, !dbg [[DBG141:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]], !dbg [[DBG142:![0-9]+]] -// CHECK9: for.body4: -// CHECK9-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG143:![0-9]+]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG144:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG143]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]], !dbg [[DBG143]] -// CHECK9-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG143]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG145:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG146:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64, !dbg [[DBG145]] -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]], !dbg [[DBG145]] -// CHECK9-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG145]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]], !dbg [[DBG147:![0-9]+]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG148:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG149:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64, !dbg [[DBG148]] -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]], !dbg [[DBG148]] -// CHECK9-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4, !dbg [[DBG148]] -// CHECK9-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]], !dbg [[DBG150:![0-9]+]] -// CHECK9-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG151:![0-9]+]] -// CHECK9-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG152:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64, !dbg [[DBG151]] -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]], !dbg [[DBG151]] -// CHECK9-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4, !dbg [[DBG153:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG154:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG155:![0-9]+]] -// CHECK9-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1, !dbg [[DBG155]] -// CHECK9-NEXT: store i32 [[DEC]], i32* [[X]], align 4, !dbg [[DBG155]] -// CHECK9-NEXT: br label [[FOR_COND2]], !dbg [[DBG142]], !llvm.loop [[LOOP156:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: br label [[FOR_INC12:%.*]], !dbg [[DBG154]] -// CHECK9: for.inc12: -// CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG157:![0-9]+]] -// CHECK9-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1, !dbg [[DBG157]] -// CHECK9-NEXT: store i8 [[INC]], i8* [[I]], align 1, !dbg [[DBG157]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG137]], !llvm.loop [[LOOP158:![0-9]+]] -// CHECK9: for.end13: -// CHECK9-NEXT: ret void, !dbg [[DBG159:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG160:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG161:![0-9]+]] -// CHECK9-NEXT: store i8 48, i8* [[I]], align 1, !dbg [[DBG162:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG163:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG164:![0-9]+]] -// CHECK9-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32, !dbg [[DBG164]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57, !dbg [[DBG165:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]], !dbg [[DBG166:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: store i32 -10, i32* [[X]], align 4, !dbg [[DBG167:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND1:%.*]], !dbg [[DBG168:![0-9]+]] -// CHECK9: for.cond1: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG169:![0-9]+]] -// CHECK9-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10, !dbg [[DBG170:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]], !dbg [[DBG171:![0-9]+]] -// CHECK9: for.body3: -// CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG172:![0-9]+]] -// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG173:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64, !dbg [[DBG172]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]], !dbg [[DBG172]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG172]] -// CHECK9-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG174:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG175:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64, !dbg [[DBG174]] -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]], !dbg [[DBG174]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !dbg [[DBG174]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]], !dbg [[DBG176:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG177:![0-9]+]] -// CHECK9-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG178:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64, !dbg [[DBG177]] -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]], !dbg [[DBG177]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !dbg [[DBG177]] -// CHECK9-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]], !dbg [[DBG179:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG180:![0-9]+]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG181:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64, !dbg [[DBG180]] -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]], !dbg [[DBG180]] -// CHECK9-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !dbg [[DBG182:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG183:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG184:![0-9]+]] -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1, !dbg [[DBG184]] -// CHECK9-NEXT: store i32 [[INC]], i32* [[X]], align 4, !dbg [[DBG184]] -// CHECK9-NEXT: br label [[FOR_COND1]], !dbg [[DBG171]], !llvm.loop [[LOOP185:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: br label [[FOR_INC11:%.*]], !dbg [[DBG183]] -// CHECK9: for.inc11: -// CHECK9-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG186:![0-9]+]] -// CHECK9-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1, !dbg [[DBG186]] -// CHECK9-NEXT: store i8 [[INC12]], i8* [[I]], align 1, !dbg [[DBG186]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG166]], !llvm.loop [[LOOP187:![0-9]+]] -// CHECK9: for.end13: -// CHECK9-NEXT: ret void, !dbg [[DBG188:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z3foov -// CHECK9-SAME: () #[[ATTR1:[0-9]+]] !dbg [[DBG189:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG190:![0-9]+]] -// CHECK9-NEXT: ret i32 0, !dbg [[DBG191:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK9-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG192:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SAVED_STACK1:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG193:![0-9]+]] -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG194:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG194]] -// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG194]] -// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG194]] -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG194]] -// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG195:![0-9]+]] -// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK1]], align 8, !dbg [[DBG195]] -// CHECK9-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG195]] -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8, !dbg [[DBG195]] -// CHECK9-NEXT: store i32 131071, i32* [[I]], align 4, !dbg [[DBG196:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG197:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG198:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP4]], 2147483647, !dbg [[DBG199:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG200:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG201:![0-9]+]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG201]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG202:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64, !dbg [[DBG203:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 [[IDXPROM]], !dbg [[DBG203]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG203]] -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[CONV]], [[TMP6]], !dbg [[DBG204:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] -// CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP7]] to float, !dbg [[DBG205]] -// CHECK9-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]], !dbg [[DBG206:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG207:![0-9]+]] -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG208:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM5:%.*]] = zext i32 [[TMP9]] to i64, !dbg [[DBG207]] -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM5]], !dbg [[DBG207]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG209:![0-9]+]] -// CHECK9-NEXT: [[ADD7:%.*]] = fadd float [[TMP10]], [[ADD4]], !dbg [[DBG209]] -// CHECK9-NEXT: store float [[ADD7]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG209]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG207]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG210:![0-9]+]] -// CHECK9-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 127, !dbg [[DBG210]] -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[I]], align 4, !dbg [[DBG210]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG200]], !llvm.loop [[LOOP211:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK1]], align 8, !dbg [[DBG205]] -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]), !dbg [[DBG205]] -// CHECK9-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG212:![0-9]+]] -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]), !dbg [[DBG212]] -// CHECK9-NEXT: ret void, !dbg [[DBG212]] -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null, !dbg [[DBG201]] -// CHECK9-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0, !dbg [[DBG201]] -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]], !dbg [[DBG201]] -// CHECK9-NEXT: unreachable, !dbg [[DBG201]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK9-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK9-NEXT: unreachable -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z17with_var_schedulev -// CHECK10-SAME: () local_unnamed_addr #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: br label [[FOR_BODY:%.*]] -// CHECK10: for.cond.cleanup: -// CHECK10-NEXT: ret void -// CHECK10: for.body: -// CHECK10-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 33, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP2]] -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 7 -// CHECK10-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 31999993 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP6:![0-9]+]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: br label [[FOR_BODY:%.*]] -// CHECK10: for.cond.cleanup: -// CHECK10-NEXT: ret void -// CHECK10: for.body: -// CHECK10-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 32000000, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP2]] -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -7 -// CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[INDVARS_IV]], 40 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP9:![0-9]+]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARRAYIDX_0:%.*]] = getelementptr inbounds float, float* [[B]], i64 131071 -// CHECK10-NEXT: [[ARRAYIDX2_0:%.*]] = getelementptr inbounds float, float* [[C]], i64 131071 -// CHECK10-NEXT: [[ARRAYIDX4_0:%.*]] = getelementptr inbounds float, float* [[D]], i64 131071 -// CHECK10-NEXT: [[ARRAYIDX7_0:%.*]] = getelementptr inbounds float, float* [[A]], i64 131071 -// CHECK10-NEXT: [[INDVARS_IV_NEXT_0:%.*]] = add nuw nsw i64 131071, 127 -// CHECK10-NEXT: br label [[FOR_BODY:%.*]] -// CHECK10: for.cond.cleanup: -// CHECK10-NEXT: ret void -// CHECK10: for.body: -// CHECK10-NEXT: [[INDVARS_IV_NEXT_PHI:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_0]], [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE:%.*]] ] -// CHECK10-NEXT: [[ARRAYIDX7_PHI:%.*]] = phi float* [ [[ARRAYIDX7_0]], [[ENTRY]] ], [ [[ARRAYIDX7_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] -// CHECK10-NEXT: [[ARRAYIDX4_PHI:%.*]] = phi float* [ [[ARRAYIDX4_0]], [[ENTRY]] ], [ [[ARRAYIDX4_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] -// CHECK10-NEXT: [[ARRAYIDX2_PHI:%.*]] = phi float* [ [[ARRAYIDX2_0]], [[ENTRY]] ], [ [[ARRAYIDX2_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] -// CHECK10-NEXT: [[ARRAYIDX_PHI:%.*]] = phi float* [ [[ARRAYIDX_0]], [[ENTRY]] ], [ [[ARRAYIDX_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX_PHI]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX2_PHI]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] -// CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX4_PHI]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP2]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7_PHI]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[TMP3:%.*]] = trunc i64 [[INDVARS_IV_NEXT_PHI]] to i32 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], -1 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK10: for.body.for.body_crit_edge: -// CHECK10-NEXT: [[ARRAYIDX_1]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV_NEXT_PHI]] -// CHECK10-NEXT: [[ARRAYIDX2_1]] = getelementptr inbounds float, float* [[C]], i64 [[INDVARS_IV_NEXT_PHI]] -// CHECK10-NEXT: [[ARRAYIDX4_1]] = getelementptr inbounds float, float* [[D]], i64 [[INDVARS_IV_NEXT_PHI]] -// CHECK10-NEXT: [[ARRAYIDX7_1]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV_NEXT_PHI]] -// CHECK10-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV_NEXT_PHI]], 127 -// CHECK10-NEXT: br label [[FOR_BODY]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: br label [[FOR_BODY:%.*]] -// CHECK10: for.cond.cleanup: -// CHECK10-NEXT: ret void -// CHECK10: for.body: -// CHECK10-NEXT: [[I_011:%.*]] = phi i64 [ 131071, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[FOR_BODY]] ] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[I_011]] -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[I_011]] -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[I_011]] -// CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP2]] -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[I_011]] -// CHECK10-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[ADD]] = add nuw nsw i64 [[I_011]], 127 -// CHECK10-NEXT: [[CMP:%.*]] = icmp ult i64 [[I_011]], 2147483520 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP11:![0-9]+]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: br label [[FOR_BODY:%.*]] -// CHECK10: for.cond.cleanup: -// CHECK10-NEXT: ret void -// CHECK10: for.body: -// CHECK10-NEXT: [[I_011:%.*]] = phi i64 [ 131071, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[FOR_BODY]] ] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[I_011]] -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[I_011]] -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[I_011]] -// CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP2]] -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[I_011]] -// CHECK10-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[ADD]] = add nuw nsw i64 [[I_011]], 127 -// CHECK10-NEXT: [[CMP:%.*]] = icmp ult i64 [[I_011]], 2147483520 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP12:![0-9]+]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: br label [[FOR_COND2_PREHEADER:%.*]] -// CHECK10: for.cond2.preheader: -// CHECK10-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC12:%.*]] ] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[DEC_0:%.*]] = add nsw i32 11, -1 -// CHECK10-NEXT: br label [[FOR_BODY4:%.*]] -// CHECK10: for.cond.cleanup: -// CHECK10-NEXT: ret void -// CHECK10: for.body4: -// CHECK10-NEXT: [[DEC_PHI:%.*]] = phi i32 [ [[DEC_0]], [[FOR_COND2_PREHEADER]] ], [ [[DEC_1:%.*]], [[FOR_BODY4_FOR_BODY4_CRIT_EDGE:%.*]] ] -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] -// CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX8]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP2]] -// CHECK10-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[CMP3_NOT:%.*]] = icmp eq i32 [[DEC_PHI]], 0 -// CHECK10-NEXT: br i1 [[CMP3_NOT]], label [[FOR_INC12]], label [[FOR_BODY4_FOR_BODY4_CRIT_EDGE]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK10: for.body4.for.body4_crit_edge: -// CHECK10-NEXT: [[DEC_1]] = add nsw i32 [[DEC_PHI]], -1 -// CHECK10-NEXT: br label [[FOR_BODY4]] -// CHECK10: for.inc12: -// CHECK10-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 -// CHECK10-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 58 -// CHECK10-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND2_PREHEADER]], !llvm.loop [[LOOP14:![0-9]+]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: br label [[FOR_COND1_PREHEADER:%.*]] -// CHECK10: for.cond1.preheader: -// CHECK10-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 48, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC11:%.*]] ] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV]] -// CHECK10-NEXT: [[INC_0:%.*]] = add nsw i32 -10, 1 -// CHECK10-NEXT: br label [[FOR_BODY3:%.*]] -// CHECK10: for.cond.cleanup: -// CHECK10-NEXT: ret void -// CHECK10: for.body3: -// CHECK10-NEXT: [[INC_PHI:%.*]] = phi i32 [ [[INC_0]], [[FOR_COND1_PREHEADER]] ], [ [[INC_1:%.*]], [[FOR_BODY3_FOR_BODY3_CRIT_EDGE:%.*]] ] -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] -// CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP2]] -// CHECK10-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_PHI]], 10 -// CHECK10-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_INC11]], label [[FOR_BODY3_FOR_BODY3_CRIT_EDGE]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK10: for.body3.for.body3_crit_edge: -// CHECK10-NEXT: [[INC_1]] = add nsw i32 [[INC_PHI]], 1 -// CHECK10-NEXT: br label [[FOR_BODY3]] -// CHECK10: for.inc11: -// CHECK10-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 -// CHECK10-NEXT: [[EXITCOND23_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 58 -// CHECK10-NEXT: br i1 [[EXITCOND23_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP16:![0-9]+]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z3foov -// CHECK10-SAME: () local_unnamed_addr #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_Z8mayThrowv() #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK10-SAME: (float* nocapture [[A:%.*]], i32 [[N:%.*]]) local_unnamed_addr #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 -// CHECK10-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP0]], align 16 -// CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[N]] to float -// CHECK10-NEXT: [[ARRAYIDX_0:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 131071 -// CHECK10-NEXT: [[ARRAYIDX6_0:%.*]] = getelementptr inbounds float, float* [[A]], i64 131071 -// CHECK10-NEXT: [[INDVARS_IV_NEXT_0:%.*]] = add nuw nsw i64 131071, 127 -// CHECK10-NEXT: br label [[FOR_BODY:%.*]] -// CHECK10: for.cond.cleanup: -// CHECK10-NEXT: ret void -// CHECK10: for.body: -// CHECK10-NEXT: [[INDVARS_IV_NEXT_PHI:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_0]], [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE:%.*]] ] -// CHECK10-NEXT: [[ARRAYIDX6_PHI:%.*]] = phi float* [ [[ARRAYIDX6_0]], [[ENTRY]] ], [ [[ARRAYIDX6_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] -// CHECK10-NEXT: [[ARRAYIDX_PHI:%.*]] = phi float* [ [[ARRAYIDX_0]], [[ENTRY]] ], [ [[ARRAYIDX_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] -// CHECK10-NEXT: call void @_Z8mayThrowv() #[[ATTR4]] -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX_PHI]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], 0.000000e+00 -// CHECK10-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]] -// CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX6_PHI]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[ADD7:%.*]] = fadd float [[TMP2]], [[ADD4]] -// CHECK10-NEXT: store float [[ADD7]], float* [[ARRAYIDX6_PHI]], align 4, !tbaa [[TBAA2]] -// CHECK10-NEXT: [[TMP3:%.*]] = trunc i64 [[INDVARS_IV_NEXT_PHI]] to i32 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], -1 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK10: for.body.for.body_crit_edge: -// CHECK10-NEXT: [[ARRAYIDX_1]] = getelementptr inbounds float, float* [[VLA2]], i64 [[INDVARS_IV_NEXT_PHI]] -// CHECK10-NEXT: [[ARRAYIDX6_1]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV_NEXT_PHI]] -// CHECK10-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV_NEXT_PHI]], 127 -// CHECK10-NEXT: br label [[FOR_BODY]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z9incrementv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 5, [[MUL]] -// CHECK11-NEXT: store i32 [[SUB]], i32* [[J]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z16range_for_singlev -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK11-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK11-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[__BEGIN15:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 -// CHECK11-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 -// CHECK11-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK11-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK11-NEXT: store i32* [[ARRAYDECAY1]], i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK11-NEXT: store i32* [[TMP3]], i32** [[DOTCAPTURE_EXPR_2]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP4]] to i64 -// CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP5]] to i64 -// CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] -// CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 -// CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1 -// CHECK11-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK11-NEXT: store i32* [[TMP6]], i32** [[__BEGIN1]], align 8 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 -// CHECK11-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP7]], [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP20]], 1 -// CHECK11-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[MUL]] -// CHECK11-NEXT: store i32* [[ADD_PTR8]], i32** [[__BEGIN15]], align 8 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[__BEGIN15]], align 8 -// CHECK11-NEXT: store i32* [[TMP21]], i32** [[A]], align 8 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP23]], 1 -// CHECK11-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv -// CHECK11-SAME: () #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK11-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK11-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 -// CHECK11-NEXT: [[__END2:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[__BEGIN119:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[__BEGIN220:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 -// CHECK11-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 -// CHECK11-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK11-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE2]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK11-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK11-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY2]], i64 10 -// CHECK11-NEXT: store i32* [[ADD_PTR3]], i32** [[__END2]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK11-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 -// CHECK11-NEXT: store i32* [[ARRAYDECAY4]], i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK11-NEXT: store i32* [[TMP4]], i32** [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: [[TMP5:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK11-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP5]], i64 0, i64 0 -// CHECK11-NEXT: store i32* [[ARRAYDECAY7]], i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[__END2]], align 8 -// CHECK11-NEXT: store i32* [[TMP6]], i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP7]] to i64 -// CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP8]] to i64 -// CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] -// CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK11-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint i32* [[TMP9]] to i64 -// CHECK11-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint i32* [[TMP10]] to i64 -// CHECK11-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]] -// CHECK11-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4 -// CHECK11-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1 -// CHECK11-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1 -// CHECK11-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]] -// CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_9]], align 8 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK11-NEXT: store i32* [[TMP11]], i32** [[__BEGIN1]], align 8 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK11-NEXT: store i32* [[TMP12]], i32** [[__BEGIN2]], align 8 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP13]], [[TMP14]] -// CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: land.lhs.true: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK11-NEXT: [[CMP18:%.*]] = icmp ult i32* [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 -// CHECK11-NEXT: store i64 [[TMP17]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 -// CHECK11-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]] -// CHECK11-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: store i64 [[TMP24]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] -// CHECK11-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK11-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint i32* [[TMP29]] to i64 -// CHECK11-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint i32* [[TMP30]] to i64 -// CHECK11-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]] -// CHECK11-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4 -// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1 -// CHECK11-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1 -// CHECK11-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1 -// CHECK11-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]] -// CHECK11-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP28]], [[MUL30]] -// CHECK11-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1 -// CHECK11-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[MUL32]] -// CHECK11-NEXT: store i32* [[ADD_PTR33]], i32** [[__BEGIN119]], align 8 -// CHECK11-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK11-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK11-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK11-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint i32* [[TMP34]] to i64 -// CHECK11-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint i32* [[TMP35]] to i64 -// CHECK11-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]] -// CHECK11-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4 -// CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1 -// CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1 -// CHECK11-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1 -// CHECK11-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]] -// CHECK11-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP33]], [[MUL41]] -// CHECK11-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK11-NEXT: [[TMP37:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK11-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint i32* [[TMP36]] to i64 -// CHECK11-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint i32* [[TMP37]] to i64 -// CHECK11-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]] -// CHECK11-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4 -// CHECK11-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1 -// CHECK11-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1 -// CHECK11-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1 -// CHECK11-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]] -// CHECK11-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]] -// CHECK11-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP32]], [[MUL51]] -// CHECK11-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1 -// CHECK11-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, i32* [[TMP31]], i64 [[MUL53]] -// CHECK11-NEXT: store i32* [[ADD_PTR54]], i32** [[__BEGIN220]], align 8 -// CHECK11-NEXT: [[TMP38:%.*]] = load i32*, i32** [[__BEGIN119]], align 8 -// CHECK11-NEXT: store i32* [[TMP38]], i32** [[A]], align 8 -// CHECK11-NEXT: [[TMP39:%.*]] = load i32*, i32** [[__BEGIN220]], align 8 -// CHECK11-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP39]], align 4 -// CHECK11-NEXT: store i32 [[TMP40]], i32* [[B]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[B]], align 4 -// CHECK11-NEXT: [[TMP42:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK11-NEXT: store i32 [[TMP41]], i32* [[TMP42]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP43:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP43]], 1 -// CHECK11-NEXT: store i64 [[ADD55]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP45]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z9incrementv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 5, [[MUL]] -// CHECK12-NEXT: store i32 [[SUB]], i32* [[J]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z16range_for_singlev -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK12-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK12-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[__BEGIN15:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK12-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 -// CHECK12-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK12-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 -// CHECK12-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK12-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK12-NEXT: store i32* [[ARRAYDECAY1]], i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK12-NEXT: store i32* [[TMP3]], i32** [[DOTCAPTURE_EXPR_2]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK12-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP4]] to i64 -// CHECK12-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP5]] to i64 -// CHECK12-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] -// CHECK12-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 -// CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1 -// CHECK12-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK12-NEXT: store i32* [[TMP6]], i32** [[__BEGIN1]], align 8 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 -// CHECK12-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP7]], [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP20]], 1 -// CHECK12-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[MUL]] -// CHECK12-NEXT: store i32* [[ADD_PTR8]], i32** [[__BEGIN15]], align 8 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[__BEGIN15]], align 8 -// CHECK12-NEXT: store i32* [[TMP21]], i32** [[A]], align 8 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP23]], 1 -// CHECK12-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv -// CHECK12-SAME: () #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK12-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK12-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 -// CHECK12-NEXT: [[__END2:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[__BEGIN119:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[__BEGIN220:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK12-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 -// CHECK12-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK12-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 -// CHECK12-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK12-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE2]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK12-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK12-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY2]], i64 10 -// CHECK12-NEXT: store i32* [[ADD_PTR3]], i32** [[__END2]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK12-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 -// CHECK12-NEXT: store i32* [[ARRAYDECAY4]], i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK12-NEXT: store i32* [[TMP4]], i32** [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK12-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP5]], i64 0, i64 0 -// CHECK12-NEXT: store i32* [[ARRAYDECAY7]], i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[__END2]], align 8 -// CHECK12-NEXT: store i32* [[TMP6]], i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK12-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP7]] to i64 -// CHECK12-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP8]] to i64 -// CHECK12-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] -// CHECK12-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK12-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint i32* [[TMP9]] to i64 -// CHECK12-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint i32* [[TMP10]] to i64 -// CHECK12-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]] -// CHECK12-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4 -// CHECK12-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1 -// CHECK12-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1 -// CHECK12-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]] -// CHECK12-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_9]], align 8 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK12-NEXT: store i32* [[TMP11]], i32** [[__BEGIN1]], align 8 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK12-NEXT: store i32* [[TMP12]], i32** [[__BEGIN2]], align 8 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP13]], [[TMP14]] -// CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: land.lhs.true: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK12-NEXT: [[CMP18:%.*]] = icmp ult i32* [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 -// CHECK12-NEXT: store i64 [[TMP17]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 -// CHECK12-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]] -// CHECK12-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: store i64 [[TMP24]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] -// CHECK12-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 -// CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK12-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint i32* [[TMP29]] to i64 -// CHECK12-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint i32* [[TMP30]] to i64 -// CHECK12-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]] -// CHECK12-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4 -// CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1 -// CHECK12-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1 -// CHECK12-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1 -// CHECK12-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]] -// CHECK12-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP28]], [[MUL30]] -// CHECK12-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1 -// CHECK12-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[MUL32]] -// CHECK12-NEXT: store i32* [[ADD_PTR33]], i32** [[__BEGIN119]], align 8 -// CHECK12-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK12-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK12-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK12-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint i32* [[TMP34]] to i64 -// CHECK12-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint i32* [[TMP35]] to i64 -// CHECK12-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]] -// CHECK12-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4 -// CHECK12-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1 -// CHECK12-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1 -// CHECK12-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1 -// CHECK12-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]] -// CHECK12-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP33]], [[MUL41]] -// CHECK12-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 -// CHECK12-NEXT: [[TMP37:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK12-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint i32* [[TMP36]] to i64 -// CHECK12-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint i32* [[TMP37]] to i64 -// CHECK12-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]] -// CHECK12-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4 -// CHECK12-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1 -// CHECK12-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1 -// CHECK12-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1 -// CHECK12-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]] -// CHECK12-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]] -// CHECK12-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP32]], [[MUL51]] -// CHECK12-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1 -// CHECK12-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, i32* [[TMP31]], i64 [[MUL53]] -// CHECK12-NEXT: store i32* [[ADD_PTR54]], i32** [[__BEGIN220]], align 8 -// CHECK12-NEXT: [[TMP38:%.*]] = load i32*, i32** [[__BEGIN119]], align 8 -// CHECK12-NEXT: store i32* [[TMP38]], i32** [[A]], align 8 -// CHECK12-NEXT: [[TMP39:%.*]] = load i32*, i32** [[__BEGIN220]], align 8 -// CHECK12-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP39]], align 4 -// CHECK12-NEXT: store i32 [[TMP40]], i32* [[B]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = load i32, i32* [[B]], align 4 -// CHECK12-NEXT: [[TMP42:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK12-NEXT: store i32 [[TMP41]], i32* [[TMP42]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP43:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP43]], 1 -// CHECK12-NEXT: store i64 [[ADD55]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP45]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9incrementv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 5 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 5, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP1]], -1 -// CHECK13-NEXT: store i32 [[DEC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z16range_for_singlev -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK13-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK13-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK13-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK13-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK13-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK13-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 -// CHECK13-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP7]], i32 1 -// CHECK13-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: br label [[FOR_COND]] -// CHECK13: for.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK13-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK13-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 -// CHECK13-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[__END2:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK13-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK13-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK13-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK13-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 -// CHECK13-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END10:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 -// CHECK13-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE2]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP6]], i64 0, i64 0 -// CHECK13-NEXT: store i32* [[ARRAYDECAY2]], i32** [[__BEGIN2]], align 8 -// CHECK13-NEXT: [[TMP7:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP7]], i64 0, i64 0 -// CHECK13-NEXT: [[ADD_PTR4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY3]], i64 10 -// CHECK13-NEXT: store i32* [[ADD_PTR4]], i32** [[__END2]], align 8 -// CHECK13-NEXT: br label [[FOR_COND5:%.*]] -// CHECK13: for.cond5: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[__END2]], align 8 -// CHECK13-NEXT: [[CMP6:%.*]] = icmp ne i32* [[TMP8]], [[TMP9]] -// CHECK13-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: store i32 [[TMP12]], i32* [[TMP13]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP14]], i32 1 -// CHECK13-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN2]], align 8 -// CHECK13-NEXT: br label [[FOR_COND5]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC8:%.*]] -// CHECK13: for.inc8: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[INCDEC_PTR9:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i32 1 -// CHECK13-NEXT: store i32* [[INCDEC_PTR9]], i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: br label [[FOR_COND]] -// CHECK13: for.end10: -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9incrementv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 5 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 5, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP1]], -1 -// CHECK14-NEXT: store i32 [[DEC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z16range_for_singlev -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK14-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK14-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK14-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK14-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK14-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK14-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 -// CHECK14-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP7]], i32 1 -// CHECK14-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: br label [[FOR_COND]] -// CHECK14: for.end: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK14-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK14-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 -// CHECK14-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[__END2:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK14-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK14-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK14-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK14-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 -// CHECK14-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END10:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 -// CHECK14-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE2]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP6]], i64 0, i64 0 -// CHECK14-NEXT: store i32* [[ARRAYDECAY2]], i32** [[__BEGIN2]], align 8 -// CHECK14-NEXT: [[TMP7:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP7]], i64 0, i64 0 -// CHECK14-NEXT: [[ADD_PTR4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY3]], i64 10 -// CHECK14-NEXT: store i32* [[ADD_PTR4]], i32** [[__END2]], align 8 -// CHECK14-NEXT: br label [[FOR_COND5:%.*]] -// CHECK14: for.cond5: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[__END2]], align 8 -// CHECK14-NEXT: [[CMP6:%.*]] = icmp ne i32* [[TMP8]], [[TMP9]] -// CHECK14-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: store i32 [[TMP12]], i32* [[TMP13]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK14-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP14]], i32 1 -// CHECK14-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN2]], align 8 -// CHECK14-NEXT: br label [[FOR_COND5]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC8:%.*]] -// CHECK14: for.inc8: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[INCDEC_PTR9:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i32 1 -// CHECK14-NEXT: store i32* [[INCDEC_PTR9]], i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: br label [[FOR_COND]] -// CHECK14: for.end10: -// CHECK14-NEXT: ret void // diff --git a/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp b/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp --- a/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp +++ b/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -528,91 +528,3 @@ // CHECK2-NEXT: store atomic volatile i8 1, i8* [[TMP5]] unordered, align 1 // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP1]], 5 -// CHECK3-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] -// CHECK3: if.then: -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A]], align 4 -// CHECK3-NEXT: br label [[IF_END]] -// CHECK3: if.end: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP1]], 5 -// CHECK4-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] -// CHECK4: if.then: -// CHECK4-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A]], align 4 -// CHECK4-NEXT: br label [[IF_END]] -// CHECK4: if.end: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret i32 0 -// diff --git a/clang/test/OpenMP/parallel_for_linear_codegen.cpp b/clang/test/OpenMP/parallel_for_linear_codegen.cpp --- a/clang/test/OpenMP/parallel_for_linear_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_linear_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -975,398 +975,3 @@ // CHECK4-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[PVAR:%.*]] = alloca float*, align 8 -// CHECK5-NEXT: [[LVAR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 -// CHECK5-NEXT: store float* [[F]], float** [[PVAR]], align 8 -// CHECK5-NEXT: store i64 0, i64* [[LVAR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[PVAR]], align 8 -// CHECK5-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3 -// CHECK5-NEXT: store float* [[ADD_PTR]], float** [[PVAR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[LVAR]], align 8 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP2]], 3 -// CHECK5-NEXT: store i64 [[ADD]], i64* [[LVAR]], align 8 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3:[0-9]+]] -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP4]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[LVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[LVAR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[PVAR]], align 8 -// CHECK5-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 1 -// CHECK5-NEXT: store i32* [[INCDEC_PTR]], i32** [[PVAR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[LVAR]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[LVAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC1]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[PVAR:%.*]] = alloca float*, align 8 -// CHECK6-NEXT: [[LVAR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 -// CHECK6-NEXT: store float* [[F]], float** [[PVAR]], align 8 -// CHECK6-NEXT: store i64 0, i64* [[LVAR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[PVAR]], align 8 -// CHECK6-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3 -// CHECK6-NEXT: store float* [[ADD_PTR]], float** [[PVAR]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[LVAR]], align 8 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP2]], 3 -// CHECK6-NEXT: store i64 [[ADD]], i64* [[LVAR]], align 8 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3:[0-9]+]] -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP4]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[LVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[LVAR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[PVAR]], align 8 -// CHECK6-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 1 -// CHECK6-NEXT: store i32* [[INCDEC_PTR]], i32** [[PVAR]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[LVAR]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[LVAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC1]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 5 -// CHECK8-NEXT: store i32 [[ADD]], i32* @g, align 4 -// CHECK8-NEXT: store i32 1, i32* @g, align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP2:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP3]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP6:%.*]] = load i8*, i8** [[TMP4]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP7]](i8* [[TMP5]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1082,62 +1082,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG22:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG22]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG23:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG24:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG26:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG27:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG30:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG30]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG30]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG31:![0-9]+]], !llvm.loop [[LOOP32:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG35:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG35]] -// diff --git a/clang/test/OpenMP/parallel_if_codegen.cpp b/clang/test/OpenMP/parallel_if_codegen.cpp --- a/clang/test/OpenMP/parallel_if_codegen.cpp +++ b/clang/test/OpenMP/parallel_if_codegen.cpp @@ -3,18 +3,18 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux -emit-llvm %s -disable-O0-optnone -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux -emit-llvm %s -disable-O0-optnone -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -410,63 +410,341 @@ // CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: call void @_Z9gtid_testv() // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: () #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 +// CHECK3-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) +// CHECK3-NEXT: ret i32 [[CALL]] +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: call void @_Z3fn4v() +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: call void @_Z3fn5v() +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: call void @_Z3fn6v() -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK3-NEXT: ret i32 [[CALL]] +// CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 +// CHECK3-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: call void @_Z3fn1v() +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: call void @_Z3fn2v() +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: call void @_Z3fn3v() -// CHECK3-NEXT: ret i32 0 +// CHECK3-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: call void @_Z9gtid_testv() // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: () #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK4-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 +// CHECK4-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) +// CHECK4-NEXT: ret i32 [[CALL]] +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: call void @_Z3fn4v() +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: call void @_Z3fn5v() +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: call void @_Z3fn6v() -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK4-NEXT: ret i32 [[CALL]] +// CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK4-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 +// CHECK4-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: call void @_Z3fn1v() +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: call void @_Z3fn2v() +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: call void @_Z3fn3v() -// CHECK4-NEXT: ret i32 0 +// CHECK4-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv @@ -638,405 +916,3 @@ // CHECK5-NEXT: call void @_Z3fn3v() // CHECK5-NEXT: ret void // -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: call void @_Z9gtid_testv() -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK6-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] -// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK6: omp_if.then: -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK6: omp_if.else: -// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 -// CHECK6-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] -// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK6-NEXT: br label [[OMP_IF_END]] -// CHECK6: omp_if.end: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: call void @_Z3fn4v() -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: call void @_Z3fn5v() -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: call void @_Z3fn6v() -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK6-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK6-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] -// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK6: omp_if.then: -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK6: omp_if.else: -// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 -// CHECK6-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] -// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK6-NEXT: br label [[OMP_IF_END]] -// CHECK6: omp_if.end: -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: call void @_Z3fn1v() -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: call void @_Z3fn2v() -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: call void @_Z3fn3v() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK7-NEXT: call void @_Z9gtid_testv() -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK7-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] -// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK7: omp_if.then: -// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK7: omp_if.else: -// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 -// CHECK7-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] -// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK7-NEXT: br label [[OMP_IF_END]] -// CHECK7: omp_if.end: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK7-NEXT: call void @_Z3fn4v() -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK7-NEXT: call void @_Z3fn5v() -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK7-NEXT: call void @_Z3fn6v() -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*)) -// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK7-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] -// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK7: omp_if.then: -// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK7: omp_if.else: -// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 -// CHECK7-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] -// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK7-NEXT: br label [[OMP_IF_END]] -// CHECK7: omp_if.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK7-NEXT: call void @_Z3fn1v() -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK7-NEXT: call void @_Z3fn2v() -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK7-NEXT: call void @_Z3fn3v() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_Z9gtid_testv() -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_Z3fn4v() -// CHECK8-NEXT: call void @_Z3fn5v() -// CHECK8-NEXT: call void @_Z3fn6v() -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: call void @_Z3fn1v() -// CHECK8-NEXT: call void @_Z3fn2v() -// CHECK8-NEXT: call void @_Z3fn3v() -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_Z9gtid_testv() -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_Z3fn4v() -// CHECK9-NEXT: call void @_Z3fn5v() -// CHECK9-NEXT: call void @_Z3fn6v() -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK9-NEXT: call void @_Z3fn1v() -// CHECK9-NEXT: call void @_Z3fn2v() -// CHECK9-NEXT: call void @_Z3fn3v() -// CHECK9-NEXT: ret i32 0 -// diff --git a/clang/test/OpenMP/parallel_master_codegen.cpp b/clang/test/OpenMP/parallel_master_codegen.cpp --- a/clang/test/OpenMP/parallel_master_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_codegen.cpp @@ -9,9 +9,9 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void foo() { extern void mayThrow(); mayThrow(); } @@ -27,13 +27,13 @@ #ifdef CK2 ///==========================================================================/// -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void parallel_master_private() { @@ -48,13 +48,13 @@ #ifdef CK3 ///==========================================================================/// -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void parallel_master_private() { @@ -69,13 +69,13 @@ #ifdef CK31 ///==========================================================================/// -// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void parallel_master_default_firstprivate() { @@ -92,13 +92,13 @@ #ifdef CK32 ///==========================================================================/// -// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 +// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" struct St { @@ -132,13 +132,13 @@ #ifdef CK4 ///==========================================================================/// -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void parallel_master_firstprivate() { @@ -153,21 +153,21 @@ #ifdef CK5 ///==========================================================================/// -// RUN: %clang_cc1 -DCK5 -verify -fopenmp -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 +// RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK5 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -DCK5 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple x86_64-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple x86_64-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" int a; @@ -189,13 +189,13 @@ #endif #ifdef CK6 ///==========================================================================/// -// RUN: %clang_cc1 -DCK6 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK33 +// RUN: %clang_cc1 -DCK6 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK6 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK6 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK34 +// RUN: %clang_cc1 -DCK6 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK35 +// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK6 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK6 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK36 +// RUN: %clang_cc1 -DCK6 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void parallel_master_reduction() { @@ -217,13 +217,13 @@ #endif #ifdef CK7 ///==========================================================================/// -// RUN: %clang_cc1 -DCK7 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK37 +// RUN: %clang_cc1 -DCK7 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK7 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK7 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK38 +// RUN: %clang_cc1 -DCK7 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -DCK7 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK39 +// RUN: %clang_cc1 -DCK7 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK7 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK7 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK40 +// RUN: %clang_cc1 -DCK7 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void parallel_master_if() { @@ -236,13 +236,13 @@ #endif #ifdef CK8 ///==========================================================================/// -// RUN: %clang_cc1 -DCK8 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK41 +// RUN: %clang_cc1 -DCK8 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK21 // RUN: %clang_cc1 -DCK8 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK8 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK42 +// RUN: %clang_cc1 -DCK8 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK8 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK43 +// RUN: %clang_cc1 -DCK8 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK8 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK8 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK44 +// RUN: %clang_cc1 -DCK8 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" typedef __INTPTR_TYPE__ intptr_t; @@ -277,13 +277,13 @@ #endif #ifdef CK9 ///==========================================================================/// -// RUN: %clang_cc1 -DCK9 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK45 +// RUN: %clang_cc1 -DCK9 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK23 // RUN: %clang_cc1 -DCK9 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK9 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK46 +// RUN: %clang_cc1 -DCK9 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 -// RUN: %clang_cc1 -DCK9 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK47 +// RUN: %clang_cc1 -DCK9 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK9 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK9 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK48 +// RUN: %clang_cc1 -DCK9 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" typedef void **omp_allocator_handle_t; extern const omp_allocator_handle_t omp_null_allocator; extern const omp_allocator_handle_t omp_default_mem_alloc; @@ -421,90 +421,96 @@ // CHECK2-NEXT: unreachable // // -// CHECK3-LABEL: define {{[^@]+}}@_Z3foov +// CHECK3-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_Z8mayThrowv() +// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK3-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@_Z15parallel_masterv -// CHECK3-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK3-NEXT: store i32 [[INC]], i32* [[A]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: // CHECK3-NEXT: ret void -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4:[0-9]+]] -// CHECK3-NEXT: unreachable // // -// CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK3-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z3foov +// CHECK4-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_Z8mayThrowv() +// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK4-NEXT: ret void // // -// CHECK4-LABEL: define {{[^@]+}}@_Z15parallel_masterv -// CHECK4-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK4-NEXT: store i32 [[INC]], i32* [[A]], align 4 +// CHECK4-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: // CHECK4-NEXT: ret void -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4:[0-9]+]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK4-NEXT: unreachable // // // CHECK5-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[A]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK5-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK5-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK5-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK5: omp_if.then: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK5-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: ret void @@ -514,1699 +520,1217 @@ // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[A]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK6-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK6-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK6-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK6: omp_if.then: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK6-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK6-NEXT: br label [[OMP_IF_END]] // CHECK6: omp_if.end: // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev +// CHECK7-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A1]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[A1]], align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK7-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 +// CHECK7-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A1]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[A1]], align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK8-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 +// CHECK8-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[A]]) +// CHECK9-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK9-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[Y_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[Y_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[A]], i64 [[TMP1]]) +// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[A:%.*]], i64 [[Y:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[Y_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[A]], %struct.St** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[Y]], i64* [[Y_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.St*, %struct.St** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[Y_ADDR]] to i32* // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK9-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK9-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK9: omp_if.then: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK9-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A1]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 +// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[B]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK9-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* @_ZN2St1yE, align 4 +// CHECK9-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK9-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4 // CHECK9-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: // CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev +// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK9-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[A]]) +// CHECK10-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK10-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[Y_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[Y_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[A]], i64 [[TMP1]]) +// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[A:%.*]], i64 [[Y:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[Y_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store %struct.St* [[A]], %struct.St** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[Y]], i64* [[Y_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.St*, %struct.St** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[Y_ADDR]] to i32* // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK10-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK10-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK10: omp_if.then: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK10-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A1]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 +// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP0]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[B]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK10-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* @_ZN2St1yE, align 4 +// CHECK10-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK10-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4 // CHECK10-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK10-NEXT: br label [[OMP_IF_END]] // CHECK10: omp_if.end: // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev +// CHECK10-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK10-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[A]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK11-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK11-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK11-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 +// CHECK11-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[A]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK12-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK12-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK12-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 +// CHECK12-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev +// CHECK13-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @a to i8*), i64 4, i8*** @a.cache.) +// CHECK13-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32* +// CHECK13-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64 +// CHECK13-NEXT: [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @a to i64), [[TMP4]] +// CHECK13-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK13: copyin.not.master: +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* @a, align 4 +// CHECK13-NEXT: store i32 [[TMP6]], i32* [[TMP3]], align 4 +// CHECK13-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK13: copyin.not.master.end: +// CHECK13-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]]) +// CHECK13-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK13-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK13-NEXT: br i1 [[TMP8]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK13: omp_if.then: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @a to i8*), i64 4, i8*** @a.cache.) +// CHECK13-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to i32* +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP10]], align 4 // CHECK13-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK13-NEXT: br label [[OMP_IF_END]] // CHECK13: omp_if.end: // CHECK13-NEXT: ret void // // -// CHECK14-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev +// CHECK14-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv // CHECK14-SAME: () #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @a to i8*), i64 4, i8*** @a.cache.) +// CHECK14-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32* +// CHECK14-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64 +// CHECK14-NEXT: [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @a to i64), [[TMP4]] +// CHECK14-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK14: copyin.not.master: +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* @a, align 4 +// CHECK14-NEXT: store i32 [[TMP6]], i32* [[TMP3]], align 4 +// CHECK14-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK14: copyin.not.master.end: +// CHECK14-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]]) +// CHECK14-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK14-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK14-NEXT: br i1 [[TMP8]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK14: omp_if.then: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @a to i8*), i64 4, i8*** @a.cache.) +// CHECK14-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to i32* +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP10]], align 4 // CHECK14-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK14-NEXT: br label [[OMP_IF_END]] // CHECK14: omp_if.end: // CHECK14-NEXT: ret void // // -// CHECK15-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev +// CHECK15-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[A]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @a) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK15-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK15-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK15-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @a to i64) +// CHECK15-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK15: copyin.not.master: +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* @a, align 4 +// CHECK15-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK15: copyin.not.master.end: +// CHECK15-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK15-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) +// CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]]) +// CHECK15-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK15-NEXT: br i1 [[TMP9]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK15: omp_if.then: +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* @a, align 4 +// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK15-NEXT: store i32 [[INC]], i32* @a, align 4 +// CHECK15-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]]) +// CHECK15-NEXT: br label [[OMP_IF_END]] +// CHECK15: omp_if.end: // CHECK15-NEXT: ret void // // -// CHECK16-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev +// CHECK15-LABEL: define {{[^@]+}}@_ZTW1a +// CHECK15-SAME: () #[[ATTR4:[0-9]+]] comdat { +// CHECK15-NEXT: ret i32* @a +// +// +// CHECK16-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv // CHECK16-SAME: () #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[A]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @a) // CHECK16-NEXT: ret void // // -// CHECK17-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev -// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK17-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[Y_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[Y_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[A]], i64 [[TMP1]]) -// CHECK17-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: ret void +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK16-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK16-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 +// CHECK16-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @a to i64) +// CHECK16-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] +// CHECK16: copyin.not.master: +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* @a, align 4 +// CHECK16-NEXT: br label [[COPYIN_NOT_MASTER_END]] +// CHECK16: copyin.not.master.end: +// CHECK16-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK16-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) +// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]]) +// CHECK16-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK16-NEXT: br i1 [[TMP9]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK16: omp_if.then: +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* @a, align 4 +// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK16-NEXT: store i32 [[INC]], i32* @a, align 4 +// CHECK16-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]]) +// CHECK16-NEXT: br label [[OMP_IF_END]] +// CHECK16: omp_if.end: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZTW1a +// CHECK16-SAME: () #[[ATTR4:[0-9]+]] comdat { +// CHECK16-NEXT: ret i32* @a // // -// CHECK17-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK17-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK17-LABEL: define {{[^@]+}}@_Z25parallel_master_reductionv +// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) +// CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G]]) // CHECK17-NEXT: ret void // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[A:%.*]], i64 [[Y:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[Y_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[A]], %struct.St** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[Y]], i64* [[Y_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.St*, %struct.St** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[Y_ADDR]] to i32* +// CHECK17-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK17-NEXT: store i32 0, i32* [[G1]], align 4 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK17-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK17-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK17: omp_if.then: -// CHECK17-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A1]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 -// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP0]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[B]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK17-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* @_ZN2St1yE, align 4 -// CHECK17-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4 +// CHECK17-NEXT: store i32 1, i32* [[G1]], align 4 // CHECK17-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK17-NEXT: br label [[OMP_IF_END]] // CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i32* [[G1]] to i8* +// CHECK17-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP7]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK17-NEXT: switch i32 [[TMP8]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK17-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK17-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK17-NEXT: ] +// CHECK17: .omp.reduction.case1: +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[G1]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK17-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK17-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK17: .omp.reduction.case2: +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[G1]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP11]] monotonic, align 4 +// CHECK17-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK17: .omp.reduction.default: // CHECK17-NEXT: ret void // // -// CHECK17-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK17-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR3]] -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK17-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK17-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK17-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK17-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK17-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK17-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK17-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK17-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 // CHECK17-NEXT: ret void // // -// CHECK18-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev +// CHECK18-LABEL: define {{[^@]+}}@_Z25parallel_master_reductionv // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK18-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[Y_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[Y_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[A]], i64 [[TMP1]]) -// CHECK18-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK18-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) +// CHECK18-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[A:%.*]], i64 [[Y:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[Y_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[A]], %struct.St** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[Y]], i64* [[Y_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.St*, %struct.St** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[Y_ADDR]] to i32* +// CHECK18-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[G1]], align 4 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK18-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK18-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK18: omp_if.then: -// CHECK18-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A1]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 -// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP0]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[B]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* @_ZN2St1yE, align 4 -// CHECK18-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4 +// CHECK18-NEXT: store i32 1, i32* [[G1]], align 4 // CHECK18-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK18-NEXT: br label [[OMP_IF_END]] // CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i32* [[G1]] to i8* +// CHECK18-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP7]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK18-NEXT: switch i32 [[TMP8]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK18-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK18-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK18-NEXT: ] +// CHECK18: .omp.reduction.case1: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[G1]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK18-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK18-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK18: .omp.reduction.case2: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[G1]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP11]] monotonic, align 4 +// CHECK18-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK18: .omp.reduction.default: // CHECK18-NEXT: ret void // // -// CHECK18-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK18-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR3]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK18-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK18-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK18-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK18-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK18-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK18-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK18-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 // CHECK18-NEXT: ret void // // -// CHECK19-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev +// CHECK19-LABEL: define {{[^@]+}}@_Z18parallel_master_ifv // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK19-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) -// CHECK19-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[A]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A1]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 -// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[A]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[B]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZN2St1yE, align 4 -// CHECK19-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK19-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4 -// CHECK19-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK19-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK19-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK19-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] +// CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK19-NEXT: ret void // // -// CHECK19-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK19-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK19-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK19-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK19-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK19-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK19-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: invoke void @_Z18parallel_master_ifv() +// CHECK19-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK19: invoke.cont: +// CHECK19-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: lpad: +// CHECK19-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK19-NEXT: catch i8* null +// CHECK19-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 +// CHECK19-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 +// CHECK19-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 +// CHECK19-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK19-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK19-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK19: omp_if.end: // CHECK19-NEXT: ret void +// CHECK19: terminate.handler: +// CHECK19-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK19-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR4:[0-9]+]] +// CHECK19-NEXT: unreachable // // -// CHECK19-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK19-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: ret void +// CHECK19-LABEL: define {{[^@]+}}@__clang_call_terminate +// CHECK19-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { +// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] +// CHECK19-NEXT: unreachable // // -// CHECK20-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev +// CHECK20-LABEL: define {{[^@]+}}@_Z18parallel_master_ifv // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK20-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) -// CHECK20-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[A]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A1]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 -// CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[A]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[B]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZN2St1yE, align 4 -// CHECK20-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK20-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4 -// CHECK20-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] +// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK20-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] +// CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK20-NEXT: ret void // // -// CHECK20-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK20-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK20-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK20-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK20-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: invoke void @_Z18parallel_master_ifv() +// CHECK20-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK20: invoke.cont: +// CHECK20-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: lpad: +// CHECK20-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK20-NEXT: catch i8* null +// CHECK20-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 +// CHECK20-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 +// CHECK20-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK20-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK20: omp_if.end: // CHECK20-NEXT: ret void +// CHECK20: terminate.handler: +// CHECK20-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK20-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR4:[0-9]+]] +// CHECK20-NEXT: unreachable // // -// CHECK20-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK20-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR3]] -// CHECK20-NEXT: ret void +// CHECK20-LABEL: define {{[^@]+}}@__clang_call_terminate +// CHECK20-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { +// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] +// CHECK20-NEXT: unreachable // // -// CHECK20-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK20-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK20-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK20-NEXT: ret void +// CHECK21-LABEL: define {{[^@]+}}@main +// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK21-NEXT: entry: +// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK21-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 4) +// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK21-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) +// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK21-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK21-NEXT: ret i32 [[CALL]] // // -// CHECK20-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK20-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: ret void +// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK21-NEXT: entry: +// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK21-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK21-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK21-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK21-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK21-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK21: omp_if.then: +// CHECK21-NEXT: invoke void @_Z3foov() +// CHECK21-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK21: invoke.cont: +// CHECK21-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK21-NEXT: br label [[OMP_IF_END]] +// CHECK21: lpad: +// CHECK21-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK21-NEXT: catch i8* null +// CHECK21-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 +// CHECK21-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 +// CHECK21-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 +// CHECK21-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK21-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK21-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK21: omp_if.end: +// CHECK21-NEXT: ret void +// CHECK21: terminate.handler: +// CHECK21-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK21-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6:[0-9]+]] +// CHECK21-NEXT: unreachable // // -// CHECK21-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK21-LABEL: define {{[^@]+}}@__clang_call_terminate +// CHECK21-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] +// CHECK21-NEXT: call void @_ZSt9terminatev() #[[ATTR6]] +// CHECK21-NEXT: unreachable +// +// +// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK21-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK21-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK21-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK21-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK21-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK21: omp_if.then: +// CHECK21-NEXT: invoke void @_Z3foov() +// CHECK21-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK21: invoke.cont: +// CHECK21-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK21-NEXT: br label [[OMP_IF_END]] +// CHECK21: lpad: +// CHECK21-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK21-NEXT: catch i8* null +// CHECK21-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 +// CHECK21-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 +// CHECK21-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 +// CHECK21-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK21-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK21-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK21: omp_if.end: // CHECK21-NEXT: ret void +// CHECK21: terminate.handler: +// CHECK21-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK21-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] +// CHECK21-NEXT: unreachable // // -// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK21-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK21-NEXT: entry: +// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK21-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2) +// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK21-NEXT: ret i32 0 +// +// +// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK21-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK21-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK21-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK21-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK21: omp_if.then: -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 +// CHECK21-NEXT: invoke void @_Z3foov() +// CHECK21-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK21: invoke.cont: // CHECK21-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK21-NEXT: br label [[OMP_IF_END]] +// CHECK21: lpad: +// CHECK21-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK21-NEXT: catch i8* null +// CHECK21-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 +// CHECK21-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 +// CHECK21-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 +// CHECK21-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK21-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK21-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK21: omp_if.end: // CHECK21-NEXT: ret void +// CHECK21: terminate.handler: +// CHECK21-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK21-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] +// CHECK21-NEXT: unreachable // // -// CHECK22-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev +// CHECK22-LABEL: define {{[^@]+}}@main // CHECK22-SAME: () #[[ATTR0:[0-9]+]] { // CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK22-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK22-NEXT: ret void +// CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK22-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 4) +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK22-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK22-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK22-NEXT: ret i32 [[CALL]] // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK22-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK22-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK22-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK22-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK22: omp_if.then: -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 +// CHECK22-NEXT: invoke void @_Z3foov() +// CHECK22-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK22: invoke.cont: // CHECK22-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK22-NEXT: br label [[OMP_IF_END]] +// CHECK22: lpad: +// CHECK22-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK22-NEXT: catch i8* null +// CHECK22-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 +// CHECK22-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 +// CHECK22-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK22-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK22: omp_if.end: +// CHECK22-NEXT: ret void +// CHECK22: terminate.handler: +// CHECK22-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK22-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6:[0-9]+]] +// CHECK22-NEXT: unreachable +// +// +// CHECK22-LABEL: define {{[^@]+}}@__clang_call_terminate +// CHECK22-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] +// CHECK22-NEXT: call void @_ZSt9terminatev() #[[ATTR6]] +// CHECK22-NEXT: unreachable +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK22-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK22-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK22-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK22: omp_if.then: +// CHECK22-NEXT: invoke void @_Z3foov() +// CHECK22-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK22: invoke.cont: +// CHECK22-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: br label [[OMP_IF_END]] +// CHECK22: lpad: +// CHECK22-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK22-NEXT: catch i8* null +// CHECK22-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 +// CHECK22-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 +// CHECK22-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK22-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK22: omp_if.end: +// CHECK22-NEXT: ret void +// CHECK22: terminate.handler: +// CHECK22-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK22-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] +// CHECK22-NEXT: unreachable +// +// +// CHECK22-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK22-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK22-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2) +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK22-NEXT: ret i32 0 +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK22-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK22-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK22-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK22: omp_if.then: +// CHECK22-NEXT: invoke void @_Z3foov() +// CHECK22-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK22: invoke.cont: +// CHECK22-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: br label [[OMP_IF_END]] +// CHECK22: lpad: +// CHECK22-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK22-NEXT: catch i8* null +// CHECK22-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 +// CHECK22-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 +// CHECK22-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK22-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK22: omp_if.end: // CHECK22-NEXT: ret void +// CHECK22: terminate.handler: +// CHECK22-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK22-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] +// CHECK22-NEXT: unreachable // // -// CHECK23-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev +// CHECK23-LABEL: define {{[^@]+}}@_Z24parallel_master_allocatev // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[MYALLOC:%.*]] = alloca i8**, align 8 +// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK23-NEXT: store i8** null, i8*** [[MYALLOC]], align 8 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[A]], align 4 +// CHECK23-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK23-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i8***)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i8*** [[MYALLOC]]) // CHECK23-NEXT: ret void // // -// CHECK24-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev +// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i8*** nonnull align 8 dereferenceable(8) [[MYALLOC:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK23-NEXT: entry: +// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK23-NEXT: [[MYALLOC_ADDR:%.*]] = alloca i8***, align 8 +// CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK23-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK23-NEXT: store i8*** [[MYALLOC]], i8**** [[MYALLOC_ADDR]], align 8 +// CHECK23-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK23-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[MYALLOC_ADDR]], align 8 +// CHECK23-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK23-NEXT: [[TMP3:%.*]] = load i8**, i8*** [[TMP0]], align 8 +// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i8** [[TMP3]] to i8* +// CHECK23-NEXT: [[DOTA__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP2]], i64 4, i8* [[CONV1]]) +// CHECK23-NEXT: [[DOTA__ADDR:%.*]] = bitcast i8* [[DOTA__VOID_ADDR]] to i32* +// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTA__ADDR]], align 4 +// CHECK23-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK23-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 +// CHECK23-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK23: omp_if.then: +// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTA__ADDR]], align 4 +// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK23-NEXT: store i32 [[INC]], i32* [[DOTA__ADDR]], align 4 +// CHECK23-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK23-NEXT: br label [[OMP_IF_END]] +// CHECK23: omp_if.end: +// CHECK23-NEXT: [[TMP8:%.*]] = bitcast i32* [[DOTA__ADDR]] to i8* +// CHECK23-NEXT: [[TMP9:%.*]] = load i8**, i8*** [[TMP0]], align 8 +// CHECK23-NEXT: [[CONV2:%.*]] = bitcast i8** [[TMP9]] to i8* +// CHECK23-NEXT: call void @__kmpc_free(i32 [[TMP2]], i8* [[TMP8]], i8* [[CONV2]]) +// CHECK23-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@_Z24parallel_master_allocatev // CHECK24-SAME: () #[[ATTR0:[0-9]+]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[MYALLOC:%.*]] = alloca i8**, align 8 +// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: store i8** null, i8*** [[MYALLOC]], align 8 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[A]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK24-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i8***)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i8*** [[MYALLOC]]) // CHECK24-NEXT: ret void // // -// CHECK25-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK25-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @a to i8*), i64 4, i8*** @a.cache.) -// CHECK25-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32* -// CHECK25-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64 -// CHECK25-NEXT: [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @a to i64), [[TMP4]] -// CHECK25-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK25: copyin.not.master: -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* @a, align 4 -// CHECK25-NEXT: store i32 [[TMP6]], i32* [[TMP3]], align 4 -// CHECK25-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK25: copyin.not.master.end: -// CHECK25-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]]) -// CHECK25-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK25-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK25-NEXT: br i1 [[TMP8]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK25: omp_if.then: -// CHECK25-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @a to i8*), i64 4, i8*** @a.cache.) -// CHECK25-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to i32* -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK25-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK25-NEXT: store i32 [[INC]], i32* [[TMP10]], align 4 -// CHECK25-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK25-NEXT: br label [[OMP_IF_END]] -// CHECK25: omp_if.end: -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK26-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @a to i8*), i64 4, i8*** @a.cache.) -// CHECK26-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32* -// CHECK26-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64 -// CHECK26-NEXT: [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @a to i64), [[TMP4]] -// CHECK26-NEXT: br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK26: copyin.not.master: -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* @a, align 4 -// CHECK26-NEXT: store i32 [[TMP6]], i32* [[TMP3]], align 4 -// CHECK26-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK26: copyin.not.master.end: -// CHECK26-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]]) -// CHECK26-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK26-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK26-NEXT: br i1 [[TMP8]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK26: omp_if.then: -// CHECK26-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @a to i8*), i64 4, i8*** @a.cache.) -// CHECK26-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to i32* -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK26-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK26-NEXT: store i32 [[INC]], i32* [[TMP10]], align 4 -// CHECK26-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK26-NEXT: br label [[OMP_IF_END]] -// CHECK26: omp_if.end: -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK27-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK27-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK27-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK28-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK28-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK28-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK29-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @a) -// CHECK29-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK29-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK29-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK29-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK29-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK29-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK29-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK29-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @a to i64) -// CHECK29-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK29: copyin.not.master: -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK29-NEXT: store i32 [[TMP3]], i32* @a, align 4 -// CHECK29-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK29: copyin.not.master.end: -// CHECK29-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK29-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) -// CHECK29-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]]) -// CHECK29-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK29-NEXT: br i1 [[TMP9]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK29: omp_if.then: -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* @a, align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK29-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]]) -// CHECK29-NEXT: br label [[OMP_IF_END]] -// CHECK29: omp_if.end: -// CHECK29-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZTW1a -// CHECK29-SAME: () #[[ATTR4:[0-9]+]] comdat { -// CHECK29-NEXT: ret i32* @a -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK30-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @a) -// CHECK30-NEXT: ret void -// -// -// CHECK30-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK30-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK30-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK30-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK30-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK30-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK30-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK30-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @a to i64) -// CHECK30-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK30: copyin.not.master: -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK30-NEXT: store i32 [[TMP3]], i32* @a, align 4 -// CHECK30-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK30: copyin.not.master.end: -// CHECK30-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK30-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) -// CHECK30-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]]) -// CHECK30-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK30-NEXT: br i1 [[TMP9]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK30: omp_if.then: -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* @a, align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK30-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]]) -// CHECK30-NEXT: br label [[OMP_IF_END]] -// CHECK30: omp_if.end: -// CHECK30-NEXT: ret void -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZTW1a -// CHECK30-SAME: () #[[ATTR4:[0-9]+]] comdat { -// CHECK30-NEXT: ret i32* @a -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK31-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK31-NEXT: ret void -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK32-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK32-NEXT: ret void -// -// -// CHECK33-LABEL: define {{[^@]+}}@_Z25parallel_master_reductionv -// CHECK33-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK33-NEXT: entry: -// CHECK33-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G]]) -// CHECK33-NEXT: ret void -// -// -// CHECK33-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK33-NEXT: entry: -// CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK33-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK33-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK33-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK33-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK33-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK33-NEXT: store i32 0, i32* [[G1]], align 4 -// CHECK33-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK33-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK33-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK33-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK33: omp_if.then: -// CHECK33-NEXT: store i32 1, i32* [[G1]], align 4 -// CHECK33-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK33-NEXT: br label [[OMP_IF_END]] -// CHECK33: omp_if.end: -// CHECK33-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK33-NEXT: [[TMP6:%.*]] = bitcast i32* [[G1]] to i8* -// CHECK33-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 -// CHECK33-NEXT: [[TMP7:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK33-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP7]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK33-NEXT: switch i32 [[TMP8]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK33-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK33-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK33-NEXT: ] -// CHECK33: .omp.reduction.case1: -// CHECK33-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK33-NEXT: [[TMP10:%.*]] = load i32, i32* [[G1]], align 4 -// CHECK33-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK33-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 -// CHECK33-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK33-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK33: .omp.reduction.case2: -// CHECK33-NEXT: [[TMP11:%.*]] = load i32, i32* [[G1]], align 4 -// CHECK33-NEXT: [[TMP12:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP11]] monotonic, align 4 -// CHECK33-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK33: .omp.reduction.default: -// CHECK33-NEXT: ret void -// -// -// CHECK33-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK33-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK33-NEXT: entry: -// CHECK33-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK33-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK33-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK33-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK33-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK33-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK33-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK33-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK33-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK33-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK33-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK33-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK33-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK33-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK33-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK33-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK33-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK33-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK33-NEXT: ret void -// -// -// CHECK34-LABEL: define {{[^@]+}}@_Z25parallel_master_reductionv -// CHECK34-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK34-NEXT: entry: -// CHECK34-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G]]) -// CHECK34-NEXT: ret void -// -// -// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK34-NEXT: entry: -// CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK34-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK34-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK34-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK34-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK34-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK34-NEXT: store i32 0, i32* [[G1]], align 4 -// CHECK34-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK34-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK34-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK34-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK34: omp_if.then: -// CHECK34-NEXT: store i32 1, i32* [[G1]], align 4 -// CHECK34-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK34-NEXT: br label [[OMP_IF_END]] -// CHECK34: omp_if.end: -// CHECK34-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK34-NEXT: [[TMP6:%.*]] = bitcast i32* [[G1]] to i8* -// CHECK34-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 -// CHECK34-NEXT: [[TMP7:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK34-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP7]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK34-NEXT: switch i32 [[TMP8]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK34-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK34-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK34-NEXT: ] -// CHECK34: .omp.reduction.case1: -// CHECK34-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK34-NEXT: [[TMP10:%.*]] = load i32, i32* [[G1]], align 4 -// CHECK34-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK34-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 -// CHECK34-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK34-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK34: .omp.reduction.case2: -// CHECK34-NEXT: [[TMP11:%.*]] = load i32, i32* [[G1]], align 4 -// CHECK34-NEXT: [[TMP12:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP11]] monotonic, align 4 -// CHECK34-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK34: .omp.reduction.default: -// CHECK34-NEXT: ret void -// -// -// CHECK34-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK34-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK34-NEXT: entry: -// CHECK34-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK34-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK34-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK34-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK34-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK34-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK34-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK34-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK34-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK34-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK34-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK34-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK34-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK34-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK34-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK34-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK34-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK34-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK34-NEXT: ret void -// -// -// CHECK35-LABEL: define {{[^@]+}}@_Z25parallel_master_reductionv -// CHECK35-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK35-NEXT: entry: -// CHECK35-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK35-NEXT: ret void -// -// -// CHECK36-LABEL: define {{[^@]+}}@_Z25parallel_master_reductionv -// CHECK36-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK36-NEXT: entry: -// CHECK36-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK36-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK36-NEXT: ret void -// -// -// CHECK37-LABEL: define {{[^@]+}}@_Z18parallel_master_ifv -// CHECK37-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK37-NEXT: entry: -// CHECK37-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK37-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK37-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK37-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK37-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] -// CHECK37-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK37-NEXT: ret void -// -// -// CHECK37-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK37-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK37-NEXT: entry: -// CHECK37-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK37-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK37-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK37-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK37-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK37-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK37-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK37-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK37-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK37-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK37: omp_if.then: -// CHECK37-NEXT: invoke void @_Z18parallel_master_ifv() -// CHECK37-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK37: invoke.cont: -// CHECK37-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK37-NEXT: br label [[OMP_IF_END]] -// CHECK37: lpad: -// CHECK37-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK37-NEXT: catch i8* null -// CHECK37-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK37-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK37-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK37-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK37-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK37-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK37: omp_if.end: -// CHECK37-NEXT: ret void -// CHECK37: terminate.handler: -// CHECK37-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK37-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR4:[0-9]+]] -// CHECK37-NEXT: unreachable -// -// -// CHECK37-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK37-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK37-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2]] -// CHECK37-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK37-NEXT: unreachable -// -// -// CHECK38-LABEL: define {{[^@]+}}@_Z18parallel_master_ifv -// CHECK38-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK38-NEXT: entry: -// CHECK38-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK38-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK38-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK38-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK38-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] -// CHECK38-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK38-NEXT: ret void -// -// -// CHECK38-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK38-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK38-NEXT: entry: -// CHECK38-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK38-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK38-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK38-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK38-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK38-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK38-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK38-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK38-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK38-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK38: omp_if.then: -// CHECK38-NEXT: invoke void @_Z18parallel_master_ifv() -// CHECK38-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK38: invoke.cont: -// CHECK38-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK38-NEXT: br label [[OMP_IF_END]] -// CHECK38: lpad: -// CHECK38-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK38-NEXT: catch i8* null -// CHECK38-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK38-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK38-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK38-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK38-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK38-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK38: omp_if.end: -// CHECK38-NEXT: ret void -// CHECK38: terminate.handler: -// CHECK38-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK38-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR4:[0-9]+]] -// CHECK38-NEXT: unreachable -// -// -// CHECK38-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK38-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK38-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2]] -// CHECK38-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK38-NEXT: unreachable -// -// -// CHECK39-LABEL: define {{[^@]+}}@_Z18parallel_master_ifv -// CHECK39-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK39-NEXT: entry: -// CHECK39-NEXT: invoke void @_Z18parallel_master_ifv() -// CHECK39-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK39: invoke.cont: -// CHECK39-NEXT: ret void -// CHECK39: terminate.lpad: -// CHECK39-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK39-NEXT: catch i8* null -// CHECK39-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK39-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR2:[0-9]+]] -// CHECK39-NEXT: unreachable -// -// -// CHECK39-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK39-SAME: (i8* [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK39-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3:[0-9]+]] -// CHECK39-NEXT: call void @_ZSt9terminatev() #[[ATTR2]] -// CHECK39-NEXT: unreachable -// -// -// CHECK40-LABEL: define {{[^@]+}}@_Z18parallel_master_ifv -// CHECK40-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK40-NEXT: entry: -// CHECK40-NEXT: invoke void @_Z18parallel_master_ifv() -// CHECK40-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK40: invoke.cont: -// CHECK40-NEXT: ret void -// CHECK40: terminate.lpad: -// CHECK40-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK40-NEXT: catch i8* null -// CHECK40-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK40-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR2:[0-9]+]] -// CHECK40-NEXT: unreachable -// -// -// CHECK40-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK40-SAME: (i8* [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK40-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3:[0-9]+]] -// CHECK40-NEXT: call void @_ZSt9terminatev() #[[ATTR2]] -// CHECK40-NEXT: unreachable -// -// -// CHECK41-LABEL: define {{[^@]+}}@main -// CHECK41-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK41-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK41-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK41-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 4) -// CHECK41-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK41-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) -// CHECK41-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK41-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK41-NEXT: ret i32 [[CALL]] -// -// -// CHECK41-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK41-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK41-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK41-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK41-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK41-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK41: omp_if.then: -// CHECK41-NEXT: invoke void @_Z3foov() -// CHECK41-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK41: invoke.cont: -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[OMP_IF_END]] -// CHECK41: lpad: -// CHECK41-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK41-NEXT: catch i8* null -// CHECK41-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK41-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK41-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK41: omp_if.end: -// CHECK41-NEXT: ret void -// CHECK41: terminate.handler: -// CHECK41-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6:[0-9]+]] -// CHECK41-NEXT: unreachable -// -// -// CHECK41-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK41-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK41-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] -// CHECK41-NEXT: call void @_ZSt9terminatev() #[[ATTR6]] -// CHECK41-NEXT: unreachable -// -// -// CHECK41-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK41-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK41-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK41-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK41-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK41-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK41: omp_if.then: -// CHECK41-NEXT: invoke void @_Z3foov() -// CHECK41-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK41: invoke.cont: -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[OMP_IF_END]] -// CHECK41: lpad: -// CHECK41-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK41-NEXT: catch i8* null -// CHECK41-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK41-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK41-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK41: omp_if.end: -// CHECK41-NEXT: ret void -// CHECK41: terminate.handler: -// CHECK41-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] -// CHECK41-NEXT: unreachable -// -// -// CHECK41-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK41-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK41-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2) -// CHECK41-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK41-NEXT: ret i32 0 -// -// -// CHECK41-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK41-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK41-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK41-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK41-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK41-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK41: omp_if.then: -// CHECK41-NEXT: invoke void @_Z3foov() -// CHECK41-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK41: invoke.cont: -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[OMP_IF_END]] -// CHECK41: lpad: -// CHECK41-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK41-NEXT: catch i8* null -// CHECK41-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK41-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK41-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK41: omp_if.end: -// CHECK41-NEXT: ret void -// CHECK41: terminate.handler: -// CHECK41-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] -// CHECK41-NEXT: unreachable -// -// -// CHECK42-LABEL: define {{[^@]+}}@main -// CHECK42-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK42-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK42-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK42-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 4) -// CHECK42-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK42-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) -// CHECK42-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK42-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK42-NEXT: ret i32 [[CALL]] -// -// -// CHECK42-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK42-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK42-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK42-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK42-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK42-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK42: omp_if.then: -// CHECK42-NEXT: invoke void @_Z3foov() -// CHECK42-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK42: invoke.cont: -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[OMP_IF_END]] -// CHECK42: lpad: -// CHECK42-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK42-NEXT: catch i8* null -// CHECK42-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK42-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK42-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK42: omp_if.end: -// CHECK42-NEXT: ret void -// CHECK42: terminate.handler: -// CHECK42-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6:[0-9]+]] -// CHECK42-NEXT: unreachable -// -// -// CHECK42-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK42-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK42-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] -// CHECK42-NEXT: call void @_ZSt9terminatev() #[[ATTR6]] -// CHECK42-NEXT: unreachable -// -// -// CHECK42-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK42-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK42-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK42-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK42-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK42-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK42: omp_if.then: -// CHECK42-NEXT: invoke void @_Z3foov() -// CHECK42-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK42: invoke.cont: -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[OMP_IF_END]] -// CHECK42: lpad: -// CHECK42-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK42-NEXT: catch i8* null -// CHECK42-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK42-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK42-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK42: omp_if.end: -// CHECK42-NEXT: ret void -// CHECK42: terminate.handler: -// CHECK42-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] -// CHECK42-NEXT: unreachable -// -// -// CHECK42-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK42-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK42-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2) -// CHECK42-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK42-NEXT: ret i32 0 -// -// -// CHECK42-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK42-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK42-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK42-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK42-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK42-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK42: omp_if.then: -// CHECK42-NEXT: invoke void @_Z3foov() -// CHECK42-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK42: invoke.cont: -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[OMP_IF_END]] -// CHECK42: lpad: -// CHECK42-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK42-NEXT: catch i8* null -// CHECK42-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK42-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK42-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK42: omp_if.end: -// CHECK42-NEXT: ret void -// CHECK42: terminate.handler: -// CHECK42-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] -// CHECK42-NEXT: unreachable -// -// -// CHECK43-LABEL: define {{[^@]+}}@main -// CHECK43-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK43-NEXT: entry: -// CHECK43-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK43-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK43-NEXT: invoke void @_Z3foov() -// CHECK43-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK43: invoke.cont: -// CHECK43-NEXT: invoke void @_Z3foov() -// CHECK43-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK43: invoke.cont1: -// CHECK43-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK43-NEXT: ret i32 [[CALL]] -// CHECK43: terminate.lpad: -// CHECK43-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK43-NEXT: catch i8* null -// CHECK43-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK43-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4:[0-9]+]] -// CHECK43-NEXT: unreachable -// -// -// CHECK43-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK43-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK43-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK43-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK43-NEXT: unreachable -// -// -// CHECK43-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK43-SAME: () #[[ATTR3:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK43-NEXT: entry: -// CHECK43-NEXT: invoke void @_Z3foov() -// CHECK43-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK43: invoke.cont: -// CHECK43-NEXT: ret i32 0 -// CHECK43: terminate.lpad: -// CHECK43-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK43-NEXT: catch i8* null -// CHECK43-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK43-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4]] -// CHECK43-NEXT: unreachable -// -// -// CHECK44-LABEL: define {{[^@]+}}@main -// CHECK44-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK44-NEXT: entry: -// CHECK44-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK44-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK44-NEXT: invoke void @_Z3foov() -// CHECK44-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK44: invoke.cont: -// CHECK44-NEXT: invoke void @_Z3foov() -// CHECK44-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK44: invoke.cont1: -// CHECK44-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK44-NEXT: ret i32 [[CALL]] -// CHECK44: terminate.lpad: -// CHECK44-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK44-NEXT: catch i8* null -// CHECK44-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK44-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4:[0-9]+]] -// CHECK44-NEXT: unreachable -// -// -// CHECK44-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK44-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK44-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK44-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK44-NEXT: unreachable -// -// -// CHECK44-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK44-SAME: () #[[ATTR3:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK44-NEXT: entry: -// CHECK44-NEXT: invoke void @_Z3foov() -// CHECK44-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK44: invoke.cont: -// CHECK44-NEXT: ret i32 0 -// CHECK44: terminate.lpad: -// CHECK44-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK44-NEXT: catch i8* null -// CHECK44-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK44-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4]] -// CHECK44-NEXT: unreachable -// -// -// CHECK45-LABEL: define {{[^@]+}}@_Z24parallel_master_allocatev -// CHECK45-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK45-NEXT: entry: -// CHECK45-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK45-NEXT: [[MYALLOC:%.*]] = alloca i8**, align 8 -// CHECK45-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK45-NEXT: store i8** null, i8*** [[MYALLOC]], align 8 -// CHECK45-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK45-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK45-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK45-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK45-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i8***)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i8*** [[MYALLOC]]) -// CHECK45-NEXT: ret void -// -// -// CHECK45-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK45-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i8*** nonnull align 8 dereferenceable(8) [[MYALLOC:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK45-NEXT: entry: -// CHECK45-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK45-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK45-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK45-NEXT: [[MYALLOC_ADDR:%.*]] = alloca i8***, align 8 -// CHECK45-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK45-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK45-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK45-NEXT: store i8*** [[MYALLOC]], i8**** [[MYALLOC_ADDR]], align 8 -// CHECK45-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK45-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[MYALLOC_ADDR]], align 8 -// CHECK45-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK45-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK45-NEXT: [[TMP3:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK45-NEXT: [[CONV1:%.*]] = bitcast i8** [[TMP3]] to i8* -// CHECK45-NEXT: [[DOTA__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP2]], i64 4, i8* [[CONV1]]) -// CHECK45-NEXT: [[DOTA__ADDR:%.*]] = bitcast i8* [[DOTA__VOID_ADDR]] to i32* -// CHECK45-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK45-NEXT: store i32 [[TMP4]], i32* [[DOTA__ADDR]], align 4 -// CHECK45-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK45-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 -// CHECK45-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK45: omp_if.then: -// CHECK45-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTA__ADDR]], align 4 -// CHECK45-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK45-NEXT: store i32 [[INC]], i32* [[DOTA__ADDR]], align 4 -// CHECK45-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK45-NEXT: br label [[OMP_IF_END]] -// CHECK45: omp_if.end: -// CHECK45-NEXT: [[TMP8:%.*]] = bitcast i32* [[DOTA__ADDR]] to i8* -// CHECK45-NEXT: [[TMP9:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK45-NEXT: [[CONV2:%.*]] = bitcast i8** [[TMP9]] to i8* -// CHECK45-NEXT: call void @__kmpc_free(i32 [[TMP2]], i8* [[TMP8]], i8* [[CONV2]]) -// CHECK45-NEXT: ret void -// -// -// CHECK46-LABEL: define {{[^@]+}}@_Z24parallel_master_allocatev -// CHECK46-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK46-NEXT: entry: -// CHECK46-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK46-NEXT: [[MYALLOC:%.*]] = alloca i8**, align 8 -// CHECK46-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK46-NEXT: store i8** null, i8*** [[MYALLOC]], align 8 -// CHECK46-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK46-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK46-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK46-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK46-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i8***)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i8*** [[MYALLOC]]) -// CHECK46-NEXT: ret void -// -// -// CHECK46-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK46-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i8*** nonnull align 8 dereferenceable(8) [[MYALLOC:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK46-NEXT: entry: -// CHECK46-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK46-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK46-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK46-NEXT: [[MYALLOC_ADDR:%.*]] = alloca i8***, align 8 -// CHECK46-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK46-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK46-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK46-NEXT: store i8*** [[MYALLOC]], i8**** [[MYALLOC_ADDR]], align 8 -// CHECK46-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK46-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[MYALLOC_ADDR]], align 8 -// CHECK46-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK46-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK46-NEXT: [[TMP3:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK46-NEXT: [[CONV1:%.*]] = bitcast i8** [[TMP3]] to i8* -// CHECK46-NEXT: [[DOTA__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP2]], i64 4, i8* [[CONV1]]) -// CHECK46-NEXT: [[DOTA__ADDR:%.*]] = bitcast i8* [[DOTA__VOID_ADDR]] to i32* -// CHECK46-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK46-NEXT: store i32 [[TMP4]], i32* [[DOTA__ADDR]], align 4 -// CHECK46-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK46-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 -// CHECK46-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK46: omp_if.then: -// CHECK46-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTA__ADDR]], align 4 -// CHECK46-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK46-NEXT: store i32 [[INC]], i32* [[DOTA__ADDR]], align 4 -// CHECK46-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK46-NEXT: br label [[OMP_IF_END]] -// CHECK46: omp_if.end: -// CHECK46-NEXT: [[TMP8:%.*]] = bitcast i32* [[DOTA__ADDR]] to i8* -// CHECK46-NEXT: [[TMP9:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK46-NEXT: [[CONV2:%.*]] = bitcast i8** [[TMP9]] to i8* -// CHECK46-NEXT: call void @__kmpc_free(i32 [[TMP2]], i8* [[TMP8]], i8* [[CONV2]]) -// CHECK46-NEXT: ret void -// -// -// CHECK47-LABEL: define {{[^@]+}}@_Z24parallel_master_allocatev -// CHECK47-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK47-NEXT: entry: -// CHECK47-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK47-NEXT: [[MYALLOC:%.*]] = alloca i8**, align 8 -// CHECK47-NEXT: store i8** null, i8*** [[MYALLOC]], align 8 -// CHECK47-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK47-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK47-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK47-NEXT: ret void -// -// -// CHECK48-LABEL: define {{[^@]+}}@_Z24parallel_master_allocatev -// CHECK48-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK48-NEXT: entry: -// CHECK48-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK48-NEXT: [[MYALLOC:%.*]] = alloca i8**, align 8 -// CHECK48-NEXT: store i8** null, i8*** [[MYALLOC]], align 8 -// CHECK48-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK48-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK48-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK48-NEXT: ret void +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i8*** nonnull align 8 dereferenceable(8) [[MYALLOC:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[MYALLOC_ADDR:%.*]] = alloca i8***, align 8 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK24-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK24-NEXT: store i8*** [[MYALLOC]], i8**** [[MYALLOC_ADDR]], align 8 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK24-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[MYALLOC_ADDR]], align 8 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i8**, i8*** [[TMP0]], align 8 +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i8** [[TMP3]] to i8* +// CHECK24-NEXT: [[DOTA__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP2]], i64 4, i8* [[CONV1]]) +// CHECK24-NEXT: [[DOTA__ADDR:%.*]] = bitcast i8* [[DOTA__VOID_ADDR]] to i32* +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTA__ADDR]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK24-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 +// CHECK24-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK24: omp_if.then: +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTA__ADDR]], align 4 +// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK24-NEXT: store i32 [[INC]], i32* [[DOTA__ADDR]], align 4 +// CHECK24-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK24-NEXT: br label [[OMP_IF_END]] +// CHECK24: omp_if.end: +// CHECK24-NEXT: [[TMP8:%.*]] = bitcast i32* [[DOTA__ADDR]] to i8* +// CHECK24-NEXT: [[TMP9:%.*]] = load i8**, i8*** [[TMP0]], align 8 +// CHECK24-NEXT: [[CONV2:%.*]] = bitcast i8** [[TMP9]] to i8* +// CHECK24-NEXT: call void @__kmpc_free(i32 [[TMP2]], i8* [[TMP8]], i8* [[CONV2]]) +// CHECK24-NEXT: ret void // diff --git a/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp --- a/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -992,25 +992,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: ret i32 0, !dbg [[DBG18:![0-9]+]] -// diff --git a/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp --- a/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1901,359 +1901,3 @@ // CHECK2-NEXT: call void @__cxx_global_var_init() // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3:%.*]] -// CHECK3: for.cond3: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK3-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK3: for.body5: -// CHECK3-NEXT: br label [[FOR_INC6:%.*]] -// CHECK3: for.inc6: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK3-NEXT: store i32 [[INC7]], i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end8: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 -// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_10]], align 1 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK3-NEXT: br label [[FOR_COND12:%.*]] -// CHECK3: for.cond12: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END25:%.*]] -// CHECK3: for.body14: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP10]], i32* [[J]], align 4 -// CHECK3-NEXT: br label [[FOR_COND15:%.*]] -// CHECK3: for.cond15: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP12]], i64 [[IDXPROM]] -// CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i8, i8* [[TMP14]], i64 [[IDXPROM16]] -// CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[ARRAYIDX17]], align 1 -// CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK3-NEXT: [[CMP18:%.*]] = icmp slt i32 [[TMP11]], [[CONV]] -// CHECK3-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END22:%.*]] -// CHECK3: for.body19: -// CHECK3-NEXT: br label [[FOR_INC20:%.*]] -// CHECK3: for.inc20: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[J]], align 4 -// CHECK3-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK3-NEXT: store i32 [[INC21]], i32* [[J]], align 4 -// CHECK3-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end22: -// CHECK3-NEXT: br label [[FOR_INC23:%.*]] -// CHECK3: for.inc23: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK3-NEXT: [[INC24:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK3-NEXT: store i32 [[INC24]], i32* [[I9]], align 4 -// CHECK3-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end25: -// CHECK3-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK3-NEXT: br label [[FOR_COND27:%.*]] -// CHECK3: for.cond27: -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK3-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK3-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END32:%.*]] -// CHECK3: for.body29: -// CHECK3-NEXT: br label [[FOR_INC30:%.*]] -// CHECK3: for.inc30: -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK3-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK3-NEXT: store i32 [[INC31]], i32* [[I26]], align 4 -// CHECK3-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end32: -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP21]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull dereferenceable(4) @s, i32 1) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: store i32* [[A2]], i32** [[A]], align 8 -// CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: store i32 0, i32* [[A3]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A4]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A5]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[A5]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_codegen.cpp -// CHECK3-SAME: () #[[ATTR1]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @__cxx_global_var_init() -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3:%.*]] -// CHECK4: for.cond3: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK4-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK4: for.body5: -// CHECK4-NEXT: br label [[FOR_INC6:%.*]] -// CHECK4: for.inc6: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK4-NEXT: store i32 [[INC7]], i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end8: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 -// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_10]], align 1 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK4-NEXT: br label [[FOR_COND12:%.*]] -// CHECK4: for.cond12: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK4-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END25:%.*]] -// CHECK4: for.body14: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i32 [[TMP10]], i32* [[J]], align 4 -// CHECK4-NEXT: br label [[FOR_COND15:%.*]] -// CHECK4: for.cond15: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK4-NEXT: [[TMP12:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP12]], i64 [[IDXPROM]] -// CHECK4-NEXT: [[TMP14:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK4-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i8, i8* [[TMP14]], i64 [[IDXPROM16]] -// CHECK4-NEXT: [[TMP16:%.*]] = load i8, i8* [[ARRAYIDX17]], align 1 -// CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK4-NEXT: [[CMP18:%.*]] = icmp slt i32 [[TMP11]], [[CONV]] -// CHECK4-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END22:%.*]] -// CHECK4: for.body19: -// CHECK4-NEXT: br label [[FOR_INC20:%.*]] -// CHECK4: for.inc20: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[J]], align 4 -// CHECK4-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK4-NEXT: store i32 [[INC21]], i32* [[J]], align 4 -// CHECK4-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end22: -// CHECK4-NEXT: br label [[FOR_INC23:%.*]] -// CHECK4: for.inc23: -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK4-NEXT: [[INC24:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK4-NEXT: store i32 [[INC24]], i32* [[I9]], align 4 -// CHECK4-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end25: -// CHECK4-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK4-NEXT: br label [[FOR_COND27:%.*]] -// CHECK4: for.cond27: -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK4-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK4-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END32:%.*]] -// CHECK4: for.body29: -// CHECK4-NEXT: br label [[FOR_INC30:%.*]] -// CHECK4: for.inc30: -// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK4-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK4-NEXT: store i32 [[INC31]], i32* [[I26]], align 4 -// CHECK4-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end32: -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP21]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull dereferenceable(4) @s, i32 1) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: store i32* [[A2]], i32** [[A]], align 8 -// CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: store i32 0, i32* [[A3]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A4]], align 4 -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A5]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[A5]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_codegen.cpp -// CHECK4-SAME: () #[[ATTR1]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @__cxx_global_var_init() -// CHECK4-NEXT: ret void -// diff --git a/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp --- a/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp @@ -7,13 +7,13 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #if !defined(ARRAY) && !defined(LOOP) @@ -2705,655 +2705,3 @@ // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 // CHECK6-NEXT: ret void // -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull dereferenceable(8) [[TTT]]) -// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull dereferenceable(8) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull dereferenceable(8) [[ARRAYINIT_BEGIN]], double 1.000000e+00) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull dereferenceable(8) [[ARRAYINIT_ELEMENT]], double 2.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull dereferenceable(8) [[VAR]], double 3.000000e+00) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) -// CHECK7-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull dereferenceable(8) [[TEST]]) #[[ATTR4]] -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull dereferenceable(8) [[TTT]]) #[[ATTR4]] -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP7]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* nonnull dereferenceable(8) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* nonnull dereferenceable(8) [[THIS1]], double [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TTT]]) -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TTT]]) #[[ATTR4]] -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP7]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIdED2Ev(%struct.S* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 0.000000e+00, double* [[F]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK7-NEXT: store double [[TMP0]], double* [[F]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull dereferenceable(8) [[TTT]]) -// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull dereferenceable(8) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull dereferenceable(8) [[ARRAYINIT_BEGIN]], double 1.000000e+00) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull dereferenceable(8) [[ARRAYINIT_ELEMENT]], double 2.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull dereferenceable(8) [[VAR]], double 3.000000e+00) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) -// CHECK8-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull dereferenceable(8) [[TEST]]) #[[ATTR4]] -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull dereferenceable(8) [[TTT]]) #[[ATTR4]] -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP7]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* nonnull dereferenceable(8) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* nonnull dereferenceable(8) [[THIS1]], double [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TTT]]) -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TTT]]) #[[ATTR4]] -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP7]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIdED2Ev(%struct.S* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 0.000000e+00, double* [[F]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK8-NEXT: store double [[TMP0]], double* [[F]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK10-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK10-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8 -// CHECK10-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK10-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK10-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: store double 1.000000e+00, double* @g, align 8 -// CHECK10-NEXT: store i32 11, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK10-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK10-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK10-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK10-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK10-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK10-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK10-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK10-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK10-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK10-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK10-NEXT: store volatile double [[TMP1]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK10-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[BLOCK_CAPTURED2]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]] to void ()* -// CHECK10-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP3]] to %struct.__block_literal_generic* -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK10-NEXT: [[TMP6:%.*]] = load i8*, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to void (i8*)* -// CHECK10-NEXT: call void [[TMP7]](i8* [[TMP5]]) -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK10-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 -// CHECK10-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK10-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* -// CHECK10-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK10-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK10-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK10-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK10-NEXT: store i32 22, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St -// CHECK11-SAME: (i32 [[N:%.*]], float* [[A:%.*]], %struct.St* [[S:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK11-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z4loopv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// diff --git a/clang/test/OpenMP/parallel_private_codegen.cpp b/clang/test/OpenMP/parallel_private_codegen.cpp --- a/clang/test/OpenMP/parallel_private_codegen.cpp +++ b/clang/test/OpenMP/parallel_private_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1366,1006 +1366,3 @@ // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK5-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK5-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK5-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK5-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK6-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK6-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK6-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK6-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK6-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK7-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B3]], i32** [[TMP4]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK7-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(32) [[REF_TMP]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK7-NEXT: store i32* [[A]], i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[C]], i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK7-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK7-NEXT: store i32 [[INC3]], i32* [[TMP11]], align 4 -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[DEC4:%.*]] = add nsw i32 [[TMP13]], -1 -// CHECK7-NEXT: store i32 [[DEC4]], i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP15]], 1 -// CHECK7-NEXT: store i32 [[DIV5]], i32* [[TMP14]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[G:%.*]] = alloca i32, align 128 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, align 128 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store i32 1, i32* [[G]], align 128 -// CHECK8-NEXT: store i32 20, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* [[G]], align 128 -// CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 32 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 40, i32* [[BLOCK_CAPTURE_ADDR1]], align 32 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK8-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP1]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[BLOCK_CAPTURED6]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[BLOCK_CAPTURED7]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP8]](i8* [[TMP6]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: store i32* [[A]], i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[C]], i32** [[_TMP3]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK8-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC4]], i32* [[TMP5]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[DEC5:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK8-NEXT: store i32 [[DEC5]], i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK8-NEXT: [[DIV6:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK8-NEXT: store i32 [[DIV6]], i32* [[TMP8]], align 4 -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/parallel_reduction_codegen.cpp b/clang/test/OpenMP/parallel_reduction_codegen.cpp --- a/clang/test/OpenMP/parallel_reduction_codegen.cpp +++ b/clang/test/OpenMP/parallel_reduction_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -80,9 +80,6 @@ }; -//CHECK: foo_array_sect -//CHECK: call void {{.+}}@__kmpc_fork_call( -//CHECK: ret void void foo_array_sect(short x[1]) { #pragma omp parallel reduction(default, + : x[:]) {} @@ -4402,1053 +4399,3 @@ // CHECK4-NEXT: store i32 [[ADD3]], i32* [[TMP23]], align 4 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK5-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 -// CHECK5-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = fptosi float [[TMP1]] to i32 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: [[CALL:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL]], 0.000000e+00 -// CHECK5-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] -// CHECK5: if.then: -// CHECK5-NEXT: br label [[WHILE_COND:%.*]] -// CHECK5: while.cond: -// CHECK5-NEXT: br label [[WHILE_BODY:%.*]] -// CHECK5: while.body: -// CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[CONV2:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX3]], align 4 -// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK5-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: if.end: -// CHECK5-NEXT: [[CALL5:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL5]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done6: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret float 0.000000e+00 -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR4]] -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK5-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK5-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK5-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK5-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK5-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP4]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP6]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP7]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK5-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK5-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK6-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 -// CHECK6-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = fptosi float [[TMP1]] to i32 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: [[CALL:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL]], 0.000000e+00 -// CHECK6-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] -// CHECK6: if.then: -// CHECK6-NEXT: br label [[WHILE_COND:%.*]] -// CHECK6: while.cond: -// CHECK6-NEXT: br label [[WHILE_BODY:%.*]] -// CHECK6: while.body: -// CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[CONV2:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX3]], align 4 -// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK6-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: if.end: -// CHECK6-NEXT: [[CALL5:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL5]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done6: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret float 0.000000e+00 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR4]] -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK6-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK6-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK6-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK6-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK6-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK6-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP4]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP6]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP7]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK6-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK6-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK7-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 -// CHECK7-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK7-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK7-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B4]], i32** [[TMP7]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK7-NEXT: store i32* [[TMP9]], i32** [[TMP8]], align 8 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(32) [[REF_TMP]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR0]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK7-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK7-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK7-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK7-NEXT: store i32 [[INC3]], i32* [[TMP17]], align 4 -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[DEC4:%.*]] = add nsw i32 [[TMP19]], -1 -// CHECK7-NEXT: store i32 [[DEC4]], i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP21]], 1 -// CHECK7-NEXT: store i32 [[DIV5]], i32* [[TMP20]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK8-SAME: (i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 -// CHECK8-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, align 128 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store i32 1, i32* @g, align 128 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR3]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK8-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK8-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP4]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[BLOCK_CAPTURED8]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED9:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK8-NEXT: store i32* [[TMP6]], i32** [[BLOCK_CAPTURED9]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP7]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP8]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP11]](i8* [[TMP9]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 -// CHECK8-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[TMP7]], align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK8-NEXT: [[DEC8:%.*]] = add nsw i32 [[TMP9]], -1 -// CHECK8-NEXT: store i32 [[DEC8]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP6]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK8-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[DIV9]], i32* [[TMP10]], align 4 -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/parallel_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_reduction_task_codegen.cpp --- a/clang/test/OpenMP/parallel_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -974,25 +974,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: ret i32 0, !dbg [[DBG18:![0-9]+]] -// diff --git a/clang/test/OpenMP/parallel_sections_codegen.cpp b/clang/test/OpenMP/parallel_sections_codegen.cpp --- a/clang/test/OpenMP/parallel_sections_codegen.cpp +++ b/clang/test/OpenMP/parallel_sections_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -fexceptions -fcxx-exceptions -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -o - %s | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -o - %s | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -fexceptions -fcxx-exceptions -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -362,117 +362,3 @@ // CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7]] // CHECK2-NEXT: unreachable // -// -// CHECK3-LABEL: define {{[^@]+}}@_Z3foov -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_Z8mayThrowv() -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z3barv -// CHECK3-SAME: () #[[ATTR0]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_Z8mayThrowv() -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: invoke void @_Z3barv() -// CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont1: -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK3-NEXT: ret i32 [[CALL]] -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR5:[0-9]+]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR4:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: ret i32 0 -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR5]] -// CHECK3-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z3foov -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_Z8mayThrowv() -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z3barv -// CHECK4-SAME: () #[[ATTR0]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_Z8mayThrowv() -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: invoke void @_Z3barv() -// CHECK4-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont1: -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK4-NEXT: ret i32 [[CALL]] -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR5:[0-9]+]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK4-SAME: () #[[ATTR4:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: ret i32 0 -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR5]] -// CHECK4-NEXT: unreachable -// diff --git a/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp --- a/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1058,25 +1058,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: ret i32 0, !dbg [[DBG18:![0-9]+]] -// diff --git a/clang/test/OpenMP/sections_firstprivate_codegen.cpp b/clang/test/OpenMP/sections_firstprivate_codegen.cpp --- a/clang/test/OpenMP/sections_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/sections_firstprivate_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1720,835 +1720,3 @@ // CHECK4-NEXT: call void @__cxx_global_var_init.2() // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @vec, i64 0, i64 0), align 4 -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x %struct.S]* @s_arr to i8*), i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @vec, i64 0, i64 0), align 4 -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x %struct.S]* @s_arr to i8*), i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 1, i32* @g, align 4 -// CHECK8-NEXT: store i32 10, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 20, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/sections_lastprivate_codegen.cpp b/clang/test/OpenMP/sections_lastprivate_codegen.cpp --- a/clang/test/OpenMP/sections_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/sections_lastprivate_codegen.cpp @@ -10,16 +10,16 @@ // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -2835,1071 +2835,3 @@ // CHECK8-NEXT: store i32 29, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 // CHECK8-NEXT: ret void // -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP2]], 1.000000e+00 -// CHECK9-NEXT: store double [[INC]], double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: [[CALL2:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL2]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP4]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[ARRAYIDX1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP3]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP2]], 1.000000e+00 -// CHECK10-NEXT: store double [[INC]], double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: [[CALL2:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL2]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP4]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[ARRAYIDX1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP3]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK12-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: store i32 1, i32* @g, align 4 -// CHECK12-NEXT: store i32 17, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: store i32 29, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK13-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP2]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC]], double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: [[CALL2:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL2]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done3: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP4]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[ARRAYIDX1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done2: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK14-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP2]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC]], double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: [[CALL2:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL2]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done3: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP4]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull dereferenceable(4) [[ARRAYIDX1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done2: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK15-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK15-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK16-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK16-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK16-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store i32 1, i32* @g, align 4 -// CHECK16-NEXT: store i32 17, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK16-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: store i32 29, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK16-NEXT: ret void -// diff --git a/clang/test/OpenMP/sections_private_codegen.cpp b/clang/test/OpenMP/sections_private_codegen.cpp --- a/clang/test/OpenMP/sections_private_codegen.cpp +++ b/clang/test/OpenMP/sections_private_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1075,626 +1075,3 @@ // CHECK4-NEXT: store i32 222, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store double 1.000000e+00, double* [[G]], align 8 -// CHECK8-NEXT: store i32 111, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile double, double* [[G]], align 8 -// CHECK8-NEXT: store volatile double [[TMP0]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 222, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/sections_reduction_codegen.cpp b/clang/test/OpenMP/sections_reduction_codegen.cpp --- a/clang/test/OpenMP/sections_reduction_codegen.cpp +++ b/clang/test/OpenMP/sections_reduction_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -2159,570 +2159,3 @@ // CHECK4-NEXT: store double [[ADD]], double* [[TMP11]], align 8 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = fptosi float [[TMP1]] to i32 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[CONV2:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 1 -// CHECK5-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX3]], align 4 -// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 1 -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR1]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done5: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR4]] -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[CONV:%.*]] = fptrunc double [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK5-NEXT: [[CONV2:%.*]] = fptrunc double [[ADD]] to float -// CHECK5-NEXT: store float [[CONV2]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK5-NEXT: [[CONV2:%.*]] = fptosi double [[ADD]] to i32 -// CHECK5-NEXT: store i32 [[CONV2]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = fptosi float [[TMP1]] to i32 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[CONV2:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 1 -// CHECK6-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX3]], align 4 -// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 1 -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR1]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done5: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR1]]) #[[ATTR4]] -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[CONV:%.*]] = fptrunc double [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK6-NEXT: [[CONV2:%.*]] = fptrunc double [[ADD]] to float -// CHECK6-NEXT: store float [[CONV2]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i32 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK6-NEXT: [[CONV2:%.*]] = fptosi double [[ADD]] to i32 -// CHECK6-NEXT: store i32 [[CONV2]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store double 1.000000e+00, double* @g, align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK8-NEXT: store volatile double [[TMP0]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/sections_reduction_task_codegen.cpp b/clang/test/OpenMP/sections_reduction_task_codegen.cpp --- a/clang/test/OpenMP/sections_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/sections_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1067,25 +1067,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: ret i32 0, !dbg [[DBG18:![0-9]+]] -// diff --git a/clang/test/OpenMP/single_codegen.cpp b/clang/test/OpenMP/single_codegen.cpp --- a/clang/test/OpenMP/single_codegen.cpp +++ b/clang/test/OpenMP/single_codegen.cpp @@ -11,11 +11,11 @@ // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -std=c++11 -fopenmp -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -std=c++11 -fopenmp-simd -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -std=c++11 -fopenmp-simd -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef ARRAY #ifndef HEADER @@ -5238,1202 +5238,3 @@ // CHECK6-NEXT: store %struct.St* [[TMP19]], %struct.St** [[TMP15]], align 8 // CHECK6-NEXT: ret void // -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull dereferenceable(4) @tc) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK7-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK7-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK7-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK7-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK7-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2) -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK7-NEXT: ret void -// CHECK7: lpad: -// CHECK7-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: cleanup -// CHECK7-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0 -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[EXN_SLOT]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[TMP3]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ARRAYCTOR_CUR]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: br label [[EH_RESUME:%.*]] -// CHECK7: eh.resume: -// CHECK7-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK7-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK7-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK7-NEXT: resume { i8*, i32 } [[LPAD_VAL2]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3foov -// CHECK7-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_Z8mayThrowv() -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR6:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1 -// CHECK7-NEXT: [[C:%.*]] = alloca %class.TestClass*, align 8 -// CHECK7-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8 -// CHECK7-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull dereferenceable(8) [[SST]]) -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) -// CHECK7-NEXT: store i8 2, i8* [[A]], align 1 -// CHECK7-NEXT: store i8 2, i8* [[A]], align 1 -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32 -// CHECK7-NEXT: ret i32 [[CONV]] -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP2]]) #[[ATTR9:[0-9]+]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK7-SAME: (%struct.SST* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK7-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull dereferenceable(8) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] comdat { -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3]] -// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z15parallel_singlev -// CHECK7-SAME: () #[[ATTR8:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: ret void -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR9]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK7-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK7-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK7-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK7-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP9:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP11:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK7-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK7-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK7-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK7-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK7-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK7-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK7-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[_TMP9]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP4]], i32** [[_TMP10]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP9]], align 8 -// CHECK7-NEXT: store i32* [[TMP5]], i32** [[_TMP11]], align 8 -// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP6]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK7-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B4]], i32** [[TMP9]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP11]], align 8 -// CHECK7-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK7-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon* nonnull dereferenceable(32) [[REF_TMP]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: ret void -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP12:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP13:%.*]] = extractvalue { i8*, i32 } [[TMP12]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP13]]) #[[ATTR9]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR8]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %class.anon* [[THIS]], %class.anon** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon*, %class.anon** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON:%.*]], %class.anon* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK7-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK7-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK7-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8 -// CHECK7-NEXT: [[TMP19:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK7-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK7-NEXT: store i32 [[INC5]], i32* [[TMP19]], align 4 -// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP21]], -1 -// CHECK7-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[TMP22:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK7-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP23]], 1 -// CHECK7-NEXT: store i32 [[DIV7]], i32* [[TMP22]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK7-SAME: (%struct.SST* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK7-NEXT: [[A2:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: [[_TMP4:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK7-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 0.000000e+00, double* [[A]], align 8 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[A3]], double** [[A2]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load double*, double** [[A2]], align 8 -// CHECK7-NEXT: store double* [[TMP0]], double** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK7-NEXT: store double* [[TMP1]], double** [[_TMP4]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP4:%.*]] = load double*, double** [[_TMP4]], align 8 -// CHECK7-NEXT: store double* [[TMP4]], double** [[TMP3]], align 8 -// CHECK7-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: ret void -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP5:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP6]]) #[[ATTR9]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SST* [[TMP1]], %struct.SST** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8 -// CHECK7-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8 -// CHECK7-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.1* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK7-SAME: (%class.anon.1* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR8]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.1*, %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1:%.*]], %class.anon.1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load double, double* [[TMP3]], align 8 -// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC]], double* [[TMP3]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[TMP5]], align 8 -// CHECK7-NEXT: store double* [[TMP6]], double** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK7-NEXT: store double* [[TMP7]], double** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = load double, double* [[TMP8]], align 8 -// CHECK7-NEXT: [[INC3:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC3]], double* [[TMP8]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull dereferenceable(4) @tc) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK8-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK8-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK8-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK8-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK8-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2) -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK8-NEXT: ret void -// CHECK8: lpad: -// CHECK8-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: cleanup -// CHECK8-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0 -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[EXN_SLOT]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[TMP3]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ARRAYCTOR_CUR]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: br label [[EH_RESUME:%.*]] -// CHECK8: eh.resume: -// CHECK8-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK8-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK8-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK8-NEXT: resume { i8*, i32 } [[LPAD_VAL2]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3foov -// CHECK8-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_Z8mayThrowv() -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR6:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1 -// CHECK8-NEXT: [[C:%.*]] = alloca %class.TestClass*, align 8 -// CHECK8-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8 -// CHECK8-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull dereferenceable(8) [[SST]]) -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) -// CHECK8-NEXT: store i8 2, i8* [[A]], align 1 -// CHECK8-NEXT: store i8 2, i8* [[A]], align 1 -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK8-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32 -// CHECK8-NEXT: ret i32 [[CONV]] -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP2]]) #[[ATTR9:[0-9]+]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK8-SAME: (%struct.SST* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK8-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull dereferenceable(8) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] comdat { -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3]] -// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z15parallel_singlev -// CHECK8-SAME: () #[[ATTR8:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: ret void -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR9]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK8-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK8-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK8-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK8-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP9:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP11:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK8-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK8-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK8-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK8-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK8-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK8-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK8-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[_TMP9]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP4]], i32** [[_TMP10]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP9]], align 8 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[_TMP11]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP6]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK8-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK8-NEXT: store i32* [[B4]], i32** [[TMP9]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP11]], align 8 -// CHECK8-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK8-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon* nonnull dereferenceable(32) [[REF_TMP]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: ret void -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP12:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP13:%.*]] = extractvalue { i8*, i32 } [[TMP12]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP13]]) #[[ATTR9]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK8-SAME: (%class.anon* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR8]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store %class.anon* [[THIS]], %class.anon** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.anon*, %class.anon** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON:%.*]], %class.anon* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK8-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK8-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8 -// CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK8-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8 -// CHECK8-NEXT: [[TMP19:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK8-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK8-NEXT: store i32 [[INC5]], i32* [[TMP19]], align 4 -// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK8-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP21]], -1 -// CHECK8-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4 -// CHECK8-NEXT: [[TMP22:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK8-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP23]], 1 -// CHECK8-NEXT: store i32 [[DIV7]], i32* [[TMP22]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK8-SAME: (%struct.SST* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK8-NEXT: [[A2:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[_TMP4:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK8-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 0.000000e+00, double* [[A]], align 8 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[A3]], double** [[A2]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load double*, double** [[A2]], align 8 -// CHECK8-NEXT: store double* [[TMP0]], double** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store double* [[TMP1]], double** [[_TMP4]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP4:%.*]] = load double*, double** [[_TMP4]], align 8 -// CHECK8-NEXT: store double* [[TMP4]], double** [[TMP3]], align 8 -// CHECK8-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: ret void -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP5:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP6]]) #[[ATTR9]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK8-SAME: (%class.anon.0* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK8-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store %struct.SST* [[TMP1]], %struct.SST** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8 -// CHECK8-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8 -// CHECK8-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.1* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK8-SAME: (%class.anon.1* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR8]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[_TMP2:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.anon.1*, %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1:%.*]], %class.anon.1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP3:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load double, double* [[TMP3]], align 8 -// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK8-NEXT: store double [[INC]], double* [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[TMP5]], align 8 -// CHECK8-NEXT: store double* [[TMP6]], double** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store double* [[TMP7]], double** [[_TMP2]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = load double, double* [[TMP8]], align 8 -// CHECK8-NEXT: [[INC3:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK8-NEXT: store double [[INC3]], double* [[TMP8]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG6:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull dereferenceable(4) @tc), !dbg [[DBG8:![0-9]+]] -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG11:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG8]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK9-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 !dbg [[DBG12:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK9-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull dereferenceable(4) [[THIS1]]), !dbg [[DBG13:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG14:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK9-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG15:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK9-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG16:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG17:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG18:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG19:![0-9]+]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG19]] -// CHECK9-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG19]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG19]] -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), !dbg [[DBG19]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG19]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG21:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG21]] -// CHECK9: lpad: -// CHECK9-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: cleanup, !dbg [[DBG22:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0, !dbg [[DBG22]] -// CHECK9-NEXT: store i8* [[TMP2]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG22]] -// CHECK9-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 1, !dbg [[DBG22]] -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG22]] -// CHECK9-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ARRAYCTOR_CUR]], !dbg [[DBG19]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG19]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG19]] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG19]] -// CHECK9-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG19]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), !dbg [[DBG19]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG19]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG19]] -// CHECK9: eh.resume: -// CHECK9-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG19]] -// CHECK9-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG19]] -// CHECK9-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG19]] -// CHECK9-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG19]] -// CHECK9-NEXT: resume { i8*, i32 } [[LPAD_VAL2]], !dbg [[DBG19]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG23:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG24:![0-9]+]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG24]] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG24]] -// CHECK9-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG24]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), !dbg [[DBG24]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG24]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: ret void, !dbg [[DBG24]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z3foov -// CHECK9-SAME: () #[[ATTR4:[0-9]+]] !dbg [[DBG25:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG26:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG27:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG28:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1 -// CHECK9-NEXT: [[C:%.*]] = alloca %class.TestClass*, align 8 -// CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8 -// CHECK9-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8, !dbg [[DBG29:![0-9]+]] -// CHECK9-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull dereferenceable(8) [[SST]]), !dbg [[DBG30:![0-9]+]] -// CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)), !dbg [[DBG31:![0-9]+]] -// CHECK9-NEXT: store i8 2, i8* [[A]], align 1, !dbg [[DBG32:![0-9]+]] -// CHECK9-NEXT: store i8 2, i8* [[A]], align 1, !dbg [[DBG33:![0-9]+]] -// CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG34:![0-9]+]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1, !dbg [[DBG35:![0-9]+]] -// CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32, !dbg [[DBG35]] -// CHECK9-NEXT: ret i32 [[CONV]], !dbg [[DBG36:![0-9]+]] -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null, !dbg [[DBG34]] -// CHECK9-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0, !dbg [[DBG34]] -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP2]]) #[[ATTR9:[0-9]+]], !dbg [[DBG34]] -// CHECK9-NEXT: unreachable, !dbg [[DBG34]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK9-SAME: (%struct.SST* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG37:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull dereferenceable(8) [[THIS1]]), !dbg [[DBG38:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG39:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG40:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8, !dbg [[DBG41:![0-9]+]] -// CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]), !dbg [[DBG41]] -// CHECK9-NEXT: ret void, !dbg [[DBG42:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] { -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3]] -// CHECK9-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] -// CHECK9-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z15parallel_singlev -// CHECK9-SAME: () #[[ATTR8:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG43:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG44:![0-9]+]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: ret void, !dbg [[DBG45:![0-9]+]] -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null, !dbg [[DBG44]] -// CHECK9-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0, !dbg [[DBG44]] -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR9]], !dbg [[DBG44]] -// CHECK9-NEXT: unreachable, !dbg [[DBG44]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK9-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG46:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK9-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[THIS1]], i32 0, i32 0, !dbg [[DBG47:![0-9]+]] -// CHECK9-NEXT: store i32 0, i32* [[A]], align 4, !dbg [[DBG47]] -// CHECK9-NEXT: ret void, !dbg [[DBG48:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK9-SAME: (%class.TestClass* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG49:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK9-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void, !dbg [[DBG50:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG51:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP9:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP11:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0, !dbg [[DBG52:![0-9]+]] -// CHECK9-NEXT: store i32 0, i32* [[A]], align 8, !dbg [[DBG52]] -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1, !dbg [[DBG53:![0-9]+]] -// CHECK9-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4, !dbg [[DBG53]] -// CHECK9-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16, !dbg [[DBG53]] -// CHECK9-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4, !dbg [[DBG53]] -// CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2, !dbg [[DBG54:![0-9]+]] -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8, !dbg [[DBG55:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP0]], i32** [[C]], align 8, !dbg [[DBG54]] -// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0, !dbg [[DBG56:![0-9]+]] -// CHECK9-NEXT: store i32* [[A3]], i32** [[A2]], align 8, !dbg [[DBG56]] -// CHECK9-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1, !dbg [[DBG57:![0-9]+]] -// CHECK9-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4, !dbg [[DBG57]] -// CHECK9-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4, !dbg [[DBG57]] -// CHECK9-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4, !dbg [[DBG57]] -// CHECK9-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32, !dbg [[DBG57]] -// CHECK9-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4, !dbg [[DBG57]] -// CHECK9-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2, !dbg [[DBG58:![0-9]+]] -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8, !dbg [[DBG58]] -// CHECK9-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8, !dbg [[DBG58]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8, !dbg [[DBG59:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8, !dbg [[DBG60:![0-9]+]] -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8, !dbg [[DBG61:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP3]], i32** [[_TMP9]], align 8, !dbg [[DBG60]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8, !dbg [[DBG62:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP4]], i32** [[_TMP10]], align 8, !dbg [[DBG63:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP9]], align 8, !dbg [[DBG64:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP5]], i32** [[_TMP11]], align 8, !dbg [[DBG63]] -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0, !dbg [[DBG65:![0-9]+]] -// CHECK9-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP6]], align 8, !dbg [[DBG65]] -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1, !dbg [[DBG65]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 8, !dbg [[DBG66:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8, !dbg [[DBG65]] -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2, !dbg [[DBG65]] -// CHECK9-NEXT: store i32* [[B4]], i32** [[TMP9]], align 8, !dbg [[DBG65]] -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3, !dbg [[DBG65]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP11]], align 8, !dbg [[DBG66]] -// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !dbg [[DBG65]] -// CHECK9-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon* nonnull dereferenceable(32) [[REF_TMP]]) -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG65]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: ret void, !dbg [[DBG67:![0-9]+]] -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP12:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null, !dbg [[DBG65]] -// CHECK9-NEXT: [[TMP13:%.*]] = extractvalue { i8*, i32 } [[TMP12]], 0, !dbg [[DBG65]] -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP13]]) #[[ATTR9]], !dbg [[DBG65]] -// CHECK9-NEXT: unreachable, !dbg [[DBG65]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK9-SAME: (%class.anon* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR8]] align 2 !dbg [[DBG68:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %class.anon* [[THIS]], %class.anon** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.anon*, %class.anon** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON:%.*]], %class.anon* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1, !dbg [[DBG69:![0-9]+]] -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8, !dbg [[DBG69]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4, !dbg [[DBG70:![0-9]+]] -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG70]] -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4, !dbg [[DBG70]] -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2, !dbg [[DBG71:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8, !dbg [[DBG71]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4, !dbg [[DBG72:![0-9]+]] -// CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1, !dbg [[DBG72]] -// CHECK9-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4, !dbg [[DBG72]] -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3, !dbg [[DBG73:![0-9]+]] -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8, !dbg [[DBG73]] -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4, !dbg [[DBG74:![0-9]+]] -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1, !dbg [[DBG74]] -// CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4, !dbg [[DBG74]] -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1, !dbg [[DBG75:![0-9]+]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8, !dbg [[DBG75]] -// CHECK9-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8, !dbg [[DBG76:![0-9]+]] -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2, !dbg [[DBG77:![0-9]+]] -// CHECK9-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8, !dbg [[DBG77]] -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3, !dbg [[DBG78:![0-9]+]] -// CHECK9-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8, !dbg [[DBG78]] -// CHECK9-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8, !dbg [[DBG76]] -// CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8, !dbg [[DBG79:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8, !dbg [[DBG80:![0-9]+]] -// CHECK9-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8, !dbg [[DBG81:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8, !dbg [[DBG80]] -// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[_TMP3]], align 8, !dbg [[DBG79]] -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4, !dbg [[DBG82:![0-9]+]] -// CHECK9-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP20]], 1, !dbg [[DBG82]] -// CHECK9-NEXT: store i32 [[INC5]], i32* [[TMP19]], align 4, !dbg [[DBG82]] -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP14]], align 4, !dbg [[DBG83:![0-9]+]] -// CHECK9-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP21]], -1, !dbg [[DBG83]] -// CHECK9-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4, !dbg [[DBG83]] -// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[_TMP4]], align 8, !dbg [[DBG81]] -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4, !dbg [[DBG84:![0-9]+]] -// CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP23]], 1, !dbg [[DBG84]] -// CHECK9-NEXT: store i32 [[DIV7]], i32* [[TMP22]], align 4, !dbg [[DBG84]] -// CHECK9-NEXT: ret void, !dbg [[DBG85:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK9-SAME: (%struct.SST* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG86:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: [[A2:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0, !dbg [[DBG87:![0-9]+]] -// CHECK9-NEXT: store double 0.000000e+00, double* [[A]], align 8, !dbg [[DBG87]] -// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0, !dbg [[DBG88:![0-9]+]] -// CHECK9-NEXT: store double* [[A3]], double** [[A2]], align 8, !dbg [[DBG88]] -// CHECK9-NEXT: [[TMP0:%.*]] = load double*, double** [[A2]], align 8, !dbg [[DBG89:![0-9]+]] -// CHECK9-NEXT: store double* [[TMP0]], double** [[TMP]], align 8, !dbg [[DBG90:![0-9]+]] -// CHECK9-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP]], align 8, !dbg [[DBG91:![0-9]+]] -// CHECK9-NEXT: store double* [[TMP1]], double** [[_TMP4]], align 8, !dbg [[DBG92:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0, !dbg [[DBG93:![0-9]+]] -// CHECK9-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP2]], align 8, !dbg [[DBG93]] -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1, !dbg [[DBG93]] -// CHECK9-NEXT: [[TMP4:%.*]] = load double*, double** [[_TMP4]], align 8, !dbg [[DBG94:![0-9]+]] -// CHECK9-NEXT: store double* [[TMP4]], double** [[TMP3]], align 8, !dbg [[DBG93]] -// CHECK9-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG93]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: ret void, !dbg [[DBG95:![0-9]+]] -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP5:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null, !dbg [[DBG93]] -// CHECK9-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0, !dbg [[DBG93]] -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP6]]) #[[ATTR9]], !dbg [[DBG93]] -// CHECK9-NEXT: unreachable, !dbg [[DBG93]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK9-SAME: (%class.anon.0* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 !dbg [[DBG96:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK9-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0, !dbg [[DBG97:![0-9]+]] -// CHECK9-NEXT: store %struct.SST* [[TMP1]], %struct.SST** [[TMP2]], align 8, !dbg [[DBG97]] -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1, !dbg [[DBG97]] -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1, !dbg [[DBG98:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8, !dbg [[DBG98]] -// CHECK9-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8, !dbg [[DBG97]] -// CHECK9-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.1* nonnull dereferenceable(16) [[REF_TMP]]), !dbg [[DBG97]] -// CHECK9-NEXT: ret void, !dbg [[DBG99:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK9-SAME: (%class.anon.1* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR8]] align 2 !dbg [[DBG100:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.anon.1*, %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1:%.*]], %class.anon.1* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1, !dbg [[DBG101:![0-9]+]] -// CHECK9-NEXT: [[TMP3:%.*]] = load double*, double** [[TMP2]], align 8, !dbg [[DBG101]] -// CHECK9-NEXT: [[TMP4:%.*]] = load double, double* [[TMP3]], align 8, !dbg [[DBG102:![0-9]+]] -// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00, !dbg [[DBG102]] -// CHECK9-NEXT: store double [[INC]], double* [[TMP3]], align 8, !dbg [[DBG102]] -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1, !dbg [[DBG103:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[TMP5]], align 8, !dbg [[DBG103]] -// CHECK9-NEXT: store double* [[TMP6]], double** [[TMP]], align 8, !dbg [[DBG104:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load double*, double** [[TMP]], align 8, !dbg [[DBG105:![0-9]+]] -// CHECK9-NEXT: store double* [[TMP7]], double** [[_TMP2]], align 8, !dbg [[DBG106:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 8, !dbg [[DBG105]] -// CHECK9-NEXT: [[TMP9:%.*]] = load double, double* [[TMP8]], align 8, !dbg [[DBG107:![0-9]+]] -// CHECK9-NEXT: [[INC3:%.*]] = fadd double [[TMP9]], 1.000000e+00, !dbg [[DBG107]] -// CHECK9-NEXT: store double [[INC3]], double* [[TMP8]], align 8, !dbg [[DBG107]] -// CHECK9-NEXT: ret void, !dbg [[DBG108:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG109:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG110:![0-9]+]] -// CHECK9-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG110]] -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z10array_funciPiP2St -// CHECK10-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], %struct.St* [[S:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: ret void -// diff --git a/clang/test/OpenMP/single_firstprivate_codegen.cpp b/clang/test/OpenMP/single_firstprivate_codegen.cpp --- a/clang/test/OpenMP/single_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/single_firstprivate_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1500,835 +1500,3 @@ // CHECK4-NEXT: call void @__cxx_global_var_init.2() // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @vec, i64 0, i64 0), align 4 -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x %struct.S]* @s_arr to i8*), i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: store i32 41, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @vec, i64 0, i64 0), align 4 -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x %struct.S]* @s_arr to i8*), i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: store i32 41, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 1, i32* @g, align 4 -// CHECK8-NEXT: store i32 37, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 31, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/single_private_codegen.cpp b/clang/test/OpenMP/single_private_codegen.cpp --- a/clang/test/OpenMP/single_private_codegen.cpp +++ b/clang/test/OpenMP/single_private_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -848,626 +848,3 @@ // CHECK4-NEXT: store i32 203, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 303, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 303, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store double 1.000000e+00, double* [[G]], align 8 -// CHECK8-NEXT: store i32 101, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile double, double* [[G]], align 8 -// CHECK8-NEXT: store volatile double [[TMP0]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 203, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: ret void -// diff --git a/clang/test/OpenMP/target_codegen_global_capture.cpp b/clang/test/OpenMP/target_codegen_global_capture.cpp --- a/clang/test/OpenMP/target_codegen_global_capture.cpp +++ b/clang/test/OpenMP/target_codegen_global_capture.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -3897,835 +3897,3 @@ // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK5-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK5-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK5-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK5-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK5-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK5-NEXT: store float [[CONV5]], float* @_ZZ3foossssE2Sb, align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK5-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK5-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK5-NEXT: store float [[CONV12]], float* @_ZZ3foossssE2Sd, align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK5-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK5-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK5-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 -// CHECK5-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK5-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK5-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK5-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 -// CHECK5-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK5-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK5-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK5-NEXT: ret i32 [[ADD27]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK5-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK5-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK5-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK5-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK5-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK5-NEXT: store float [[CONV5]], float* @_ZZ3barssssE2Sb, align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK5-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK5-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK5-NEXT: store float [[CONV12]], float* @_ZZ3barssssE2Sd, align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK5-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK5-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK5-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 -// CHECK5-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK5-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK5-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK5-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 -// CHECK5-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK5-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK5-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK5-NEXT: ret i32 [[ADD27]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK5-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK5-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK5-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK5-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK5-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK5-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK5-NEXT: store float [[CONV5]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK5-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK5-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK5-NEXT: store float [[CONV12]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK5-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK5-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK5-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 -// CHECK5-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK5-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK5-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK5-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 -// CHECK5-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK5-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK5-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK5-NEXT: ret i32 [[ADD27]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK6-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK6-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK6-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK6-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK6-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK6-NEXT: store float [[CONV5]], float* @_ZZ3foossssE2Sb, align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK6-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK6-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK6-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK6-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK6-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK6-NEXT: store float [[CONV12]], float* @_ZZ3foossssE2Sd, align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK6-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK6-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK6-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 -// CHECK6-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK6-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK6-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK6-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK6-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 -// CHECK6-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK6-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK6-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK6-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK6-NEXT: ret i32 [[ADD27]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK6-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK6-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK6-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK6-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK6-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK6-NEXT: store float [[CONV5]], float* @_ZZ3barssssE2Sb, align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK6-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK6-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK6-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK6-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK6-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK6-NEXT: store float [[CONV12]], float* @_ZZ3barssssE2Sd, align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK6-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK6-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK6-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 -// CHECK6-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK6-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK6-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK6-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK6-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 -// CHECK6-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK6-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK6-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK6-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK6-NEXT: ret i32 [[ADD27]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK6-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK6-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK6-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK6-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK6-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK6-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK6-NEXT: store float [[CONV5]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK6-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK6-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK6-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK6-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK6-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK6-NEXT: store float [[CONV12]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK6-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK6-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK6-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 -// CHECK6-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK6-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK6-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK6-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK6-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 -// CHECK6-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK6-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK6-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK6-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK6-NEXT: ret i32 [[ADD27]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK7-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK7-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK7-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK7-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK7-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK7-NEXT: store float [[CONV5]], float* @_ZZ3foossssE2Sb, align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK7-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK7-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK7-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK7-NEXT: store float [[CONV12]], float* @_ZZ3foossssE2Sd, align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK7-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK7-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK7-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 -// CHECK7-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK7-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK7-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK7-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 -// CHECK7-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK7-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK7-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK7-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK7-NEXT: ret i32 [[ADD27]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK7-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK7-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK7-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK7-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK7-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK7-NEXT: store float [[CONV5]], float* @_ZZ3barssssE2Sb, align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK7-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK7-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK7-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK7-NEXT: store float [[CONV12]], float* @_ZZ3barssssE2Sd, align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK7-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK7-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK7-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 -// CHECK7-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK7-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK7-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK7-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 -// CHECK7-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK7-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK7-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK7-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK7-NEXT: ret i32 [[ADD27]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK7-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK7-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK7-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK7-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK7-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK7-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK7-NEXT: store float [[CONV5]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK7-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK7-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK7-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK7-NEXT: store float [[CONV12]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK7-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK7-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK7-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 -// CHECK7-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK7-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK7-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK7-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 -// CHECK7-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK7-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK7-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK7-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK7-NEXT: ret i32 [[ADD27]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK8-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK8-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK8-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK8-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK8-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK8-NEXT: store float [[CONV5]], float* @_ZZ3foossssE2Sb, align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK8-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK8-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK8-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK8-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK8-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK8-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK8-NEXT: store float [[CONV12]], float* @_ZZ3foossssE2Sd, align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK8-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK8-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK8-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 -// CHECK8-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK8-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK8-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK8-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK8-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 -// CHECK8-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK8-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK8-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK8-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK8-NEXT: ret i32 [[ADD27]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK8-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK8-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK8-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK8-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK8-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK8-NEXT: store float [[CONV5]], float* @_ZZ3barssssE2Sb, align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK8-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK8-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK8-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK8-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK8-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK8-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK8-NEXT: store float [[CONV12]], float* @_ZZ3barssssE2Sd, align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK8-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK8-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK8-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 -// CHECK8-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK8-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK8-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK8-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK8-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 -// CHECK8-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK8-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK8-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK8-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK8-NEXT: ret i32 [[ADD27]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK8-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK8-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK8-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK8-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK8-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK8-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK8-NEXT: store float [[CONV5]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK8-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK8-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK8-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK8-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK8-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK8-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK8-NEXT: store float [[CONV12]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK8-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK8-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK8-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 -// CHECK8-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK8-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK8-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK8-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK8-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 -// CHECK8-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK8-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK8-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK8-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK8-NEXT: ret i32 [[ADD27]] -// diff --git a/clang/test/OpenMP/target_map_codegen_03.cpp b/clang/test/OpenMP/target_map_codegen_03.cpp --- a/clang/test/OpenMP/target_map_codegen_03.cpp +++ b/clang/test/OpenMP/target_map_codegen_03.cpp @@ -25,12 +25,12 @@ // RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 @@ -1040,59 +1040,3 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK13-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK14-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK15-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK16-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: ret void -// diff --git a/clang/test/OpenMP/target_parallel_codegen.cpp b/clang/test/OpenMP/target_parallel_codegen.cpp --- a/clang/test/OpenMP/target_parallel_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_codegen.cpp @@ -7,65 +7,65 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -4359,907 +4359,1957 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK5-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK5-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK5-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK5-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK5-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK5-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK5-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK5-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK5: .cancel.exit: +// CHECK5-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK5: .cancel.continue: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK5-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK5-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK5-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK5-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK5-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK5-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double // CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK5-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK5-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK5-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK5-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK5-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK5-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK5-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK5-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK5-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK5-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK5-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK5-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK5-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK5-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK5-NEXT: ret i32 [[TMP18]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK5-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK5-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK5-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK5-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK5-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK5-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK5-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK5-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK5-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK5-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK5-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK5-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK5-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK5-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK5-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK5-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK5-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK5-NEXT: ret i32 [[ADD9]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK5-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK5-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK5-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK5-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK5-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK5-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP4]] +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK6-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK6-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK6-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK6-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK6-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK6-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK6-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK6-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK6-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK6: .cancel.exit: +// CHECK6-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK6: .cancel.continue: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK6-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK6-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK6-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK6-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK6-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK6-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double // CHECK6-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK6-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK6-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK6-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK6-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK6-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK6-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK6-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK6-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK6-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK6-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK6-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK6-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK6-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK6-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK6-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK6-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK6-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK6-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK6-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK6-NEXT: ret i32 [[TMP18]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK6-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK6-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK6-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK6-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK6-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK6-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK6-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK6-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK6-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK6-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK6-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK6-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK6-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK6-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK6-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK6-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK6-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK6-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK6-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK6-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK6-NEXT: ret i32 [[ADD9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK6-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK6-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK6-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK6-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK6-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK6-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP4]] +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK7-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK7-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK7-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK7: .cancel.exit: +// CHECK7-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK7: .cancel.continue: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK7-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK7-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK7-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK7-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK7-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK7-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 // CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK7-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK7-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK7-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK7-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK7-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK7-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK7-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK7-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK7-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK7-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK7-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK7-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK7-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK7-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK7-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK7-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK7-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK7-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK7-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK7-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK7-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK7-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK7-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK7-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK7-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK7-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK7-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 // CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK7-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK7-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK7-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK7-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 // CHECK7-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK7-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK7-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK7-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK7-NEXT: ret i32 [[TMP16]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK7-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK7-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK7-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK7-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK7-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK7-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK7-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 // CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK7-NEXT: store double [[INC]], double* [[A3]], align 4 // CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK7-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] +// CHECK7-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 // CHECK7-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK7-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK7-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK7-NEXT: ret i32 [[ADD9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK7-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK7-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK7-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP4]] +// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK7-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK8-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK8-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK8-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK8-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK8: .cancel.exit: +// CHECK8-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK8: .cancel.continue: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK8-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK8-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK8-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK8-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK8-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK8-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 // CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK8-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK8-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK8-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK8-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK8-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK8-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK8-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK8-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK8-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK8-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK8-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK8-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK8-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK8-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK8-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK8-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK8-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK8-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK8-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK8-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK8-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK8-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK8-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK8-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK8-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK8-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK8-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK8-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK8-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK8-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 // CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK8-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK8-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK8-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK8-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 // CHECK8-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK8-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK8-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK8-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK8-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK8-NEXT: ret i32 [[TMP16]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK8-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK8-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK8-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK8-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK8-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK8-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK8-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK8-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK8-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK8-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK8-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 // CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK8-NEXT: store double [[INC]], double* [[A3]], align 4 // CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK8-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] +// CHECK8-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] // CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 // CHECK8-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK8-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK8-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK8-NEXT: ret i32 [[ADD9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK8-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK8-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK8-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP4]] +// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK8-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] +// CHECK9-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK9-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK9-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* +// CHECK9-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 +// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* +// CHECK9-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 +// CHECK9-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK9-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK9-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 +// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* +// CHECK9-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK9-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP38]], align 8 +// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK9-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] +// CHECK9: omp_offload.failed10: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT11]] +// CHECK9: omp_offload.cont11: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK9-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 +// CHECK9-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 +// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] +// CHECK9: omp_if.then15: +// CHECK9-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK9-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK9-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 +// CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64* +// CHECK9-NEXT: store i64 [[TMP44]], i64* [[TMP50]], align 8 +// CHECK9-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* +// CHECK9-NEXT: store i64 [[TMP44]], i64* [[TMP52]], align 8 +// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP53]], align 8 +// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP54]], align 8 +// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** +// CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 +// CHECK9-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** +// CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 +// CHECK9-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 40, i64* [[TMP59]], align 8 +// CHECK9-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP60]], align 8 +// CHECK9-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP62]], align 8 +// CHECK9-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP64]], align 8 +// CHECK9-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP65]], align 8 +// CHECK9-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP66]], align 8 +// CHECK9-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** +// CHECK9-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 +// CHECK9-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** +// CHECK9-NEXT: store float* [[VLA]], float** [[TMP70]], align 8 +// CHECK9-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK9-NEXT: store i64 [[TMP46]], i64* [[TMP71]], align 8 +// CHECK9-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP72]], align 8 +// CHECK9-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** +// CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 +// CHECK9-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** +// CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8 +// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK9-NEXT: store i64 400, i64* [[TMP77]], align 8 +// CHECK9-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP78]], align 8 +// CHECK9-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* +// CHECK9-NEXT: store i64 5, i64* [[TMP80]], align 8 +// CHECK9-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* +// CHECK9-NEXT: store i64 5, i64* [[TMP82]], align 8 +// CHECK9-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK9-NEXT: store i64 8, i64* [[TMP83]], align 8 +// CHECK9-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 +// CHECK9-NEXT: store i8* null, i8** [[TMP84]], align 8 +// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP86]], align 8 +// CHECK9-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP88]], align 8 +// CHECK9-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK9-NEXT: store i64 8, i64* [[TMP89]], align 8 +// CHECK9-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 +// CHECK9-NEXT: store i8* null, i8** [[TMP90]], align 8 +// CHECK9-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** +// CHECK9-NEXT: store double* [[VLA1]], double** [[TMP92]], align 8 +// CHECK9-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** +// CHECK9-NEXT: store double* [[VLA1]], double** [[TMP94]], align 8 +// CHECK9-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK9-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 8 +// CHECK9-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 +// CHECK9-NEXT: store i8* null, i8** [[TMP96]], align 8 +// CHECK9-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** +// CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8 +// CHECK9-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** +// CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8 +// CHECK9-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK9-NEXT: store i64 16, i64* [[TMP101]], align 8 +// CHECK9-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 +// CHECK9-NEXT: store i8* null, i8** [[TMP102]], align 8 +// CHECK9-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 +// CHECK9-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] +// CHECK9: omp_offload.failed19: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT20]] +// CHECK9: omp_offload.cont20: +// CHECK9-NEXT: br label [[OMP_IF_END22:%.*]] +// CHECK9: omp_if.else21: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END22]] +// CHECK9: omp_if.end22: +// CHECK9-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) +// CHECK9-NEXT: ret i32 [[TMP108]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: () #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK9-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK9-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK9-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20 +// CHECK9-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] +// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK9-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK9: omp_offload.failed.i: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]] +// CHECK9-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK9: .omp_outlined..1.exit: +// CHECK9-NEXT: ret i32 0 +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 +// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -5269,12 +6319,12 @@ // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5300,7 +6350,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -5318,12 +6368,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5347,7 +6397,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -5381,12 +6431,12 @@ // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5458,81 +6508,307 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@_Z3bari +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK9-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP8]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK9-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK9-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK9-NEXT: store double* [[A]], double** [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 8, i64* [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 4, i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK9-NEXT: store i64 2, i64* [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK9-NEXT: store i64 2, i64* [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK9-NEXT: store i64 8, i64* [[TMP32]], align 8 +// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK9-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK9-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 +// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK9-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] +// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK9-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] +// CHECK9-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK9-NEXT: ret i32 [[ADD4]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK9-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP31]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: ret void +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK9-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP24]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -5554,12 +6830,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5597,82 +6873,472 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: ret void -// -// +// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK10-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK10-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK10-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK10-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR3:[0-9]+]] +// CHECK10-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK10-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* +// CHECK10-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* +// CHECK10-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 +// CHECK10-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK10-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK10-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 +// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* +// CHECK10-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK10-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP38]], align 8 +// CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK10-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] +// CHECK10: omp_offload.failed10: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT11]] +// CHECK10: omp_offload.cont11: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK10-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 +// CHECK10-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 +// CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] +// CHECK10: omp_if.then15: +// CHECK10-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK10-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK10-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 +// CHECK10-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64* +// CHECK10-NEXT: store i64 [[TMP44]], i64* [[TMP50]], align 8 +// CHECK10-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* +// CHECK10-NEXT: store i64 [[TMP44]], i64* [[TMP52]], align 8 +// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP53]], align 8 +// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP54]], align 8 +// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 +// CHECK10-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 +// CHECK10-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 40, i64* [[TMP59]], align 8 +// CHECK10-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP60]], align 8 +// CHECK10-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP62]], align 8 +// CHECK10-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP64]], align 8 +// CHECK10-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP65]], align 8 +// CHECK10-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP66]], align 8 +// CHECK10-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** +// CHECK10-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 +// CHECK10-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** +// CHECK10-NEXT: store float* [[VLA]], float** [[TMP70]], align 8 +// CHECK10-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK10-NEXT: store i64 [[TMP46]], i64* [[TMP71]], align 8 +// CHECK10-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP72]], align 8 +// CHECK10-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 +// CHECK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8 +// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK10-NEXT: store i64 400, i64* [[TMP77]], align 8 +// CHECK10-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP78]], align 8 +// CHECK10-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* +// CHECK10-NEXT: store i64 5, i64* [[TMP80]], align 8 +// CHECK10-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* +// CHECK10-NEXT: store i64 5, i64* [[TMP82]], align 8 +// CHECK10-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK10-NEXT: store i64 8, i64* [[TMP83]], align 8 +// CHECK10-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 +// CHECK10-NEXT: store i8* null, i8** [[TMP84]], align 8 +// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP86]], align 8 +// CHECK10-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP88]], align 8 +// CHECK10-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK10-NEXT: store i64 8, i64* [[TMP89]], align 8 +// CHECK10-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 +// CHECK10-NEXT: store i8* null, i8** [[TMP90]], align 8 +// CHECK10-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** +// CHECK10-NEXT: store double* [[VLA1]], double** [[TMP92]], align 8 +// CHECK10-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** +// CHECK10-NEXT: store double* [[VLA1]], double** [[TMP94]], align 8 +// CHECK10-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK10-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 8 +// CHECK10-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 +// CHECK10-NEXT: store i8* null, i8** [[TMP96]], align 8 +// CHECK10-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 +// CHECK10-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8 +// CHECK10-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 +// CHECK10-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8 +// CHECK10-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK10-NEXT: store i64 16, i64* [[TMP101]], align 8 +// CHECK10-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 +// CHECK10-NEXT: store i8* null, i8** [[TMP102]], align 8 +// CHECK10-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 +// CHECK10-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] +// CHECK10: omp_offload.failed19: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT20]] +// CHECK10: omp_offload.cont20: +// CHECK10-NEXT: br label [[OMP_IF_END22:%.*]] +// CHECK10: omp_if.else21: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END22]] +// CHECK10: omp_if.end22: +// CHECK10-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) +// CHECK10-NEXT: ret i32 [[TMP108]] +// +// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: () #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK10-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK10-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK10-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20 +// CHECK10-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] +// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK10-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK10: omp_offload.failed.i: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]] +// CHECK10-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK10: .omp_outlined..1.exit: +// CHECK10-NEXT: ret i32 0 +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 +// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -5682,12 +7348,12 @@ // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5713,7 +7379,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -5731,12 +7397,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5760,7 +7426,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -5794,12 +7460,12 @@ // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5871,81 +7537,307 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@_Z3bari +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK10-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP8]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK10-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK10-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK10-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK10-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK10-NEXT: store double* [[A]], double** [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 8, i64* [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 4, i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK10-NEXT: store i64 2, i64* [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK10-NEXT: store i64 2, i64* [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK10-NEXT: store i64 8, i64* [[TMP32]], align 8 +// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK10-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK10-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 +// CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK10-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] +// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK10-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] +// CHECK10-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK10-NEXT: ret i32 [[ADD4]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP31]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: ret void +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK10-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP24]] // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -5967,12 +7859,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6010,8 +7902,81 @@ // CHECK10-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: ret void +// +// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -6032,12 +7997,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6067,25 +8032,336 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK10-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK11-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* +// CHECK11-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK11-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK11-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP31]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* +// CHECK11-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* +// CHECK11-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 +// CHECK11-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] +// CHECK11: omp_offload.failed8: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT9]] +// CHECK11: omp_offload.cont9: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 +// CHECK11-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 +// CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 +// CHECK11-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] +// CHECK11: omp_if.then12: +// CHECK11-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK11-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 +// CHECK11-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK11-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 +// CHECK11-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 +// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32* +// CHECK11-NEXT: store i32 [[TMP42]], i32* [[TMP50]], align 4 +// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* +// CHECK11-NEXT: store i32 [[TMP42]], i32* [[TMP52]], align 4 +// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP53]], align 4 +// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** +// CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 +// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** +// CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 +// CHECK11-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 40, i64* [[TMP59]], align 4 +// CHECK11-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP60]], align 4 +// CHECK11-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP62]], align 4 +// CHECK11-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP64]], align 4 +// CHECK11-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP65]], align 4 +// CHECK11-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP66]], align 4 +// CHECK11-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** +// CHECK11-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 +// CHECK11-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** +// CHECK11-NEXT: store float* [[VLA]], float** [[TMP70]], align 4 +// CHECK11-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK11-NEXT: store i64 [[TMP45]], i64* [[TMP71]], align 4 +// CHECK11-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP72]], align 4 +// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** +// CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 +// CHECK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** +// CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4 +// CHECK11-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK11-NEXT: store i64 400, i64* [[TMP77]], align 4 +// CHECK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP78]], align 4 +// CHECK11-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* +// CHECK11-NEXT: store i32 5, i32* [[TMP80]], align 4 +// CHECK11-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* +// CHECK11-NEXT: store i32 5, i32* [[TMP82]], align 4 +// CHECK11-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK11-NEXT: store i64 4, i64* [[TMP83]], align 4 +// CHECK11-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 +// CHECK11-NEXT: store i8* null, i8** [[TMP84]], align 4 +// CHECK11-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP86]], align 4 +// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP88]], align 4 +// CHECK11-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK11-NEXT: store i64 4, i64* [[TMP89]], align 4 +// CHECK11-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 +// CHECK11-NEXT: store i8* null, i8** [[TMP90]], align 4 +// CHECK11-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** +// CHECK11-NEXT: store double* [[VLA1]], double** [[TMP92]], align 4 +// CHECK11-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** +// CHECK11-NEXT: store double* [[VLA1]], double** [[TMP94]], align 4 +// CHECK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK11-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 4 +// CHECK11-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 +// CHECK11-NEXT: store i8* null, i8** [[TMP96]], align 4 +// CHECK11-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** +// CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4 +// CHECK11-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** +// CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4 +// CHECK11-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK11-NEXT: store i64 12, i64* [[TMP101]], align 4 +// CHECK11-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 +// CHECK11-NEXT: store i8* null, i8** [[TMP102]], align 4 +// CHECK11-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 +// CHECK11-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK11: omp_offload.failed16: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK11: omp_offload.cont17: +// CHECK11-NEXT: br label [[OMP_IF_END19:%.*]] +// CHECK11: omp_if.else18: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END19]] +// CHECK11: omp_if.end19: +// CHECK11-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) +// CHECK11-NEXT: ret i32 [[TMP108]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK11-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK11-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK11-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK11-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK11-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] +// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK11-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK11: omp_offload.failed.i: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]] +// CHECK11-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK11: .omp_outlined..1.exit: +// CHECK11-NEXT: ret i32 0 +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 +// CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -6095,12 +8371,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6126,7 +8402,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6142,12 +8418,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6170,7 +8446,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -6202,12 +8478,12 @@ // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6278,78 +8554,304 @@ // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@_Z3bari +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP8]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK11-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK11-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK11-NEXT: store double* [[A]], double** [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 8, i64* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK11-NEXT: store i32 2, i32* [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK11-NEXT: store i32 2, i32* [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK11-NEXT: store i64 4, i64* [[TMP32]], align 4 +// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK11-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK11-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 +// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK11-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK11-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] +// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK11-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] +// CHECK11-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK11-NEXT: ret i32 [[ADD3]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK11-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP31]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 -// CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: ret void +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK11-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP24]] // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -6369,12 +8871,12 @@ // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6411,8 +8913,78 @@ // CHECK11-NEXT: ret void // // +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6431,12 +9003,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6465,25 +9037,336 @@ // CHECK11-NEXT: ret void // // +// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK11-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK12-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK12-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR3:[0-9]+]] +// CHECK12-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK12-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* +// CHECK12-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK12-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK12-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP31]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* +// CHECK12-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* +// CHECK12-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 +// CHECK12-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] +// CHECK12: omp_offload.failed8: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT9]] +// CHECK12: omp_offload.cont9: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 +// CHECK12-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 +// CHECK12-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 +// CHECK12-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] +// CHECK12: omp_if.then12: +// CHECK12-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK12-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 +// CHECK12-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK12-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 +// CHECK12-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 +// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32* +// CHECK12-NEXT: store i32 [[TMP42]], i32* [[TMP50]], align 4 +// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* +// CHECK12-NEXT: store i32 [[TMP42]], i32* [[TMP52]], align 4 +// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP53]], align 4 +// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 +// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 +// CHECK12-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 40, i64* [[TMP59]], align 4 +// CHECK12-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP60]], align 4 +// CHECK12-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP62]], align 4 +// CHECK12-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP64]], align 4 +// CHECK12-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP65]], align 4 +// CHECK12-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP66]], align 4 +// CHECK12-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** +// CHECK12-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 +// CHECK12-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** +// CHECK12-NEXT: store float* [[VLA]], float** [[TMP70]], align 4 +// CHECK12-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK12-NEXT: store i64 [[TMP45]], i64* [[TMP71]], align 4 +// CHECK12-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP72]], align 4 +// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 +// CHECK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4 +// CHECK12-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK12-NEXT: store i64 400, i64* [[TMP77]], align 4 +// CHECK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP78]], align 4 +// CHECK12-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* +// CHECK12-NEXT: store i32 5, i32* [[TMP80]], align 4 +// CHECK12-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* +// CHECK12-NEXT: store i32 5, i32* [[TMP82]], align 4 +// CHECK12-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK12-NEXT: store i64 4, i64* [[TMP83]], align 4 +// CHECK12-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 +// CHECK12-NEXT: store i8* null, i8** [[TMP84]], align 4 +// CHECK12-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP86]], align 4 +// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP88]], align 4 +// CHECK12-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK12-NEXT: store i64 4, i64* [[TMP89]], align 4 +// CHECK12-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 +// CHECK12-NEXT: store i8* null, i8** [[TMP90]], align 4 +// CHECK12-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** +// CHECK12-NEXT: store double* [[VLA1]], double** [[TMP92]], align 4 +// CHECK12-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** +// CHECK12-NEXT: store double* [[VLA1]], double** [[TMP94]], align 4 +// CHECK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK12-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 4 +// CHECK12-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 +// CHECK12-NEXT: store i8* null, i8** [[TMP96]], align 4 +// CHECK12-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 +// CHECK12-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4 +// CHECK12-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 +// CHECK12-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4 +// CHECK12-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK12-NEXT: store i64 12, i64* [[TMP101]], align 4 +// CHECK12-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 +// CHECK12-NEXT: store i8* null, i8** [[TMP102]], align 4 +// CHECK12-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 +// CHECK12-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK12: omp_offload.failed16: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK12: omp_offload.cont17: +// CHECK12-NEXT: br label [[OMP_IF_END19:%.*]] +// CHECK12: omp_if.else18: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END19]] +// CHECK12: omp_if.end19: +// CHECK12-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) +// CHECK12-NEXT: ret i32 [[TMP108]] +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: () #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK12-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK12-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK12-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK12-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] +// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK12-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK12: omp_offload.failed.i: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]] +// CHECK12-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK12: .omp_outlined..1.exit: +// CHECK12-NEXT: ret i32 0 +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 +// CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -6493,12 +9376,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6524,7 +9407,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6540,12 +9423,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6568,7 +9451,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -6600,12 +9483,12 @@ // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6676,78 +9559,304 @@ // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@_Z3bari +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP8]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK12-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK12-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK12-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK12-NEXT: store double* [[A]], double** [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 8, i64* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK12-NEXT: store i32 2, i32* [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK12-NEXT: store i32 2, i32* [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK12-NEXT: store i64 4, i64* [[TMP32]], align 4 +// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK12-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK12-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 +// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK12-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK12-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] +// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK12-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] +// CHECK12-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK12-NEXT: ret i32 [[ADD3]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK12-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK12-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP31]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 -// CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: ret void +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK12-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP24]] // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -6767,12 +9876,12 @@ // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6809,8 +9918,78 @@ // CHECK12-NEXT: ret void // // +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: ret void +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6829,12 +10008,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6863,8338 +10042,1631 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK12-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK13-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK13-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK13-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK13-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK13: .cancel.exit: +// CHECK13-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK13: .cancel.continue: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK13-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK13-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK13-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK13-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK13-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK13-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK13-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK13-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK13-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK13-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK13-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double // CHECK13-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK13-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK13-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK13-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK13-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK13-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK13-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK13-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK13-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK13-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK13-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK13-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK13-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK13-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK13-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK13-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK13-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK13-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK13-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK13-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK13-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK13-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK13-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK13-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK13-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK13-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK13-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK13-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK13-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK13-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK13-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK13-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP8]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK13-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK13-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK13-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK13-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK13-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK13-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK13-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK13-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK13-NEXT: ret i32 [[ADD9]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK13-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK13-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK13-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK13-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK13-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK13-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP4]] +// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK13-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK14-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK14-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK14-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK14-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK14: .cancel.exit: +// CHECK14-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK14: .cancel.continue: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK14-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK14-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK14-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK14-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK14-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK14-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK14-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK14-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK14-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK14-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK14-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK14-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double // CHECK14-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK14-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK14-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK14-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK14-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK14-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK14-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK14-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK14-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK14-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK14-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK14-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK14-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK14-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK14-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK14-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK14-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK14-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK14-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK14-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK14-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK14-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK14-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK14-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK14-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK14-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK14-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK14-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK14-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK14-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK14-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK14-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK14-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK14-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK14-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK14-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK14-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP8]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK14-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK14-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK14-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK14-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK14-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK14-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK14-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK14-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK14-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK14-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK14-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK14-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK14-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK14-NEXT: ret i32 [[ADD9]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK14-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK14-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK14-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK14-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK14-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK14-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK14-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP4]] +// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK14-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: ret void // // -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK15-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK15-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK15-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK15-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK15: .cancel.exit: +// CHECK15-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK15: .cancel.continue: +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK15-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK15-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK15-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK15-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK15-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 // CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK15-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK15-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK15-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK15-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK15-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK15-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK15-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK15-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK15-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK15-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK15-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK15-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK15-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK15-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK15-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK15-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK15-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK15-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK15-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK15-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK15-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK15-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK15-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK15-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK15-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK15-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK15-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK15-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK15-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK15-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK15-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK15-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK15-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 // CHECK15-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK15-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK15-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK15-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK15-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK15-NEXT: ret i32 [[TMP16]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK15-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK15-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK15-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK15-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK15-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK15-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK15-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK15-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK15-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK15-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK15-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK15-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK15-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 // CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK15-NEXT: store double [[INC]], double* [[A3]], align 4 // CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK15-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] +// CHECK15-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 // CHECK15-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK15-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK15-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK15-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK15-NEXT: ret i32 [[ADD9]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK15-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK15-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP4]] +// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK15-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: ret void // // -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK16-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK16-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK16-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK16-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK16-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK16: .cancel.exit: +// CHECK16-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK16: .cancel.continue: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK16-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK16-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK16-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK16-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK16-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK16-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 // CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK16-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK16-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK16-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK16-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK16-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK16-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK16-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK16-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK16-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK16-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK16-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK16-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK16-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK16-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK16-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK16-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK16-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK16-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK16-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK16-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK16-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK16-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK16-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK16-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK16-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK16-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK16-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK16-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK16-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK16-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK16-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK16-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK16-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK16-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK16-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 // CHECK16-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK16-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK16-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK16-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK16-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 // CHECK16-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK16-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK16-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK16-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK16-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK16-NEXT: ret i32 [[TMP16]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK16-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK16-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK16-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK16-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK16-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK16-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK16-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK16-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK16-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK16-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK16-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK16-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK16-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 // CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK16-NEXT: store double [[INC]], double* [[A3]], align 4 // CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK16-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] +// CHECK16-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] // CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 // CHECK16-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK16-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK16-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK16-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK16-NEXT: ret i32 [[ADD9]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK16-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP4]] +// CHECK16-NEXT: ret void // // -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 -// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* -// CHECK17-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 -// CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* -// CHECK17-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 -// CHECK17-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK17-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK17-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 -// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* -// CHECK17-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK17-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP38]], align 8 -// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 -// CHECK17-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] -// CHECK17: omp_offload.failed10: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT11]] -// CHECK17: omp_offload.cont11: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* -// CHECK17-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 -// CHECK17-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 -// CHECK17-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 -// CHECK17-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] -// CHECK17: omp_if.then15: -// CHECK17-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 -// CHECK17-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK17-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 -// CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64* -// CHECK17-NEXT: store i64 [[TMP44]], i64* [[TMP50]], align 8 -// CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* -// CHECK17-NEXT: store i64 [[TMP44]], i64* [[TMP52]], align 8 -// CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP53]], align 8 -// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP54]], align 8 -// CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 -// CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 -// CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 40, i64* [[TMP59]], align 8 -// CHECK17-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP60]], align 8 -// CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP62]], align 8 -// CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP64]], align 8 -// CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP65]], align 8 -// CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP66]], align 8 -// CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** -// CHECK17-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 -// CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** -// CHECK17-NEXT: store float* [[VLA]], float** [[TMP70]], align 8 -// CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK17-NEXT: store i64 [[TMP46]], i64* [[TMP71]], align 8 -// CHECK17-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP72]], align 8 -// CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 -// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8 -// CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK17-NEXT: store i64 400, i64* [[TMP77]], align 8 -// CHECK17-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP78]], align 8 -// CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* -// CHECK17-NEXT: store i64 5, i64* [[TMP80]], align 8 -// CHECK17-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* -// CHECK17-NEXT: store i64 5, i64* [[TMP82]], align 8 -// CHECK17-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK17-NEXT: store i64 8, i64* [[TMP83]], align 8 -// CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 -// CHECK17-NEXT: store i8* null, i8** [[TMP84]], align 8 -// CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP86]], align 8 -// CHECK17-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP88]], align 8 -// CHECK17-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK17-NEXT: store i64 8, i64* [[TMP89]], align 8 -// CHECK17-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 -// CHECK17-NEXT: store i8* null, i8** [[TMP90]], align 8 -// CHECK17-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** -// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP92]], align 8 -// CHECK17-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** -// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP94]], align 8 -// CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK17-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 8 -// CHECK17-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 -// CHECK17-NEXT: store i8* null, i8** [[TMP96]], align 8 -// CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 -// CHECK17-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8 -// CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 -// CHECK17-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8 -// CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK17-NEXT: store i64 16, i64* [[TMP101]], align 8 -// CHECK17-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 -// CHECK17-NEXT: store i8* null, i8** [[TMP102]], align 8 -// CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 -// CHECK17-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] -// CHECK17: omp_offload.failed19: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT20]] -// CHECK17: omp_offload.cont20: -// CHECK17-NEXT: br label [[OMP_IF_END22:%.*]] -// CHECK17: omp_if.else21: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END22]] -// CHECK17: omp_if.end22: -// CHECK17-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) -// CHECK17-NEXT: ret i32 [[TMP108]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK17-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK17-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20 -// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] -// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK17: omp_offload.failed.i: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]] -// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK17: .omp_outlined..1.exit: -// CHECK17-NEXT: ret i32 0 -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) -// CHECK17-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK17-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK17: .cancel.exit: -// CHECK17-NEXT: br label [[DOTCANCEL_CONTINUE]] -// CHECK17: .cancel.continue: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double -// CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 -// CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float -// CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double -// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 -// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 -// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK17-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] -// CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 -// CHECK17-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK17-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 -// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 -// CHECK17-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK17-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 -// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK17-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 -// CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 -// CHECK17-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP8]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK17-NEXT: store double* [[A]], double** [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 8, i64* [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 4, i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK17-NEXT: store i64 2, i64* [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK17-NEXT: store i64 2, i64* [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8 -// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 -// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK17-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] -// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK17-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK17-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] -// CHECK17-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK17-NEXT: ret i32 [[ADD4]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP31]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP24]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 -// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK17-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] -// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK17-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR3:[0-9]+]] -// CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 -// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* -// CHECK18-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 -// CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* -// CHECK18-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 -// CHECK18-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK18-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK18-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 -// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* -// CHECK18-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK18-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP38]], align 8 -// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 -// CHECK18-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] -// CHECK18: omp_offload.failed10: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT11]] -// CHECK18: omp_offload.cont11: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* -// CHECK18-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 -// CHECK18-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 -// CHECK18-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 -// CHECK18-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] -// CHECK18: omp_if.then15: -// CHECK18-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 -// CHECK18-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK18-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 -// CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64* -// CHECK18-NEXT: store i64 [[TMP44]], i64* [[TMP50]], align 8 -// CHECK18-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* -// CHECK18-NEXT: store i64 [[TMP44]], i64* [[TMP52]], align 8 -// CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP53]], align 8 -// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP54]], align 8 -// CHECK18-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 -// CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 -// CHECK18-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 40, i64* [[TMP59]], align 8 -// CHECK18-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP60]], align 8 -// CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP62]], align 8 -// CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP64]], align 8 -// CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP65]], align 8 -// CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP66]], align 8 -// CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** -// CHECK18-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 -// CHECK18-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** -// CHECK18-NEXT: store float* [[VLA]], float** [[TMP70]], align 8 -// CHECK18-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK18-NEXT: store i64 [[TMP46]], i64* [[TMP71]], align 8 -// CHECK18-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP72]], align 8 -// CHECK18-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 -// CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8 -// CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK18-NEXT: store i64 400, i64* [[TMP77]], align 8 -// CHECK18-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP78]], align 8 -// CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* -// CHECK18-NEXT: store i64 5, i64* [[TMP80]], align 8 -// CHECK18-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* -// CHECK18-NEXT: store i64 5, i64* [[TMP82]], align 8 -// CHECK18-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK18-NEXT: store i64 8, i64* [[TMP83]], align 8 -// CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 -// CHECK18-NEXT: store i8* null, i8** [[TMP84]], align 8 -// CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP86]], align 8 -// CHECK18-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP88]], align 8 -// CHECK18-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK18-NEXT: store i64 8, i64* [[TMP89]], align 8 -// CHECK18-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 -// CHECK18-NEXT: store i8* null, i8** [[TMP90]], align 8 -// CHECK18-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** -// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP92]], align 8 -// CHECK18-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** -// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP94]], align 8 -// CHECK18-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK18-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 8 -// CHECK18-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 -// CHECK18-NEXT: store i8* null, i8** [[TMP96]], align 8 -// CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 -// CHECK18-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8 -// CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 -// CHECK18-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8 -// CHECK18-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK18-NEXT: store i64 16, i64* [[TMP101]], align 8 -// CHECK18-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 -// CHECK18-NEXT: store i8* null, i8** [[TMP102]], align 8 -// CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 -// CHECK18-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] -// CHECK18: omp_offload.failed19: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT20]] -// CHECK18: omp_offload.cont20: -// CHECK18-NEXT: br label [[OMP_IF_END22:%.*]] -// CHECK18: omp_if.else21: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END22]] -// CHECK18: omp_if.end22: -// CHECK18-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) -// CHECK18-NEXT: ret i32 [[TMP108]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK18-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK18-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20 -// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] -// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK18: omp_offload.failed.i: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]] -// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK18: .omp_outlined..1.exit: -// CHECK18-NEXT: ret i32 0 -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) -// CHECK18-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK18-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK18: .cancel.exit: -// CHECK18-NEXT: br label [[DOTCANCEL_CONTINUE]] -// CHECK18: .cancel.continue: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double -// CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 -// CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float -// CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double -// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 -// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK18-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 -// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK18-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK18-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] -// CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 -// CHECK18-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK18-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 -// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 -// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK18-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 -// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK18-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 -// CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 -// CHECK18-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP8]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK18-NEXT: store double* [[A]], double** [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 8, i64* [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 4, i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK18-NEXT: store i64 2, i64* [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK18-NEXT: store i64 2, i64* [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8 -// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 -// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK18-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] -// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK18-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK18-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] -// CHECK18-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK18-NEXT: ret i32 [[ADD4]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP31]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP24]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 -// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK18-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] -// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK18-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR3:[0-9]+]] -// CHECK19-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK19-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* -// CHECK19-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 -// CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK19-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK19-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP31]], align 4 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* -// CHECK19-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* -// CHECK19-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 -// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 -// CHECK19-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] -// CHECK19: omp_offload.failed8: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT9]] -// CHECK19: omp_offload.cont9: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 -// CHECK19-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 -// CHECK19-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 -// CHECK19-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] -// CHECK19: omp_if.then12: -// CHECK19-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 -// CHECK19-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 -// CHECK19-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK19-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 -// CHECK19-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 -// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32* -// CHECK19-NEXT: store i32 [[TMP42]], i32* [[TMP50]], align 4 -// CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* -// CHECK19-NEXT: store i32 [[TMP42]], i32* [[TMP52]], align 4 -// CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP53]], align 4 -// CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 -// CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 -// CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 40, i64* [[TMP59]], align 4 -// CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP60]], align 4 -// CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP62]], align 4 -// CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP64]], align 4 -// CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP65]], align 4 -// CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP66]], align 4 -// CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** -// CHECK19-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 -// CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** -// CHECK19-NEXT: store float* [[VLA]], float** [[TMP70]], align 4 -// CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK19-NEXT: store i64 [[TMP45]], i64* [[TMP71]], align 4 -// CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP72]], align 4 -// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 -// CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4 -// CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK19-NEXT: store i64 400, i64* [[TMP77]], align 4 -// CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP78]], align 4 -// CHECK19-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* -// CHECK19-NEXT: store i32 5, i32* [[TMP80]], align 4 -// CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* -// CHECK19-NEXT: store i32 5, i32* [[TMP82]], align 4 -// CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK19-NEXT: store i64 4, i64* [[TMP83]], align 4 -// CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 -// CHECK19-NEXT: store i8* null, i8** [[TMP84]], align 4 -// CHECK19-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP86]], align 4 -// CHECK19-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP88]], align 4 -// CHECK19-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK19-NEXT: store i64 4, i64* [[TMP89]], align 4 -// CHECK19-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 -// CHECK19-NEXT: store i8* null, i8** [[TMP90]], align 4 -// CHECK19-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** -// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP92]], align 4 -// CHECK19-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** -// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP94]], align 4 -// CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK19-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 4 -// CHECK19-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 -// CHECK19-NEXT: store i8* null, i8** [[TMP96]], align 4 -// CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 -// CHECK19-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4 -// CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 -// CHECK19-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4 -// CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK19-NEXT: store i64 12, i64* [[TMP101]], align 4 -// CHECK19-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 -// CHECK19-NEXT: store i8* null, i8** [[TMP102]], align 4 -// CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 -// CHECK19-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK19: omp_offload.failed16: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK19: omp_offload.cont17: -// CHECK19-NEXT: br label [[OMP_IF_END19:%.*]] -// CHECK19: omp_if.else18: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END19]] -// CHECK19: omp_if.end19: -// CHECK19-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) -// CHECK19-NEXT: ret i32 [[TMP108]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK19-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 -// CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK19-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] -// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK19: omp_offload.failed.i: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]] -// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK19: .omp_outlined..1.exit: -// CHECK19-NEXT: ret i32 0 -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) -// CHECK19-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK19-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK19: .cancel.exit: -// CHECK19-NEXT: br label [[DOTCANCEL_CONTINUE]] -// CHECK19: .cancel.continue: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double -// CHECK19-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK19-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float -// CHECK19-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK19-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK19-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double -// CHECK19-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 -// CHECK19-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float -// CHECK19-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 -// CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK19-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK19-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK19-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 -// CHECK19-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] -// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 -// CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK19-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK19-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 -// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK19-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK19-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 -// CHECK19-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 -// CHECK19-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP8]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 -// CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK19-NEXT: store double* [[A]], double** [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 8, i64* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK19-NEXT: store i32 2, i32* [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK19-NEXT: store i32 2, i32* [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK19-NEXT: store i64 4, i64* [[TMP32]], align 4 -// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 -// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK19-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK19-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK19-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] -// CHECK19-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK19-NEXT: ret i32 [[ADD3]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP31]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP24]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK19-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK19-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK19-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] -// CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK19-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 -// CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR3:[0-9]+]] -// CHECK20-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK20-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* -// CHECK20-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 -// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK20-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK20-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP31]], align 4 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* -// CHECK20-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* -// CHECK20-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 -// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 -// CHECK20-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] -// CHECK20: omp_offload.failed8: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT9]] -// CHECK20: omp_offload.cont9: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 -// CHECK20-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 -// CHECK20-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 -// CHECK20-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] -// CHECK20: omp_if.then12: -// CHECK20-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 -// CHECK20-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 -// CHECK20-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK20-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 -// CHECK20-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 -// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32* -// CHECK20-NEXT: store i32 [[TMP42]], i32* [[TMP50]], align 4 -// CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* -// CHECK20-NEXT: store i32 [[TMP42]], i32* [[TMP52]], align 4 -// CHECK20-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP53]], align 4 -// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 -// CHECK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 -// CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 40, i64* [[TMP59]], align 4 -// CHECK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP60]], align 4 -// CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP62]], align 4 -// CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP64]], align 4 -// CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP65]], align 4 -// CHECK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP66]], align 4 -// CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** -// CHECK20-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 -// CHECK20-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** -// CHECK20-NEXT: store float* [[VLA]], float** [[TMP70]], align 4 -// CHECK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK20-NEXT: store i64 [[TMP45]], i64* [[TMP71]], align 4 -// CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP72]], align 4 -// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 -// CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4 -// CHECK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK20-NEXT: store i64 400, i64* [[TMP77]], align 4 -// CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP78]], align 4 -// CHECK20-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* -// CHECK20-NEXT: store i32 5, i32* [[TMP80]], align 4 -// CHECK20-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* -// CHECK20-NEXT: store i32 5, i32* [[TMP82]], align 4 -// CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK20-NEXT: store i64 4, i64* [[TMP83]], align 4 -// CHECK20-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 -// CHECK20-NEXT: store i8* null, i8** [[TMP84]], align 4 -// CHECK20-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP86]], align 4 -// CHECK20-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP88]], align 4 -// CHECK20-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK20-NEXT: store i64 4, i64* [[TMP89]], align 4 -// CHECK20-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 -// CHECK20-NEXT: store i8* null, i8** [[TMP90]], align 4 -// CHECK20-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** -// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP92]], align 4 -// CHECK20-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** -// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP94]], align 4 -// CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK20-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 4 -// CHECK20-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 -// CHECK20-NEXT: store i8* null, i8** [[TMP96]], align 4 -// CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 -// CHECK20-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4 -// CHECK20-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 -// CHECK20-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4 -// CHECK20-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK20-NEXT: store i64 12, i64* [[TMP101]], align 4 -// CHECK20-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 -// CHECK20-NEXT: store i8* null, i8** [[TMP102]], align 4 -// CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 -// CHECK20-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK20: omp_offload.failed16: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK20: omp_offload.cont17: -// CHECK20-NEXT: br label [[OMP_IF_END19:%.*]] -// CHECK20: omp_if.else18: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END19]] -// CHECK20: omp_if.end19: -// CHECK20-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) -// CHECK20-NEXT: ret i32 [[TMP108]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK20-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 -// CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK20-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] -// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK20: omp_offload.failed.i: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]] -// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK20: .omp_outlined..1.exit: -// CHECK20-NEXT: ret i32 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) -// CHECK20-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK20-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK20: .cancel.exit: -// CHECK20-NEXT: br label [[DOTCANCEL_CONTINUE]] -// CHECK20: .cancel.continue: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double -// CHECK20-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK20-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float -// CHECK20-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK20-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK20-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double -// CHECK20-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 -// CHECK20-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float -// CHECK20-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 -// CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK20-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK20-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK20-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 -// CHECK20-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] -// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 -// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK20-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK20-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 -// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK20-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK20-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 -// CHECK20-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 -// CHECK20-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP8]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 -// CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK20-NEXT: store double* [[A]], double** [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 8, i64* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK20-NEXT: store i32 2, i32* [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK20-NEXT: store i32 2, i32* [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK20-NEXT: store i64 4, i64* [[TMP32]], align 4 -// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 -// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK20-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] -// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK20-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK20-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] -// CHECK20-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK20-NEXT: ret i32 [[ADD3]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP31]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP24]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK20-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK20-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK20-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] -// CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK20-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 -// CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK21-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK21-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK21-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK21-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK21-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK21-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK21-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK21-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK21-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK21-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK21-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK21-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK21-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK21-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK21-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK21-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK21-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK21-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK21-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK21-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK21-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK21-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK21-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK21-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK21-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK21-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK21-NEXT: ret i32 [[TMP18]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP8]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK21-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK21-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK21-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK21-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK21-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK21-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK21-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK21-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK21-NEXT: ret i32 [[ADD9]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK21-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP4]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK22-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK22-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK22-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK22-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK22-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK22-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK22-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK22-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK22-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK22-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK22-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK22-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK22-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK22-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK22-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK22-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK22-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK22-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK22-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK22-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK22-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK22-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK22-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK22-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK22-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK22-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK22-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK22-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK22-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK22-NEXT: ret i32 [[TMP18]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP8]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK22-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK22-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK22-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK22-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK22-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK22-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK22-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK22-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK22-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK22-NEXT: ret i32 [[ADD9]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK22-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK22-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP4]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK23-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK23-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK23-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK23-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK23-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK23-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK23-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK23-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK23-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK23-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK23-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK23-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK23-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK23-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK23-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK23-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK23-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK23-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK23-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK23-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK23-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK23-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK23-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK23-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK23-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK23-NEXT: ret i32 [[TMP16]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP8]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK23-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK23-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK23-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK23-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK23-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK23-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK23-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK23-NEXT: ret i32 [[ADD9]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK23-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP4]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK24-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK24-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK24-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK24-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK24-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK24-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK24-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK24-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK24-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK24-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK24-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK24-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK24-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK24-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK24-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK24-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK24-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK24-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK24-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK24-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK24-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK24-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK24-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK24-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK24-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK24-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK24-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK24-NEXT: ret i32 [[TMP16]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP8]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK24-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK24-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK24-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK24-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK24-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK24-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK24-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK24-NEXT: ret i32 [[ADD9]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK24-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP4]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK25-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK25-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) -// CHECK25-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK25-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK25: .cancel.exit: -// CHECK25-NEXT: br label [[DOTCANCEL_CONTINUE]] -// CHECK25: .cancel.continue: -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double -// CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 -// CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float -// CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double -// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 -// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK25-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 -// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK25-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 -// CHECK25-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK25-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] -// CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 -// CHECK25-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK25-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 -// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 -// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK25-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 -// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK25-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 -// CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 -// CHECK25-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 -// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK25-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] -// CHECK25-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK25-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK26-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK26-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) -// CHECK26-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK26-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK26: .cancel.exit: -// CHECK26-NEXT: br label [[DOTCANCEL_CONTINUE]] -// CHECK26: .cancel.continue: -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 -// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double -// CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 -// CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float -// CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double -// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 -// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK26-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 -// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK26-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 -// CHECK26-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK26-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] -// CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 -// CHECK26-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK26-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 -// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 -// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK26-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 -// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK26-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 -// CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 -// CHECK26-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 -// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK26-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] -// CHECK26-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK26-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK27-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) -// CHECK27-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK27-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK27: .cancel.exit: -// CHECK27-NEXT: br label [[DOTCANCEL_CONTINUE]] -// CHECK27: .cancel.continue: -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double -// CHECK27-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK27-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float -// CHECK27-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK27-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double -// CHECK27-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 -// CHECK27-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float -// CHECK27-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 -// CHECK27-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK27-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK27-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK27-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 -// CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] -// CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 -// CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK27-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK27-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 -// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK27-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK27-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 -// CHECK27-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 -// CHECK27-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 -// CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK27-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] -// CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK28-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) -// CHECK28-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK28-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK28: .cancel.exit: -// CHECK28-NEXT: br label [[DOTCANCEL_CONTINUE]] -// CHECK28: .cancel.continue: -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double -// CHECK28-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK28-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float -// CHECK28-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK28-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double -// CHECK28-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 -// CHECK28-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float -// CHECK28-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 -// CHECK28-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK28-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK28-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK28-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 -// CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] -// CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 -// CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK28-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK28-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 -// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK28-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK28-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 -// CHECK28-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 -// CHECK28-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 -// CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK28-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] -// CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK29-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK29-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK29-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK29-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK29-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK29-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK29-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK29-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK29-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK29-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK29-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK29-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK29-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK29-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK29-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK29-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK29-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK29-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK29-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK29-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK29-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK29-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK29-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK29-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK29-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK29-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK29-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK29-NEXT: ret i32 [[TMP18]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP8]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK29-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK29-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK29-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK29-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK29-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK29-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK29-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK29-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK29-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK29-NEXT: ret i32 [[ADD9]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK29-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK29-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP4]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK30-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK30-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK30-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK30-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK30-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK30-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK30-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK30-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK30-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK30-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK30-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK30-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK30-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK30-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK30-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK30-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK30-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK30-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK30-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK30-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK30-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK30-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK30-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK30-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK30-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK30-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK30-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK30-NEXT: ret i32 [[TMP18]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP8]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK30-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK30-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK30-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK30-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK30-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK30-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK30-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK30-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK30-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK30-NEXT: ret i32 [[ADD9]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK30-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK30-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP4]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK31-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK31-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK31-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK31-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK31-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK31-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK31-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK31-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK31-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK31-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK31-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK31-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK31-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK31-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK31-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK31-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK31-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK31-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK31-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK31-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK31-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK31-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK31-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK31-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK31-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK31-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK31-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK31-NEXT: ret i32 [[TMP16]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK31-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK31-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK31-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK31-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK31-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK31-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK31-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK31-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK31-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK31-NEXT: ret i32 [[ADD9]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK31-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK31-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP4]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK32-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK32-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK32-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK32-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK32-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK32-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK32-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK32-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK32-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK32-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK32-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK32-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK32-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK32-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK32-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK32-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK32-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK32-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK32-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK32-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK32-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK32-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK32-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK32-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK32-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK32-NEXT: ret i32 [[TMP16]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK32-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK32-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK32-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK32-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK32-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK32-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK32-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK32-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK32-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK32-NEXT: ret i32 [[ADD9]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK32-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK32-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP4]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK16-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK16-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK16-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: ret void // diff --git a/clang/test/OpenMP/target_parallel_for_codegen.cpp b/clang/test/OpenMP/target_parallel_for_codegen.cpp --- a/clang/test/OpenMP/target_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_codegen.cpp @@ -7,65 +7,65 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK26 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -6824,1457 +6824,3548 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: ret i64 0 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK5-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK5-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK5-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK5-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3:%.*]] -// CHECK5: for.cond3: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK5: for.body5: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end8: -// CHECK5-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK5-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK5-NEXT: br label [[FOR_COND9:%.*]] -// CHECK5: for.cond9: -// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK5-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK5-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK5: for.body11: -// CHECK5-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK5-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK5-NEXT: br label [[FOR_INC14:%.*]] -// CHECK5: for.inc14: -// CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK5-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 +// CHECK5-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK5-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK5-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK5: .cancel.exit: +// CHECK5-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK5: .cancel.continue: +// CHECK5-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK5-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK5-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK5: .cancel.exit2: +// CHECK5-NEXT: br label [[CANCEL_EXIT]] +// CHECK5: .cancel.continue3: +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK5-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK5: cancel.cont: +// CHECK5-NEXT: ret void +// CHECK5: cancel.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK5-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK5-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[LIN4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A5:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 +// CHECK5-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK5-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end15: -// CHECK5-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK5-NEXT: br label [[FOR_COND17:%.*]] -// CHECK5: for.cond17: -// CHECK5-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK5-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK5-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK5-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK5: for.body20: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK5-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK5-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK5-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK5-NEXT: br label [[FOR_INC25:%.*]] -// CHECK5: for.inc25: -// CHECK5-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK5-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK5-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK5-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK5-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK5-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK5: for.end29: -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK5-NEXT: br label [[FOR_COND31:%.*]] -// CHECK5: for.cond31: -// CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK5-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK5-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK5-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK5: for.body34: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK5-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK5-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK5-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK5-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK5-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK5-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK5-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK5-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK5-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK5-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK5-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK5-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK5-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK5-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK5-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK5-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK5-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK5-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK5-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK5-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK5-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK5-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK5-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK5-NEXT: br label [[FOR_INC53:%.*]] -// CHECK5: for.inc53: -// CHECK5-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK5-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK5-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK5-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK5-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK5-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK5: for.end57: -// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK5-NEXT: ret i32 [[TMP29]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK5-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] +// CHECK5-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK5-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK5-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK5-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] +// CHECK5-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 +// CHECK5-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 +// CHECK5-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK5-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK5: .omp.linear.pu: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK5-NEXT: [[CONV18:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK5-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP21]] +// CHECK5-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]] +// CHECK5-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32 +// CHECK5-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK5-NEXT: [[CONV22:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK5-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP23]] +// CHECK5-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]] +// CHECK5-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32 +// CHECK5-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8 +// CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK5: .omp.linear.pu.done: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK5-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: ret i64 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK5-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK5-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 +// CHECK5-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK5-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK5-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK5-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 +// CHECK5-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK5-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK5-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK5-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 +// CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 +// CHECK5-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK5-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK5-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK5-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 +// CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK5-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 +// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 +// CHECK5-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK5-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 +// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK5-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK5-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK5-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK5-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK5-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK5-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK5-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK5-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK5-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK5-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK5-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK5-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK5-NEXT: ret i32 [[ADD9]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK5-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 +// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK5-NEXT: store double [[INC]], double* [[A5]], align 8 +// CHECK5-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK5-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK5-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 +// CHECK5-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK5-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK5-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK5-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK5-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK5-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK5-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: ret i64 0 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK6-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK6-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK6-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK6-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK6-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end8: -// CHECK6-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK6-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK6-NEXT: br label [[FOR_COND9:%.*]] -// CHECK6: for.cond9: -// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK6-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK6-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK6: for.body11: -// CHECK6-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK6-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK6-NEXT: br label [[FOR_INC14:%.*]] -// CHECK6: for.inc14: -// CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK6-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 +// CHECK6-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK6-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK6-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK6: .cancel.exit: +// CHECK6-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK6: .cancel.continue: +// CHECK6-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK6-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK6-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK6: .cancel.exit2: +// CHECK6-NEXT: br label [[CANCEL_EXIT]] +// CHECK6: .cancel.continue3: +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK6-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK6: cancel.cont: +// CHECK6-NEXT: ret void +// CHECK6: cancel.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK6-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK6-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[LIN4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK6-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK6-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK6-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end15: -// CHECK6-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK6-NEXT: br label [[FOR_COND17:%.*]] -// CHECK6: for.cond17: -// CHECK6-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK6-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK6-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK6-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK6: for.body20: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK6-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK6-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK6-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK6-NEXT: br label [[FOR_INC25:%.*]] -// CHECK6: for.inc25: -// CHECK6-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK6-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK6-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK6-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK6-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK6-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK6: for.end29: -// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK6-NEXT: br label [[FOR_COND31:%.*]] -// CHECK6: for.cond31: -// CHECK6-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK6-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK6-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK6-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK6: for.body34: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK6-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK6-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK6-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK6-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK6-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK6-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK6-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK6-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK6-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK6-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK6-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK6-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK6-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK6-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK6-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK6-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK6-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK6-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK6-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK6-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK6-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK6-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK6-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK6-NEXT: br label [[FOR_INC53:%.*]] -// CHECK6: for.inc53: -// CHECK6-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK6-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK6-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK6-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK6-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK6-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK6: for.end57: -// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK6-NEXT: ret i32 [[TMP29]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK6-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK6-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] +// CHECK6-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK6-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK6-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK6-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] +// CHECK6-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 +// CHECK6-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK6-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 +// CHECK6-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK6-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK6: .omp.linear.pu: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK6-NEXT: [[CONV18:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK6-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP21]] +// CHECK6-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]] +// CHECK6-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32 +// CHECK6-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK6-NEXT: [[CONV22:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK6-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP23]] +// CHECK6-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]] +// CHECK6-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32 +// CHECK6-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8 +// CHECK6-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK6: .omp.linear.pu.done: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK6-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: ret i64 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK6-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK6-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 +// CHECK6-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK6-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK6-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK6-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK6-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK6-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 +// CHECK6-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK6-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK6-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK6-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 +// CHECK6-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK6-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 +// CHECK6-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK6-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK6-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK6-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK6-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 +// CHECK6-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK6-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 +// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 +// CHECK6-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK6-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 +// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK6-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK6-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK6-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK6-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK6-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK6-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK6-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK6-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK6-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK6-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK6-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK6-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK6-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK6-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK6-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK6-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK6-NEXT: ret i32 [[ADD9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK6-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 +// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK6-NEXT: store double [[INC]], double* [[A5]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK6-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK6-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 +// CHECK6-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK6-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK6-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK6-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK6-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK6-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK6-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: ret i64 0 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK7-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK7-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK7-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK7-NEXT: br label [[FOR_INC7:%.*]] -// CHECK7: for.inc7: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK7-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK7: for.body11: -// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK7-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK7-NEXT: br label [[FOR_INC14:%.*]] -// CHECK7: for.inc14: -// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK7-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 +// CHECK7-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK7-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK7-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK7: .cancel.exit: +// CHECK7-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK7: .cancel.continue: +// CHECK7-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK7-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK7-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK7: .cancel.exit2: +// CHECK7-NEXT: br label [[CANCEL_EXIT]] +// CHECK7: .cancel.continue3: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK7: cancel.cont: +// CHECK7-NEXT: ret void +// CHECK7: cancel.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK7-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[LIN2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK7-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end15: -// CHECK7-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK7-NEXT: br label [[FOR_COND17:%.*]] -// CHECK7: for.cond17: -// CHECK7-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK7-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK7-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK7-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK7: for.body20: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK7-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK7-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK7-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK7-NEXT: br label [[FOR_INC25:%.*]] -// CHECK7: for.inc25: -// CHECK7-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK7-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK7-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK7-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK7-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK7-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end29: -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK7-NEXT: br label [[FOR_COND31:%.*]] -// CHECK7: for.cond31: -// CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK7-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK7-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK7-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK7: for.body34: -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK7-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK7-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK7-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK7-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK7-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK7-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK7-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK7-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK7-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK7-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK7-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK7-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK7-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK7-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK7-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK7-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK7-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK7-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK7-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK7-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK7-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK7-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK7-NEXT: br label [[FOR_INC53:%.*]] -// CHECK7: for.inc53: -// CHECK7-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK7-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK7-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK7-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK7-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK7-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end57: -// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK7-NEXT: ret i32 [[TMP27]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK7-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK7-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] +// CHECK7-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK7-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK7-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] +// CHECK7-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 +// CHECK7-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 +// CHECK7-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK7-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK7: .omp.linear.pu: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK7-NEXT: [[CONV16:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK7-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP21]] +// CHECK7-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]] +// CHECK7-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32 +// CHECK7-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK7-NEXT: [[CONV20:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK7-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP23]] +// CHECK7-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]] +// CHECK7-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32 +// CHECK7-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK7: .omp.linear.pu.done: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK7-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: ret i64 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK7-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK7-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK7-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK7-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK7-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double +// CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK7-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK7-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK7-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 +// CHECK7-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK7-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 +// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK7-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK7-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK7-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 +// CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK7-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 +// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 +// CHECK7-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK7-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 +// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK7-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK7-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK7-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK7-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK7-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK7-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK7-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK7-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK7-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK7-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK7-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK7-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK7-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK7-NEXT: ret i32 [[ADD9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK7-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 +// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK7-NEXT: store double [[INC]], double* [[A4]], align 4 +// CHECK7-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK7-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK7-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 +// CHECK7-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK7-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK7-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK7-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK7-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP5]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK7-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: ret i64 0 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK8-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK8-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK8-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK8-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK8-NEXT: br label [[FOR_INC7:%.*]] -// CHECK8: for.inc7: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK8-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK8: for.body11: -// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK8-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK8-NEXT: br label [[FOR_INC14:%.*]] -// CHECK8: for.inc14: -// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK8-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 +// CHECK8-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK8-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK8-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK8: .cancel.exit: +// CHECK8-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK8: .cancel.continue: +// CHECK8-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK8-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK8-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK8: .cancel.exit2: +// CHECK8-NEXT: br label [[CANCEL_EXIT]] +// CHECK8: .cancel.continue3: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK8: cancel.cont: +// CHECK8-NEXT: ret void +// CHECK8: cancel.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK8-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK8-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[LIN2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK8-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK8-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK8-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end15: -// CHECK8-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK8-NEXT: br label [[FOR_COND17:%.*]] -// CHECK8: for.cond17: -// CHECK8-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK8-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK8-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK8-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK8: for.body20: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK8-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK8-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK8-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK8-NEXT: br label [[FOR_INC25:%.*]] -// CHECK8: for.inc25: -// CHECK8-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK8-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK8-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK8-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK8-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK8-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end29: -// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK8-NEXT: br label [[FOR_COND31:%.*]] -// CHECK8: for.cond31: -// CHECK8-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK8-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK8-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK8-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK8: for.body34: -// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK8-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK8-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK8-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK8-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK8-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK8-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK8-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK8-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK8-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK8-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK8-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK8-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK8-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK8-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK8-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK8-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK8-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK8-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK8-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK8-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK8-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK8-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK8-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK8-NEXT: br label [[FOR_INC53:%.*]] -// CHECK8: for.inc53: -// CHECK8-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK8-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK8-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK8-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK8-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK8-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end57: -// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK8-NEXT: ret i32 [[TMP27]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK8-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK8-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] +// CHECK8-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK8-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK8-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK8-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] +// CHECK8-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 +// CHECK8-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK8-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 +// CHECK8-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK8-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK8: .omp.linear.pu: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK8-NEXT: [[CONV16:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK8-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK8-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP21]] +// CHECK8-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]] +// CHECK8-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32 +// CHECK8-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK8-NEXT: [[CONV20:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK8-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK8-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP23]] +// CHECK8-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]] +// CHECK8-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32 +// CHECK8-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK8: .omp.linear.pu.done: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK8-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: ret i64 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK8-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK8-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK8-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK8-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK8-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK8-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double +// CHECK8-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK8-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK8-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK8-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 +// CHECK8-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK8-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK8-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK8-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 +// CHECK8-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK8-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK8-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK8-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK8-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK8-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK8-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK8-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 +// CHECK8-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK8-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 +// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 +// CHECK8-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK8-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 +// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK8-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK8-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK8-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK8-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK8-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK8-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK8-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK8-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK8-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK8-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK8-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK8-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK8-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK8-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK8-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK8-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK8-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK8-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK8-NEXT: ret i32 [[ADD9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK8-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 +// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK8-NEXT: store double [[INC]], double* [[A4]], align 4 +// CHECK8-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK8-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK8-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 +// CHECK8-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK8-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK8-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK8-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK8-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP5]] +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK8-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK8-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: ret i64 0 +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK9-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK9-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK9-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() +// CHECK9-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 +// CHECK9-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR3]] +// CHECK9-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* +// CHECK9-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK9-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK9-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK9-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK9-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 +// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK9-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 +// CHECK9-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK9-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* +// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 +// CHECK9-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) +// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* +// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* +// CHECK9-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) +// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* +// CHECK9-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) +// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) +// CHECK9-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 +// CHECK9-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) +// CHECK9-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* +// CHECK9-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 +// CHECK9-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 +// CHECK9-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* +// CHECK9-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 +// CHECK9-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 +// CHECK9-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* +// CHECK9-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 +// CHECK9-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* +// CHECK9-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 +// CHECK9-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP70]], align 8 +// CHECK9-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* +// CHECK9-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 +// CHECK9-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* +// CHECK9-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 +// CHECK9-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP75]], align 8 +// CHECK9-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 +// CHECK9-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] +// CHECK9: omp_offload.failed13: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT14]] +// CHECK9: omp_offload.cont14: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* +// CHECK9-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 +// CHECK9-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 +// CHECK9-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 +// CHECK9-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 +// CHECK9-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] +// CHECK9: omp_if.then19: +// CHECK9-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK9-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK9-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 +// CHECK9-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* +// CHECK9-NEXT: store i64 [[TMP82]], i64* [[TMP90]], align 8 +// CHECK9-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64* +// CHECK9-NEXT: store i64 [[TMP82]], i64* [[TMP92]], align 8 +// CHECK9-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP93]], align 8 +// CHECK9-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP94]], align 8 +// CHECK9-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** +// CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 +// CHECK9-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** +// CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 +// CHECK9-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 40, i64* [[TMP99]], align 8 +// CHECK9-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP100]], align 8 +// CHECK9-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP102]], align 8 +// CHECK9-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP104]], align 8 +// CHECK9-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP105]], align 8 +// CHECK9-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP106]], align 8 +// CHECK9-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** +// CHECK9-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 +// CHECK9-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float** +// CHECK9-NEXT: store float* [[VLA]], float** [[TMP110]], align 8 +// CHECK9-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK9-NEXT: store i64 [[TMP86]], i64* [[TMP111]], align 8 +// CHECK9-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP112]], align 8 +// CHECK9-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** +// CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 +// CHECK9-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]** +// CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8 +// CHECK9-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK9-NEXT: store i64 400, i64* [[TMP117]], align 8 +// CHECK9-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP118]], align 8 +// CHECK9-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64* +// CHECK9-NEXT: store i64 5, i64* [[TMP120]], align 8 +// CHECK9-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* +// CHECK9-NEXT: store i64 5, i64* [[TMP122]], align 8 +// CHECK9-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK9-NEXT: store i64 8, i64* [[TMP123]], align 8 +// CHECK9-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 +// CHECK9-NEXT: store i8* null, i8** [[TMP124]], align 8 +// CHECK9-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP126]], align 8 +// CHECK9-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 +// CHECK9-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK9-NEXT: store i64 8, i64* [[TMP129]], align 8 +// CHECK9-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 +// CHECK9-NEXT: store i8* null, i8** [[TMP130]], align 8 +// CHECK9-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** +// CHECK9-NEXT: store double* [[VLA1]], double** [[TMP132]], align 8 +// CHECK9-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double** +// CHECK9-NEXT: store double* [[VLA1]], double** [[TMP134]], align 8 +// CHECK9-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK9-NEXT: store i64 [[TMP88]], i64* [[TMP135]], align 8 +// CHECK9-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 +// CHECK9-NEXT: store i8* null, i8** [[TMP136]], align 8 +// CHECK9-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** +// CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8 +// CHECK9-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT** +// CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8 +// CHECK9-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK9-NEXT: store i64 16, i64* [[TMP141]], align 8 +// CHECK9-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 +// CHECK9-NEXT: store i8* null, i8** [[TMP142]], align 8 +// CHECK9-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64* +// CHECK9-NEXT: store i64 [[TMP84]], i64* [[TMP144]], align 8 +// CHECK9-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64* +// CHECK9-NEXT: store i64 [[TMP84]], i64* [[TMP146]], align 8 +// CHECK9-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK9-NEXT: store i64 4, i64* [[TMP147]], align 8 +// CHECK9-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 +// CHECK9-NEXT: store i8* null, i8** [[TMP148]], align 8 +// CHECK9-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 +// CHECK9-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] +// CHECK9: omp_offload.failed23: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT24]] +// CHECK9: omp_offload.cont24: +// CHECK9-NEXT: br label [[OMP_IF_END26:%.*]] +// CHECK9: omp_if.else25: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END26]] +// CHECK9: omp_if.end26: +// CHECK9-NEXT: [[TMP154:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP155]]) +// CHECK9-NEXT: ret i32 [[TMP154]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK9-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8350,8 +10441,113 @@ // CHECK9-NEXT: br label [[CANCEL_CONT]] // // +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[K1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) +// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] +// CHECK9-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 +// CHECK9-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] +// CHECK9-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK9-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK9: .omp.linear.pu: +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8 +// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP14]], 27 +// CHECK9-NEXT: store i64 [[ADD6]], i64* [[K_ADDR]], align 8 +// CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK9: .omp.linear.pu.done: +// CHECK9-NEXT: ret void +// +// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -8377,12 +10573,12 @@ // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8413,7 +10609,7 @@ // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK9-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -8421,7 +10617,7 @@ // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 @@ -8503,14 +10699,113 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK9-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK9-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: ret i64 0 +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 +// CHECK9-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK9-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK9-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 +// CHECK9-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK9-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 +// CHECK9-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK9-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK9-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK9-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK9-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK9-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 +// CHECK9-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK9-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK9-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 +// CHECK9-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK9-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 +// CHECK9-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK9-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] +// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK9-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] +// CHECK9: omp_offload.failed.i: +// CHECK9-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK9-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* +// CHECK9-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23 +// CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK9-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* +// CHECK9-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23 +// CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK9-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* +// CHECK9-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23 +// CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !23 +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] +// CHECK9: .omp_outlined..3.exit: +// CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8528,12 +10823,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8608,7 +10903,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -8650,12 +10945,12 @@ // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8799,66 +11094,307 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@_Z3bari +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK9-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP8]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK9-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK9-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK9-NEXT: store double* [[A]], double** [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 8, i64* [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 4, i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK9-NEXT: store i64 2, i64* [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK9-NEXT: store i64 2, i64* [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK9-NEXT: store i64 8, i64* [[TMP32]], align 8 +// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK9-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK9-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 +// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK9-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] +// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK9-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] +// CHECK9-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK9-NEXT: ret i32 [[ADD4]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK9-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP31]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK9-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP24]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -8880,12 +11416,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8973,34 +11509,92 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void +// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9080,15 +11674,347 @@ // CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR5]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret i64 0 +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK10-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK10-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK10-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK10-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK10-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() +// CHECK10-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 +// CHECK10-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR3]] +// CHECK10-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* +// CHECK10-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK10-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK10-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK10-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK10-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 +// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK10-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 +// CHECK10-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK10-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* +// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 +// CHECK10-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) +// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* +// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* +// CHECK10-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) +// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* +// CHECK10-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) +// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) +// CHECK10-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 +// CHECK10-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) +// CHECK10-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* +// CHECK10-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 +// CHECK10-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 +// CHECK10-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* +// CHECK10-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 +// CHECK10-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 +// CHECK10-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* +// CHECK10-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 +// CHECK10-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* +// CHECK10-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 +// CHECK10-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP70]], align 8 +// CHECK10-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* +// CHECK10-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 +// CHECK10-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* +// CHECK10-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 +// CHECK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP75]], align 8 +// CHECK10-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 +// CHECK10-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] +// CHECK10: omp_offload.failed13: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT14]] +// CHECK10: omp_offload.cont14: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* +// CHECK10-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 +// CHECK10-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 +// CHECK10-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 +// CHECK10-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 +// CHECK10-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] +// CHECK10: omp_if.then19: +// CHECK10-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK10-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK10-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 +// CHECK10-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* +// CHECK10-NEXT: store i64 [[TMP82]], i64* [[TMP90]], align 8 +// CHECK10-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64* +// CHECK10-NEXT: store i64 [[TMP82]], i64* [[TMP92]], align 8 +// CHECK10-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP93]], align 8 +// CHECK10-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP94]], align 8 +// CHECK10-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 +// CHECK10-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 +// CHECK10-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 40, i64* [[TMP99]], align 8 +// CHECK10-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP100]], align 8 +// CHECK10-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP102]], align 8 +// CHECK10-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP104]], align 8 +// CHECK10-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP105]], align 8 +// CHECK10-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP106]], align 8 +// CHECK10-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** +// CHECK10-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 +// CHECK10-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float** +// CHECK10-NEXT: store float* [[VLA]], float** [[TMP110]], align 8 +// CHECK10-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK10-NEXT: store i64 [[TMP86]], i64* [[TMP111]], align 8 +// CHECK10-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP112]], align 8 +// CHECK10-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 +// CHECK10-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]** +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8 +// CHECK10-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK10-NEXT: store i64 400, i64* [[TMP117]], align 8 +// CHECK10-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP118]], align 8 +// CHECK10-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64* +// CHECK10-NEXT: store i64 5, i64* [[TMP120]], align 8 +// CHECK10-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* +// CHECK10-NEXT: store i64 5, i64* [[TMP122]], align 8 +// CHECK10-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK10-NEXT: store i64 8, i64* [[TMP123]], align 8 +// CHECK10-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 +// CHECK10-NEXT: store i8* null, i8** [[TMP124]], align 8 +// CHECK10-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP126]], align 8 +// CHECK10-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 +// CHECK10-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK10-NEXT: store i64 8, i64* [[TMP129]], align 8 +// CHECK10-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 +// CHECK10-NEXT: store i8* null, i8** [[TMP130]], align 8 +// CHECK10-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** +// CHECK10-NEXT: store double* [[VLA1]], double** [[TMP132]], align 8 +// CHECK10-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double** +// CHECK10-NEXT: store double* [[VLA1]], double** [[TMP134]], align 8 +// CHECK10-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK10-NEXT: store i64 [[TMP88]], i64* [[TMP135]], align 8 +// CHECK10-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 +// CHECK10-NEXT: store i8* null, i8** [[TMP136]], align 8 +// CHECK10-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 +// CHECK10-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8 +// CHECK10-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 +// CHECK10-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT** +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8 +// CHECK10-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK10-NEXT: store i64 16, i64* [[TMP141]], align 8 +// CHECK10-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 +// CHECK10-NEXT: store i8* null, i8** [[TMP142]], align 8 +// CHECK10-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 +// CHECK10-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64* +// CHECK10-NEXT: store i64 [[TMP84]], i64* [[TMP144]], align 8 +// CHECK10-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 +// CHECK10-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64* +// CHECK10-NEXT: store i64 [[TMP84]], i64* [[TMP146]], align 8 +// CHECK10-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK10-NEXT: store i64 4, i64* [[TMP147]], align 8 +// CHECK10-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 +// CHECK10-NEXT: store i8* null, i8** [[TMP148]], align 8 +// CHECK10-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 +// CHECK10-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] +// CHECK10: omp_offload.failed23: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT24]] +// CHECK10: omp_offload.cont24: +// CHECK10-NEXT: br label [[OMP_IF_END26:%.*]] +// CHECK10: omp_if.else25: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END26]] +// CHECK10: omp_if.end26: +// CHECK10-NEXT: [[TMP154:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP155]]) +// CHECK10-NEXT: ret i32 [[TMP154]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK10-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9164,8 +12090,113 @@ // CHECK10-NEXT: br label [[CANCEL_CONT]] // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[K1:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) +// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] +// CHECK10-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] +// CHECK10-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK10-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK10: .omp.linear.pu: +// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8 +// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP14]], 27 +// CHECK10-NEXT: store i64 [[ADD6]], i64* [[K_ADDR]], align 8 +// CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK10: .omp.linear.pu.done: +// CHECK10-NEXT: ret void +// +// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -9191,12 +12222,12 @@ // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9227,7 +12258,7 @@ // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK10-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK10-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -9235,7 +12266,7 @@ // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 @@ -9317,14 +12348,113 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK10-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK10-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: ret i64 0 +// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 +// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 +// CHECK10-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK10-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK10-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 +// CHECK10-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK10-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 +// CHECK10-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK10-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK10-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK10-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK10-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK10-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 +// CHECK10-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK10-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK10-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 +// CHECK10-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK10-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 +// CHECK10-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK10-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK10-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] +// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK10-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] +// CHECK10: omp_offload.failed.i: +// CHECK10-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK10-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* +// CHECK10-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23 +// CHECK10-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK10-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* +// CHECK10-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23 +// CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK10-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* +// CHECK10-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23 +// CHECK10-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !23 +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] +// CHECK10: .omp_outlined..3.exit: +// CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9342,12 +12472,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9422,7 +12552,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -9464,12 +12594,12 @@ // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9613,66 +12743,307 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@_Z3bari +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK10-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP8]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK10-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK10-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK10-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK10-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK10-NEXT: store double* [[A]], double** [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 8, i64* [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 4, i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK10-NEXT: store i64 2, i64* [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK10-NEXT: store i64 2, i64* [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK10-NEXT: store i64 8, i64* [[TMP32]], align 8 +// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK10-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK10-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 +// CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK10-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] +// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK10-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] +// CHECK10-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK10-NEXT: ret i32 [[ADD4]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP31]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: ret void +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK10-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP24]] // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -9694,12 +13065,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9787,8 +13158,66 @@ // CHECK10-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9809,12 +13238,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9894,15 +13323,337 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK10-SAME: () #[[ATTR5]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK10-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void +// CHECK11-NEXT: ret i64 0 +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK11-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK11-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 +// CHECK11-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() +// CHECK11-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR3]] +// CHECK11-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK11-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 +// CHECK11-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) +// CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* +// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) +// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* +// CHECK11-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) +// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 +// CHECK11-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK11-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 +// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 +// CHECK11-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK11-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 +// CHECK11-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK11-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* +// CHECK11-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 +// CHECK11-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* +// CHECK11-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 +// CHECK11-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP66]], align 4 +// CHECK11-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* +// CHECK11-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 +// CHECK11-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* +// CHECK11-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 +// CHECK11-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP71]], align 4 +// CHECK11-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 +// CHECK11-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] +// CHECK11: omp_offload.failed9: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT10]] +// CHECK11: omp_offload.cont10: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 +// CHECK11-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 +// CHECK11-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 +// CHECK11-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] +// CHECK11: omp_if.then13: +// CHECK11-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK11-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 +// CHECK11-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK11-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 +// CHECK11-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 +// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* +// CHECK11-NEXT: store i32 [[TMP78]], i32* [[TMP88]], align 4 +// CHECK11-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* +// CHECK11-NEXT: store i32 [[TMP78]], i32* [[TMP90]], align 4 +// CHECK11-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP91]], align 4 +// CHECK11-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP92]], align 4 +// CHECK11-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** +// CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 +// CHECK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** +// CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 +// CHECK11-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 40, i64* [[TMP97]], align 4 +// CHECK11-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP98]], align 4 +// CHECK11-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP100]], align 4 +// CHECK11-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP102]], align 4 +// CHECK11-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP103]], align 4 +// CHECK11-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP104]], align 4 +// CHECK11-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** +// CHECK11-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 +// CHECK11-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** +// CHECK11-NEXT: store float* [[VLA]], float** [[TMP108]], align 4 +// CHECK11-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK11-NEXT: store i64 [[TMP83]], i64* [[TMP109]], align 4 +// CHECK11-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP110]], align 4 +// CHECK11-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** +// CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 +// CHECK11-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** +// CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4 +// CHECK11-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK11-NEXT: store i64 400, i64* [[TMP115]], align 4 +// CHECK11-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP116]], align 4 +// CHECK11-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32* +// CHECK11-NEXT: store i32 5, i32* [[TMP118]], align 4 +// CHECK11-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* +// CHECK11-NEXT: store i32 5, i32* [[TMP120]], align 4 +// CHECK11-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK11-NEXT: store i64 4, i64* [[TMP121]], align 4 +// CHECK11-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 +// CHECK11-NEXT: store i8* null, i8** [[TMP122]], align 4 +// CHECK11-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP124]], align 4 +// CHECK11-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP126]], align 4 +// CHECK11-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK11-NEXT: store i64 4, i64* [[TMP127]], align 4 +// CHECK11-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 +// CHECK11-NEXT: store i8* null, i8** [[TMP128]], align 4 +// CHECK11-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double** +// CHECK11-NEXT: store double* [[VLA1]], double** [[TMP130]], align 4 +// CHECK11-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** +// CHECK11-NEXT: store double* [[VLA1]], double** [[TMP132]], align 4 +// CHECK11-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK11-NEXT: store i64 [[TMP86]], i64* [[TMP133]], align 4 +// CHECK11-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 +// CHECK11-NEXT: store i8* null, i8** [[TMP134]], align 4 +// CHECK11-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT** +// CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4 +// CHECK11-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** +// CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4 +// CHECK11-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK11-NEXT: store i64 12, i64* [[TMP139]], align 4 +// CHECK11-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 +// CHECK11-NEXT: store i8* null, i8** [[TMP140]], align 4 +// CHECK11-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32* +// CHECK11-NEXT: store i32 [[TMP80]], i32* [[TMP142]], align 4 +// CHECK11-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32* +// CHECK11-NEXT: store i32 [[TMP80]], i32* [[TMP144]], align 4 +// CHECK11-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK11-NEXT: store i64 4, i64* [[TMP145]], align 4 +// CHECK11-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 +// CHECK11-NEXT: store i8* null, i8** [[TMP146]], align 4 +// CHECK11-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0 +// CHECK11-NEXT: br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK11: omp_offload.failed17: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK11: omp_offload.cont18: +// CHECK11-NEXT: br label [[OMP_IF_END20:%.*]] +// CHECK11: omp_if.else19: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END20]] +// CHECK11: omp_if.end20: +// CHECK11-NEXT: [[TMP152:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP153]]) +// CHECK11-NEXT: ret i32 [[TMP152]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK11-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9978,8 +13729,108 @@ // CHECK11-NEXT: br label [[CANCEL_CONT]] // // +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK11-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[K1:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 +// CHECK11-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] +// CHECK11-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 +// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] +// CHECK11-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK11-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK11: .omp.linear.pu: +// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8 +// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP15]], 27 +// CHECK11-NEXT: store i64 [[ADD5]], i64* [[TMP0]], align 8 +// CHECK11-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK11: .omp.linear.pu.done: +// CHECK11-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -10001,12 +13852,12 @@ // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10035,7 +13886,7 @@ // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK11-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK11-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -10043,7 +13894,7 @@ // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) // CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 @@ -10125,14 +13976,111 @@ // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK11-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK11-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: ret i64 0 +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK11-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK11-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK11-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK11-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK11-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK11-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK11-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK11-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK11-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK11-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK11-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK11-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK11-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK11-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK11-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK11-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK11-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK11-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] +// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK11-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] +// CHECK11: omp_offload.failed.i: +// CHECK11-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK11-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK11-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK11-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK11-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !24 +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] +// CHECK11: .omp_outlined..3.exit: +// CHECK11-NEXT: ret i32 0 // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10148,12 +14096,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10227,7 +14175,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -10265,12 +14213,12 @@ // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10412,63 +14360,304 @@ // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@_Z3bari +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP8]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK11-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK11-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK11-NEXT: store double* [[A]], double** [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 8, i64* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK11-NEXT: store i32 2, i32* [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK11-NEXT: store i32 2, i32* [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK11-NEXT: store i64 4, i64* [[TMP32]], align 4 +// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK11-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK11-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 +// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK11-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK11-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] +// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK11-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] +// CHECK11-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK11-NEXT: ret i32 [[ADD3]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK11-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP31]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK11-NEXT: ret void +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK11-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP24]] // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -10488,12 +14677,12 @@ // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10580,8 +14769,63 @@ // CHECK11-NEXT: ret void // // +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10600,12 +14844,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10684,15 +14928,337 @@ // CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK11-SAME: () #[[ATTR5]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK11-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret i64 0 +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK12-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK12-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK12-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 +// CHECK12-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() +// CHECK12-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR3]] +// CHECK12-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK12-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK12-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK12-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 +// CHECK12-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) +// CHECK12-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK12-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* +// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) +// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* +// CHECK12-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) +// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 +// CHECK12-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK12-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 +// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 +// CHECK12-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK12-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 +// CHECK12-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK12-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* +// CHECK12-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 +// CHECK12-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* +// CHECK12-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 +// CHECK12-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP66]], align 4 +// CHECK12-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* +// CHECK12-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 +// CHECK12-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* +// CHECK12-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 +// CHECK12-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP71]], align 4 +// CHECK12-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 +// CHECK12-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] +// CHECK12: omp_offload.failed9: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT10]] +// CHECK12: omp_offload.cont10: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 +// CHECK12-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 +// CHECK12-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 +// CHECK12-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] +// CHECK12: omp_if.then13: +// CHECK12-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK12-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 +// CHECK12-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK12-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 +// CHECK12-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 +// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* +// CHECK12-NEXT: store i32 [[TMP78]], i32* [[TMP88]], align 4 +// CHECK12-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* +// CHECK12-NEXT: store i32 [[TMP78]], i32* [[TMP90]], align 4 +// CHECK12-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP91]], align 4 +// CHECK12-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP92]], align 4 +// CHECK12-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 +// CHECK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 +// CHECK12-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 40, i64* [[TMP97]], align 4 +// CHECK12-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP98]], align 4 +// CHECK12-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP100]], align 4 +// CHECK12-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP102]], align 4 +// CHECK12-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP103]], align 4 +// CHECK12-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP104]], align 4 +// CHECK12-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** +// CHECK12-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 +// CHECK12-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** +// CHECK12-NEXT: store float* [[VLA]], float** [[TMP108]], align 4 +// CHECK12-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK12-NEXT: store i64 [[TMP83]], i64* [[TMP109]], align 4 +// CHECK12-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP110]], align 4 +// CHECK12-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 +// CHECK12-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4 +// CHECK12-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK12-NEXT: store i64 400, i64* [[TMP115]], align 4 +// CHECK12-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP116]], align 4 +// CHECK12-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32* +// CHECK12-NEXT: store i32 5, i32* [[TMP118]], align 4 +// CHECK12-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* +// CHECK12-NEXT: store i32 5, i32* [[TMP120]], align 4 +// CHECK12-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK12-NEXT: store i64 4, i64* [[TMP121]], align 4 +// CHECK12-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 +// CHECK12-NEXT: store i8* null, i8** [[TMP122]], align 4 +// CHECK12-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP124]], align 4 +// CHECK12-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP126]], align 4 +// CHECK12-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK12-NEXT: store i64 4, i64* [[TMP127]], align 4 +// CHECK12-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 +// CHECK12-NEXT: store i8* null, i8** [[TMP128]], align 4 +// CHECK12-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double** +// CHECK12-NEXT: store double* [[VLA1]], double** [[TMP130]], align 4 +// CHECK12-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** +// CHECK12-NEXT: store double* [[VLA1]], double** [[TMP132]], align 4 +// CHECK12-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK12-NEXT: store i64 [[TMP86]], i64* [[TMP133]], align 4 +// CHECK12-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 +// CHECK12-NEXT: store i8* null, i8** [[TMP134]], align 4 +// CHECK12-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 +// CHECK12-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT** +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4 +// CHECK12-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 +// CHECK12-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4 +// CHECK12-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK12-NEXT: store i64 12, i64* [[TMP139]], align 4 +// CHECK12-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 +// CHECK12-NEXT: store i8* null, i8** [[TMP140]], align 4 +// CHECK12-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 +// CHECK12-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32* +// CHECK12-NEXT: store i32 [[TMP80]], i32* [[TMP142]], align 4 +// CHECK12-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 +// CHECK12-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32* +// CHECK12-NEXT: store i32 [[TMP80]], i32* [[TMP144]], align 4 +// CHECK12-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK12-NEXT: store i64 4, i64* [[TMP145]], align 4 +// CHECK12-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 +// CHECK12-NEXT: store i8* null, i8** [[TMP146]], align 4 +// CHECK12-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0 +// CHECK12-NEXT: br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK12: omp_offload.failed17: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK12: omp_offload.cont18: +// CHECK12-NEXT: br label [[OMP_IF_END20:%.*]] +// CHECK12: omp_if.else19: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END20]] +// CHECK12: omp_if.end20: +// CHECK12-NEXT: [[TMP152:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP153]]) +// CHECK12-NEXT: ret i32 [[TMP152]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK12-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10768,8 +15334,108 @@ // CHECK12-NEXT: br label [[CANCEL_CONT]] // // +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK12-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[K1:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 +// CHECK12-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] +// CHECK12-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 +// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] +// CHECK12-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK12-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK12: .omp.linear.pu: +// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8 +// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP15]], 27 +// CHECK12-NEXT: store i64 [[ADD5]], i64* [[TMP0]], align 8 +// CHECK12-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK12: .omp.linear.pu.done: +// CHECK12-NEXT: ret void +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -10791,12 +15457,12 @@ // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10825,7 +15491,7 @@ // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK12-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK12-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -10833,7 +15499,7 @@ // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) // CHECK12-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 @@ -10915,14 +15581,111 @@ // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK12-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK12-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: ret i64 0 +// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK12-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK12-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK12-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK12-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK12-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK12-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK12-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK12-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK12-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK12-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK12-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK12-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK12-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK12-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK12-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK12-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK12-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK12-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK12-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] +// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK12-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] +// CHECK12: omp_offload.failed.i: +// CHECK12-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK12-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK12-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK12-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK12-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !24 +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] +// CHECK12: .omp_outlined..3.exit: +// CHECK12-NEXT: ret i32 0 // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10938,12 +15701,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11017,7 +15780,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -11055,12 +15818,12 @@ // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11202,63 +15965,304 @@ // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@_Z3bari +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP8]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK12-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK12-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK12-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK12-NEXT: store double* [[A]], double** [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 8, i64* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK12-NEXT: store i32 2, i32* [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK12-NEXT: store i32 2, i32* [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK12-NEXT: store i64 4, i64* [[TMP32]], align 4 +// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK12-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK12-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 +// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK12-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK12-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] +// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK12-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] +// CHECK12-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK12-NEXT: ret i32 [[ADD3]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK12-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK12-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP31]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK12-NEXT: ret void +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK12-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP24]] // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -11278,12 +16282,12 @@ // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11370,8 +16374,63 @@ // CHECK12-NEXT: ret void // // +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11390,12 +16449,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11474,14044 +16533,3217 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK12-SAME: () #[[ATTR5]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK12-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: ret i64 0 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK13-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK13-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK13-NEXT: br label [[FOR_COND3:%.*]] -// CHECK13: for.cond3: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK13-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body5: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK13-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK13-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK13-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK13-NEXT: br label [[FOR_COND9:%.*]] -// CHECK13: for.cond9: -// CHECK13-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK13-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK13-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK13: for.body11: -// CHECK13-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK13-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK13-NEXT: br label [[FOR_INC14:%.*]] -// CHECK13: for.inc14: -// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK13-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 +// CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK13-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK13-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK13: .cancel.exit: +// CHECK13-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK13: .cancel.continue: +// CHECK13-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK13-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK13-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK13: .cancel.exit2: +// CHECK13-NEXT: br label [[CANCEL_EXIT]] +// CHECK13: .cancel.continue3: +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK13-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK13-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK13: cancel.cont: +// CHECK13-NEXT: ret void +// CHECK13: cancel.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK13-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK13-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[LIN4:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[A5:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 +// CHECK13-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK13-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK13-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK13-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK13-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK13-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK13-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK13-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end15: -// CHECK13-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK13-NEXT: br label [[FOR_COND17:%.*]] -// CHECK13: for.cond17: -// CHECK13-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK13-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK13-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK13-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK13: for.body20: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK13-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK13-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK13-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK13-NEXT: br label [[FOR_INC25:%.*]] -// CHECK13: for.inc25: -// CHECK13-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK13-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK13-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK13-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK13-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK13-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end29: -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK13-NEXT: br label [[FOR_COND31:%.*]] -// CHECK13: for.cond31: -// CHECK13-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK13-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK13-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK13-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK13: for.body34: -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK13-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK13-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK13-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK13-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK13-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK13-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK13-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK13-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK13-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK13-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK13-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK13-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK13-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK13-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK13-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK13-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK13-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK13-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK13-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK13-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK13-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK13-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK13-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK13-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK13-NEXT: br label [[FOR_INC53:%.*]] -// CHECK13: for.inc53: -// CHECK13-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK13-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK13-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK13-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK13-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK13-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end57: -// CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK13-NEXT: ret i32 [[TMP29]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK13-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK13-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK13-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK13-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] +// CHECK13-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK13-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK13-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK13-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK13-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] +// CHECK13-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 +// CHECK13-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 +// CHECK13-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK13-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK13-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 +// CHECK13-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK13-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK13: .omp.linear.pu: +// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK13-NEXT: [[CONV18:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK13-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP21]] +// CHECK13-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]] +// CHECK13-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32 +// CHECK13-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8 +// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK13-NEXT: [[CONV22:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK13-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK13-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP23]] +// CHECK13-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]] +// CHECK13-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32 +// CHECK13-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8 +// CHECK13-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK13: .omp.linear.pu.done: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK13-SAME: () #[[ATTR2:[0-9]+]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP8]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK13-NEXT: ret i64 0 +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK13-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK13-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK13-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 +// CHECK13-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK13-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK13-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK13: omp.dispatch.cond: +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK13: omp.dispatch.body: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK13-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK13-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK13-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK13-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK13-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK13-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 +// CHECK13-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK13-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK13-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 +// CHECK13-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK13-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 +// CHECK13-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK13-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 +// CHECK13-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK13-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 +// CHECK13-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK13-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 +// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 +// CHECK13-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK13-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 +// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK13-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK13-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK13-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK13-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK13-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK13: omp.dispatch.inc: +// CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK13-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK13-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK13: omp.dispatch.end: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK13-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK13-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK13-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK13-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK13-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK13-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK13-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK13-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK13-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK13-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK13-NEXT: ret i32 [[ADD9]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK13-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 +// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK13-NEXT: store double [[INC]], double* [[A5]], align 8 +// CHECK13-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK13-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK13-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 +// CHECK13-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK13-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK13-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK13-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK13-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK13-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK13-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK13-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK13-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK13-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK13-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK13-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK13-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK13-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK14-SAME: () #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: ret i64 0 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void // // -// CHECK14-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK14-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK14-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK14-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK14-NEXT: br label [[FOR_COND3:%.*]] -// CHECK14: for.cond3: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK14-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK14-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body5: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK14-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK14-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK14-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK14-NEXT: br label [[FOR_COND9:%.*]] -// CHECK14: for.cond9: -// CHECK14-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK14-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK14-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK14: for.body11: -// CHECK14-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK14-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK14-NEXT: br label [[FOR_INC14:%.*]] -// CHECK14: for.inc14: -// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK14-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 +// CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK14-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK14-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK14: .cancel.exit: +// CHECK14-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK14: .cancel.continue: +// CHECK14-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK14-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK14-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK14: .cancel.exit2: +// CHECK14-NEXT: br label [[CANCEL_EXIT]] +// CHECK14: .cancel.continue3: +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK14-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK14-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK14: cancel.cont: +// CHECK14-NEXT: ret void +// CHECK14: cancel.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK14-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK14-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[LIN4:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[A5:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 +// CHECK14-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK14-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK14-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK14-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK14-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK14-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK14-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK14-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK14-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end15: -// CHECK14-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK14-NEXT: br label [[FOR_COND17:%.*]] -// CHECK14: for.cond17: -// CHECK14-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK14-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK14-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK14-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK14: for.body20: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK14-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK14-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK14-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK14-NEXT: br label [[FOR_INC25:%.*]] -// CHECK14: for.inc25: -// CHECK14-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK14-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK14-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK14-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK14-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK14-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end29: -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK14-NEXT: br label [[FOR_COND31:%.*]] -// CHECK14: for.cond31: -// CHECK14-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK14-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK14-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK14-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK14: for.body34: -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK14-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK14-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK14-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK14-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK14-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK14-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK14-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK14-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK14-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK14-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK14-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK14-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK14-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK14-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK14-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK14-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK14-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK14-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK14-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK14-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK14-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK14-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK14-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK14-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK14-NEXT: br label [[FOR_INC53:%.*]] -// CHECK14: for.inc53: -// CHECK14-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK14-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK14-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK14-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK14-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK14-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end57: -// CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK14-NEXT: ret i32 [[TMP29]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK14-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK14-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK14-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK14-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] +// CHECK14-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK14-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK14-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK14-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK14-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK14-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] +// CHECK14-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 +// CHECK14-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 +// CHECK14-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK14-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK14-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK14-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 +// CHECK14-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK14-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK14: .omp.linear.pu: +// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK14-NEXT: [[CONV18:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK14-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP21]] +// CHECK14-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]] +// CHECK14-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32 +// CHECK14-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8 +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK14-NEXT: [[CONV22:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK14-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK14-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP23]] +// CHECK14-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]] +// CHECK14-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32 +// CHECK14-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8 +// CHECK14-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK14: .omp.linear.pu.done: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK14-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: ret i64 0 +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK14-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK14-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK14-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK14-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 +// CHECK14-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK14-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK14-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK14: omp.dispatch.cond: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK14: omp.dispatch.body: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK14-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK14-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK14-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK14-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK14-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK14-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 +// CHECK14-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK14-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK14-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK14-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 +// CHECK14-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK14-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 +// CHECK14-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK14-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 +// CHECK14-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK14-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK14-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK14-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 +// CHECK14-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK14-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 +// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 +// CHECK14-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK14-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 +// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK14-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK14-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK14-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK14-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK14-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK14: omp.dispatch.inc: +// CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK14-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK14-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK14: omp.dispatch.end: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP8]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK14-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK14-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK14-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK14-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK14-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK14-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK14-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK14-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK14-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK14-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK14-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK14-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK14-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK14-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK14-NEXT: ret i32 [[ADD9]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK14-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 +// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK14-NEXT: store double [[INC]], double* [[A5]], align 8 +// CHECK14-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK14-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK14-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 +// CHECK14-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK14-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK14-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK14-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK14-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK14-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK14-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK14-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK14-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK14-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK14-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK14-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK14-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK14-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: ret i64 0 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void // // -// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK15-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK15-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3:%.*]] -// CHECK15: for.cond3: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK15-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body5: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK15-NEXT: br label [[FOR_INC7:%.*]] -// CHECK15: for.inc7: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK15-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK15-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK15-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK15-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK15-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 +// CHECK15-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK15-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK15-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK15: .cancel.exit: +// CHECK15-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK15: .cancel.continue: +// CHECK15-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK15-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK15-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK15: .cancel.exit2: +// CHECK15-NEXT: br label [[CANCEL_EXIT]] +// CHECK15: .cancel.continue3: +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK15-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK15-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK15: cancel.cont: +// CHECK15-NEXT: ret void +// CHECK15: cancel.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK15-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK15-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[LIN2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A3:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 +// CHECK15-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK15-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK15-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK15-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK15-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK15-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK15-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK15-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK15-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end15: -// CHECK15-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK15-NEXT: br label [[FOR_COND17:%.*]] -// CHECK15: for.cond17: -// CHECK15-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK15-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK15-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK15-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK15: for.body20: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK15-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK15-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK15-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK15-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK15-NEXT: br label [[FOR_INC25:%.*]] -// CHECK15: for.inc25: -// CHECK15-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK15-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK15-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK15-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK15-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK15-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end29: -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK15-NEXT: br label [[FOR_COND31:%.*]] -// CHECK15: for.cond31: -// CHECK15-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK15-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK15-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK15-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK15: for.body34: -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK15-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK15-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK15-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK15-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK15-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK15-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK15-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK15-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK15-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK15-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK15-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK15-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK15-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK15-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK15-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK15-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK15-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK15-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK15-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK15-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK15-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK15-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK15-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK15-NEXT: br label [[FOR_INC53:%.*]] -// CHECK15: for.inc53: -// CHECK15-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK15-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK15-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK15-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK15-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK15-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end57: -// CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK15-NEXT: ret i32 [[TMP27]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK15-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK15-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK15-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK15-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] +// CHECK15-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK15-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK15-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK15-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK15-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] +// CHECK15-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 +// CHECK15-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 +// CHECK15-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK15-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK15-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK15-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 +// CHECK15-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK15-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK15: .omp.linear.pu: +// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK15-NEXT: [[CONV16:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK15-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK15-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP21]] +// CHECK15-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]] +// CHECK15-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32 +// CHECK15-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK15-NEXT: [[CONV20:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK15-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK15-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP23]] +// CHECK15-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]] +// CHECK15-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32 +// CHECK15-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK15: .omp.linear.pu.done: +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK15-SAME: () #[[ATTR2:[0-9]+]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-NEXT: ret i64 0 +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK15-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK15-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK15-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK15-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK15-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK15-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK15: omp.dispatch.cond: +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK15-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK15: omp.dispatch.body: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK15-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK15-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 +// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double +// CHECK15-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK15-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK15-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK15-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 +// CHECK15-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK15-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK15-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK15-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 +// CHECK15-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK15-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK15-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK15-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK15-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK15-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK15-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK15-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 +// CHECK15-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK15-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 +// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 +// CHECK15-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK15-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 +// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK15-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK15-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK15-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK15-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK15-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK15: omp.dispatch.inc: +// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK15-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK15-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK15: omp.dispatch.end: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK15-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK15-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK15-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK15-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK15-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK15-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK15-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK15-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK15-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK15-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK15-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK15-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK15-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK15-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK15-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK15-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK15-NEXT: ret i32 [[ADD9]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK15-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 +// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK15-NEXT: store double [[INC]], double* [[A4]], align 4 +// CHECK15-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK15-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK15-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 +// CHECK15-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK15-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK15-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK15-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK15-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP5]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK15-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK15-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK15-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK15-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK15-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK15-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK15-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK15-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK16-SAME: () #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: ret i64 0 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void // // -// CHECK16-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK16-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK16-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK16-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3:%.*]] -// CHECK16: for.cond3: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK16-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body5: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK16-NEXT: br label [[FOR_INC7:%.*]] -// CHECK16: for.inc7: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK16-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK16-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK16-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK16-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK16-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 +// CHECK16-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK16-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK16-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK16: .cancel.exit: +// CHECK16-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK16: .cancel.continue: +// CHECK16-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK16-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK16-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK16: .cancel.exit2: +// CHECK16-NEXT: br label [[CANCEL_EXIT]] +// CHECK16: .cancel.continue3: +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK16-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK16-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK16: cancel.cont: +// CHECK16-NEXT: ret void +// CHECK16: cancel.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK16-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK16-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK16-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[LIN2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A3:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 +// CHECK16-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK16-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK16-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK16-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK16-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK16-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK16-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK16-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK16-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK16-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end15: -// CHECK16-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK16-NEXT: br label [[FOR_COND17:%.*]] -// CHECK16: for.cond17: -// CHECK16-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK16-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK16-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK16-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK16: for.body20: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK16-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK16-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK16-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK16-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK16-NEXT: br label [[FOR_INC25:%.*]] -// CHECK16: for.inc25: -// CHECK16-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK16-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK16-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK16-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK16-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK16-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end29: -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK16-NEXT: br label [[FOR_COND31:%.*]] -// CHECK16: for.cond31: -// CHECK16-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK16-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK16-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK16-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK16: for.body34: -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK16-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK16-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK16-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK16-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK16-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK16-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK16-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK16-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK16-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK16-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK16-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK16-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK16-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK16-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK16-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK16-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK16-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK16-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK16-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK16-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK16-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK16-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK16-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK16-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK16-NEXT: br label [[FOR_INC53:%.*]] -// CHECK16: for.inc53: -// CHECK16-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK16-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK16-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK16-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK16-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK16-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end57: -// CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK16-NEXT: ret i32 [[TMP27]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK16-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK16-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK16-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK16-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] +// CHECK16-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK16-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK16-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK16-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK16-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK16-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] +// CHECK16-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 +// CHECK16-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK16-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK16-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK16-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 +// CHECK16-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK16-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK16: .omp.linear.pu: +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK16-NEXT: [[CONV16:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK16-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK16-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP21]] +// CHECK16-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]] +// CHECK16-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32 +// CHECK16-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK16-NEXT: [[CONV20:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK16-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK16-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP23]] +// CHECK16-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]] +// CHECK16-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32 +// CHECK16-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK16: .omp.linear.pu.done: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK16-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: ret i64 0 +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK16-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK16-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK16-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK16-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK16-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK16-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK16: omp.dispatch.cond: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK16-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK16: omp.dispatch.body: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK16-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK16-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double +// CHECK16-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK16-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK16-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK16-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 +// CHECK16-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK16-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK16-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK16-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 +// CHECK16-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK16-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK16-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK16-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK16-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK16-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK16-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK16-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 +// CHECK16-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK16-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 +// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 +// CHECK16-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK16-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 +// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK16-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK16-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK16-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK16-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK16-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK16: omp.dispatch.inc: +// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK16-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK16-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK16: omp.dispatch.end: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK16-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK16-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK16-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK16-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK16-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK16-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK16-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK16-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK16-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK16-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK16-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK16-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK16-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK16-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK16-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK16-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK16-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK16-NEXT: ret i32 [[ADD9]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK16-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 +// CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK16-NEXT: store double [[INC]], double* [[A4]], align 4 +// CHECK16-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK16-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK16-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 +// CHECK16-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK16-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK16-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK16-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK16-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP5]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: ret i64 0 -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK17-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK17-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK17-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK17-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 -// CHECK17-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR3]] -// CHECK17-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 -// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* -// CHECK17-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK17-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK17-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 -// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 -// CHECK17-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 -// CHECK17-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK17-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* -// CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 -// CHECK17-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) -// CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* -// CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* -// CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) -// CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* -// CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) -// CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) -// CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 -// CHECK17-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) -// CHECK17-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* -// CHECK17-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 -// CHECK17-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 -// CHECK17-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* -// CHECK17-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 -// CHECK17-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 -// CHECK17-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* -// CHECK17-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 -// CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* -// CHECK17-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 -// CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP70]], align 8 -// CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* -// CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 -// CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* -// CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 -// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP75]], align 8 -// CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 -// CHECK17-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] -// CHECK17: omp_offload.failed13: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT14]] -// CHECK17: omp_offload.cont14: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* -// CHECK17-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 -// CHECK17-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 -// CHECK17-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 -// CHECK17-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 -// CHECK17-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] -// CHECK17: omp_if.then19: -// CHECK17-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 -// CHECK17-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK17-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 -// CHECK17-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* -// CHECK17-NEXT: store i64 [[TMP82]], i64* [[TMP90]], align 8 -// CHECK17-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64* -// CHECK17-NEXT: store i64 [[TMP82]], i64* [[TMP92]], align 8 -// CHECK17-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP93]], align 8 -// CHECK17-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP94]], align 8 -// CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 -// CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 -// CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 40, i64* [[TMP99]], align 8 -// CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP100]], align 8 -// CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP102]], align 8 -// CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP104]], align 8 -// CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP105]], align 8 -// CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP106]], align 8 -// CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** -// CHECK17-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 -// CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float** -// CHECK17-NEXT: store float* [[VLA]], float** [[TMP110]], align 8 -// CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK17-NEXT: store i64 [[TMP86]], i64* [[TMP111]], align 8 -// CHECK17-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP112]], align 8 -// CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 -// CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]** -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8 -// CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK17-NEXT: store i64 400, i64* [[TMP117]], align 8 -// CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP118]], align 8 -// CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64* -// CHECK17-NEXT: store i64 5, i64* [[TMP120]], align 8 -// CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* -// CHECK17-NEXT: store i64 5, i64* [[TMP122]], align 8 -// CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK17-NEXT: store i64 8, i64* [[TMP123]], align 8 -// CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 -// CHECK17-NEXT: store i8* null, i8** [[TMP124]], align 8 -// CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP126]], align 8 -// CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 -// CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK17-NEXT: store i64 8, i64* [[TMP129]], align 8 -// CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 -// CHECK17-NEXT: store i8* null, i8** [[TMP130]], align 8 -// CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** -// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP132]], align 8 -// CHECK17-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double** -// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP134]], align 8 -// CHECK17-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK17-NEXT: store i64 [[TMP88]], i64* [[TMP135]], align 8 -// CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 -// CHECK17-NEXT: store i8* null, i8** [[TMP136]], align 8 -// CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 -// CHECK17-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8 -// CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 -// CHECK17-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT** -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8 -// CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK17-NEXT: store i64 16, i64* [[TMP141]], align 8 -// CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 -// CHECK17-NEXT: store i8* null, i8** [[TMP142]], align 8 -// CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 -// CHECK17-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64* -// CHECK17-NEXT: store i64 [[TMP84]], i64* [[TMP144]], align 8 -// CHECK17-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 -// CHECK17-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64* -// CHECK17-NEXT: store i64 [[TMP84]], i64* [[TMP146]], align 8 -// CHECK17-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK17-NEXT: store i64 4, i64* [[TMP147]], align 8 -// CHECK17-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 -// CHECK17-NEXT: store i8* null, i8** [[TMP148]], align 8 -// CHECK17-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 -// CHECK17-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] -// CHECK17: omp_offload.failed23: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT24]] -// CHECK17: omp_offload.cont24: -// CHECK17-NEXT: br label [[OMP_IF_END26:%.*]] -// CHECK17: omp_if.else25: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END26]] -// CHECK17: omp_if.end26: -// CHECK17-NEXT: [[TMP154:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP155]]) -// CHECK17-NEXT: ret i32 [[TMP154]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK17-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK17-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK17-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK17: .cancel.exit: -// CHECK17-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK17: .cancel.continue: -// CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK17-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 -// CHECK17-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK17: .cancel.exit2: -// CHECK17-NEXT: br label [[CANCEL_EXIT]] -// CHECK17: .cancel.continue3: -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK17-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK17: cancel.cont: -// CHECK17-NEXT: ret void -// CHECK17: cancel.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK17-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[K1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) -// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] -// CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !11 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 -// CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] -// CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK17: .omp.linear.pu: -// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8 -// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP14]], 27 -// CHECK17-NEXT: store i64 [[ADD6]], i64* [[K_ADDR]], align 8 -// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK17: .omp.linear.pu.done: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 -// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) -// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 -// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] -// CHECK17-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK17-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 -// CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] -// CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 -// CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 -// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 -// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 -// CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK17: .omp.linear.pu: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK17-NEXT: [[CONV18:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK17-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP21]] -// CHECK17-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]] -// CHECK17-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32 -// CHECK17-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 -// CHECK17-NEXT: [[CONV22:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK17-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK17-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP23]] -// CHECK17-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]] -// CHECK17-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32 -// CHECK17-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8 -// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK17: .omp.linear.pu.done: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 -// CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 -// CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 -// CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 -// CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 -// CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 -// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] -// CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK17-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] -// CHECK17: omp_offload.failed.i: -// CHECK17-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* -// CHECK17-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23 -// CHECK17-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* -// CHECK17-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23 -// CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK17-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* -// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23 -// CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !23 -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] -// CHECK17: .omp_outlined..3.exit: -// CHECK17-NEXT: ret i32 0 -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] -// CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] -// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 -// CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double -// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double -// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] -// CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 -// CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP8]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK17-NEXT: store double* [[A]], double** [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 8, i64* [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 4, i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK17-NEXT: store i64 2, i64* [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK17-NEXT: store i64 2, i64* [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8 -// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 -// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK17-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] -// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK17-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK17-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] -// CHECK17-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK17-NEXT: ret i32 [[ADD4]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP31]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP24]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK17-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 -// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 -// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] -// CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK17-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 -// CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK17-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] -// CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 -// CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR5]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: ret i64 0 -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK18-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK18-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK18-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK18-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 -// CHECK18-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR3]] -// CHECK18-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 -// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* -// CHECK18-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 -// CHECK18-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK18-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK18-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 -// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 -// CHECK18-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 -// CHECK18-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK18-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* -// CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 -// CHECK18-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) -// CHECK18-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* -// CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* -// CHECK18-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) -// CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* -// CHECK18-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) -// CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) -// CHECK18-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 -// CHECK18-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) -// CHECK18-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* -// CHECK18-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 -// CHECK18-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 -// CHECK18-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* -// CHECK18-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 -// CHECK18-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 -// CHECK18-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* -// CHECK18-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 -// CHECK18-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* -// CHECK18-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 -// CHECK18-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP70]], align 8 -// CHECK18-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* -// CHECK18-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 -// CHECK18-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* -// CHECK18-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 -// CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP75]], align 8 -// CHECK18-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 -// CHECK18-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] -// CHECK18: omp_offload.failed13: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT14]] -// CHECK18: omp_offload.cont14: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* -// CHECK18-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 -// CHECK18-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 -// CHECK18-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 -// CHECK18-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 -// CHECK18-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] -// CHECK18: omp_if.then19: -// CHECK18-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 -// CHECK18-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK18-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 -// CHECK18-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* -// CHECK18-NEXT: store i64 [[TMP82]], i64* [[TMP90]], align 8 -// CHECK18-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64* -// CHECK18-NEXT: store i64 [[TMP82]], i64* [[TMP92]], align 8 -// CHECK18-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP93]], align 8 -// CHECK18-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP94]], align 8 -// CHECK18-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 -// CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 -// CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 40, i64* [[TMP99]], align 8 -// CHECK18-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP100]], align 8 -// CHECK18-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP102]], align 8 -// CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP104]], align 8 -// CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP105]], align 8 -// CHECK18-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP106]], align 8 -// CHECK18-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** -// CHECK18-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 -// CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float** -// CHECK18-NEXT: store float* [[VLA]], float** [[TMP110]], align 8 -// CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK18-NEXT: store i64 [[TMP86]], i64* [[TMP111]], align 8 -// CHECK18-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP112]], align 8 -// CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 -// CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]** -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8 -// CHECK18-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK18-NEXT: store i64 400, i64* [[TMP117]], align 8 -// CHECK18-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP118]], align 8 -// CHECK18-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64* -// CHECK18-NEXT: store i64 5, i64* [[TMP120]], align 8 -// CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* -// CHECK18-NEXT: store i64 5, i64* [[TMP122]], align 8 -// CHECK18-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK18-NEXT: store i64 8, i64* [[TMP123]], align 8 -// CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 -// CHECK18-NEXT: store i8* null, i8** [[TMP124]], align 8 -// CHECK18-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP126]], align 8 -// CHECK18-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 -// CHECK18-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK18-NEXT: store i64 8, i64* [[TMP129]], align 8 -// CHECK18-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 -// CHECK18-NEXT: store i8* null, i8** [[TMP130]], align 8 -// CHECK18-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** -// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP132]], align 8 -// CHECK18-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double** -// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP134]], align 8 -// CHECK18-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK18-NEXT: store i64 [[TMP88]], i64* [[TMP135]], align 8 -// CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 -// CHECK18-NEXT: store i8* null, i8** [[TMP136]], align 8 -// CHECK18-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 -// CHECK18-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8 -// CHECK18-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 -// CHECK18-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT** -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8 -// CHECK18-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK18-NEXT: store i64 16, i64* [[TMP141]], align 8 -// CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 -// CHECK18-NEXT: store i8* null, i8** [[TMP142]], align 8 -// CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 -// CHECK18-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64* -// CHECK18-NEXT: store i64 [[TMP84]], i64* [[TMP144]], align 8 -// CHECK18-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 -// CHECK18-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64* -// CHECK18-NEXT: store i64 [[TMP84]], i64* [[TMP146]], align 8 -// CHECK18-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK18-NEXT: store i64 4, i64* [[TMP147]], align 8 -// CHECK18-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 -// CHECK18-NEXT: store i8* null, i8** [[TMP148]], align 8 -// CHECK18-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 -// CHECK18-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] -// CHECK18: omp_offload.failed23: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT24]] -// CHECK18: omp_offload.cont24: -// CHECK18-NEXT: br label [[OMP_IF_END26:%.*]] -// CHECK18: omp_if.else25: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END26]] -// CHECK18: omp_if.end26: -// CHECK18-NEXT: [[TMP154:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP155]]) -// CHECK18-NEXT: ret i32 [[TMP154]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK18-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK18-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK18-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK18: .cancel.exit: -// CHECK18-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK18: .cancel.continue: -// CHECK18-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK18-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 -// CHECK18-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK18: .cancel.exit2: -// CHECK18-NEXT: br label [[CANCEL_EXIT]] -// CHECK18: .cancel.continue3: -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK18-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK18: cancel.cont: -// CHECK18-NEXT: ret void -// CHECK18: cancel.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK18-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[K1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) -// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] -// CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !11 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK18-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 -// CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] -// CHECK18-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK18-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK18: .omp.linear.pu: -// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8 -// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP14]], 27 -// CHECK18-NEXT: store i64 [[ADD6]], i64* [[K_ADDR]], align 8 -// CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK18: .omp.linear.pu.done: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[LIN4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A5:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 -// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK18-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) -// CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 -// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK18-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK18-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] -// CHECK18-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] -// CHECK18-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK18-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 -// CHECK18-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK18-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] -// CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 -// CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 -// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 -// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 -// CHECK18-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK18: .omp.linear.pu: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK18-NEXT: [[CONV18:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK18-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP21]] -// CHECK18-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]] -// CHECK18-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32 -// CHECK18-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 -// CHECK18-NEXT: [[CONV22:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK18-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK18-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP23]] -// CHECK18-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]] -// CHECK18-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32 -// CHECK18-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8 -// CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK18: .omp.linear.pu.done: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 -// CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 -// CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 -// CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 -// CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 -// CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 -// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] -// CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK18-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] -// CHECK18: omp_offload.failed.i: -// CHECK18-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* -// CHECK18-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23 -// CHECK18-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* -// CHECK18-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23 -// CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK18-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* -// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23 -// CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !23 -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] -// CHECK18: .omp_outlined..3.exit: -// CHECK18-NEXT: ret i32 0 -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[IT:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] -// CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[IT:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] -// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 -// CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double -// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK18-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double -// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK18-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK18-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK18-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK18-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK18-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK18-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] -// CHECK18-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK18-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK18-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK18-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 -// CHECK18-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK18-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK18-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK18-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK18-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK18-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK18-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK18-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP8]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK18-NEXT: store double* [[A]], double** [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 8, i64* [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 4, i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK18-NEXT: store i64 2, i64* [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK18-NEXT: store i64 2, i64* [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8 -// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 -// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK18-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] -// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK18-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK18-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] -// CHECK18-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK18-NEXT: ret i32 [[ADD4]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP31]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP24]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK18-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 -// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK18-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 -// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK18-NEXT: store double [[INC]], double* [[A5]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK18-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] -// CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK18-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 -// CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK18-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] -// CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 -// CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR5]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: ret i64 0 -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK19-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK19-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 -// CHECK19-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK19-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR3]] -// CHECK19-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 -// CHECK19-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 -// CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 -// CHECK19-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK19-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* -// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 -// CHECK19-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) -// CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* -// CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) -// CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* -// CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) -// CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* -// CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) -// CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 -// CHECK19-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) -// CHECK19-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 -// CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 -// CHECK19-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* -// CHECK19-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 -// CHECK19-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 -// CHECK19-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* -// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 -// CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* -// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 -// CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP66]], align 4 -// CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* -// CHECK19-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 -// CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* -// CHECK19-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 -// CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP71]], align 4 -// CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 -// CHECK19-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] -// CHECK19: omp_offload.failed9: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT10]] -// CHECK19: omp_offload.cont10: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 -// CHECK19-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 -// CHECK19-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 -// CHECK19-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] -// CHECK19: omp_if.then13: -// CHECK19-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 -// CHECK19-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 -// CHECK19-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK19-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 -// CHECK19-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 -// CHECK19-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* -// CHECK19-NEXT: store i32 [[TMP78]], i32* [[TMP88]], align 4 -// CHECK19-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* -// CHECK19-NEXT: store i32 [[TMP78]], i32* [[TMP90]], align 4 -// CHECK19-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP91]], align 4 -// CHECK19-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP92]], align 4 -// CHECK19-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 -// CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 -// CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 40, i64* [[TMP97]], align 4 -// CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP98]], align 4 -// CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP100]], align 4 -// CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP102]], align 4 -// CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP103]], align 4 -// CHECK19-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP104]], align 4 -// CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** -// CHECK19-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 -// CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** -// CHECK19-NEXT: store float* [[VLA]], float** [[TMP108]], align 4 -// CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK19-NEXT: store i64 [[TMP83]], i64* [[TMP109]], align 4 -// CHECK19-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP110]], align 4 -// CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 -// CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4 -// CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK19-NEXT: store i64 400, i64* [[TMP115]], align 4 -// CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP116]], align 4 -// CHECK19-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32* -// CHECK19-NEXT: store i32 5, i32* [[TMP118]], align 4 -// CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* -// CHECK19-NEXT: store i32 5, i32* [[TMP120]], align 4 -// CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK19-NEXT: store i64 4, i64* [[TMP121]], align 4 -// CHECK19-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 -// CHECK19-NEXT: store i8* null, i8** [[TMP122]], align 4 -// CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP124]], align 4 -// CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP126]], align 4 -// CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK19-NEXT: store i64 4, i64* [[TMP127]], align 4 -// CHECK19-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 -// CHECK19-NEXT: store i8* null, i8** [[TMP128]], align 4 -// CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double** -// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP130]], align 4 -// CHECK19-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** -// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP132]], align 4 -// CHECK19-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK19-NEXT: store i64 [[TMP86]], i64* [[TMP133]], align 4 -// CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 -// CHECK19-NEXT: store i8* null, i8** [[TMP134]], align 4 -// CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 -// CHECK19-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT** -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4 -// CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 -// CHECK19-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4 -// CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK19-NEXT: store i64 12, i64* [[TMP139]], align 4 -// CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 -// CHECK19-NEXT: store i8* null, i8** [[TMP140]], align 4 -// CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 -// CHECK19-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32* -// CHECK19-NEXT: store i32 [[TMP80]], i32* [[TMP142]], align 4 -// CHECK19-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 -// CHECK19-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32* -// CHECK19-NEXT: store i32 [[TMP80]], i32* [[TMP144]], align 4 -// CHECK19-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK19-NEXT: store i64 4, i64* [[TMP145]], align 4 -// CHECK19-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 -// CHECK19-NEXT: store i8* null, i8** [[TMP146]], align 4 -// CHECK19-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0 -// CHECK19-NEXT: br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK19: omp_offload.failed17: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK19: omp_offload.cont18: -// CHECK19-NEXT: br label [[OMP_IF_END20:%.*]] -// CHECK19: omp_if.else19: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END20]] -// CHECK19: omp_if.end20: -// CHECK19-NEXT: [[TMP152:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP153]]) -// CHECK19-NEXT: ret i32 [[TMP152]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK19-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK19-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK19: .cancel.exit: -// CHECK19-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK19: .cancel.continue: -// CHECK19-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK19-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 -// CHECK19-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK19: .cancel.exit2: -// CHECK19-NEXT: br label [[CANCEL_EXIT]] -// CHECK19: .cancel.continue3: -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK19-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK19: cancel.cont: -// CHECK19-NEXT: ret void -// CHECK19: cancel.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK19-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK19-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[K1:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 -// CHECK19-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) -// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] -// CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK19-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 -// CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] -// CHECK19-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK19: .omp.linear.pu: -// CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8 -// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP15]], 27 -// CHECK19-NEXT: store i64 [[ADD5]], i64* [[TMP0]], align 8 -// CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK19: .omp.linear.pu.done: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 -// CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) -// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK19-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 -// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK19-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK19-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] -// CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] -// CHECK19-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK19-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 -// CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] -// CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] -// CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 -// CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 -// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 -// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 -// CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK19: .omp.linear.pu: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK19-NEXT: [[CONV16:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK19-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK19-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP21]] -// CHECK19-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]] -// CHECK19-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32 -// CHECK19-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 -// CHECK19-NEXT: [[CONV20:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK19-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK19-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP23]] -// CHECK19-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]] -// CHECK19-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32 -// CHECK19-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK19: .omp.linear.pu.done: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK19-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 -// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 -// CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 -// CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 -// CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 -// CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 -// CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 -// CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] -// CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK19-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] -// CHECK19: omp_offload.failed.i: -// CHECK19-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* -// CHECK19-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 -// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK19-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK19-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !24 -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] -// CHECK19: .omp_outlined..3.exit: -// CHECK19-NEXT: ret i32 0 -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] -// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] -// CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 -// CHECK19-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double -// CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 -// CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float -// CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 -// CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double -// CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 -// CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 -// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] -// CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 -// CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 -// CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 -// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 -// CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 -// CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP8]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 -// CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK19-NEXT: store double* [[A]], double** [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 8, i64* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK19-NEXT: store i32 2, i32* [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK19-NEXT: store i32 2, i32* [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK19-NEXT: store i64 4, i64* [[TMP32]], align 4 -// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 -// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK19-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK19-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK19-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] -// CHECK19-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK19-NEXT: ret i32 [[ADD3]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP31]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP24]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK19-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 -// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK19-NEXT: store double [[INC]], double* [[A4]], align 4 -// CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] -// CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK19-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 -// CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK19-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK19-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] -// CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 -// CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR5]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: ret i64 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK20-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK20-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 -// CHECK20-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK20-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR3]] -// CHECK20-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 -// CHECK20-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 -// CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 -// CHECK20-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK20-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* -// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 -// CHECK20-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) -// CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* -// CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) -// CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* -// CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) -// CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* -// CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) -// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 -// CHECK20-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) -// CHECK20-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 -// CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 -// CHECK20-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* -// CHECK20-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 -// CHECK20-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 -// CHECK20-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* -// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 -// CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* -// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 -// CHECK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP66]], align 4 -// CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* -// CHECK20-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 -// CHECK20-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* -// CHECK20-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 -// CHECK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP71]], align 4 -// CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 -// CHECK20-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] -// CHECK20: omp_offload.failed9: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT10]] -// CHECK20: omp_offload.cont10: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 -// CHECK20-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 -// CHECK20-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 -// CHECK20-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] -// CHECK20: omp_if.then13: -// CHECK20-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 -// CHECK20-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 -// CHECK20-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK20-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 -// CHECK20-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 -// CHECK20-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* -// CHECK20-NEXT: store i32 [[TMP78]], i32* [[TMP88]], align 4 -// CHECK20-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* -// CHECK20-NEXT: store i32 [[TMP78]], i32* [[TMP90]], align 4 -// CHECK20-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP91]], align 4 -// CHECK20-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP92]], align 4 -// CHECK20-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 -// CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 -// CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 40, i64* [[TMP97]], align 4 -// CHECK20-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP98]], align 4 -// CHECK20-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP100]], align 4 -// CHECK20-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP102]], align 4 -// CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP103]], align 4 -// CHECK20-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP104]], align 4 -// CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** -// CHECK20-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 -// CHECK20-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** -// CHECK20-NEXT: store float* [[VLA]], float** [[TMP108]], align 4 -// CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK20-NEXT: store i64 [[TMP83]], i64* [[TMP109]], align 4 -// CHECK20-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP110]], align 4 -// CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 -// CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4 -// CHECK20-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK20-NEXT: store i64 400, i64* [[TMP115]], align 4 -// CHECK20-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP116]], align 4 -// CHECK20-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32* -// CHECK20-NEXT: store i32 5, i32* [[TMP118]], align 4 -// CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* -// CHECK20-NEXT: store i32 5, i32* [[TMP120]], align 4 -// CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK20-NEXT: store i64 4, i64* [[TMP121]], align 4 -// CHECK20-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 -// CHECK20-NEXT: store i8* null, i8** [[TMP122]], align 4 -// CHECK20-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP124]], align 4 -// CHECK20-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP126]], align 4 -// CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK20-NEXT: store i64 4, i64* [[TMP127]], align 4 -// CHECK20-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 -// CHECK20-NEXT: store i8* null, i8** [[TMP128]], align 4 -// CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double** -// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP130]], align 4 -// CHECK20-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** -// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP132]], align 4 -// CHECK20-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK20-NEXT: store i64 [[TMP86]], i64* [[TMP133]], align 4 -// CHECK20-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 -// CHECK20-NEXT: store i8* null, i8** [[TMP134]], align 4 -// CHECK20-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 -// CHECK20-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT** -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4 -// CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 -// CHECK20-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4 -// CHECK20-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK20-NEXT: store i64 12, i64* [[TMP139]], align 4 -// CHECK20-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 -// CHECK20-NEXT: store i8* null, i8** [[TMP140]], align 4 -// CHECK20-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 -// CHECK20-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32* -// CHECK20-NEXT: store i32 [[TMP80]], i32* [[TMP142]], align 4 -// CHECK20-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 -// CHECK20-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32* -// CHECK20-NEXT: store i32 [[TMP80]], i32* [[TMP144]], align 4 -// CHECK20-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK20-NEXT: store i64 4, i64* [[TMP145]], align 4 -// CHECK20-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 -// CHECK20-NEXT: store i8* null, i8** [[TMP146]], align 4 -// CHECK20-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0 -// CHECK20-NEXT: br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK20: omp_offload.failed17: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK20: omp_offload.cont18: -// CHECK20-NEXT: br label [[OMP_IF_END20:%.*]] -// CHECK20: omp_if.else19: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END20]] -// CHECK20: omp_if.end20: -// CHECK20-NEXT: [[TMP152:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP153]]) -// CHECK20-NEXT: ret i32 [[TMP152]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK20-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK20-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK20-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK20: .cancel.exit: -// CHECK20-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK20: .cancel.continue: -// CHECK20-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK20-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 -// CHECK20-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK20: .cancel.exit2: -// CHECK20-NEXT: br label [[CANCEL_EXIT]] -// CHECK20: .cancel.continue3: -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK20-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK20: cancel.cont: -// CHECK20-NEXT: ret void -// CHECK20: cancel.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK20-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK20-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[K1:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 -// CHECK20-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) -// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] -// CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK20-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 -// CHECK20-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] -// CHECK20-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK20-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK20: .omp.linear.pu: -// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8 -// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP15]], 27 -// CHECK20-NEXT: store i64 [[ADD5]], i64* [[TMP0]], align 8 -// CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK20: .omp.linear.pu.done: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[LIN2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 -// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) -// CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK20-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 -// CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK20-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK20-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] -// CHECK20-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] -// CHECK20-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK20-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 -// CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] -// CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] -// CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 -// CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 -// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 -// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 -// CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK20-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK20: .omp.linear.pu: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK20-NEXT: [[CONV16:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK20-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK20-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP21]] -// CHECK20-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]] -// CHECK20-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32 -// CHECK20-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 -// CHECK20-NEXT: [[CONV20:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK20-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK20-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP23]] -// CHECK20-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]] -// CHECK20-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32 -// CHECK20-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK20: .omp.linear.pu.done: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK20-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 -// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 -// CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 -// CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 -// CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 -// CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 -// CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 -// CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]] -// CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK20-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] -// CHECK20: omp_offload.failed.i: -// CHECK20-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* -// CHECK20-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 -// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK20-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK20-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !24 -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] -// CHECK20: .omp_outlined..3.exit: -// CHECK20-NEXT: ret i32 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[IT:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] -// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[IT:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] -// CHECK20-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 -// CHECK20-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double -// CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 -// CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float -// CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 -// CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double -// CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 -// CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 -// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK20-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] -// CHECK20-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 -// CHECK20-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 -// CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 -// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 -// CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 -// CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK20-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP8]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 -// CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK20-NEXT: store double* [[A]], double** [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 8, i64* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK20-NEXT: store i32 2, i32* [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK20-NEXT: store i32 2, i32* [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK20-NEXT: store i64 4, i64* [[TMP32]], align 4 -// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 -// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK20-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] -// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK20-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK20-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] -// CHECK20-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK20-NEXT: ret i32 [[ADD3]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP31]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP24]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK20-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 -// CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK20-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK20-NEXT: store double [[INC]], double* [[A4]], align 4 -// CHECK20-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK20-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] -// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK20-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 -// CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK20-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK20-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] -// CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 -// CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR5]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: ret i64 0 -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK21-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK21-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK21-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK21-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK21-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK21-NEXT: br label [[FOR_COND3:%.*]] -// CHECK21: for.cond3: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK21-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK21-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK21: for.body5: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK21-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK21-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK21-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK21: for.end8: -// CHECK21-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK21-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK21-NEXT: br label [[FOR_COND9:%.*]] -// CHECK21: for.cond9: -// CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK21-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK21-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK21: for.body11: -// CHECK21-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK21-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK21-NEXT: br label [[FOR_INC14:%.*]] -// CHECK21: for.inc14: -// CHECK21-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK21-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK21-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end15: -// CHECK21-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK21-NEXT: br label [[FOR_COND17:%.*]] -// CHECK21: for.cond17: -// CHECK21-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK21-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK21-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK21-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK21: for.body20: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK21-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK21-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK21-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK21-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK21-NEXT: br label [[FOR_INC25:%.*]] -// CHECK21: for.inc25: -// CHECK21-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK21-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK21-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK21-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK21-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK21-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK21: for.end29: -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK21-NEXT: br label [[FOR_COND31:%.*]] -// CHECK21: for.cond31: -// CHECK21-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK21-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK21-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK21-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK21: for.body34: -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK21-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK21-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK21-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK21-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK21-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK21-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK21-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK21-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK21-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK21-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK21-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK21-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK21-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK21-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK21-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK21-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK21-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK21-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK21-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK21-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK21-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK21-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK21-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK21-NEXT: br label [[FOR_INC53:%.*]] -// CHECK21: for.inc53: -// CHECK21-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK21-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK21-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK21-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK21-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK21-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK21: for.end57: -// CHECK21-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK21-NEXT: ret i32 [[TMP29]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP8]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK21-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK21-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK21-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK21-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK21-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK21-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK21-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK21-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK21-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK21-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK21-NEXT: ret i32 [[ADD9]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK21-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK21-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK21-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP6]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK21-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP5]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: ret i64 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK22-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK22-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK22-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK22-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK22-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK22-NEXT: br label [[FOR_COND3:%.*]] -// CHECK22: for.cond3: -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK22-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK22-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK22: for.body5: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK22-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK22-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK22-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK22: for.end8: -// CHECK22-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK22-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK22-NEXT: br label [[FOR_COND9:%.*]] -// CHECK22: for.cond9: -// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK22-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK22-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK22: for.body11: -// CHECK22-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK22-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK22-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK22-NEXT: br label [[FOR_INC14:%.*]] -// CHECK22: for.inc14: -// CHECK22-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK22-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK22-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK22: for.end15: -// CHECK22-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK22-NEXT: br label [[FOR_COND17:%.*]] -// CHECK22: for.cond17: -// CHECK22-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK22-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK22-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK22-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK22: for.body20: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK22-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK22-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK22-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK22-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK22-NEXT: br label [[FOR_INC25:%.*]] -// CHECK22: for.inc25: -// CHECK22-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK22-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK22-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK22-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK22-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK22-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK22: for.end29: -// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK22-NEXT: br label [[FOR_COND31:%.*]] -// CHECK22: for.cond31: -// CHECK22-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK22-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK22-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK22-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK22: for.body34: -// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK22-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK22-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK22-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK22-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK22-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK22-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK22-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK22-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK22-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK22-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK22-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK22-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK22-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK22-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK22-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK22-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK22-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK22-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK22-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK22-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK22-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK22-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK22-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK22-NEXT: br label [[FOR_INC53:%.*]] -// CHECK22: for.inc53: -// CHECK22-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK22-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK22-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK22-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK22-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK22-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK22: for.end57: -// CHECK22-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK22-NEXT: ret i32 [[TMP29]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP8]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK22-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK22-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK22-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK22-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK22-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK22-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK22-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK22-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK22-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK22-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK22-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK22-NEXT: ret i32 [[ADD9]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK22-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK22-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK22-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK22-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP6]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK22-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP5]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK23-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: ret i64 0 -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK23-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK23-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK23-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK23-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK23-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK23-NEXT: br label [[FOR_COND3:%.*]] -// CHECK23: for.cond3: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK23-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK23-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK23: for.body5: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK23-NEXT: br label [[FOR_INC7:%.*]] -// CHECK23: for.inc7: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK23-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK23-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK23-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK23: for.end8: -// CHECK23-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK23-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK23-NEXT: br label [[FOR_COND9:%.*]] -// CHECK23: for.cond9: -// CHECK23-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK23-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK23-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK23: for.body11: -// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK23-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK23-NEXT: br label [[FOR_INC14:%.*]] -// CHECK23: for.inc14: -// CHECK23-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK23-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK23-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK23-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK23: for.end15: -// CHECK23-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK23-NEXT: br label [[FOR_COND17:%.*]] -// CHECK23: for.cond17: -// CHECK23-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK23-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK23-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK23-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK23: for.body20: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK23-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK23-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK23-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK23-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK23-NEXT: br label [[FOR_INC25:%.*]] -// CHECK23: for.inc25: -// CHECK23-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK23-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK23-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK23-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK23-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK23-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK23: for.end29: -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK23-NEXT: br label [[FOR_COND31:%.*]] -// CHECK23: for.cond31: -// CHECK23-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK23-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK23-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK23-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK23: for.body34: -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK23-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK23-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK23-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK23-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK23-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK23-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK23-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK23-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK23-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK23-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK23-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK23-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK23-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK23-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK23-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK23-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK23-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK23-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK23-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK23-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK23-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK23-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK23-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK23-NEXT: br label [[FOR_INC53:%.*]] -// CHECK23: for.inc53: -// CHECK23-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK23-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK23-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK23-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK23-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK23-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK23: for.end57: -// CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK23-NEXT: ret i32 [[TMP27]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP8]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK23-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK23-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK23-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK23-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK23-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK23-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK23-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK23-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK23-NEXT: ret i32 [[ADD9]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK23-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK23-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK23-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP6]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK23-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP5]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: ret i64 0 -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK24-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK24-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK24-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK24-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK24-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK24-NEXT: br label [[FOR_COND3:%.*]] -// CHECK24: for.cond3: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK24-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK24-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK24: for.body5: -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK24-NEXT: br label [[FOR_INC7:%.*]] -// CHECK24: for.inc7: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK24-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK24-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK24-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK24: for.end8: -// CHECK24-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK24-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK24-NEXT: br label [[FOR_COND9:%.*]] -// CHECK24: for.cond9: -// CHECK24-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK24-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK24-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK24: for.body11: -// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK24-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK24-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK24-NEXT: br label [[FOR_INC14:%.*]] -// CHECK24: for.inc14: -// CHECK24-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK24-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK24-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK24-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK24: for.end15: -// CHECK24-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK24-NEXT: br label [[FOR_COND17:%.*]] -// CHECK24: for.cond17: -// CHECK24-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK24-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK24-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK24-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK24: for.body20: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK24-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK24-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK24-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK24-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK24-NEXT: br label [[FOR_INC25:%.*]] -// CHECK24: for.inc25: -// CHECK24-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK24-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK24-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK24-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK24-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK24-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK24: for.end29: -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK24-NEXT: br label [[FOR_COND31:%.*]] -// CHECK24: for.cond31: -// CHECK24-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK24-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK24-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK24-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK24: for.body34: -// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK24-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK24-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK24-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK24-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK24-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK24-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK24-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK24-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK24-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK24-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK24-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK24-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK24-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK24-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK24-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK24-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK24-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK24-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK24-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK24-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK24-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK24-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK24-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK24-NEXT: br label [[FOR_INC53:%.*]] -// CHECK24: for.inc53: -// CHECK24-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK24-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK24-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK24-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK24-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK24-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK24: for.end57: -// CHECK24-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK24-NEXT: ret i32 [[TMP27]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP8]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK24-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK24-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK24-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK24-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK24-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK24-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK24-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK24-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK24-NEXT: ret i32 [[ADD9]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK24-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK24-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK24-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP6]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK24-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP5]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK25-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK25-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK25-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK25: .cancel.exit: -// CHECK25-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK25: .cancel.continue: -// CHECK25-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK25-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 -// CHECK25-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK25: .cancel.exit2: -// CHECK25-NEXT: br label [[CANCEL_EXIT]] -// CHECK25: .cancel.continue3: -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK25-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK25-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK25: cancel.cont: -// CHECK25-NEXT: ret void -// CHECK25: cancel.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK25-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK25-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 -// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[LIN4:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[A5:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] -// CHECK25-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 -// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK25-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) -// CHECK25-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK25-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] -// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 -// CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK25-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK25-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] -// CHECK25-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] -// CHECK25-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK25-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 -// CHECK25-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK25-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] -// CHECK25-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] -// CHECK25-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 -// CHECK25-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 -// CHECK25-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 -// CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 -// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 -// CHECK25-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK25-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK25: .omp.linear.pu: -// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK25-NEXT: [[CONV18:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK25-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK25-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP21]] -// CHECK25-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]] -// CHECK25-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32 -// CHECK25-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8 -// CHECK25-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 -// CHECK25-NEXT: [[CONV22:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK25-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK25-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP23]] -// CHECK25-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]] -// CHECK25-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32 -// CHECK25-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8 -// CHECK25-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK25: .omp.linear.pu.done: -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK25-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: ret i64 0 -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i16, align 2 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[IT:%.*]] = alloca i16, align 2 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] -// CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK25-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK25-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK25-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK25-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK25-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 -// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[IT:%.*]] = alloca i8, align 1 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK25: omp.dispatch.cond: -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK25: omp.dispatch.body: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] -// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 -// CHECK25-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 -// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double -// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK25-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double -// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK25-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK25-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK25-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK25-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK25-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK25-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK25-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] -// CHECK25-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK25-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK25-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK25-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 -// CHECK25-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK25-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK25-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK25-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK25-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK25-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK25-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK25: omp.dispatch.inc: -// CHECK25-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK25-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK25-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK25: omp.dispatch.end: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK25-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] -// CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 -// CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK25-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 -// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK25-NEXT: store double [[INC]], double* [[A5]], align 8 -// CHECK25-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK25-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] -// CHECK25-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK25-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 -// CHECK25-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK25-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK25-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] -// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] -// CHECK25-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 -// CHECK25-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK26-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK26-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK26-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK26: .cancel.exit: -// CHECK26-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK26: .cancel.continue: -// CHECK26-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK26-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 -// CHECK26-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK26: .cancel.exit2: -// CHECK26-NEXT: br label [[CANCEL_EXIT]] -// CHECK26: .cancel.continue3: -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK26-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK26-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK26: cancel.cont: -// CHECK26-NEXT: ret void -// CHECK26: cancel.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK26-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK26-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 -// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[LIN4:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[A5:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] -// CHECK26-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 -// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK26-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) -// CHECK26-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK26-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] -// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 -// CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK26-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK26-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] -// CHECK26-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] -// CHECK26-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK26-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 -// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 -// CHECK26-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK26-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] -// CHECK26-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] -// CHECK26-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 -// CHECK26-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 -// CHECK26-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 -// CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 -// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 -// CHECK26-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK26-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK26: .omp.linear.pu: -// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK26-NEXT: [[CONV18:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK26-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK26-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP21]] -// CHECK26-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]] -// CHECK26-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32 -// CHECK26-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8 -// CHECK26-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 -// CHECK26-NEXT: [[CONV22:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK26-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK26-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP23]] -// CHECK26-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]] -// CHECK26-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32 -// CHECK26-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8 -// CHECK26-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK26: .omp.linear.pu.done: -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK26-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: ret i64 0 -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i16, align 2 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[IT:%.*]] = alloca i16, align 2 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] -// CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK26-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK26-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK26-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK26-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK26-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 -// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 -// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[IT:%.*]] = alloca i8, align 1 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK26: omp.dispatch.cond: -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK26: omp.dispatch.body: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] -// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 -// CHECK26-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 -// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double -// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK26-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double -// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK26-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK26-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK26-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK26-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK26-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK26-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK26-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] -// CHECK26-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK26-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK26-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK26-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 -// CHECK26-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK26-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK26-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK26-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK26-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK26-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK26-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK26: omp.dispatch.inc: -// CHECK26-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK26-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK26-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK26: omp.dispatch.end: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK26-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] -// CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 -// CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK26-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 -// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK26-NEXT: store double [[INC]], double* [[A5]], align 8 -// CHECK26-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK26-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] -// CHECK26-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK26-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 -// CHECK26-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK26-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK26-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] -// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] -// CHECK26-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 -// CHECK26-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK27-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK27-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK27-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK27: .cancel.exit: -// CHECK27-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK27: .cancel.continue: -// CHECK27-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK27-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 -// CHECK27-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK27: .cancel.exit2: -// CHECK27-NEXT: br label [[CANCEL_EXIT]] -// CHECK27: .cancel.continue3: -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK27-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK27-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK27: cancel.cont: -// CHECK27-NEXT: ret void -// CHECK27: cancel.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK27-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK27-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK27-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[LIN2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A3:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] -// CHECK27-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 -// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK27-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) -// CHECK27-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK27-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] -// CHECK27-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 -// CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK27-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK27-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] -// CHECK27-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] -// CHECK27-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK27-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 -// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 -// CHECK27-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK27-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] -// CHECK27-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] -// CHECK27-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 -// CHECK27-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 -// CHECK27-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 -// CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 -// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 -// CHECK27-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK27-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK27: .omp.linear.pu: -// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK27-NEXT: [[CONV16:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK27-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK27-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP21]] -// CHECK27-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]] -// CHECK27-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32 -// CHECK27-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 -// CHECK27-NEXT: [[CONV20:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK27-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK27-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP23]] -// CHECK27-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]] -// CHECK27-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32 -// CHECK27-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK27: .omp.linear.pu.done: -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK27-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: ret i64 0 -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i16, align 2 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[IT:%.*]] = alloca i16, align 2 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] -// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK27-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK27-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK27-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK27-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK27-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[IT:%.*]] = alloca i8, align 1 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK27-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK27: omp.dispatch.cond: -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK27: omp.dispatch.body: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK27-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] -// CHECK27-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 -// CHECK27-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 -// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double -// CHECK27-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 -// CHECK27-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float -// CHECK27-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK27-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 -// CHECK27-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double -// CHECK27-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 -// CHECK27-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK27-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 -// CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK27-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK27-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] -// CHECK27-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 -// CHECK27-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK27-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK27-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 -// CHECK27-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK27-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 -// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK27-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK27-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 -// CHECK27-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 -// CHECK27-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK27-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK27: omp.dispatch.inc: -// CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK27-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK27-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK27: omp.dispatch.end: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK27-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] -// CHECK27-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 -// CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK27-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 -// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK27-NEXT: store double [[INC]], double* [[A4]], align 4 -// CHECK27-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK27-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] -// CHECK27-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK27-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 -// CHECK27-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK27-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK27-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK27-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] -// CHECK27-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 -// CHECK27-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK28-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK28-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK28-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK28: .cancel.exit: -// CHECK28-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK28: .cancel.continue: -// CHECK28-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) -// CHECK28-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 -// CHECK28-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] -// CHECK28: .cancel.exit2: -// CHECK28-NEXT: br label [[CANCEL_EXIT]] -// CHECK28: .cancel.continue3: -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK28-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK28-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK28: cancel.cont: -// CHECK28-NEXT: ret void -// CHECK28: cancel.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK28-NEXT: br label [[CANCEL_CONT]] -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK28-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK28-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[LIN2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A3:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] -// CHECK28-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 -// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK28-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) -// CHECK28-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK28-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] -// CHECK28-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 -// CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK28-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK28-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] -// CHECK28-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] -// CHECK28-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK28-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 -// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 -// CHECK28-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK28-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] -// CHECK28-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] -// CHECK28-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 -// CHECK28-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 -// CHECK28-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 -// CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 -// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 -// CHECK28-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK28-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] -// CHECK28: .omp.linear.pu: -// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 -// CHECK28-NEXT: [[CONV16:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK28-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK28-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP21]] -// CHECK28-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]] -// CHECK28-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32 -// CHECK28-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 -// CHECK28-NEXT: [[CONV20:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK28-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 -// CHECK28-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP23]] -// CHECK28-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]] -// CHECK28-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32 -// CHECK28-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] -// CHECK28: .omp.linear.pu.done: -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK28-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: ret i64 0 -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i16, align 2 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[IT:%.*]] = alloca i16, align 2 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] -// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK28-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK28-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK28-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK28-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i8, align 1 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[IT:%.*]] = alloca i8, align 1 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK28-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK28: omp.dispatch.cond: -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK28: omp.dispatch.body: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK28-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] -// CHECK28-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 -// CHECK28-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 -// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double -// CHECK28-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 -// CHECK28-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float -// CHECK28-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK28-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 -// CHECK28-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double -// CHECK28-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 -// CHECK28-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK28-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 -// CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK28-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK28-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] -// CHECK28-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 -// CHECK28-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK28-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK28-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 -// CHECK28-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK28-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 -// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK28-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK28-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 -// CHECK28-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 -// CHECK28-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK28-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK28: omp.dispatch.inc: -// CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK28-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK28-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK28: omp.dispatch.end: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK28-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] -// CHECK28-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 -// CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] -// CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK28-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 -// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK28-NEXT: store double [[INC]], double* [[A4]], align 4 -// CHECK28-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK28-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] -// CHECK28-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK28-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 -// CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK28-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK28-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK28-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] -// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] -// CHECK28-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 -// CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK29-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: ret i64 0 -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK29-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK29-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK29-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK29-NEXT: br label [[FOR_COND3:%.*]] -// CHECK29: for.cond3: -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK29-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK29-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK29: for.body5: -// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK29-NEXT: br label [[FOR_INC7:%.*]] -// CHECK29: for.inc7: -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK29-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK29-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK29-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK29: for.end8: -// CHECK29-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK29-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK29-NEXT: br label [[FOR_COND9:%.*]] -// CHECK29: for.cond9: -// CHECK29-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK29-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK29-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK29: for.body11: -// CHECK29-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK29-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK29-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK29-NEXT: br label [[FOR_INC14:%.*]] -// CHECK29: for.inc14: -// CHECK29-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK29-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK29-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK29-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK29: for.end15: -// CHECK29-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK29-NEXT: br label [[FOR_COND17:%.*]] -// CHECK29: for.cond17: -// CHECK29-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK29-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK29-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK29-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK29: for.body20: -// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK29-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK29-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK29-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK29-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK29-NEXT: br label [[FOR_INC25:%.*]] -// CHECK29: for.inc25: -// CHECK29-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK29-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK29-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK29-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK29-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK29-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK29: for.end29: -// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK29-NEXT: br label [[FOR_COND31:%.*]] -// CHECK29: for.cond31: -// CHECK29-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK29-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK29-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK29-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK29: for.body34: -// CHECK29-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK29-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK29-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK29-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK29-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK29-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK29-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK29-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK29-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK29-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK29-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK29-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK29-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK29-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK29-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK29-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK29-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK29-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK29-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK29-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK29-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK29-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK29-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK29-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK29-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK29-NEXT: br label [[FOR_INC53:%.*]] -// CHECK29: for.inc53: -// CHECK29-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK29-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK29-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK29-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK29-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK29-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK29: for.end57: -// CHECK29-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK29-NEXT: ret i32 [[TMP29]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP8]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK29-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK29-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK29-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK29-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK29-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK29-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK29-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK29-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK29-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK29-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK29-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK29-NEXT: ret i32 [[ADD9]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK29-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK29-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK29-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK29-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP6]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK29-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP5]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK30-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: ret i64 0 -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK30-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK30-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK30-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK30-NEXT: br label [[FOR_COND3:%.*]] -// CHECK30: for.cond3: -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK30-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK30-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK30: for.body5: -// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK30-NEXT: br label [[FOR_INC7:%.*]] -// CHECK30: for.inc7: -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK30-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK30-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK30-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK30: for.end8: -// CHECK30-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK30-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK30-NEXT: br label [[FOR_COND9:%.*]] -// CHECK30: for.cond9: -// CHECK30-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK30-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK30-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK30: for.body11: -// CHECK30-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK30-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK30-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK30-NEXT: br label [[FOR_INC14:%.*]] -// CHECK30: for.inc14: -// CHECK30-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK30-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK30-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK30-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK30: for.end15: -// CHECK30-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK30-NEXT: br label [[FOR_COND17:%.*]] -// CHECK30: for.cond17: -// CHECK30-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK30-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK30-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK30-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK30: for.body20: -// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK30-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK30-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK30-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK30-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK30-NEXT: br label [[FOR_INC25:%.*]] -// CHECK30: for.inc25: -// CHECK30-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK30-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK30-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK30-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK30-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK30-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK30: for.end29: -// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK30-NEXT: br label [[FOR_COND31:%.*]] -// CHECK30: for.cond31: -// CHECK30-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK30-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK30-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK30-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK30: for.body34: -// CHECK30-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK30-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK30-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK30-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK30-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK30-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK30-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK30-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK30-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK30-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK30-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK30-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK30-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK30-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK30-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK30-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK30-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK30-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK30-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK30-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK30-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK30-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK30-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK30-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK30-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK30-NEXT: br label [[FOR_INC53:%.*]] -// CHECK30: for.inc53: -// CHECK30-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK30-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK30-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK30-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK30-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK30-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK30: for.end57: -// CHECK30-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK30-NEXT: ret i32 [[TMP29]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP8]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK30-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK30-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK30-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK30-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK30-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK30-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK30-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK30-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK30-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK30-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK30-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK30-NEXT: ret i32 [[ADD9]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK30-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK30-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK30-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK30-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP6]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK30-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP5]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK31-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: ret i64 0 -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK31-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK31-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK31-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK31-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK31-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK31-NEXT: br label [[FOR_COND3:%.*]] -// CHECK31: for.cond3: -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK31-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK31-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK31: for.body5: -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK31-NEXT: br label [[FOR_INC7:%.*]] -// CHECK31: for.inc7: -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK31-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK31-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK31-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK31: for.end8: -// CHECK31-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK31-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK31-NEXT: br label [[FOR_COND9:%.*]] -// CHECK31: for.cond9: -// CHECK31-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK31-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK31-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK31: for.body11: -// CHECK31-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK31-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK31-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK31-NEXT: br label [[FOR_INC14:%.*]] -// CHECK31: for.inc14: -// CHECK31-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK31-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK31-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK31-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK31: for.end15: -// CHECK31-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK31-NEXT: br label [[FOR_COND17:%.*]] -// CHECK31: for.cond17: -// CHECK31-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK31-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK31-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK31-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK31: for.body20: -// CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK31-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK31-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK31-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK31-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK31-NEXT: br label [[FOR_INC25:%.*]] -// CHECK31: for.inc25: -// CHECK31-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK31-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK31-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK31-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK31-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK31-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK31: for.end29: -// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK31-NEXT: br label [[FOR_COND31:%.*]] -// CHECK31: for.cond31: -// CHECK31-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK31-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK31-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK31-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK31: for.body34: -// CHECK31-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK31-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK31-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK31-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK31-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK31-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK31-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK31-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK31-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK31-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK31-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK31-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK31-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK31-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK31-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK31-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK31-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK31-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK31-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK31-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK31-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK31-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK31-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK31-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK31-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK31-NEXT: br label [[FOR_INC53:%.*]] -// CHECK31: for.inc53: -// CHECK31-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK31-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK31-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK31-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK31-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK31-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK31: for.end57: -// CHECK31-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK31-NEXT: ret i32 [[TMP27]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK31-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK31-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK31-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK31-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK31-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK31-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK31-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK31-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK31-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK31-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK31-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK31-NEXT: ret i32 [[ADD9]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK31-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK31-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK31-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK31-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP6]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK31-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP5]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK32-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: ret i64 0 -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK32-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK32-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK32-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK32-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK32-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK32-NEXT: br label [[FOR_COND3:%.*]] -// CHECK32: for.cond3: -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK32-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK32: for.body5: -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK32-NEXT: br label [[FOR_INC7:%.*]] -// CHECK32: for.inc7: -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK32-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK32-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK32-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK32: for.end8: -// CHECK32-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK32-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK32-NEXT: br label [[FOR_COND9:%.*]] -// CHECK32: for.cond9: -// CHECK32-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK32-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK32-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK32: for.body11: -// CHECK32-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK32-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK32-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK32-NEXT: br label [[FOR_INC14:%.*]] -// CHECK32: for.inc14: -// CHECK32-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK32-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK32-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK32-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK32: for.end15: -// CHECK32-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK32-NEXT: br label [[FOR_COND17:%.*]] -// CHECK32: for.cond17: -// CHECK32-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK32-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK32-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK32-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK32: for.body20: -// CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK32-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK32-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK32-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK32-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK32-NEXT: br label [[FOR_INC25:%.*]] -// CHECK32: for.inc25: -// CHECK32-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK32-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK32-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK32-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK32-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK32-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK32: for.end29: -// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK32-NEXT: br label [[FOR_COND31:%.*]] -// CHECK32: for.cond31: -// CHECK32-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK32-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK32-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK32-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK32: for.body34: -// CHECK32-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK32-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK32-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK32-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK32-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK32-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK32-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK32-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK32-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK32-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK32-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK32-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK32-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK32-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK32-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK32-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK32-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK32-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK32-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK32-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK32-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK32-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK32-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK32-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK32-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK32-NEXT: br label [[FOR_INC53:%.*]] -// CHECK32: for.inc53: -// CHECK32-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK32-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK32-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK32-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK32-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK32-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK32: for.end57: -// CHECK32-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK32-NEXT: ret i32 [[TMP27]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK32-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK32-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK32-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK32-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK32-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK32-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK32-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK32-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK32-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK32-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK32-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK32-NEXT: ret i32 [[ADD9]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK32-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK32-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK32-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK32-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP6]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK32-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP5]] +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK16-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK16-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK16-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK16-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK16-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK16-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK16-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK16-NEXT: ret void // diff --git a/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1108,62 +1108,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG22:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG22]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG23:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG24:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG26:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG27:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG30:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG30]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG30]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG31:![0-9]+]], !llvm.loop [[LOOP32:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG35:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG35]] -// diff --git a/clang/test/OpenMP/target_parallel_if_codegen.cpp b/clang/test/OpenMP/target_parallel_if_codegen.cpp --- a/clang/test/OpenMP/target_parallel_if_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_if_codegen.cpp @@ -7,64 +7,64 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2334,445 +2334,1238 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK5: omp_if.then: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK5: omp_if.else: +// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK5-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] +// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK5-NEXT: br label [[OMP_IF_END]] +// CHECK5: omp_if.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK5-SAME: () #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 +// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK5: omp_if.then: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK5: omp_if.else: +// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK5-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]] +// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK5-NEXT: br label [[OMP_IF_END]] +// CHECK5: omp_if.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK5-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK5-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK5-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK5-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK5-NEXT: ret i32 [[CONV7]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK5: omp_if.then: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK5: omp_if.else: +// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK5-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK5-NEXT: br label [[OMP_IF_END]] +// CHECK5: omp_if.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: ret i32 [[ADD]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK5-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]] +// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK5-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK6: omp_if.then: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK6: omp_if.else: +// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK6-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] +// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_IF_END]] +// CHECK6: omp_if.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK6-SAME: () #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 +// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK6: omp_if.then: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK6: omp_if.else: +// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK6-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]] +// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_IF_END]] +// CHECK6: omp_if.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK6-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK6-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK6-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK6-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK6-NEXT: ret i32 [[CONV7]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: ret i32 [[ADD]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK6: omp_if.then: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK6: omp_if.else: +// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK6-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_IF_END]] +// CHECK6: omp_if.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK6-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]] +// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK6-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK7-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK7-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.else: +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK7-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK7-SAME: () #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.else: +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK7-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK7-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK7-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK7-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK7-NEXT: ret i32 [[CONV7]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: ret i32 [[ADD]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.else: +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK7-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK7-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK7-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK7-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK8-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK8-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.else: +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK8-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.else: +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK8-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK8-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK8-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK8-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK8-NEXT: ret i32 [[CONV7]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.else: +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK8-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK8-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: ret i32 [[ADD]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK8-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK8-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z3bari +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP6]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK9-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 +// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** +// CHECK9-NEXT: store double* [[A]], double** [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1 +// CHECK9-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK9-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR2:[0-9]+]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5 +// CHECK9-NEXT: [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8 +// CHECK9-NEXT: store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK9-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK9-NEXT: [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1 +// CHECK9-NEXT: [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8* +// CHECK9-NEXT: [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8 +// CHECK9-NEXT: store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1 +// CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4 +// CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** +// CHECK9-NEXT: store double* [[A13]], double** [[TMP33]], align 8 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP34]], align 8 +// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* +// CHECK9-NEXT: store i64 [[TMP28]], i64* [[TMP36]], align 8 +// CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* +// CHECK9-NEXT: store i64 [[TMP28]], i64* [[TMP38]], align 8 +// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK9-NEXT: [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1 +// CHECK9-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) +// CHECK9-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 +// CHECK9-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] +// CHECK9: omp_offload.failed18: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT19]] +// CHECK9: omp_offload.cont19: // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK9-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]] // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: -// CHECK9-NEXT: ret void +// CHECK9-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP46:%.*]] = load double, double* [[A20]], align 8 +// CHECK9-NEXT: [[CONV21:%.*]] = fptosi double [[TMP46]] to i32 +// CHECK9-NEXT: ret i32 [[CONV21]] // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: () #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 +// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK9-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK9-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK9-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK9-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) +// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK9-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 +// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] +// CHECK9: omp_if.then5: +// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK9: omp_offload.failed6: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK9: omp_offload.cont7: +// CHECK9-NEXT: br label [[OMP_IF_END9:%.*]] +// CHECK9: omp_if.else8: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_IF_END9]] +// CHECK9: omp_if.end9: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK9-NEXT: ret i32 [[ADD]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[A_CASTED1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) +// CHECK9-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK9-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32* +// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP13]], i16* [[CONV3]], align 2 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK9-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK9-NEXT: store i64 [[TMP12]], i64* [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK9-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK9-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK9: omp_offload.failed7: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK9: omp_offload.cont8: +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP29]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2796,20 +3589,20 @@ // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9: omp_if.else: // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK9-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]] +// CHECK9-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2830,7 +3623,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -2846,20 +3639,20 @@ // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9: omp_if.else: // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK9-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK9-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2873,8 +3666,61 @@ // CHECK9-NEXT: ret void // // +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK9-SAME: () #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -2890,13 +3736,13 @@ // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK9-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]] +// CHECK9-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2912,7 +3758,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2930,12 +3776,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2955,61 +3801,315 @@ // CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z3bari +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP6]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK10-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 +// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** +// CHECK10-NEXT: store double* [[A]], double** [[TMP8]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1 +// CHECK10-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK10-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR2:[0-9]+]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5 +// CHECK10-NEXT: [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8 +// CHECK10-NEXT: store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK10-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK10-NEXT: [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1 +// CHECK10-NEXT: [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8* +// CHECK10-NEXT: [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8 +// CHECK10-NEXT: store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1 +// CHECK10-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4 +// CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** +// CHECK10-NEXT: store double* [[A13]], double** [[TMP33]], align 8 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP34]], align 8 +// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* +// CHECK10-NEXT: store i64 [[TMP28]], i64* [[TMP36]], align 8 +// CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* +// CHECK10-NEXT: store i64 [[TMP28]], i64* [[TMP38]], align 8 +// CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK10-NEXT: [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1 +// CHECK10-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) +// CHECK10-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 +// CHECK10-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] +// CHECK10: omp_offload.failed18: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT19]] +// CHECK10: omp_offload.cont19: // CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK10-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]] // CHECK10-NEXT: br label [[OMP_IF_END]] // CHECK10: omp_if.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: ret void +// CHECK10-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP46:%.*]] = load double, double* [[A20]], align 8 +// CHECK10-NEXT: [[CONV21:%.*]] = fptosi double [[TMP46]] to i32 +// CHECK10-NEXT: ret i32 [[CONV21]] // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 +// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK10-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK10-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK10-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP5]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP8]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK10-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK10-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) +// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK10-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 +// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 +// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] +// CHECK10: omp_if.then5: +// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK10-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK10: omp_offload.failed6: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK10: omp_offload.cont7: +// CHECK10-NEXT: br label [[OMP_IF_END9:%.*]] +// CHECK10: omp_if.else8: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_IF_END9]] +// CHECK10: omp_if.end9: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK10-NEXT: ret i32 [[ADD]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: ret void +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[A_CASTED1:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) +// CHECK10-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK10-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32* +// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP13]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK10-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK10-NEXT: store i64 [[TMP12]], i64* [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK10-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK10-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK10: omp_offload.failed7: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK10: omp_offload.cont8: +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP29]] // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3033,20 +4133,20 @@ // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10: omp_if.else: // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK10-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]] +// CHECK10-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] // CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: br label [[OMP_IF_END]] // CHECK10: omp_if.end: // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3067,7 +4167,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -3083,20 +4183,20 @@ // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10: omp_if.else: // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK10-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] // CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: br label [[OMP_IF_END]] // CHECK10: omp_if.end: // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3110,8 +4210,61 @@ // CHECK10-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK10-SAME: () #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -3127,13 +4280,13 @@ // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK10-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]] +// CHECK10-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] // CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3149,7 +4302,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3167,12 +4320,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3192,61 +4345,312 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK10-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z3bari +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP6]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK11-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 +// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK11-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK11-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** +// CHECK11-NEXT: store double* [[A]], double** [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1 +// CHECK11-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK11-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR2:[0-9]+]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5 +// CHECK11-NEXT: [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8 +// CHECK11-NEXT: store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK11-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK11-NEXT: [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1 +// CHECK11-NEXT: [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8* +// CHECK11-NEXT: [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8 +// CHECK11-NEXT: store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4 +// CHECK11-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11: omp_if.then: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK11-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** +// CHECK11-NEXT: store double* [[A12]], double** [[TMP33]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* +// CHECK11-NEXT: store i32 [[TMP28]], i32* [[TMP36]], align 4 +// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK11-NEXT: store i32 [[TMP28]], i32* [[TMP38]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK11-NEXT: [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1 +// CHECK11-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) +// CHECK11-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 +// CHECK11-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK11: omp_offload.failed17: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK11: omp_offload.cont18: // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11: omp_if.else: -// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK11-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] -// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]] // CHECK11-NEXT: br label [[OMP_IF_END]] // CHECK11: omp_if.end: -// CHECK11-NEXT: ret void +// CHECK11-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP46:%.*]] = load double, double* [[A19]], align 4 +// CHECK11-NEXT: [[CONV20:%.*]] = fptosi double [[TMP46]] to i32 +// CHECK11-NEXT: ret i32 [[CONV20]] // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 +// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK11-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK11-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK11-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK11-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) +// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK11-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 +// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] +// CHECK11: omp_if.then5: +// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK11-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK11: omp_offload.failed6: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK11: omp_offload.cont7: +// CHECK11-NEXT: br label [[OMP_IF_END9:%.*]] +// CHECK11: omp_if.else8: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_IF_END9]] +// CHECK11: omp_if.end9: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK11-NEXT: ret i32 [[ADD]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: ret void +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[A_CASTED1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) +// CHECK11-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK11-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], i32* [[A_CASTED1]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP13]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK11-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK11-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK11: omp_offload.failed5: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK11: omp_offload.cont6: +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP29]] // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3268,20 +4672,20 @@ // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11: omp_if.then: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11: omp_if.else: // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK11-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]] +// CHECK11-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] // CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: br label [[OMP_IF_END]] // CHECK11: omp_if.end: // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3301,7 +4705,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -3317,20 +4721,20 @@ // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11: omp_if.then: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11: omp_if.else: // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK11-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK11-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] // CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: br label [[OMP_IF_END]] // CHECK11: omp_if.end: // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3344,8 +4748,61 @@ // CHECK11-NEXT: ret void // // +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK11-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] +// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK11-SAME: () #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -3359,13 +4816,13 @@ // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK11-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]] +// CHECK11-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] // CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3380,7 +4837,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3396,12 +4853,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3420,61 +4877,312 @@ // CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK11-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z3bari +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP6]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK12-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 +// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK12-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK12-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** +// CHECK12-NEXT: store double* [[A]], double** [[TMP8]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1 +// CHECK12-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK12-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR2:[0-9]+]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5 +// CHECK12-NEXT: [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8 +// CHECK12-NEXT: store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK12-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK12-NEXT: [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1 +// CHECK12-NEXT: [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8* +// CHECK12-NEXT: [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8 +// CHECK12-NEXT: store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4 +// CHECK12-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12: omp_if.then: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** +// CHECK12-NEXT: store double* [[A12]], double** [[TMP33]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* +// CHECK12-NEXT: store i32 [[TMP28]], i32* [[TMP36]], align 4 +// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK12-NEXT: store i32 [[TMP28]], i32* [[TMP38]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK12-NEXT: [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1 +// CHECK12-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) +// CHECK12-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 +// CHECK12-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK12: omp_offload.failed17: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK12: omp_offload.cont18: // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12: omp_if.else: -// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK12-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] -// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]] // CHECK12-NEXT: br label [[OMP_IF_END]] // CHECK12: omp_if.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: ret void +// CHECK12-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP46:%.*]] = load double, double* [[A19]], align 4 +// CHECK12-NEXT: [[CONV20:%.*]] = fptosi double [[TMP46]] to i32 +// CHECK12-NEXT: ret i32 [[CONV20]] // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK12-SAME: () #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 +// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK12-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK12-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK12-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP5]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP8]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK12-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK12-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) +// CHECK12-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK12-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 +// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] +// CHECK12: omp_if.then5: +// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK12-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK12: omp_offload.failed6: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK12: omp_offload.cont7: +// CHECK12-NEXT: br label [[OMP_IF_END9:%.*]] +// CHECK12: omp_if.else8: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_IF_END9]] +// CHECK12: omp_if.end9: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK12-NEXT: ret i32 [[ADD]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: ret void +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[A_CASTED1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) +// CHECK12-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK12-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP11]], i32* [[A_CASTED1]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP13]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK12-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK12-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK12: omp_offload.failed5: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK12: omp_offload.cont6: +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP29]] // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3496,20 +5204,20 @@ // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12: omp_if.then: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12: omp_if.else: // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK12-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]] +// CHECK12-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] // CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK12-NEXT: br label [[OMP_IF_END]] // CHECK12: omp_if.end: // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3529,7 +5237,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -3545,20 +5253,20 @@ // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12: omp_if.then: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12: omp_if.else: // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK12-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK12-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] // CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK12-NEXT: br label [[OMP_IF_END]] // CHECK12: omp_if.end: // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3572,8 +5280,61 @@ // CHECK12-NEXT: ret void // // +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK12-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK12-SAME: () #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -3587,13 +5348,13 @@ // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK12-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]] +// CHECK12-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] // CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3608,7 +5369,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3624,12 +5385,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3648,4236 +5409,939 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK12-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK13: omp_if.then: +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK13: omp_if.else: +// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK13-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] +// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK13-NEXT: br label [[OMP_IF_END]] +// CHECK13: omp_if.end: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK13-SAME: () #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 +// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK13: omp_if.then: +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK13: omp_if.else: +// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK13-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]] +// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK13-NEXT: br label [[OMP_IF_END]] +// CHECK13: omp_if.end: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK13-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK13-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK13-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK13-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK13-NEXT: ret i32 [[CONV7]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK13-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK13: omp_if.then: +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK13: omp_if.else: +// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK13-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK13-NEXT: br label [[OMP_IF_END]] +// CHECK13: omp_if.end: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK13-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: ret i32 [[ADD]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK13-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]] +// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK13-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK14: omp_if.then: +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK14: omp_if.else: +// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK14-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] +// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK14-NEXT: br label [[OMP_IF_END]] +// CHECK14: omp_if.end: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK14-SAME: () #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 +// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK14: omp_if.then: +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK14: omp_if.else: +// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK14-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]] +// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK14-NEXT: br label [[OMP_IF_END]] +// CHECK14: omp_if.end: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK14-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK14-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK14-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK14-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK14-NEXT: ret i32 [[CONV7]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: ret i32 [[ADD]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK14-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK14: omp_if.then: +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK14: omp_if.else: +// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK14-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK14-NEXT: br label [[OMP_IF_END]] +// CHECK14: omp_if.end: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK14-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK14-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]] +// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK14-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK15-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK15-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK15-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK15: omp_if.then: +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK15: omp_if.else: +// CHECK15-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK15-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] +// CHECK15-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK15-NEXT: br label [[OMP_IF_END]] +// CHECK15: omp_if.end: +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK15-SAME: () #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK15-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK15: omp_if.then: +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK15-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK15: omp_if.else: +// CHECK15-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK15-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]] +// CHECK15-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK15-NEXT: br label [[OMP_IF_END]] +// CHECK15: omp_if.end: +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK15-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK15-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK15-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK15-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK15-NEXT: ret i32 [[CONV7]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK15-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK15-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK15: omp_if.then: +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK15-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK15: omp_if.else: +// CHECK15-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK15-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK15-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK15-NEXT: br label [[OMP_IF_END]] +// CHECK15: omp_if.end: +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK15-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: ret i32 [[ADD]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK15-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]] +// CHECK15-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK15-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK16-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK16-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK16-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK16: omp_if.then: +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK16: omp_if.else: +// CHECK16-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK16-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] +// CHECK16-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK16-NEXT: br label [[OMP_IF_END]] +// CHECK16: omp_if.end: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK16-SAME: () #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK16-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK16: omp_if.then: +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK16-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK16: omp_if.else: +// CHECK16-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK16-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]] +// CHECK16-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK16-NEXT: br label [[OMP_IF_END]] +// CHECK16: omp_if.end: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK16-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK16-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK16-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK16-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK16-NEXT: ret i32 [[CONV7]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK16-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 +// CHECK16-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK16: omp_if.then: +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK16-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK16: omp_if.else: +// CHECK16-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK16-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] +// CHECK16-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK16-NEXT: br label [[OMP_IF_END]] +// CHECK16: omp_if.end: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK16-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: ret i32 [[ADD]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK16-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]] +// CHECK16-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK16-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP6]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK17-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK17-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK17-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK17-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** -// CHECK17-NEXT: store double* [[A]], double** [[TMP8]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1 -// CHECK17-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR2:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5 -// CHECK17-NEXT: [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8 -// CHECK17-NEXT: store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1 -// CHECK17-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 -// CHECK17-NEXT: [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1 -// CHECK17-NEXT: [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8* -// CHECK17-NEXT: [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8 -// CHECK17-NEXT: store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1 -// CHECK17-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8 -// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4 -// CHECK17-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** -// CHECK17-NEXT: store double* [[A13]], double** [[TMP33]], align 8 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP34]], align 8 -// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* -// CHECK17-NEXT: store i64 [[TMP28]], i64* [[TMP36]], align 8 -// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* -// CHECK17-NEXT: store i64 [[TMP28]], i64* [[TMP38]], align 8 -// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 -// CHECK17-NEXT: [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1 -// CHECK17-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) -// CHECK17-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 -// CHECK17-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] -// CHECK17: omp_offload.failed18: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT19]] -// CHECK17: omp_offload.cont19: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP46:%.*]] = load double, double* [[A20]], align 8 -// CHECK17-NEXT: [[CONV21:%.*]] = fptosi double [[TMP46]] to i32 -// CHECK17-NEXT: ret i32 [[CONV21]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK17-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK17-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK17-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK17-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK17-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP5]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP8]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK17-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK17-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) -// CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK17-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 -// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] -// CHECK17: omp_if.then5: -// CHECK17-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK17-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK17: omp_offload.failed6: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK17: omp_offload.cont7: -// CHECK17-NEXT: br label [[OMP_IF_END9:%.*]] -// CHECK17: omp_if.else8: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_IF_END9]] -// CHECK17: omp_if.end9: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK17-NEXT: ret i32 [[ADD]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[A_CASTED1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) -// CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 -// CHECK17-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32* -// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK17: omp_offload.failed7: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK17: omp_offload.cont8: -// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP29]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 -// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK17-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] -// CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK17-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] -// CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK17-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] -// CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK17-SAME: () #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK17-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] -// CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP6]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK18-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK18-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK18-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK18-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** -// CHECK18-NEXT: store double* [[A]], double** [[TMP8]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1 -// CHECK18-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5 -// CHECK18-NEXT: [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8 -// CHECK18-NEXT: store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1 -// CHECK18-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 -// CHECK18-NEXT: [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1 -// CHECK18-NEXT: [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8* -// CHECK18-NEXT: [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8 -// CHECK18-NEXT: store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1 -// CHECK18-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8 -// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4 -// CHECK18-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** -// CHECK18-NEXT: store double* [[A13]], double** [[TMP33]], align 8 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP34]], align 8 -// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* -// CHECK18-NEXT: store i64 [[TMP28]], i64* [[TMP36]], align 8 -// CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* -// CHECK18-NEXT: store i64 [[TMP28]], i64* [[TMP38]], align 8 -// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 -// CHECK18-NEXT: [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1 -// CHECK18-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) -// CHECK18-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 -// CHECK18-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] -// CHECK18: omp_offload.failed18: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT19]] -// CHECK18: omp_offload.cont19: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP46:%.*]] = load double, double* [[A20]], align 8 -// CHECK18-NEXT: [[CONV21:%.*]] = fptosi double [[TMP46]] to i32 -// CHECK18-NEXT: ret i32 [[CONV21]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK18-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK18-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK18-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK18-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK18-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP5]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP8]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK18-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK18-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) -// CHECK18-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK18-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 -// CHECK18-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 -// CHECK18-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] -// CHECK18: omp_if.then5: -// CHECK18-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK18-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK18: omp_offload.failed6: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK18: omp_offload.cont7: -// CHECK18-NEXT: br label [[OMP_IF_END9:%.*]] -// CHECK18: omp_if.else8: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_IF_END9]] -// CHECK18: omp_if.end9: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK18-NEXT: ret i32 [[ADD]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[A_CASTED1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) -// CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 -// CHECK18-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32* -// CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK18: omp_offload.failed7: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK18: omp_offload.cont8: -// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP29]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 -// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK18-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] -// CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK18-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] -// CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK18-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] -// CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK18-SAME: () #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK18-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] -// CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP6]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK19-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK19-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK19-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK19-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** -// CHECK19-NEXT: store double* [[A]], double** [[TMP8]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1 -// CHECK19-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5 -// CHECK19-NEXT: [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8 -// CHECK19-NEXT: store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1 -// CHECK19-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 -// CHECK19-NEXT: [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1 -// CHECK19-NEXT: [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8* -// CHECK19-NEXT: [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8 -// CHECK19-NEXT: store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1 -// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4 -// CHECK19-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** -// CHECK19-NEXT: store double* [[A12]], double** [[TMP33]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP34]], align 4 -// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* -// CHECK19-NEXT: store i32 [[TMP28]], i32* [[TMP36]], align 4 -// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK19-NEXT: store i32 [[TMP28]], i32* [[TMP38]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 -// CHECK19-NEXT: [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1 -// CHECK19-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) -// CHECK19-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 -// CHECK19-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK19: omp_offload.failed17: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK19: omp_offload.cont18: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP46:%.*]] = load double, double* [[A19]], align 4 -// CHECK19-NEXT: [[CONV20:%.*]] = fptosi double [[TMP46]] to i32 -// CHECK19-NEXT: ret i32 [[CONV20]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK19-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK19-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK19-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK19-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK19-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP5]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP8]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK19-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK19-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) -// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK19-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 -// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] -// CHECK19: omp_if.then5: -// CHECK19-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK19-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK19: omp_offload.failed6: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK19: omp_offload.cont7: -// CHECK19-NEXT: br label [[OMP_IF_END9:%.*]] -// CHECK19: omp_if.else8: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_IF_END9]] -// CHECK19: omp_if.end9: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK19-NEXT: ret i32 [[ADD]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[A_CASTED1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) -// CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 -// CHECK19-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP11]], i32* [[A_CASTED1]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP13]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK19: omp_offload.failed5: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK19: omp_offload.cont6: -// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP29]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK19-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] -// CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK19-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] -// CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK19-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] -// CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK19-SAME: () #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK19-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] -// CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP6]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK20-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK20-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK20-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK20-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** -// CHECK20-NEXT: store double* [[A]], double** [[TMP8]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1 -// CHECK20-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5 -// CHECK20-NEXT: [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8 -// CHECK20-NEXT: store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1 -// CHECK20-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 -// CHECK20-NEXT: [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1 -// CHECK20-NEXT: [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8* -// CHECK20-NEXT: [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8 -// CHECK20-NEXT: store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1 -// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4 -// CHECK20-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** -// CHECK20-NEXT: store double* [[A12]], double** [[TMP33]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP34]], align 4 -// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* -// CHECK20-NEXT: store i32 [[TMP28]], i32* [[TMP36]], align 4 -// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK20-NEXT: store i32 [[TMP28]], i32* [[TMP38]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 -// CHECK20-NEXT: [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1 -// CHECK20-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) -// CHECK20-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 -// CHECK20-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK20: omp_offload.failed17: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK20: omp_offload.cont18: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP46:%.*]] = load double, double* [[A19]], align 4 -// CHECK20-NEXT: [[CONV20:%.*]] = fptosi double [[TMP46]] to i32 -// CHECK20-NEXT: ret i32 [[CONV20]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK20-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK20-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK20-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK20-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK20-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP5]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP8]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK20-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK20-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) -// CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK20-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 -// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] -// CHECK20: omp_if.then5: -// CHECK20-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK20-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK20: omp_offload.failed6: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK20: omp_offload.cont7: -// CHECK20-NEXT: br label [[OMP_IF_END9:%.*]] -// CHECK20: omp_if.else8: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_IF_END9]] -// CHECK20: omp_if.end9: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK20-NEXT: ret i32 [[ADD]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[A_CASTED1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) -// CHECK20-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 -// CHECK20-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP11]], i32* [[A_CASTED1]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP13]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) -// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK20: omp_offload.failed5: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK20: omp_offload.cont6: -// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP29]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK20-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] -// CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK20-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] -// CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK20-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] -// CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK20-SAME: () #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK20-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] -// CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP6]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK21-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK21-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK21-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK21-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK21-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK21-NEXT: ret i32 [[CONV7]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: ret i32 [[ADD]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK21-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP6]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK22-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK22-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK22-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK22-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK22-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK22-NEXT: ret i32 [[CONV7]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: ret i32 [[ADD]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK22-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP6]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK23-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK23-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK23-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK23-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK23-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK23-NEXT: ret i32 [[CONV7]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: ret i32 [[ADD]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK23-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP6]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK24-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK24-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK24-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK24-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK24-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK24-NEXT: ret i32 [[CONV7]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: ret i32 [[ADD]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK24-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK25-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK25: omp_if.then: -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK25: omp_if.else: -// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK25-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] -// CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK25-NEXT: br label [[OMP_IF_END]] -// CHECK25: omp_if.end: -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK25-SAME: () #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 -// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 -// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK25: omp_if.then: -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) -// CHECK25-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK25: omp_if.else: -// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK25-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]] -// CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK25-NEXT: br label [[OMP_IF_END]] -// CHECK25: omp_if.end: -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK25-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 -// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK25: omp_if.then: -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK25-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK25: omp_if.else: -// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK25-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] -// CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK25-NEXT: br label [[OMP_IF_END]] -// CHECK25: omp_if.end: -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK25-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK25-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]] -// CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK26-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK26: omp_if.then: -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK26: omp_if.else: -// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK26-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] -// CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK26-NEXT: br label [[OMP_IF_END]] -// CHECK26: omp_if.end: -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK26-SAME: () #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 -// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 -// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK26: omp_if.then: -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) -// CHECK26-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK26: omp_if.else: -// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK26-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]] -// CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK26-NEXT: br label [[OMP_IF_END]] -// CHECK26: omp_if.end: -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK26-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 -// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK26: omp_if.then: -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK26-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK26: omp_if.else: -// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK26-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] -// CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK26-NEXT: br label [[OMP_IF_END]] -// CHECK26: omp_if.end: -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK26-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK26-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]] -// CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK27-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK27: omp_if.then: -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK27: omp_if.else: -// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK27-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] -// CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK27-NEXT: br label [[OMP_IF_END]] -// CHECK27: omp_if.end: -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK27-SAME: () #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 -// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK27: omp_if.then: -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) -// CHECK27-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK27: omp_if.else: -// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK27-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]] -// CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK27-NEXT: br label [[OMP_IF_END]] -// CHECK27: omp_if.end: -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK27-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 -// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK27: omp_if.then: -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK27-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK27: omp_if.else: -// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK27-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] -// CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK27-NEXT: br label [[OMP_IF_END]] -// CHECK27: omp_if.end: -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK27-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK27-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]] -// CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK28-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK28: omp_if.then: -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK28: omp_if.else: -// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK28-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]] -// CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK28-NEXT: br label [[OMP_IF_END]] -// CHECK28: omp_if.end: -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK28-SAME: () #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 -// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK28: omp_if.then: -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) -// CHECK28-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK28: omp_if.else: -// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK28-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]] -// CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK28-NEXT: br label [[OMP_IF_END]] -// CHECK28: omp_if.end: -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK28-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 -// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 -// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK28: omp_if.then: -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK28-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK28: omp_if.else: -// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK28-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]] -// CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK28-NEXT: br label [[OMP_IF_END]] -// CHECK28: omp_if.end: -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK28-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK28-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]] -// CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP6]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK29-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK29-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK29-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK29-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK29-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK29-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK29-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK29-NEXT: ret i32 [[CONV7]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK29-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK29-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK29-NEXT: ret i32 [[ADD]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK29-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP6]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK30-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK30-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK30-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK30-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK30-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK30-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK30-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK30-NEXT: ret i32 [[CONV7]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK30-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK30-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK30-NEXT: ret i32 [[ADD]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK30-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP6]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK31-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK31-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK31-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK31-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK31-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK31-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK31-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK31-NEXT: ret i32 [[CONV7]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK31-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK31-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK31-NEXT: ret i32 [[ADD]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK31-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP6]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK32-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK32-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK32-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK32-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK32-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK32-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK32-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK32-NEXT: ret i32 [[CONV7]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK32-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK32-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK32-NEXT: ret i32 [[ADD]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK32-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: ret void // diff --git a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp --- a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp @@ -7,65 +7,65 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1989,426 +1989,1004 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK5-NEXT: ret i32 [[CONV4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK5-SAME: () #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: ret i32 [[ADD2]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK6-NEXT: ret i32 [[CONV4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: ret i32 [[ADD2]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK7-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK7-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK7-NEXT: ret i32 [[CONV4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: ret i32 [[ADD2]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK7-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK8-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK8-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK8-NEXT: ret i32 [[CONV4]] +// CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: ret i32 [[ADD2]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK8-SAME: () #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK8-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z3bari +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP6]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK9-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK9-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK9-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK9-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK9-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) +// CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK9-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK9: omp_offload.failed7: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK9: omp_offload.cont8: +// CHECK9-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK9-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK9-NEXT: ret i32 [[CONV10]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) +// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK9-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK9-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK9-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK9: omp_offload.failed7: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK9: omp_offload.cont8: +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK9-NEXT: ret i32 [[ADD9]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) +// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK9-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK9-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK9-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 +// CHECK9-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) +// CHECK9-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK9-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK9: omp_offload.failed3: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK9: omp_offload.cont4: +// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP30]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2427,12 +3005,12 @@ // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2453,19 +3031,19 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2479,17 +3057,63 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK9-SAME: () #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK9-SAME: () #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2499,7 +3123,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2524,12 +3148,12 @@ // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2549,54 +3173,277 @@ // CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@_Z3bari +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP6]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK10-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK10-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK10-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK10-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK10-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) +// CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK10-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK10: omp_offload.failed7: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK10: omp_offload.cont8: +// CHECK10-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK10-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK10-NEXT: ret i32 [[CONV10]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: ret void +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) +// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK10-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK10-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK10-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK10: omp_offload.failed7: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK10: omp_offload.cont8: +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK10-NEXT: ret i32 [[ADD9]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) +// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK10-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK10-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK10-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 +// CHECK10-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) +// CHECK10-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK10-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK10: omp_offload.failed3: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK10: omp_offload.cont4: +// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP30]] // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2615,12 +3462,12 @@ // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2641,19 +3488,19 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2667,17 +3514,63 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK10-SAME: () #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2687,7 +3580,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2712,12 +3605,12 @@ // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2737,52 +3630,272 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: ret void +// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@_Z3bari +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP6]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK11-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: ret void +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK11-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK11-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK11-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK11-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) +// CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK11-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK11: omp_offload.failed6: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK11: omp_offload.cont7: +// CHECK11-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK11-NEXT: ret i32 [[CONV]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) +// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK11-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK11-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK11: omp_offload.failed6: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK11: omp_offload.cont7: +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK11-NEXT: ret i32 [[ADD8]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) +// CHECK11-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK11-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK11-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 +// CHECK11-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) +// CHECK11-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK11-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK11: omp_offload.failed2: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK11: omp_offload.cont3: +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP30]] // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2798,12 +3911,12 @@ // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2823,19 +3936,19 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2849,17 +3962,61 @@ // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK11-SAME: () #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK11-SAME: () #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2869,7 +4026,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2892,12 +4049,12 @@ // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2916,52 +4073,272 @@ // CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void +// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@_Z3bari +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP6]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK12-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK12-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK12-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK12-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK12-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) +// CHECK12-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK12-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK12: omp_offload.failed6: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK12: omp_offload.cont7: +// CHECK12-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK12-NEXT: ret i32 [[CONV]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: ret void +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) +// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK12-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK12-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK12: omp_offload.failed6: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK12: omp_offload.cont7: +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK12-NEXT: ret i32 [[ADD8]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) +// CHECK12-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK12-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK12-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 +// CHECK12-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) +// CHECK12-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK12-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK12: omp_offload.failed2: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK12: omp_offload.cont3: +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP30]] // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2977,12 +4354,12 @@ // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3002,19 +4379,19 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3028,17 +4405,61 @@ // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK12-SAME: () #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK12-SAME: () #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3048,7 +4469,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3071,12 +4492,12 @@ // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3095,3652 +4516,743 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK12-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK13-NEXT: ret i32 [[CONV4]] +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK13-SAME: () #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: ret i32 [[ADD2]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK14-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK14-NEXT: ret i32 [[CONV4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK14-SAME: () #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void // // -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: ret i32 [[ADD2]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK15-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK15-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK15-NEXT: ret i32 [[CONV4]] +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK15-SAME: () #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void // // -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: ret i32 [[ADD2]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK15-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK16-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK16-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK16-NEXT: ret i32 [[CONV4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK16-SAME: () #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void // // -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: ret i32 [[ADD2]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK16-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP6]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK17-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK17-NEXT: store double* [[A]], double** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK17-NEXT: store double* [[A3]], double** [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) -// CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK17: omp_offload.failed7: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK17: omp_offload.cont8: -// CHECK17-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 -// CHECK17-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK17-NEXT: ret i32 [[CONV10]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) -// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* -// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK17: omp_offload.failed7: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK17: omp_offload.cont8: -// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 -// CHECK17-NEXT: ret i32 [[ADD9]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) -// CHECK17-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK17-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* -// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK17-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 -// CHECK17-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) -// CHECK17-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK17-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK17: omp_offload.failed3: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK17: omp_offload.cont4: -// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP30]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK17-SAME: () #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP6]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK18-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK18-NEXT: store double* [[A]], double** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK18-NEXT: store double* [[A3]], double** [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) -// CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK18: omp_offload.failed7: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK18: omp_offload.cont8: -// CHECK18-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 -// CHECK18-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK18-NEXT: ret i32 [[CONV10]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) -// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* -// CHECK18-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK18: omp_offload.failed7: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK18: omp_offload.cont8: -// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 -// CHECK18-NEXT: ret i32 [[ADD9]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) -// CHECK18-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK18-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* -// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK18-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 -// CHECK18-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) -// CHECK18-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK18-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK18: omp_offload.failed3: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK18: omp_offload.cont4: -// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP30]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK18-SAME: () #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP6]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK19-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK19-NEXT: store double* [[A]], double** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK19-NEXT: store double* [[A2]], double** [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) -// CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK19: omp_offload.failed6: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK19: omp_offload.cont7: -// CHECK19-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK19-NEXT: ret i32 [[CONV]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) -// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK19: omp_offload.failed6: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK19: omp_offload.cont7: -// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 -// CHECK19-NEXT: ret i32 [[ADD8]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) -// CHECK19-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK19-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK19-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 -// CHECK19-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) -// CHECK19-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK19-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK19: omp_offload.failed2: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK19: omp_offload.cont3: -// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP30]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK19-SAME: () #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP6]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK20-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK20-NEXT: store double* [[A]], double** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK20-NEXT: store double* [[A2]], double** [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) -// CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK20: omp_offload.failed6: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK20: omp_offload.cont7: -// CHECK20-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK20-NEXT: ret i32 [[CONV]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) -// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) -// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK20: omp_offload.failed6: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK20: omp_offload.cont7: -// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 -// CHECK20-NEXT: ret i32 [[ADD8]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) -// CHECK20-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK20-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK20-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 -// CHECK20-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) -// CHECK20-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK20-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK20: omp_offload.failed2: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK20: omp_offload.cont3: -// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP30]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK20-SAME: () #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP6]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK21-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK21-NEXT: ret i32 [[CONV4]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: ret i32 [[ADD2]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP6]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK22-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK22-NEXT: ret i32 [[CONV4]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: ret i32 [[ADD2]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP6]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK23-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK23-NEXT: ret i32 [[CONV4]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: ret i32 [[ADD2]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP6]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK24-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK24-NEXT: ret i32 [[CONV4]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: ret i32 [[ADD2]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK25-SAME: () #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK26-SAME: () #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK27-SAME: () #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK28-SAME: () #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP6]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK29-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK29-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK29-NEXT: ret i32 [[CONV4]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: ret i32 [[ADD2]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP6]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK30-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK30-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK30-NEXT: ret i32 [[CONV4]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: ret i32 [[ADD2]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP6]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK31-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK31-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK31-NEXT: ret i32 [[CONV4]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: ret i32 [[ADD2]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP6]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK32-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK32-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK32-NEXT: ret i32 [[CONV4]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: ret i32 [[ADD2]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: ret void // diff --git a/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp b/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp --- a/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1000,25 +1000,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: ret i32 0, !dbg [[DBG18:![0-9]+]] -// diff --git a/clang/test/OpenMP/target_teams_codegen.cpp b/clang/test/OpenMP/target_teams_codegen.cpp --- a/clang/test/OpenMP/target_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_codegen.cpp @@ -7,64 +7,64 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK26 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -5752,978 +5752,2488 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK5-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK5-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK5-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK5-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK5-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK5-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK5-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK5-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK5-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK5-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK5-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK5-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK5-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK5-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK5-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK5-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK5-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK5-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK5-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK5-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK5-NEXT: ret i32 [[TMP20]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK5-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK5-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK5-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK5-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK5-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK5-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK5-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK5-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK5-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK5-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK5-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK5-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK5-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK5-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK5-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK5-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK5-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK5-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK5-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK5-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[F:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK5-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK5-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK5-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK5-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK5-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK5-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK5-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK5-NEXT: ret i32 [[ADD9]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK5-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP4]] +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK5-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK5-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK5-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK5-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK5-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK6-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK6-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK6-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK6-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK6-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK6-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK6-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK6-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK6-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK6-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK6-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK6-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK6-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK6-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK6-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK6-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK6-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK6-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK6-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK6-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK6-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK6-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK6-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK6-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK6-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK6-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK6-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK6-NEXT: ret i32 [[TMP20]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK6-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK6-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK6-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK6-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK6-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK6-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK6-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK6-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK6-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK6-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK6-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK6-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK6-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK6-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK6-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK6-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK6-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK6-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK6-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK6-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK6-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK6-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK6-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK6-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[F:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK6-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK6-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK6-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK6-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK6-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK6-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK6-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK6-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK6-NEXT: ret i32 [[ADD9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK6-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP4]] +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK6-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK6-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK6-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK6-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK6-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK7-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK7-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK7-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK7-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK7-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK7-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK7-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK7-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK7-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK7-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK7-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK7-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK7-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK7-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK7-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK7-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK7-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK7-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK7-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK7-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK7-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK7-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK7-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK7-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK7-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK7-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK7-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK7-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[F:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK7-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK7-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK7-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK7-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK7-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK7-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK7-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK7-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK7-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK7-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK7-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK7-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK7-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK7-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK7-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK7-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK7-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK7-NEXT: ret i32 [[TMP18]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK7-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK7-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK7-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK7-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK7-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK7-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK7-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK7-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK7-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK7-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK7-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK7-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK7-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK7-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK7-NEXT: ret i32 [[ADD9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK7-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP4]] +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK8-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK8-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK8-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK8-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK8-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK8-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK8-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK8-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK8-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK8-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK8-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK8-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK8-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK8-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK8-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK8-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK8-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK8-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK8-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK8-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK8-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK8-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK8-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK8-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK8-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK8-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK8-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK8-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK8-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK8-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[F:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK8-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK8-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK8-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK8-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK8-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK8-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK8-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK8-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK8-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK8-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK8-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK8-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK8-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK8-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK8-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK8-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK8-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK8-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK8-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK8-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK8-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK8-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK8-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK8-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK8-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK8-NEXT: ret i32 [[TMP18]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK8-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK8-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK8-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK8-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK8-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK8-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 // CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK8-NEXT: store double [[INC]], double* [[A3]], align 4 // CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK8-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] +// CHECK8-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] // CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 // CHECK8-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK8-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK8-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK8-NEXT: ret i32 [[ADD9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK8-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP4]] +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK8-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK8-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK8-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 +// CHECK9-NEXT: [[NN:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK9-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK9-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK9-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK9-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK9-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 +// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK9-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 +// CHECK9-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) +// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK9-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) +// CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) +// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) +// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 +// CHECK9-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 +// CHECK9-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* +// CHECK9-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 +// CHECK9-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 +// CHECK9-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* +// CHECK9-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 +// CHECK9-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* +// CHECK9-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 +// CHECK9-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP65]], align 8 +// CHECK9-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 +// CHECK9-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK9-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 +// CHECK9-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK9-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* +// CHECK9-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 +// CHECK9-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 +// CHECK9-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK9-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 +// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK9-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 +// CHECK9-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK9-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 +// CHECK9-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK9-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 +// CHECK9-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP84]], align 8 +// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 +// CHECK9-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] +// CHECK9: omp_offload.failed19: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT20]] +// CHECK9: omp_offload.cont20: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* +// CHECK9-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 +// CHECK9-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 +// CHECK9-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 +// CHECK9-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] +// CHECK9: omp_if.then24: +// CHECK9-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK9-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK9-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 +// CHECK9-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64* +// CHECK9-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8 +// CHECK9-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* +// CHECK9-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8 +// CHECK9-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP99]], align 8 +// CHECK9-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP100]], align 8 +// CHECK9-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** +// CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 +// CHECK9-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** +// CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 +// CHECK9-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 40, i64* [[TMP105]], align 8 +// CHECK9-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP106]], align 8 +// CHECK9-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8 +// CHECK9-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 +// CHECK9-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP111]], align 8 +// CHECK9-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP112]], align 8 +// CHECK9-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** +// CHECK9-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 +// CHECK9-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** +// CHECK9-NEXT: store float* [[VLA]], float** [[TMP116]], align 8 +// CHECK9-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK9-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8 +// CHECK9-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP118]], align 8 +// CHECK9-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** +// CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 +// CHECK9-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** +// CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8 +// CHECK9-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK9-NEXT: store i64 400, i64* [[TMP123]], align 8 +// CHECK9-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP124]], align 8 +// CHECK9-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* +// CHECK9-NEXT: store i64 5, i64* [[TMP126]], align 8 +// CHECK9-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* +// CHECK9-NEXT: store i64 5, i64* [[TMP128]], align 8 +// CHECK9-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK9-NEXT: store i64 8, i64* [[TMP129]], align 8 +// CHECK9-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 +// CHECK9-NEXT: store i8* null, i8** [[TMP130]], align 8 +// CHECK9-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8 +// CHECK9-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8 +// CHECK9-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK9-NEXT: store i64 8, i64* [[TMP135]], align 8 +// CHECK9-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 +// CHECK9-NEXT: store i8* null, i8** [[TMP136]], align 8 +// CHECK9-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** +// CHECK9-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 +// CHECK9-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** +// CHECK9-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8 +// CHECK9-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK9-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8 +// CHECK9-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 +// CHECK9-NEXT: store i8* null, i8** [[TMP142]], align 8 +// CHECK9-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** +// CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 +// CHECK9-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** +// CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8 +// CHECK9-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK9-NEXT: store i64 16, i64* [[TMP147]], align 8 +// CHECK9-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 +// CHECK9-NEXT: store i8* null, i8** [[TMP148]], align 8 +// CHECK9-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 +// CHECK9-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] +// CHECK9: omp_offload.failed28: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT29]] +// CHECK9: omp_offload.cont29: +// CHECK9-NEXT: br label [[OMP_IF_END31:%.*]] +// CHECK9: omp_if.else30: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END31]] +// CHECK9: omp_if.end31: +// CHECK9-NEXT: store i32 0, i32* [[NN]], align 4 +// CHECK9-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK9-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4 +// CHECK9-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK9-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* +// CHECK9-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8 +// CHECK9-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* +// CHECK9-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8 +// CHECK9-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP160]], align 8 +// CHECK9-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 +// CHECK9-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] +// CHECK9: omp_offload.failed36: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT37]] +// CHECK9: omp_offload.cont37: +// CHECK9-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK9-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* +// CHECK9-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4 +// CHECK9-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 +// CHECK9-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64* +// CHECK9-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8 +// CHECK9-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64* +// CHECK9-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8 +// CHECK9-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP171]], align 8 +// CHECK9-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 +// CHECK9-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] +// CHECK9: omp_offload.failed43: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT44]] +// CHECK9: omp_offload.cont44: +// CHECK9-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) +// CHECK9-NEXT: ret i32 [[TMP176]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 @@ -6742,7 +8252,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6754,8 +8264,146 @@ // CHECK9-NEXT: ret void // // +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK9-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 +// CHECK9-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK9-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK9-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 +// CHECK9-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK9-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 +// CHECK9-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK9-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK9-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK9-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK9-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK9-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 +// CHECK9-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK9-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK9-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 +// CHECK9-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK9-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 +// CHECK9-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK9-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK9-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK9-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK9: omp_offload.failed.i: +// CHECK9-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK9-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* +// CHECK9-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23 +// CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK9-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* +// CHECK9-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23 +// CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23 +// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK9-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* +// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23 +// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23 +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK9: .omp_outlined..1.exit: +// CHECK9-NEXT: ret i32 0 +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 +// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK9-NEXT: ret void +// +// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -6765,12 +8413,12 @@ // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6788,7 +8436,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -6806,12 +8454,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6835,7 +8483,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -6869,12 +8517,12 @@ // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6947,7 +8595,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -6957,12 +8605,12 @@ // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6976,12 +8624,12 @@ // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6994,7 +8642,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -7004,12 +8652,12 @@ // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7018,12 +8666,12 @@ // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7035,18 +8683,50 @@ // CHECK9-NEXT: ret void // // +// CHECK9-LABEL: define {{[^@]+}}@_Z6bazzzziPi +// CHECK9-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK9-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: ret void +// +// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK9-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..19 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7059,81 +8739,307 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@_Z3bari +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK9-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP8]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK9-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK9-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK9-NEXT: store double* [[A]], double** [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 8, i64* [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 4, i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK9-NEXT: store i64 2, i64* [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK9-NEXT: store i64 2, i64* [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK9-NEXT: store i64 8, i64* [[TMP32]], align 8 +// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK9-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK9-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 +// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK9-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] +// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK9-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] +// CHECK9-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK9-NEXT: ret i32 [[ADD4]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK9-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP31]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: ret void +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK9-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP24]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -7155,12 +9061,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7198,8 +9104,81 @@ // CHECK9-NEXT: ret void // // +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..24 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: ret void +// +// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7220,12 +9199,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..27 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7255,14 +9234,389 @@ // CHECK9-NEXT: ret void // // +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR4]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 +// CHECK10-NEXT: [[NN:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK10-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK10-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK10-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK10-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK10-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK10-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK10-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 +// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK10-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 +// CHECK10-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) +// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK10-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) +// CHECK10-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) +// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) +// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 +// CHECK10-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK10-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] +// CHECK10-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* +// CHECK10-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 +// CHECK10-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 +// CHECK10-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* +// CHECK10-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 +// CHECK10-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* +// CHECK10-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 +// CHECK10-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP65]], align 8 +// CHECK10-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 +// CHECK10-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK10-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 +// CHECK10-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK10-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* +// CHECK10-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 +// CHECK10-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 +// CHECK10-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK10-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 +// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK10-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 +// CHECK10-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK10-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 +// CHECK10-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK10-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 +// CHECK10-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP84]], align 8 +// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 +// CHECK10-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] +// CHECK10: omp_offload.failed19: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT20]] +// CHECK10: omp_offload.cont20: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* +// CHECK10-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 +// CHECK10-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 +// CHECK10-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 +// CHECK10-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] +// CHECK10: omp_if.then24: +// CHECK10-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK10-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK10-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 +// CHECK10-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64* +// CHECK10-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8 +// CHECK10-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* +// CHECK10-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8 +// CHECK10-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP99]], align 8 +// CHECK10-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP100]], align 8 +// CHECK10-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 +// CHECK10-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 +// CHECK10-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 40, i64* [[TMP105]], align 8 +// CHECK10-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP106]], align 8 +// CHECK10-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8 +// CHECK10-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 +// CHECK10-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP111]], align 8 +// CHECK10-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP112]], align 8 +// CHECK10-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** +// CHECK10-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 +// CHECK10-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** +// CHECK10-NEXT: store float* [[VLA]], float** [[TMP116]], align 8 +// CHECK10-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK10-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8 +// CHECK10-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP118]], align 8 +// CHECK10-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 +// CHECK10-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8 +// CHECK10-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK10-NEXT: store i64 400, i64* [[TMP123]], align 8 +// CHECK10-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP124]], align 8 +// CHECK10-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* +// CHECK10-NEXT: store i64 5, i64* [[TMP126]], align 8 +// CHECK10-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* +// CHECK10-NEXT: store i64 5, i64* [[TMP128]], align 8 +// CHECK10-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK10-NEXT: store i64 8, i64* [[TMP129]], align 8 +// CHECK10-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 +// CHECK10-NEXT: store i8* null, i8** [[TMP130]], align 8 +// CHECK10-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8 +// CHECK10-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8 +// CHECK10-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK10-NEXT: store i64 8, i64* [[TMP135]], align 8 +// CHECK10-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 +// CHECK10-NEXT: store i8* null, i8** [[TMP136]], align 8 +// CHECK10-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** +// CHECK10-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 +// CHECK10-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** +// CHECK10-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8 +// CHECK10-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK10-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8 +// CHECK10-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 +// CHECK10-NEXT: store i8* null, i8** [[TMP142]], align 8 +// CHECK10-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 +// CHECK10-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 +// CHECK10-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 +// CHECK10-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8 +// CHECK10-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK10-NEXT: store i64 16, i64* [[TMP147]], align 8 +// CHECK10-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 +// CHECK10-NEXT: store i8* null, i8** [[TMP148]], align 8 +// CHECK10-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 +// CHECK10-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] +// CHECK10: omp_offload.failed28: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT29]] +// CHECK10: omp_offload.cont29: +// CHECK10-NEXT: br label [[OMP_IF_END31:%.*]] +// CHECK10: omp_if.else30: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END31]] +// CHECK10: omp_if.end31: +// CHECK10-NEXT: store i32 0, i32* [[NN]], align 4 +// CHECK10-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK10-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4 +// CHECK10-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK10-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* +// CHECK10-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8 +// CHECK10-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* +// CHECK10-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8 +// CHECK10-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP160]], align 8 +// CHECK10-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 +// CHECK10-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] +// CHECK10: omp_offload.failed36: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT37]] +// CHECK10: omp_offload.cont37: +// CHECK10-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK10-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* +// CHECK10-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4 +// CHECK10-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 +// CHECK10-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64* +// CHECK10-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8 +// CHECK10-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64* +// CHECK10-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8 +// CHECK10-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP171]], align 8 +// CHECK10-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 +// CHECK10-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] +// CHECK10: omp_offload.failed43: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT44]] +// CHECK10: omp_offload.cont44: +// CHECK10-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) +// CHECK10-NEXT: ret i32 [[TMP176]] +// +// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 @@ -7280,21 +9634,159 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK10-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 +// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 +// CHECK10-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK10-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK10-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 +// CHECK10-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK10-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 +// CHECK10-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK10-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK10-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK10-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK10-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK10-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 +// CHECK10-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK10-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK10-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 +// CHECK10-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK10-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 +// CHECK10-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK10-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK10-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] +// CHECK10-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK10-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK10: omp_offload.failed.i: +// CHECK10-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK10-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* +// CHECK10-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23 +// CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK10-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* +// CHECK10-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23 +// CHECK10-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23 +// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK10-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* +// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23 +// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23 +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK10: .omp_outlined..1.exit: +// CHECK10-NEXT: ret i32 0 +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 +// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -7304,12 +9796,12 @@ // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7327,7 +9819,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7345,12 +9837,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7374,7 +9866,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -7408,12 +9900,12 @@ // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7486,7 +9978,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -7496,12 +9988,12 @@ // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7515,12 +10007,12 @@ // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7533,7 +10025,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -7543,12 +10035,12 @@ // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7557,12 +10049,12 @@ // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7574,18 +10066,50 @@ // CHECK10-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@_Z6bazzzziPi +// CHECK10-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK10-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: ret void +// +// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK10-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..19 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7598,81 +10122,307 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@_Z3bari +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK10-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP8]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK10-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK10-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK10-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK10-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK10-NEXT: store double* [[A]], double** [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 8, i64* [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 4, i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK10-NEXT: store i64 2, i64* [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK10-NEXT: store i64 2, i64* [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK10-NEXT: store i64 8, i64* [[TMP32]], align 8 +// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK10-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK10-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 +// CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK10-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] +// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK10-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] +// CHECK10-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK10-NEXT: ret i32 [[ADD4]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP31]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: ret void +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK10-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP24]] // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -7694,12 +10444,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7737,8 +10487,81 @@ // CHECK10-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..24 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: ret void +// +// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7759,12 +10582,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..27 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7794,14 +10617,382 @@ // CHECK10-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK10-SAME: () #[[ATTR4]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK10-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 +// CHECK11-NEXT: [[NN:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* +// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 +// CHECK11-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) +// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* +// CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK11-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) +// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK11-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) +// CHECK11-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 +// CHECK11-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) +// CHECK11-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK11-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 +// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK11-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* +// CHECK11-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 +// CHECK11-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* +// CHECK11-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 +// CHECK11-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP63]], align 4 +// CHECK11-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 +// CHECK11-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 +// CHECK11-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 +// CHECK11-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* +// CHECK11-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 +// CHECK11-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 +// CHECK11-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK11-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 +// CHECK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK11-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 +// CHECK11-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK11-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 +// CHECK11-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK11-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 +// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK11-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 +// CHECK11-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK11: omp_offload.failed15: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK11: omp_offload.cont16: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 +// CHECK11-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 +// CHECK11-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 +// CHECK11-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] +// CHECK11: omp_if.then19: +// CHECK11-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK11-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 +// CHECK11-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK11-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 +// CHECK11-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 +// CHECK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* +// CHECK11-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4 +// CHECK11-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32* +// CHECK11-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4 +// CHECK11-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP99]], align 4 +// CHECK11-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP100]], align 4 +// CHECK11-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** +// CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 +// CHECK11-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** +// CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 +// CHECK11-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 40, i64* [[TMP105]], align 4 +// CHECK11-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP106]], align 4 +// CHECK11-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4 +// CHECK11-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 +// CHECK11-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP111]], align 4 +// CHECK11-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP112]], align 4 +// CHECK11-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** +// CHECK11-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 +// CHECK11-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** +// CHECK11-NEXT: store float* [[VLA]], float** [[TMP116]], align 4 +// CHECK11-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK11-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4 +// CHECK11-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP118]], align 4 +// CHECK11-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** +// CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 +// CHECK11-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** +// CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4 +// CHECK11-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK11-NEXT: store i64 400, i64* [[TMP123]], align 4 +// CHECK11-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP124]], align 4 +// CHECK11-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* +// CHECK11-NEXT: store i32 5, i32* [[TMP126]], align 4 +// CHECK11-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* +// CHECK11-NEXT: store i32 5, i32* [[TMP128]], align 4 +// CHECK11-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK11-NEXT: store i64 4, i64* [[TMP129]], align 4 +// CHECK11-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 +// CHECK11-NEXT: store i8* null, i8** [[TMP130]], align 4 +// CHECK11-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4 +// CHECK11-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4 +// CHECK11-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK11-NEXT: store i64 4, i64* [[TMP135]], align 4 +// CHECK11-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 +// CHECK11-NEXT: store i8* null, i8** [[TMP136]], align 4 +// CHECK11-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** +// CHECK11-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 +// CHECK11-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** +// CHECK11-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4 +// CHECK11-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK11-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4 +// CHECK11-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 +// CHECK11-NEXT: store i8* null, i8** [[TMP142]], align 4 +// CHECK11-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** +// CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 +// CHECK11-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** +// CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4 +// CHECK11-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK11-NEXT: store i64 12, i64* [[TMP147]], align 4 +// CHECK11-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 +// CHECK11-NEXT: store i8* null, i8** [[TMP148]], align 4 +// CHECK11-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 +// CHECK11-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] +// CHECK11: omp_offload.failed23: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT24]] +// CHECK11: omp_offload.cont24: +// CHECK11-NEXT: br label [[OMP_IF_END26:%.*]] +// CHECK11: omp_if.else25: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END26]] +// CHECK11: omp_if.end26: +// CHECK11-NEXT: store i32 0, i32* [[NN]], align 4 +// CHECK11-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK11-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4 +// CHECK11-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK11-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32* +// CHECK11-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4 +// CHECK11-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32* +// CHECK11-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4 +// CHECK11-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP160]], align 4 +// CHECK11-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 +// CHECK11-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK11: omp_offload.failed30: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK11: omp_offload.cont31: +// CHECK11-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK11-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4 +// CHECK11-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 +// CHECK11-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32* +// CHECK11-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4 +// CHECK11-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32* +// CHECK11-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4 +// CHECK11-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP171]], align 4 +// CHECK11-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 +// CHECK11-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] +// CHECK11: omp_offload.failed36: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT37]] +// CHECK11: omp_offload.cont37: +// CHECK11-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) +// CHECK11-NEXT: ret i32 [[TMP176]] +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 @@ -7818,7 +11009,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7830,8 +11021,141 @@ // CHECK11-NEXT: ret void // // +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK11-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK11-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK11-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK11-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK11-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK11-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK11-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK11-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK11-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK11-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK11-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK11-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK11-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK11-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK11-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK11-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK11-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK11-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK11-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] +// CHECK11-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK11-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK11: omp_offload.failed.i: +// CHECK11-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK11-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK11-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK11-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK11-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 +// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK11: .omp_outlined..1.exit: +// CHECK11-NEXT: ret i32 0 +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 +// CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -7841,12 +11165,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7864,7 +11188,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -7880,12 +11204,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7908,7 +11232,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -7940,12 +11264,12 @@ // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8017,7 +11341,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -8025,12 +11349,12 @@ // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8042,12 +11366,12 @@ // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8059,7 +11383,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -8067,12 +11391,12 @@ // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8080,49 +11404,439 @@ // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z6bazzzziPi +// CHECK11-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK11-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK11-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..19 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[F:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK11-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@_Z3bari +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP8]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK11-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK11-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK11-NEXT: store double* [[A]], double** [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 8, i64* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK11-NEXT: store i32 2, i32* [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK11-NEXT: store i32 2, i32* [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK11-NEXT: store i64 4, i64* [[TMP32]], align 4 +// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK11-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK11-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 +// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK11-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK11-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] +// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK11-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] +// CHECK11-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK11-NEXT: ret i32 [[ADD3]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK11-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP31]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK11-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP24]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[F:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -8149,12 +11863,12 @@ // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..24 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8191,71 +11905,8 @@ // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] -// CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK11-NEXT: ret void -// -// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -8274,12 +11925,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..27 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8308,14 +11959,382 @@ // CHECK11-NEXT: ret void // // +// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK11-SAME: () #[[ATTR4]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK11-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 +// CHECK12-NEXT: [[NN:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK12-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* +// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 +// CHECK12-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) +// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* +// CHECK12-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK12-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK12-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) +// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK12-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) +// CHECK12-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 +// CHECK12-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) +// CHECK12-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] +// CHECK12-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK12-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 +// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK12-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* +// CHECK12-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 +// CHECK12-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* +// CHECK12-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 +// CHECK12-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP63]], align 4 +// CHECK12-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 +// CHECK12-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 +// CHECK12-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 +// CHECK12-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* +// CHECK12-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 +// CHECK12-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 +// CHECK12-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK12-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 +// CHECK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK12-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 +// CHECK12-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK12-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 +// CHECK12-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK12-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 +// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK12-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 +// CHECK12-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK12: omp_offload.failed15: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK12: omp_offload.cont16: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 +// CHECK12-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 +// CHECK12-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 +// CHECK12-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] +// CHECK12: omp_if.then19: +// CHECK12-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK12-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 +// CHECK12-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK12-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 +// CHECK12-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 +// CHECK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* +// CHECK12-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4 +// CHECK12-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32* +// CHECK12-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4 +// CHECK12-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP99]], align 4 +// CHECK12-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP100]], align 4 +// CHECK12-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 +// CHECK12-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 +// CHECK12-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 40, i64* [[TMP105]], align 4 +// CHECK12-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP106]], align 4 +// CHECK12-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4 +// CHECK12-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 +// CHECK12-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP111]], align 4 +// CHECK12-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP112]], align 4 +// CHECK12-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** +// CHECK12-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 +// CHECK12-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** +// CHECK12-NEXT: store float* [[VLA]], float** [[TMP116]], align 4 +// CHECK12-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK12-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4 +// CHECK12-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP118]], align 4 +// CHECK12-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 +// CHECK12-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4 +// CHECK12-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK12-NEXT: store i64 400, i64* [[TMP123]], align 4 +// CHECK12-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP124]], align 4 +// CHECK12-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* +// CHECK12-NEXT: store i32 5, i32* [[TMP126]], align 4 +// CHECK12-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* +// CHECK12-NEXT: store i32 5, i32* [[TMP128]], align 4 +// CHECK12-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK12-NEXT: store i64 4, i64* [[TMP129]], align 4 +// CHECK12-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 +// CHECK12-NEXT: store i8* null, i8** [[TMP130]], align 4 +// CHECK12-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4 +// CHECK12-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4 +// CHECK12-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK12-NEXT: store i64 4, i64* [[TMP135]], align 4 +// CHECK12-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 +// CHECK12-NEXT: store i8* null, i8** [[TMP136]], align 4 +// CHECK12-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** +// CHECK12-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 +// CHECK12-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** +// CHECK12-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4 +// CHECK12-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK12-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4 +// CHECK12-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 +// CHECK12-NEXT: store i8* null, i8** [[TMP142]], align 4 +// CHECK12-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 +// CHECK12-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 +// CHECK12-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 +// CHECK12-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4 +// CHECK12-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK12-NEXT: store i64 12, i64* [[TMP147]], align 4 +// CHECK12-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 +// CHECK12-NEXT: store i8* null, i8** [[TMP148]], align 4 +// CHECK12-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 +// CHECK12-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] +// CHECK12: omp_offload.failed23: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT24]] +// CHECK12: omp_offload.cont24: +// CHECK12-NEXT: br label [[OMP_IF_END26:%.*]] +// CHECK12: omp_if.else25: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END26]] +// CHECK12: omp_if.end26: +// CHECK12-NEXT: store i32 0, i32* [[NN]], align 4 +// CHECK12-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK12-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4 +// CHECK12-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK12-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32* +// CHECK12-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4 +// CHECK12-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32* +// CHECK12-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4 +// CHECK12-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP160]], align 4 +// CHECK12-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 +// CHECK12-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK12: omp_offload.failed30: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK12: omp_offload.cont31: +// CHECK12-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK12-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4 +// CHECK12-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 +// CHECK12-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32* +// CHECK12-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4 +// CHECK12-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32* +// CHECK12-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4 +// CHECK12-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP171]], align 4 +// CHECK12-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 +// CHECK12-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] +// CHECK12: omp_offload.failed36: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT37]] +// CHECK12: omp_offload.cont37: +// CHECK12-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) +// CHECK12-NEXT: ret i32 [[TMP176]] +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 @@ -8332,7 +12351,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8344,8 +12363,141 @@ // CHECK12-NEXT: ret void // // +// CHECK12-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK12-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK12-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK12-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK12-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK12-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK12-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK12-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK12-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK12-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK12-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK12-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK12-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK12-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK12-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK12-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK12-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK12-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK12-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK12-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK12-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] +// CHECK12-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK12-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK12: omp_offload.failed.i: +// CHECK12-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK12-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK12-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK12-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK12-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 +// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK12: .omp_outlined..1.exit: +// CHECK12-NEXT: ret i32 0 +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 +// CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -8355,12 +12507,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8378,7 +12530,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -8394,12 +12546,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8422,7 +12574,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -8454,12 +12606,12 @@ // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8531,7 +12683,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -8539,12 +12691,12 @@ // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8556,12 +12708,12 @@ // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8573,7 +12725,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -8581,12 +12733,12 @@ // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8594,12 +12746,12 @@ // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8611,18 +12763,49 @@ // CHECK12-NEXT: ret void // // +// CHECK12-LABEL: define {{[^@]+}}@_Z6bazzzziPi +// CHECK12-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP5]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK12-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: ret void +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK12-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..19 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8635,8 +12818,367 @@ // CHECK12-NEXT: ret void // // +// CHECK12-LABEL: define {{[^@]+}}@_Z3bari +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP8]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK12-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK12-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK12-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK12-NEXT: store double* [[A]], double** [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 8, i64* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK12-NEXT: store i32 2, i32* [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK12-NEXT: store i32 2, i32* [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK12-NEXT: store i64 4, i64* [[TMP32]], align 4 +// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK12-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK12-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 +// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK12-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK12-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] +// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK12-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] +// CHECK12-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK12-NEXT: ret i32 [[ADD3]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK12-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK12-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP31]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK12-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP24]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK12-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK12-NEXT: ret void +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -8663,12 +13205,12 @@ // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..24 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8705,71 +13247,8 @@ // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK12-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] -// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK12-NEXT: ret void -// -// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -8788,10484 +13267,2149 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..27 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK12-SAME: () #[[ATTR4]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: ret void +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK13-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK13-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK13-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK13-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK13-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK13-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK13-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK13-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK13-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK13-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK13-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK13-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK13-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK13-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK13-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK13-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK13-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK13-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK13-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK13-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK13-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK13-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK13-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK13-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK13-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK13-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK13-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK13-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK13-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK13-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[F:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK13-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK13-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK13-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK13-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK13-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK13-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK13-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK13-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK13-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK13-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK13-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK13-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK14-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK14-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK14-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK14-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK14-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK14-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK14-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK14-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK14-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK14-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK14-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK14-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK14-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK14-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK14-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK14-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK14-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK14-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK14-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK14-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK14-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK14-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK14-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK14-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK14-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK14-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK14-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK14-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK14-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK14-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK14-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK14-NEXT: ret void +// // +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK14-NEXT: ret void // -// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK13-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK13-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK13-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK13-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK13-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK13-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK13-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK13-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK13-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK13-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK13-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK13-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK13-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK13-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK13-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK13-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK13-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK13-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK13-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK13-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK13-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK13-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK13-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK13-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK13-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK13-NEXT: ret i32 [[TMP20]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK13-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: ret void // +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 +// CHECK14-NEXT: ret void // -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP8]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK13-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK13-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK13-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK13-NEXT: ret i32 [[ADD9]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK13-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP4]] // +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK14-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK14-NEXT: ret void // -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK14-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK14-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK14-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK14-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK14-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK14-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK14-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK14-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK14-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK14-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK14-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK14-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK14-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK14-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK14-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK14-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK14-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK14-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK14-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK14-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK14-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK14-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK14-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK14-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK14-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK14-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK14-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK14-NEXT: ret i32 [[TMP20]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK14-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[F:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK14-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK14-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 +// CHECK14-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK14-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK14-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK14-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK14-NEXT: ret void // // -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP8]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK14-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK14-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK14-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK14-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK14-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK14-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK14-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK14-NEXT: ret i32 [[ADD9]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK14-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK14-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK14-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK14-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK14-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP4]] +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK14-NEXT: ret void // // -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK14-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK14-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK14-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK15-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK15-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK15-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK15-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK15-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK15-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK15-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK15-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK15-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK15-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK15-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK15-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK15-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK15-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK15-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK15-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK15-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK15-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK15-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK15-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK15-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK15-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK15-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK15-NEXT: ret i32 [[TMP18]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK15-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK15-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK15-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK15-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK15-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK15-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK15-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK15-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK15-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK15-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK15-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK15-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK15-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK15-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK15-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK15-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK15-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK15-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK15-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK15-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK15-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK15-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK15-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK15-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK15-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK15-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK15-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK15-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK15-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK15-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[F:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK15-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK15-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK15-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK15-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK15-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK15-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK15-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK15-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK15-NEXT: ret void // // -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK15-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK15-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 // CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK15-NEXT: store double [[INC]], double* [[A3]], align 4 // CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK15-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] +// CHECK15-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 // CHECK15-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK15-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK15-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK15-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK15-NEXT: ret i32 [[ADD9]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK15-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP4]] +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK15-NEXT: ret void // // -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK15-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK15-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK16-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK16-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK16-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK16-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK16-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK16-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK16-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK16-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK16-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK16-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK16-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK16-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK16-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK16-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK16-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK16-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK16-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK16-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK16-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK16-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK16-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK16-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK16-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK16-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK16-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK16-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK16-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK16-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK16-NEXT: ret i32 [[TMP18]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK16-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK16-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK16-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK16-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK16-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK16-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK16-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK16-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK16-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK16-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK16-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK16-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK16-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK16-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK16-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK16-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK16-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK16-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK16-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK16-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK16-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK16-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK16-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK16-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK16-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK16-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK16-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK16-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK16-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK16-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK16-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK16-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK16-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 // CHECK16-NEXT: ret void // // -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK16-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[F:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK16-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK16-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK16-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK16-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK16-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK16-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK16-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK16-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK16-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK16-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 // CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK16-NEXT: store double [[INC]], double* [[A3]], align 4 // CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK16-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] +// CHECK16-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] // CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 // CHECK16-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK16-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK16-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK16-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK16-NEXT: ret i32 [[ADD9]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK16-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP4]] +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK16-NEXT: ret void // // -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 -// CHECK17-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 -// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* -// CHECK17-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 -// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 -// CHECK17-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 -// CHECK17-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) -// CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* -// CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* -// CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) -// CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* -// CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) -// CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) -// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 -// CHECK17-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) -// CHECK17-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 -// CHECK17-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* -// CHECK17-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 -// CHECK17-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 -// CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* -// CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 -// CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* -// CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 -// CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP65]], align 8 -// CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 -// CHECK17-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* -// CHECK17-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 -// CHECK17-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 -// CHECK17-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* -// CHECK17-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 -// CHECK17-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 -// CHECK17-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 -// CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 -// CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP79]], align 8 -// CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 -// CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* -// CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 -// CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP84]], align 8 -// CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 -// CHECK17-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] -// CHECK17: omp_offload.failed19: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT20]] -// CHECK17: omp_offload.cont20: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* -// CHECK17-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 -// CHECK17-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 -// CHECK17-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 -// CHECK17-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] -// CHECK17: omp_if.then24: -// CHECK17-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 -// CHECK17-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK17-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 -// CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64* -// CHECK17-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8 -// CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* -// CHECK17-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8 -// CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP99]], align 8 -// CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP100]], align 8 -// CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 -// CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 -// CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 40, i64* [[TMP105]], align 8 -// CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP106]], align 8 -// CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8 -// CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 -// CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP111]], align 8 -// CHECK17-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP112]], align 8 -// CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** -// CHECK17-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 -// CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** -// CHECK17-NEXT: store float* [[VLA]], float** [[TMP116]], align 8 -// CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK17-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8 -// CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP118]], align 8 -// CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 -// CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8 -// CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK17-NEXT: store i64 400, i64* [[TMP123]], align 8 -// CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP124]], align 8 -// CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* -// CHECK17-NEXT: store i64 5, i64* [[TMP126]], align 8 -// CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* -// CHECK17-NEXT: store i64 5, i64* [[TMP128]], align 8 -// CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK17-NEXT: store i64 8, i64* [[TMP129]], align 8 -// CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 -// CHECK17-NEXT: store i8* null, i8** [[TMP130]], align 8 -// CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8 -// CHECK17-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8 -// CHECK17-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK17-NEXT: store i64 8, i64* [[TMP135]], align 8 -// CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 -// CHECK17-NEXT: store i8* null, i8** [[TMP136]], align 8 -// CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** -// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 -// CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** -// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8 -// CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK17-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8 -// CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 -// CHECK17-NEXT: store i8* null, i8** [[TMP142]], align 8 -// CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 -// CHECK17-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 -// CHECK17-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 -// CHECK17-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8 -// CHECK17-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK17-NEXT: store i64 16, i64* [[TMP147]], align 8 -// CHECK17-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 -// CHECK17-NEXT: store i8* null, i8** [[TMP148]], align 8 -// CHECK17-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 -// CHECK17-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] -// CHECK17: omp_offload.failed28: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT29]] -// CHECK17: omp_offload.cont29: -// CHECK17-NEXT: br label [[OMP_IF_END31:%.*]] -// CHECK17: omp_if.else30: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END31]] -// CHECK17: omp_if.end31: -// CHECK17-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK17-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 -// CHECK17-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4 -// CHECK17-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK17-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* -// CHECK17-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8 -// CHECK17-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* -// CHECK17-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8 -// CHECK17-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP160]], align 8 -// CHECK17-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 -// CHECK17-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] -// CHECK17: omp_offload.failed36: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT37]] -// CHECK17: omp_offload.cont37: -// CHECK17-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 -// CHECK17-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* -// CHECK17-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4 -// CHECK17-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 -// CHECK17-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64* -// CHECK17-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8 -// CHECK17-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64* -// CHECK17-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8 -// CHECK17-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP171]], align 8 -// CHECK17-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 -// CHECK17-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] -// CHECK17: omp_offload.failed43: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT44]] -// CHECK17: omp_offload.cont44: -// CHECK17-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) -// CHECK17-NEXT: ret i32 [[TMP176]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 -// CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 -// CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 -// CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 -// CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 -// CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 -// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK17-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] -// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK17: omp_offload.failed.i: -// CHECK17-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* -// CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23 -// CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* -// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23 -// CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23 -// CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK17-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* -// CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23 -// CHECK17-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23 -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK17: .omp_outlined..1.exit: -// CHECK17-NEXT: ret i32 0 -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double -// CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 -// CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float -// CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double -// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 -// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 -// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK17-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] -// CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 -// CHECK17-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK17-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 -// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 -// CHECK17-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK17-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 -// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK17-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 -// CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 -// CHECK17-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK17-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 -// CHECK17-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK17-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[F:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP8]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK17-NEXT: store double* [[A]], double** [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 8, i64* [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 4, i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK17-NEXT: store i64 2, i64* [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK17-NEXT: store i64 2, i64* [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8 -// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 -// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK17-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] -// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK17-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK17-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] -// CHECK17-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK17-NEXT: ret i32 [[ADD4]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP31]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP24]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 -// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK17-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] -// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK17-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR4]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 -// CHECK18-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 -// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* -// CHECK18-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 -// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 -// CHECK18-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK18-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 -// CHECK18-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) -// CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* -// CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* -// CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) -// CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* -// CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) -// CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) -// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 -// CHECK18-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) -// CHECK18-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 -// CHECK18-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] -// CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* -// CHECK18-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 -// CHECK18-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 -// CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* -// CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 -// CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* -// CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 -// CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP65]], align 8 -// CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 -// CHECK18-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* -// CHECK18-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 -// CHECK18-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 -// CHECK18-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* -// CHECK18-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 -// CHECK18-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 -// CHECK18-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 -// CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 -// CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP79]], align 8 -// CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 -// CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* -// CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 -// CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP84]], align 8 -// CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 -// CHECK18-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] -// CHECK18: omp_offload.failed19: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT20]] -// CHECK18: omp_offload.cont20: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* -// CHECK18-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 -// CHECK18-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 -// CHECK18-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 -// CHECK18-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] -// CHECK18: omp_if.then24: -// CHECK18-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 -// CHECK18-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK18-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 -// CHECK18-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64* -// CHECK18-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8 -// CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* -// CHECK18-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8 -// CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP99]], align 8 -// CHECK18-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP100]], align 8 -// CHECK18-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 -// CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 -// CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 40, i64* [[TMP105]], align 8 -// CHECK18-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP106]], align 8 -// CHECK18-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8 -// CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 -// CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP111]], align 8 -// CHECK18-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP112]], align 8 -// CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** -// CHECK18-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 -// CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** -// CHECK18-NEXT: store float* [[VLA]], float** [[TMP116]], align 8 -// CHECK18-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK18-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8 -// CHECK18-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP118]], align 8 -// CHECK18-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 -// CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8 -// CHECK18-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK18-NEXT: store i64 400, i64* [[TMP123]], align 8 -// CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP124]], align 8 -// CHECK18-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* -// CHECK18-NEXT: store i64 5, i64* [[TMP126]], align 8 -// CHECK18-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* -// CHECK18-NEXT: store i64 5, i64* [[TMP128]], align 8 -// CHECK18-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK18-NEXT: store i64 8, i64* [[TMP129]], align 8 -// CHECK18-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 -// CHECK18-NEXT: store i8* null, i8** [[TMP130]], align 8 -// CHECK18-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8 -// CHECK18-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8 -// CHECK18-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK18-NEXT: store i64 8, i64* [[TMP135]], align 8 -// CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 -// CHECK18-NEXT: store i8* null, i8** [[TMP136]], align 8 -// CHECK18-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** -// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 -// CHECK18-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** -// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8 -// CHECK18-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK18-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8 -// CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 -// CHECK18-NEXT: store i8* null, i8** [[TMP142]], align 8 -// CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 -// CHECK18-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 -// CHECK18-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 -// CHECK18-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8 -// CHECK18-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK18-NEXT: store i64 16, i64* [[TMP147]], align 8 -// CHECK18-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 -// CHECK18-NEXT: store i8* null, i8** [[TMP148]], align 8 -// CHECK18-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 -// CHECK18-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] -// CHECK18: omp_offload.failed28: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT29]] -// CHECK18: omp_offload.cont29: -// CHECK18-NEXT: br label [[OMP_IF_END31:%.*]] -// CHECK18: omp_if.else30: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END31]] -// CHECK18: omp_if.end31: -// CHECK18-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK18-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 -// CHECK18-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4 -// CHECK18-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK18-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* -// CHECK18-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8 -// CHECK18-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* -// CHECK18-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8 -// CHECK18-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP160]], align 8 -// CHECK18-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 -// CHECK18-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] -// CHECK18: omp_offload.failed36: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT37]] -// CHECK18: omp_offload.cont37: -// CHECK18-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 -// CHECK18-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* -// CHECK18-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4 -// CHECK18-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 -// CHECK18-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64* -// CHECK18-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8 -// CHECK18-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64* -// CHECK18-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8 -// CHECK18-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP171]], align 8 -// CHECK18-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 -// CHECK18-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] -// CHECK18: omp_offload.failed43: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT44]] -// CHECK18: omp_offload.cont44: -// CHECK18-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) -// CHECK18-NEXT: ret i32 [[TMP176]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 -// CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 -// CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 -// CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 -// CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 -// CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 -// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK18-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] -// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK18: omp_offload.failed.i: -// CHECK18-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* -// CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23 -// CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* -// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23 -// CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23 -// CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK18-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* -// CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23 -// CHECK18-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23 -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK18: .omp_outlined..1.exit: -// CHECK18-NEXT: ret i32 0 -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double -// CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 -// CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float -// CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double -// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 -// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK18-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 -// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK18-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK18-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] -// CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 -// CHECK18-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK18-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 -// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 -// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK18-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 -// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK18-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 -// CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 -// CHECK18-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK18-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 -// CHECK18-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK18-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[F:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP8]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK18-NEXT: store double* [[A]], double** [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 8, i64* [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 4, i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK18-NEXT: store i64 2, i64* [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK18-NEXT: store i64 2, i64* [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8 -// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 -// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK18-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] -// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK18-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK18-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] -// CHECK18-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK18-NEXT: ret i32 [[ADD4]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP31]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP24]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 -// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK18-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] -// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK18-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR4]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 -// CHECK19-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* -// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 -// CHECK19-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) -// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* -// CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) -// CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* -// CHECK19-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) -// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* -// CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) -// CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 -// CHECK19-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) -// CHECK19-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] -// CHECK19-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* -// CHECK19-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 -// CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 -// CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* -// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 -// CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* -// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 -// CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP63]], align 4 -// CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 -// CHECK19-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 -// CHECK19-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 -// CHECK19-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* -// CHECK19-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 -// CHECK19-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 -// CHECK19-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 -// CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* -// CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 -// CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP77]], align 4 -// CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 -// CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* -// CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 -// CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 -// CHECK19-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK19: omp_offload.failed15: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK19: omp_offload.cont16: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 -// CHECK19-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 -// CHECK19-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 -// CHECK19-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] -// CHECK19: omp_if.then19: -// CHECK19-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 -// CHECK19-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 -// CHECK19-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK19-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 -// CHECK19-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 -// CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* -// CHECK19-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4 -// CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32* -// CHECK19-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4 -// CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP99]], align 4 -// CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP100]], align 4 -// CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 -// CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 -// CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 40, i64* [[TMP105]], align 4 -// CHECK19-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP106]], align 4 -// CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4 -// CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 -// CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP111]], align 4 -// CHECK19-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP112]], align 4 -// CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** -// CHECK19-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 -// CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** -// CHECK19-NEXT: store float* [[VLA]], float** [[TMP116]], align 4 -// CHECK19-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK19-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4 -// CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP118]], align 4 -// CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 -// CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4 -// CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK19-NEXT: store i64 400, i64* [[TMP123]], align 4 -// CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP124]], align 4 -// CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* -// CHECK19-NEXT: store i32 5, i32* [[TMP126]], align 4 -// CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* -// CHECK19-NEXT: store i32 5, i32* [[TMP128]], align 4 -// CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK19-NEXT: store i64 4, i64* [[TMP129]], align 4 -// CHECK19-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 -// CHECK19-NEXT: store i8* null, i8** [[TMP130]], align 4 -// CHECK19-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4 -// CHECK19-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4 -// CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK19-NEXT: store i64 4, i64* [[TMP135]], align 4 -// CHECK19-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 -// CHECK19-NEXT: store i8* null, i8** [[TMP136]], align 4 -// CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** -// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 -// CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** -// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4 -// CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK19-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4 -// CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 -// CHECK19-NEXT: store i8* null, i8** [[TMP142]], align 4 -// CHECK19-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 -// CHECK19-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 -// CHECK19-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 -// CHECK19-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4 -// CHECK19-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK19-NEXT: store i64 12, i64* [[TMP147]], align 4 -// CHECK19-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 -// CHECK19-NEXT: store i8* null, i8** [[TMP148]], align 4 -// CHECK19-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 -// CHECK19-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] -// CHECK19: omp_offload.failed23: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT24]] -// CHECK19: omp_offload.cont24: -// CHECK19-NEXT: br label [[OMP_IF_END26:%.*]] -// CHECK19: omp_if.else25: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END26]] -// CHECK19: omp_if.end26: -// CHECK19-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK19-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 -// CHECK19-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32* -// CHECK19-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4 -// CHECK19-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32* -// CHECK19-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4 -// CHECK19-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP160]], align 4 -// CHECK19-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 -// CHECK19-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK19: omp_offload.failed30: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK19: omp_offload.cont31: -// CHECK19-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 -// CHECK19-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4 -// CHECK19-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 -// CHECK19-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32* -// CHECK19-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4 -// CHECK19-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32* -// CHECK19-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4 -// CHECK19-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP171]], align 4 -// CHECK19-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 -// CHECK19-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] -// CHECK19: omp_offload.failed36: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT37]] -// CHECK19: omp_offload.cont37: -// CHECK19-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) -// CHECK19-NEXT: ret i32 [[TMP176]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK19-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 -// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 -// CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 -// CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 -// CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 -// CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 -// CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 -// CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] -// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK19: omp_offload.failed.i: -// CHECK19-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* -// CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 -// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 -// CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK19: .omp_outlined..1.exit: -// CHECK19-NEXT: ret i32 0 -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double -// CHECK19-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK19-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float -// CHECK19-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK19-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK19-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double -// CHECK19-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 -// CHECK19-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float -// CHECK19-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 -// CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK19-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK19-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK19-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 -// CHECK19-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] -// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 -// CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK19-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK19-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 -// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK19-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK19-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 -// CHECK19-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 -// CHECK19-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK19-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK19-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK19-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP5]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK19-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK19-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[F:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP8]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 -// CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK19-NEXT: store double* [[A]], double** [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 8, i64* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK19-NEXT: store i32 2, i32* [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK19-NEXT: store i32 2, i32* [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK19-NEXT: store i64 4, i64* [[TMP32]], align 4 -// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 -// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK19-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK19-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK19-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] -// CHECK19-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK19-NEXT: ret i32 [[ADD3]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP31]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP24]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK19-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK19-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK19-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] -// CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK19-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 -// CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR4]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 -// CHECK20-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* -// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 -// CHECK20-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) -// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* -// CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) -// CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* -// CHECK20-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) -// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* -// CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) -// CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 -// CHECK20-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) -// CHECK20-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] -// CHECK20-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* -// CHECK20-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 -// CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 -// CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* -// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 -// CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* -// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 -// CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP63]], align 4 -// CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 -// CHECK20-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 -// CHECK20-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 -// CHECK20-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* -// CHECK20-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 -// CHECK20-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 -// CHECK20-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 -// CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* -// CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 -// CHECK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP77]], align 4 -// CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 -// CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* -// CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 -// CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 -// CHECK20-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK20: omp_offload.failed15: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK20: omp_offload.cont16: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 -// CHECK20-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 -// CHECK20-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 -// CHECK20-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] -// CHECK20: omp_if.then19: -// CHECK20-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 -// CHECK20-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 -// CHECK20-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK20-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 -// CHECK20-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 -// CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* -// CHECK20-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4 -// CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32* -// CHECK20-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4 -// CHECK20-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP99]], align 4 -// CHECK20-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP100]], align 4 -// CHECK20-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 -// CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 -// CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 40, i64* [[TMP105]], align 4 -// CHECK20-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP106]], align 4 -// CHECK20-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4 -// CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 -// CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP111]], align 4 -// CHECK20-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP112]], align 4 -// CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** -// CHECK20-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 -// CHECK20-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** -// CHECK20-NEXT: store float* [[VLA]], float** [[TMP116]], align 4 -// CHECK20-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK20-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4 -// CHECK20-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP118]], align 4 -// CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 -// CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4 -// CHECK20-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK20-NEXT: store i64 400, i64* [[TMP123]], align 4 -// CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP124]], align 4 -// CHECK20-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* -// CHECK20-NEXT: store i32 5, i32* [[TMP126]], align 4 -// CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* -// CHECK20-NEXT: store i32 5, i32* [[TMP128]], align 4 -// CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK20-NEXT: store i64 4, i64* [[TMP129]], align 4 -// CHECK20-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 -// CHECK20-NEXT: store i8* null, i8** [[TMP130]], align 4 -// CHECK20-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4 -// CHECK20-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4 -// CHECK20-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK20-NEXT: store i64 4, i64* [[TMP135]], align 4 -// CHECK20-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 -// CHECK20-NEXT: store i8* null, i8** [[TMP136]], align 4 -// CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** -// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 -// CHECK20-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** -// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4 -// CHECK20-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK20-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4 -// CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 -// CHECK20-NEXT: store i8* null, i8** [[TMP142]], align 4 -// CHECK20-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 -// CHECK20-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 -// CHECK20-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 -// CHECK20-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4 -// CHECK20-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK20-NEXT: store i64 12, i64* [[TMP147]], align 4 -// CHECK20-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 -// CHECK20-NEXT: store i8* null, i8** [[TMP148]], align 4 -// CHECK20-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 -// CHECK20-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] -// CHECK20: omp_offload.failed23: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT24]] -// CHECK20: omp_offload.cont24: -// CHECK20-NEXT: br label [[OMP_IF_END26:%.*]] -// CHECK20: omp_if.else25: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END26]] -// CHECK20: omp_if.end26: -// CHECK20-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK20-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 -// CHECK20-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4 -// CHECK20-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK20-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32* -// CHECK20-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4 -// CHECK20-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32* -// CHECK20-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4 -// CHECK20-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP160]], align 4 -// CHECK20-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 -// CHECK20-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK20: omp_offload.failed30: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK20: omp_offload.cont31: -// CHECK20-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 -// CHECK20-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4 -// CHECK20-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 -// CHECK20-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32* -// CHECK20-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4 -// CHECK20-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32* -// CHECK20-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4 -// CHECK20-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP171]], align 4 -// CHECK20-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 -// CHECK20-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] -// CHECK20: omp_offload.failed36: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT37]] -// CHECK20: omp_offload.cont37: -// CHECK20-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) -// CHECK20-NEXT: ret i32 [[TMP176]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK20-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 -// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 -// CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 -// CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 -// CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 -// CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 -// CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 -// CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] -// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK20: omp_offload.failed.i: -// CHECK20-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* -// CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 -// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 -// CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK20: .omp_outlined..1.exit: -// CHECK20-NEXT: ret i32 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double -// CHECK20-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK20-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float -// CHECK20-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK20-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK20-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double -// CHECK20-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 -// CHECK20-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float -// CHECK20-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 -// CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK20-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK20-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK20-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 -// CHECK20-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] -// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 -// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK20-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK20-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 -// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK20-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK20-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 -// CHECK20-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 -// CHECK20-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK20-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK20-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK20-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP5]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK20-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK20-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[F:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP8]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 -// CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK20-NEXT: store double* [[A]], double** [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 8, i64* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK20-NEXT: store i32 2, i32* [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK20-NEXT: store i32 2, i32* [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK20-NEXT: store i64 4, i64* [[TMP32]], align 4 -// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 -// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK20-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] -// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK20-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK20-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] -// CHECK20-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK20-NEXT: ret i32 [[ADD3]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP31]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP24]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK20-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK20-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK20-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] -// CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK20-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 -// CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR4]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK21-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK21-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK21-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK21-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK21-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK21-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK21-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK21-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK21-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK21-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK21-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK21-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK21-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK21-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK21-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK21-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK21-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK21-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK21-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK21-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK21-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK21-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK21-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK21-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK21-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK21-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK21-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK21-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK21-NEXT: ret i32 [[TMP20]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK21-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK21-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP8]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK21-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK21-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK21-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK21-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK21-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK21-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK21-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK21-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK21-NEXT: ret i32 [[ADD9]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK21-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP4]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK22-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK22-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK22-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK22-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK22-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK22-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK22-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK22-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK22-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK22-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK22-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK22-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK22-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK22-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK22-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK22-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK22-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK22-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK22-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK22-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK22-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK22-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK22-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK22-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK22-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK22-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK22-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK22-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK22-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK22-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK22-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK22-NEXT: ret i32 [[TMP20]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK22-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK22-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP8]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK22-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK22-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK22-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK22-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK22-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK22-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK22-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK22-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK22-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK22-NEXT: ret i32 [[ADD9]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK22-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK22-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP4]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK23-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK23-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK23-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK23-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK23-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK23-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK23-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK23-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK23-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK23-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK23-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK23-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK23-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK23-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK23-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK23-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK23-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK23-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK23-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK23-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK23-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK23-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK23-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK23-NEXT: ret i32 [[TMP18]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK23-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK23-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP8]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK23-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK23-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK23-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK23-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK23-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK23-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK23-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK23-NEXT: ret i32 [[ADD9]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK23-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP4]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK24-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK24-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK24-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK24-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK24-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK24-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK24-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK24-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK24-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK24-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK24-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK24-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK24-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK24-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK24-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK24-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK24-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK24-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK24-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK24-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK24-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK24-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK24-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK24-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK24-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK24-NEXT: ret i32 [[TMP18]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK24-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK24-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP8]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK24-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK24-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK24-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK24-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK24-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK24-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK24-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK24-NEXT: ret i32 [[ADD9]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK24-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP4]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double -// CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 -// CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float -// CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double -// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 -// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK25-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 -// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK25-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 -// CHECK25-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK25-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] -// CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 -// CHECK25-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK25-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 -// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 -// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK25-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 -// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK25-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 -// CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 -// CHECK25-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK25-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[F:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 -// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK25-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] -// CHECK25-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK25-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 -// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double -// CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 -// CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float -// CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double -// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 -// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK26-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 -// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK26-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 -// CHECK26-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK26-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] -// CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 -// CHECK26-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK26-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 -// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 -// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK26-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 -// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK26-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 -// CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 -// CHECK26-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK26-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[F:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 -// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 -// CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 -// CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 -// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK26-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] -// CHECK26-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK26-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double -// CHECK27-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK27-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float -// CHECK27-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK27-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double -// CHECK27-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 -// CHECK27-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float -// CHECK27-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 -// CHECK27-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK27-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK27-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK27-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 -// CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] -// CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 -// CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK27-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK27-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 -// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK27-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK27-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 -// CHECK27-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 -// CHECK27-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK27-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK27-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK27-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[F:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 -// CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK27-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] -// CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double -// CHECK28-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK28-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float -// CHECK28-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK28-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double -// CHECK28-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 -// CHECK28-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float -// CHECK28-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 -// CHECK28-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK28-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK28-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK28-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 -// CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] -// CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 -// CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 -// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 -// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK28-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK28-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 -// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK28-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK28-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 -// CHECK28-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 -// CHECK28-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK28-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK28-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK28-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[F:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 -// CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK28-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] -// CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 -// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK29-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK29-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK29-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK29-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK29-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK29-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK29-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK29-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK29-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK29-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK29-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK29-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK29-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK29-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK29-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK29-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK29-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK29-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK29-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK29-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK29-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK29-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK29-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK29-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK29-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK29-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK29-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK29-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK29-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK29-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK29-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK29-NEXT: ret i32 [[TMP20]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK29-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK29-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP8]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK29-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK29-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK29-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK29-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK29-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK29-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK29-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK29-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK29-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK29-NEXT: ret i32 [[ADD9]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK29-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK29-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP4]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK30-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK30-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK30-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK30-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK30-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK30-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK30-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK30-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK30-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK30-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK30-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK30-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK30-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK30-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK30-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK30-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK30-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK30-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK30-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK30-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK30-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK30-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK30-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK30-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK30-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK30-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK30-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK30-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK30-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK30-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK30-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK30-NEXT: ret i32 [[TMP20]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK30-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK30-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: ret void -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP8]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK30-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK30-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK30-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK30-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK30-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK30-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK30-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK30-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK30-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK30-NEXT: ret i32 [[ADD9]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK30-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK30-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP4]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK31-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK31-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK31-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK31-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK31-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK31-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK31-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK31-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK31-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK31-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK31-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK31-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK31-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK31-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK31-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK31-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK31-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK31-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK31-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK31-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK31-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK31-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK31-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK31-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK31-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK31-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK31-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK31-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK31-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK31-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK31-NEXT: ret i32 [[TMP18]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK31-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK31-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: ret void -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK31-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK31-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK31-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK31-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK31-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK31-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK31-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK31-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK31-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK31-NEXT: ret i32 [[ADD9]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK31-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK31-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP4]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK32-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK32-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK32-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK32-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK32-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK32-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK32-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK32-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK32-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK32-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK32-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK32-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK32-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK32-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK32-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK32-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK32-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK32-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK32-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK32-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK32-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK32-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK32-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK32-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK32-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK32-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK32-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK32-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK32-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK32-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK32-NEXT: ret i32 [[TMP18]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK32-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK32-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: ret void -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK32-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK32-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK32-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK32-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK32-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK32-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK32-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK32-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK32-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK32-NEXT: ret i32 [[ADD9]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK32-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK32-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP4]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK16-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK16-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK16-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_codegen.cpp @@ -7,65 +7,65 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK26 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -7098,1420 +7098,3700 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK5-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK5-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK5-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK5-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK5-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK5-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK5-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK5-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK5-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK5-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK5-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK5-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK5-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK5-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK5-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11 +// CHECK5-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK5-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11 +// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK5-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK5-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK5-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK5-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK5-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK5-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 +// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK5-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK5-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK5-NEXT: br label [[FOR_COND4:%.*]] -// CHECK5: for.cond4: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK5-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK5-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body6: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK5-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK5-NEXT: br label [[FOR_COND11:%.*]] -// CHECK5: for.cond11: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK5-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK5-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK5: for.body13: -// CHECK5-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK5-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK5-NEXT: br label [[FOR_INC16:%.*]] -// CHECK5: for.inc16: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK5-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK5-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK5-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end18: -// CHECK5-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK5-NEXT: br label [[FOR_COND20:%.*]] -// CHECK5: for.cond20: -// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK5-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK5: for.body22: -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK5-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK5-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK5-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK5-NEXT: br label [[FOR_INC27:%.*]] -// CHECK5: for.inc27: -// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK5-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK5-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK5: for.end29: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK5-NEXT: br label [[FOR_COND32:%.*]] -// CHECK5: for.cond32: -// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK5-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK5-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK5: for.body34: -// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK5-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK5-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK5-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK5-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK5-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK5-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK5-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK5-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK5-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK5-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK5-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK5-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK5-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK5-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK5-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK5-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK5-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK5-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK5-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK5-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK5-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK5-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK5-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK5-NEXT: br label [[FOR_INC53:%.*]] -// CHECK5: for.inc53: -// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK5-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK5-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK5-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK5: for.end55: -// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK5-NEXT: ret i32 [[TMP31]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK5-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK5-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK5-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 +// CHECK5-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK5-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK5-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK5-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK5-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK5-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK5-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK5-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK5-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK5-NEXT: ret i32 [[ADD10]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK5-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: store double [[ADD5]], double* [[A]], align 8 +// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 +// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK5-NEXT: store double [[INC]], double* [[A6]], align 8 +// CHECK5-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK5-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK5-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK5-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK6-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK6-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK6-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK6-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK6-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK6-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK6-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK6-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK6-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK6-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK6-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK6-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK6-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK6-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK6-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK6-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK6-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK6-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK6-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK6-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK6-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK6-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11 +// CHECK6-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK6-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11 +// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK6-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK6-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK6-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK6-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK6-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK6-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK6-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 +// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK6-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK6-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK6-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK6-NEXT: br label [[FOR_COND4:%.*]] -// CHECK6: for.cond4: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK6-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK6-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body6: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK6-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK6-NEXT: br label [[FOR_COND11:%.*]] -// CHECK6: for.cond11: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK6-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK6-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK6: for.body13: -// CHECK6-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK6-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK6-NEXT: br label [[FOR_INC16:%.*]] -// CHECK6: for.inc16: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK6-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK6-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK6-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end18: -// CHECK6-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK6-NEXT: br label [[FOR_COND20:%.*]] -// CHECK6: for.cond20: -// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK6-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK6: for.body22: -// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK6-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK6-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK6-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK6-NEXT: br label [[FOR_INC27:%.*]] -// CHECK6: for.inc27: -// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK6-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK6-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK6: for.end29: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK6-NEXT: br label [[FOR_COND32:%.*]] -// CHECK6: for.cond32: -// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK6-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK6-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK6: for.body34: -// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK6-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK6-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK6-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK6-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK6-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK6-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK6-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK6-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK6-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK6-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK6-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK6-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK6-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK6-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK6-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK6-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK6-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK6-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK6-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK6-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK6-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK6-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK6-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK6-NEXT: br label [[FOR_INC53:%.*]] -// CHECK6: for.inc53: -// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK6-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK6-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK6-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK6: for.end55: -// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK6-NEXT: ret i32 [[TMP31]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK6-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK6-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK6-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK6-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK6-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 +// CHECK6-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK6-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK6-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK6-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK6-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK6-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK6-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK6-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK6-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK6-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK6-NEXT: ret i32 [[ADD10]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK6-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: store double [[ADD5]], double* [[A]], align 8 +// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 +// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK6-NEXT: store double [[INC]], double* [[A6]], align 8 +// CHECK6-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK6-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK6-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK6-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK7-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK7-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK7-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK7-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double +// CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK7-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK7-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK7-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK7-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK7-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK7-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK7-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK7-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK7-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK7-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK7-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK7-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK7-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK7-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK7-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I31:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK7-NEXT: br label [[FOR_COND4:%.*]] -// CHECK7: for.cond4: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK7-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK7-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK7: for.body6: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: br label [[FOR_INC7:%.*]] -// CHECK7: for.inc7: -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK7-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK7-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end9: -// CHECK7-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK7-NEXT: br label [[FOR_COND11:%.*]] -// CHECK7: for.cond11: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK7-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK7-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK7: for.body13: -// CHECK7-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK7-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK7-NEXT: br label [[FOR_INC16:%.*]] -// CHECK7: for.inc16: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK7-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK7-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK7-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end18: -// CHECK7-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK7-NEXT: br label [[FOR_COND20:%.*]] -// CHECK7: for.cond20: -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK7-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK7-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK7: for.body22: -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK7-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK7-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK7-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK7-NEXT: br label [[FOR_INC27:%.*]] -// CHECK7: for.inc27: -// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK7-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK7-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK7-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end29: -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK7-NEXT: br label [[FOR_COND32:%.*]] -// CHECK7: for.cond32: -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK7-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK7-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK7: for.body34: -// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK7-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK7-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK7-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK7-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK7-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK7-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK7-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK7-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK7-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK7-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK7-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK7-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK7-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK7-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK7-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK7-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK7-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK7-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK7-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK7-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK7-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK7-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK7-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK7-NEXT: br label [[FOR_INC53:%.*]] -// CHECK7: for.inc53: -// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK7-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK7-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK7-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end55: -// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK7-NEXT: ret i32 [[TMP29]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK7-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK7-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK7-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK7-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK7-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK7-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK7-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK7-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK7-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK7-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK7-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK7-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK7-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK7-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK7-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK7-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK7-NEXT: ret i32 [[ADD10]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK7-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK7-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK7-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK7-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK7-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK7-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK7-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP5]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK8-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK8-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK8-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK8-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK8-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double +// CHECK8-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK8-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK8-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK8-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK8-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK8-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK8-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK8-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK8-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK8-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK8-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK8-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK8-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK8-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK8-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK8-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK8-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK8-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK8-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK8-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK8-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK8-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK8-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK8-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I31:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK8-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK8-NEXT: br label [[FOR_COND4:%.*]] -// CHECK8: for.cond4: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK8-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK8-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK8: for.body6: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: br label [[FOR_INC7:%.*]] -// CHECK8: for.inc7: -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK8-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK8-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end9: -// CHECK8-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK8-NEXT: br label [[FOR_COND11:%.*]] -// CHECK8: for.cond11: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK8-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK8-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK8: for.body13: -// CHECK8-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK8-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK8-NEXT: br label [[FOR_INC16:%.*]] -// CHECK8: for.inc16: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK8-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK8-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK8-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end18: -// CHECK8-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK8-NEXT: br label [[FOR_COND20:%.*]] -// CHECK8: for.cond20: -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK8-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK8-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK8: for.body22: -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK8-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK8-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK8-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK8-NEXT: br label [[FOR_INC27:%.*]] -// CHECK8: for.inc27: -// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK8-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK8-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK8-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end29: -// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK8-NEXT: br label [[FOR_COND32:%.*]] -// CHECK8: for.cond32: -// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK8-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK8-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK8: for.body34: -// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK8-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK8-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK8-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK8-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK8-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK8-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK8-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK8-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK8-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK8-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK8-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK8-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK8-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK8-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK8-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK8-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK8-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK8-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK8-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK8-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK8-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK8-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK8-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK8-NEXT: br label [[FOR_INC53:%.*]] -// CHECK8: for.inc53: -// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK8-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK8-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK8-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end55: -// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK8-NEXT: ret i32 [[TMP29]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK8-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK8-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK8-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK8-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK8-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK8-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK8-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK8-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK8-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK8-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK8-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK8-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK8-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK8-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK8-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK8-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK8-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK8-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK8-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK8-NEXT: ret i32 [[ADD10]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK8-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK8-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK8-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK8-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK8-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK8-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK8-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP5]] +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[_TMP19:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A_CASTED23:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 +// CHECK9-NEXT: [[_TMP32:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK9-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK9-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK9-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK9-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK9-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 +// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK9-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 +// CHECK9-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) +// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK9-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) +// CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) +// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) +// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 +// CHECK9-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 +// CHECK9-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* +// CHECK9-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 +// CHECK9-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 +// CHECK9-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* +// CHECK9-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 +// CHECK9-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* +// CHECK9-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 +// CHECK9-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP65]], align 8 +// CHECK9-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 +// CHECK9-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK9-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 +// CHECK9-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK9-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* +// CHECK9-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 +// CHECK9-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 +// CHECK9-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK9-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 +// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK9-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 +// CHECK9-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK9-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 +// CHECK9-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK9-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 +// CHECK9-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP84]], align 8 +// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 +// CHECK9-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]] +// CHECK9: omp_offload.failed20: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT21]] +// CHECK9: omp_offload.cont21: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK9-NEXT: [[TMP90:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32* +// CHECK9-NEXT: store i32 [[TMP90]], i32* [[CONV24]], align 4 +// CHECK9-NEXT: [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8 +// CHECK9-NEXT: [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK9-NEXT: [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32* +// CHECK9-NEXT: store i32 [[TMP92]], i32* [[CONV26]], align 4 +// CHECK9-NEXT: [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8 +// CHECK9-NEXT: [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20 +// CHECK9-NEXT: br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]] +// CHECK9: omp_if.then28: +// CHECK9-NEXT: [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK9-NEXT: [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK9-NEXT: [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8 +// CHECK9-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* +// CHECK9-NEXT: store i64 [[TMP91]], i64* [[TMP99]], align 8 +// CHECK9-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* +// CHECK9-NEXT: store i64 [[TMP91]], i64* [[TMP101]], align 8 +// CHECK9-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP102]], align 8 +// CHECK9-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP103]], align 8 +// CHECK9-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** +// CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8 +// CHECK9-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** +// CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8 +// CHECK9-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 40, i64* [[TMP108]], align 8 +// CHECK9-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP109]], align 8 +// CHECK9-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP111]], align 8 +// CHECK9-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP113]], align 8 +// CHECK9-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP114]], align 8 +// CHECK9-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP115]], align 8 +// CHECK9-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** +// CHECK9-NEXT: store float* [[VLA]], float** [[TMP117]], align 8 +// CHECK9-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float** +// CHECK9-NEXT: store float* [[VLA]], float** [[TMP119]], align 8 +// CHECK9-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK9-NEXT: store i64 [[TMP95]], i64* [[TMP120]], align 8 +// CHECK9-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP121]], align 8 +// CHECK9-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** +// CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8 +// CHECK9-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]** +// CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 8 +// CHECK9-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK9-NEXT: store i64 400, i64* [[TMP126]], align 8 +// CHECK9-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP127]], align 8 +// CHECK9-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i64* +// CHECK9-NEXT: store i64 5, i64* [[TMP129]], align 8 +// CHECK9-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64* +// CHECK9-NEXT: store i64 5, i64* [[TMP131]], align 8 +// CHECK9-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK9-NEXT: store i64 8, i64* [[TMP132]], align 8 +// CHECK9-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5 +// CHECK9-NEXT: store i8* null, i8** [[TMP133]], align 8 +// CHECK9-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP135]], align 8 +// CHECK9-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP137]], align 8 +// CHECK9-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK9-NEXT: store i64 8, i64* [[TMP138]], align 8 +// CHECK9-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6 +// CHECK9-NEXT: store i8* null, i8** [[TMP139]], align 8 +// CHECK9-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double** +// CHECK9-NEXT: store double* [[VLA1]], double** [[TMP141]], align 8 +// CHECK9-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double** +// CHECK9-NEXT: store double* [[VLA1]], double** [[TMP143]], align 8 +// CHECK9-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK9-NEXT: store i64 [[TMP97]], i64* [[TMP144]], align 8 +// CHECK9-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7 +// CHECK9-NEXT: store i8* null, i8** [[TMP145]], align 8 +// CHECK9-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT** +// CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 8 +// CHECK9-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT** +// CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 8 +// CHECK9-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK9-NEXT: store i64 16, i64* [[TMP150]], align 8 +// CHECK9-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8 +// CHECK9-NEXT: store i8* null, i8** [[TMP151]], align 8 +// CHECK9-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* +// CHECK9-NEXT: store i64 [[TMP93]], i64* [[TMP153]], align 8 +// CHECK9-NEXT: [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i64* +// CHECK9-NEXT: store i64 [[TMP93]], i64* [[TMP155]], align 8 +// CHECK9-NEXT: [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK9-NEXT: store i64 4, i64* [[TMP156]], align 8 +// CHECK9-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9 +// CHECK9-NEXT: store i8* null, i8** [[TMP157]], align 8 +// CHECK9-NEXT: [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0 +// CHECK9-NEXT: br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK9: omp_offload.failed33: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK9: omp_offload.cont34: +// CHECK9-NEXT: br label [[OMP_IF_END36:%.*]] +// CHECK9: omp_if.else35: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END36]] +// CHECK9: omp_if.end36: +// CHECK9-NEXT: [[TMP163:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP164]]) +// CHECK9-NEXT: ret i32 [[TMP163]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 @@ -8530,7 +10810,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8592,8 +10872,197 @@ // CHECK9-NEXT: ret void // // +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK9-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 +// CHECK9-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK9-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK9-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 +// CHECK9-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK9-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 +// CHECK9-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK9-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK9-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK9-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK9-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK9-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 +// CHECK9-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK9-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK9-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK9-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 +// CHECK9-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK9-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20 +// CHECK9-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK9-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] +// CHECK9-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK9-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK9: omp_offload.failed.i: +// CHECK9-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK9-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* +// CHECK9-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20 +// CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK9-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* +// CHECK9-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20 +// CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20 +// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK9-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* +// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20 +// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20 +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK9: .omp_outlined..1.exit: +// CHECK9-NEXT: ret i32 0 +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 +// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK9-NEXT: ret void +// +// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -8603,12 +11072,12 @@ // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8676,7 +11145,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8694,12 +11163,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8773,7 +11242,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -8815,12 +11284,12 @@ // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8893,59 +11362,59 @@ // CHECK9: omp.dispatch.body: // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !21 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !21 // CHECK9-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 // CHECK9-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK9-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 // CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !21 // CHECK9-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK9-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21 // CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] // CHECK9-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] // CHECK9-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK9-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !21 // CHECK9-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK9-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !21 // CHECK9-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK9-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !21 // CHECK9-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 // CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 // CHECK9-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK9-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK9-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK9-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK9: omp.dispatch.inc: @@ -8963,174 +11432,344 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@_Z3bari +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK9-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP8]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK9-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK9-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK9-NEXT: store double* [[A]], double** [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 8, i64* [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 4, i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK9-NEXT: store i64 2, i64* [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK9-NEXT: store i64 2, i64* [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK9-NEXT: store i64 8, i64* [[TMP32]], align 8 +// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK9-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK9-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 +// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK9-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] +// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK9-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] +// CHECK9-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK9-NEXT: ret i32 [[ADD4]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 -// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK9-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK9-NEXT: store i8 [[TMP6]], i8* [[CONV3]], align 1 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8 +// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] // CHECK9-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK9-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK9-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 -// CHECK9-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] -// CHECK9-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 -// CHECK9-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 -// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 -// CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 -// CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 -// CHECK9-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 -// CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 -// CHECK9-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 -// CHECK9-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK9-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 -// CHECK9-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void +// CHECK9-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK9-NEXT: [[ADD8:%.*]] = add i32 [[TMP40]], 1 +// CHECK9-NEXT: [[TMP41:%.*]] = zext i32 [[ADD8]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) +// CHECK9-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK9-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP44]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9: omp_if.then: +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK9-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK9: omp_if.else: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_IF_END]] +// CHECK9: omp_if.end: +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP24]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -9152,12 +11791,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9245,8 +11884,174 @@ // CHECK9-NEXT: ret void // // +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 +// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK9-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK9-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK9-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK9-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK9-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK9-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK9-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK9-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK9-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK9-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 +// CHECK9-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK9-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK9-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK9-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK9-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9267,12 +12072,12 @@ // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9352,14 +12157,361 @@ // CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR4]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[_TMP19:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A_CASTED23:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 +// CHECK10-NEXT: [[_TMP32:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK10-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK10-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK10-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK10-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK10-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK10-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK10-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 +// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK10-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 +// CHECK10-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) +// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK10-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) +// CHECK10-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) +// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) +// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 +// CHECK10-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK10-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] +// CHECK10-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* +// CHECK10-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 +// CHECK10-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 +// CHECK10-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* +// CHECK10-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 +// CHECK10-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* +// CHECK10-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 +// CHECK10-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP65]], align 8 +// CHECK10-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 +// CHECK10-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK10-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 +// CHECK10-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK10-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* +// CHECK10-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 +// CHECK10-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 +// CHECK10-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK10-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 +// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK10-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 +// CHECK10-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK10-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 +// CHECK10-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK10-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 +// CHECK10-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP84]], align 8 +// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 +// CHECK10-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]] +// CHECK10: omp_offload.failed20: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT21]] +// CHECK10: omp_offload.cont21: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK10-NEXT: [[TMP90:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32* +// CHECK10-NEXT: store i32 [[TMP90]], i32* [[CONV24]], align 4 +// CHECK10-NEXT: [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8 +// CHECK10-NEXT: [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK10-NEXT: [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32* +// CHECK10-NEXT: store i32 [[TMP92]], i32* [[CONV26]], align 4 +// CHECK10-NEXT: [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8 +// CHECK10-NEXT: [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20 +// CHECK10-NEXT: br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]] +// CHECK10: omp_if.then28: +// CHECK10-NEXT: [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK10-NEXT: [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK10-NEXT: [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8 +// CHECK10-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* +// CHECK10-NEXT: store i64 [[TMP91]], i64* [[TMP99]], align 8 +// CHECK10-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* +// CHECK10-NEXT: store i64 [[TMP91]], i64* [[TMP101]], align 8 +// CHECK10-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP102]], align 8 +// CHECK10-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP103]], align 8 +// CHECK10-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8 +// CHECK10-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8 +// CHECK10-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 40, i64* [[TMP108]], align 8 +// CHECK10-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP109]], align 8 +// CHECK10-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP111]], align 8 +// CHECK10-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP113]], align 8 +// CHECK10-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP114]], align 8 +// CHECK10-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP115]], align 8 +// CHECK10-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** +// CHECK10-NEXT: store float* [[VLA]], float** [[TMP117]], align 8 +// CHECK10-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float** +// CHECK10-NEXT: store float* [[VLA]], float** [[TMP119]], align 8 +// CHECK10-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK10-NEXT: store i64 [[TMP95]], i64* [[TMP120]], align 8 +// CHECK10-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP121]], align 8 +// CHECK10-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8 +// CHECK10-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]** +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 8 +// CHECK10-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK10-NEXT: store i64 400, i64* [[TMP126]], align 8 +// CHECK10-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP127]], align 8 +// CHECK10-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i64* +// CHECK10-NEXT: store i64 5, i64* [[TMP129]], align 8 +// CHECK10-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64* +// CHECK10-NEXT: store i64 5, i64* [[TMP131]], align 8 +// CHECK10-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK10-NEXT: store i64 8, i64* [[TMP132]], align 8 +// CHECK10-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5 +// CHECK10-NEXT: store i8* null, i8** [[TMP133]], align 8 +// CHECK10-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP135]], align 8 +// CHECK10-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP137]], align 8 +// CHECK10-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK10-NEXT: store i64 8, i64* [[TMP138]], align 8 +// CHECK10-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6 +// CHECK10-NEXT: store i8* null, i8** [[TMP139]], align 8 +// CHECK10-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double** +// CHECK10-NEXT: store double* [[VLA1]], double** [[TMP141]], align 8 +// CHECK10-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double** +// CHECK10-NEXT: store double* [[VLA1]], double** [[TMP143]], align 8 +// CHECK10-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK10-NEXT: store i64 [[TMP97]], i64* [[TMP144]], align 8 +// CHECK10-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7 +// CHECK10-NEXT: store i8* null, i8** [[TMP145]], align 8 +// CHECK10-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8 +// CHECK10-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT** +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 8 +// CHECK10-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8 +// CHECK10-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT** +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 8 +// CHECK10-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK10-NEXT: store i64 16, i64* [[TMP150]], align 8 +// CHECK10-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8 +// CHECK10-NEXT: store i8* null, i8** [[TMP151]], align 8 +// CHECK10-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9 +// CHECK10-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* +// CHECK10-NEXT: store i64 [[TMP93]], i64* [[TMP153]], align 8 +// CHECK10-NEXT: [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9 +// CHECK10-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i64* +// CHECK10-NEXT: store i64 [[TMP93]], i64* [[TMP155]], align 8 +// CHECK10-NEXT: [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK10-NEXT: store i64 4, i64* [[TMP156]], align 8 +// CHECK10-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9 +// CHECK10-NEXT: store i8* null, i8** [[TMP157]], align 8 +// CHECK10-NEXT: [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0 +// CHECK10-NEXT: br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK10: omp_offload.failed33: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK10: omp_offload.cont34: +// CHECK10-NEXT: br label [[OMP_IF_END36:%.*]] +// CHECK10: omp_if.else35: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END36]] +// CHECK10: omp_if.end36: +// CHECK10-NEXT: [[TMP163:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP164]]) +// CHECK10-NEXT: ret i32 [[TMP163]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 @@ -9378,7 +12530,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9440,8 +12592,197 @@ // CHECK10-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK10-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 +// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 +// CHECK10-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK10-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK10-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 +// CHECK10-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK10-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 +// CHECK10-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK10-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK10-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK10-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK10-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK10-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 +// CHECK10-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK10-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK10-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK10-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 +// CHECK10-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK10-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20 +// CHECK10-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK10-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK10-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] +// CHECK10-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] +// CHECK10-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK10-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK10: omp_offload.failed.i: +// CHECK10-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK10-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* +// CHECK10-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20 +// CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK10-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* +// CHECK10-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20 +// CHECK10-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20 +// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK10-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* +// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20 +// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20 +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK10: .omp_outlined..1.exit: +// CHECK10-NEXT: ret i32 0 +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 +// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -9451,12 +12792,12 @@ // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9524,7 +12865,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9542,12 +12883,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9621,7 +12962,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -9663,12 +13004,12 @@ // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9741,59 +13082,59 @@ // CHECK10: omp.dispatch.body: // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !21 // CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !21 // CHECK10-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double // CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 // CHECK10-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK10-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21 // CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 // CHECK10-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !21 // CHECK10-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK10-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21 // CHECK10-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] // CHECK10-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] // CHECK10-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK10-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !21 // CHECK10-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK10-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21 // CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !21 // CHECK10-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK10-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21 // CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !21 // CHECK10-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 // CHECK10-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 // CHECK10-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK10-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK10-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK10-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK10-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK10: omp.dispatch.inc: @@ -9811,8 +13152,460 @@ // CHECK10-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@_Z3bari +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK10-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP8]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK10-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK10-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK10-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK10-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK10-NEXT: store double* [[A]], double** [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 8, i64* [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 4, i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK10-NEXT: store i64 2, i64* [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK10-NEXT: store i64 2, i64* [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK10-NEXT: store i64 8, i64* [[TMP32]], align 8 +// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK10-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK10-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 +// CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK10-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] +// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK10-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] +// CHECK10-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK10-NEXT: ret i32 [[ADD4]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP6]], i8* [[CONV3]], align 1 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8 +// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK10-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] +// CHECK10-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK10-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK10-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK10-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK10-NEXT: [[ADD8:%.*]] = add i32 [[TMP40]], 1 +// CHECK10-NEXT: [[TMP41:%.*]] = zext i32 [[ADD8]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) +// CHECK10-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK10-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP44]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK10-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP24]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK10-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double [[ADD5]], double* [[A]], align 8 +// CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 +// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK10-NEXT: store double [[INC]], double* [[A6]], align 8 +// CHECK10-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK10-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK10-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK10-NEXT: ret void +// +// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -9849,12 +13642,12 @@ // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK10-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9977,124 +13770,8 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK10-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK10-NEXT: store double [[ADD5]], double* [[A]], align 8 -// CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 -// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK10-NEXT: store double [[INC]], double* [[A6]], align 8 -// CHECK10-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 -// CHECK10-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK10-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10115,12 +13792,12 @@ // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10200,14 +13877,355 @@ // CHECK10-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK10-SAME: () #[[ATTR4]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK10-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED19:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 +// CHECK11-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* +// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 +// CHECK11-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) +// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* +// CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK11-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) +// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK11-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) +// CHECK11-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 +// CHECK11-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]]) +// CHECK11-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK11-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 +// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK11-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* +// CHECK11-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 +// CHECK11-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* +// CHECK11-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 +// CHECK11-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP63]], align 4 +// CHECK11-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 +// CHECK11-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 +// CHECK11-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 +// CHECK11-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* +// CHECK11-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 +// CHECK11-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 +// CHECK11-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK11-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 +// CHECK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK11-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 +// CHECK11-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK11-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 +// CHECK11-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK11-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 +// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK11-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 +// CHECK11-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK11: omp_offload.failed16: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK11: omp_offload.cont17: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK11-NEXT: [[TMP88:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP88]], i32* [[A_CASTED19]], align 4 +// CHECK11-NEXT: [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4 +// CHECK11-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK11-NEXT: store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK11-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK11-NEXT: [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20 +// CHECK11-NEXT: br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]] +// CHECK11: omp_if.then22: +// CHECK11-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK11-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 +// CHECK11-NEXT: [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK11-NEXT: [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8 +// CHECK11-NEXT: [[TMP97:%.*]] = sext i32 [[TMP96]] to i64 +// CHECK11-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* +// CHECK11-NEXT: store i32 [[TMP89]], i32* [[TMP99]], align 4 +// CHECK11-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* +// CHECK11-NEXT: store i32 [[TMP89]], i32* [[TMP101]], align 4 +// CHECK11-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP102]], align 4 +// CHECK11-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP103]], align 4 +// CHECK11-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** +// CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4 +// CHECK11-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** +// CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4 +// CHECK11-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 40, i64* [[TMP108]], align 4 +// CHECK11-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP109]], align 4 +// CHECK11-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP111]], align 4 +// CHECK11-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP113]], align 4 +// CHECK11-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP114]], align 4 +// CHECK11-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP115]], align 4 +// CHECK11-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** +// CHECK11-NEXT: store float* [[VLA]], float** [[TMP117]], align 4 +// CHECK11-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float** +// CHECK11-NEXT: store float* [[VLA]], float** [[TMP119]], align 4 +// CHECK11-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK11-NEXT: store i64 [[TMP94]], i64* [[TMP120]], align 4 +// CHECK11-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP121]], align 4 +// CHECK11-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** +// CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4 +// CHECK11-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]** +// CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 4 +// CHECK11-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK11-NEXT: store i64 400, i64* [[TMP126]], align 4 +// CHECK11-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP127]], align 4 +// CHECK11-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32* +// CHECK11-NEXT: store i32 5, i32* [[TMP129]], align 4 +// CHECK11-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32* +// CHECK11-NEXT: store i32 5, i32* [[TMP131]], align 4 +// CHECK11-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK11-NEXT: store i64 4, i64* [[TMP132]], align 4 +// CHECK11-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5 +// CHECK11-NEXT: store i8* null, i8** [[TMP133]], align 4 +// CHECK11-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP135]], align 4 +// CHECK11-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP137]], align 4 +// CHECK11-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK11-NEXT: store i64 4, i64* [[TMP138]], align 4 +// CHECK11-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6 +// CHECK11-NEXT: store i8* null, i8** [[TMP139]], align 4 +// CHECK11-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double** +// CHECK11-NEXT: store double* [[VLA1]], double** [[TMP141]], align 4 +// CHECK11-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double** +// CHECK11-NEXT: store double* [[VLA1]], double** [[TMP143]], align 4 +// CHECK11-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK11-NEXT: store i64 [[TMP97]], i64* [[TMP144]], align 4 +// CHECK11-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7 +// CHECK11-NEXT: store i8* null, i8** [[TMP145]], align 4 +// CHECK11-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT** +// CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 4 +// CHECK11-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT** +// CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 4 +// CHECK11-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK11-NEXT: store i64 12, i64* [[TMP150]], align 4 +// CHECK11-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8 +// CHECK11-NEXT: store i8* null, i8** [[TMP151]], align 4 +// CHECK11-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* +// CHECK11-NEXT: store i32 [[TMP91]], i32* [[TMP153]], align 4 +// CHECK11-NEXT: [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32* +// CHECK11-NEXT: store i32 [[TMP91]], i32* [[TMP155]], align 4 +// CHECK11-NEXT: [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK11-NEXT: store i64 4, i64* [[TMP156]], align 4 +// CHECK11-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9 +// CHECK11-NEXT: store i8* null, i8** [[TMP157]], align 4 +// CHECK11-NEXT: [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0 +// CHECK11-NEXT: br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] +// CHECK11: omp_offload.failed27: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT28]] +// CHECK11: omp_offload.cont28: +// CHECK11-NEXT: br label [[OMP_IF_END30:%.*]] +// CHECK11: omp_if.else29: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END30]] +// CHECK11: omp_if.end30: +// CHECK11-NEXT: [[TMP163:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP164]]) +// CHECK11-NEXT: ret i32 [[TMP163]] +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 @@ -10224,7 +14242,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10286,8 +14304,192 @@ // CHECK11-NEXT: ret void // // +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK11-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK11-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK11-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK11-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK11-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK11-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK11-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK11-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK11-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK11-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK11-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK11-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK11-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK11-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK11-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK11-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK11-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK11-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK11-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK11-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] +// CHECK11-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] +// CHECK11-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK11-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK11: omp_offload.failed.i: +// CHECK11-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK11-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK11-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21 +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK11-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK11-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21 +// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21 +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK11: .omp_outlined..1.exit: +// CHECK11-NEXT: ret i32 0 +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 +// CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK11-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -10297,12 +14499,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10370,7 +14572,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10386,12 +14588,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10464,7 +14666,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -10502,12 +14704,12 @@ // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10578,59 +14780,59 @@ // CHECK11: omp.dispatch.body: // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double // CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 // CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float -// CHECK11-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK11-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double // CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK11-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !22 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22 // CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] // CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] // CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 -// CHECK11-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !22 // CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK11-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK11-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK11-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 // CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 // CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 -// CHECK11-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK11-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK11: omp.dispatch.inc: @@ -10648,8 +14850,453 @@ // CHECK11-NEXT: ret void // // +// CHECK11-LABEL: define {{[^@]+}}@_Z3bari +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP8]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK11-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK11-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK11-NEXT: store double* [[A]], double** [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 8, i64* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK11-NEXT: store i32 2, i32* [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK11-NEXT: store i32 2, i32* [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK11-NEXT: store i64 4, i64* [[TMP32]], align 4 +// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK11-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK11-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 +// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK11-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK11-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] +// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK11-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] +// CHECK11-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK11-NEXT: ret i32 [[ADD3]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK11-NEXT: store i8 [[TMP6]], i8* [[CONV1]], align 1 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4 +// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] +// CHECK11-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK11-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK11-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK11-NEXT: [[ADD6:%.*]] = add i32 [[TMP40]], 1 +// CHECK11-NEXT: [[TMP41:%.*]] = zext i32 [[ADD6]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) +// CHECK11-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK11-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP44]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11: omp_if.then: +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK11-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK11: omp_if.else: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_IF_END]] +// CHECK11: omp_if.end: +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP24]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK11-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK11-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK11-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK11-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK11-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK11-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -10682,12 +15329,12 @@ // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK11-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10779,150 +15426,37 @@ // CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 -// CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK11-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 -// CHECK11-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 -// CHECK11-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 -// CHECK11-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK11-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 -// CHECK11-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK11-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK11-NEXT: store double [[ADD4]], double* [[A]], align 4 -// CHECK11-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK11-NEXT: store double [[INC]], double* [[A5]], align 4 -// CHECK11-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK11-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK11-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK11-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK11-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK11-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK11-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK11-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10941,12 +15475,12 @@ // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11025,14 +15559,355 @@ // CHECK11-NEXT: ret void // // +// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK11-SAME: () #[[ATTR4]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK11-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED19:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 +// CHECK12-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK12-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* +// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 +// CHECK12-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) +// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* +// CHECK12-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK12-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK12-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) +// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK12-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) +// CHECK12-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 +// CHECK12-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]]) +// CHECK12-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] +// CHECK12-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK12-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 +// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK12-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* +// CHECK12-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 +// CHECK12-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* +// CHECK12-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 +// CHECK12-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP63]], align 4 +// CHECK12-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 +// CHECK12-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 +// CHECK12-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 +// CHECK12-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* +// CHECK12-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 +// CHECK12-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 +// CHECK12-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK12-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 +// CHECK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK12-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 +// CHECK12-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK12-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 +// CHECK12-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK12-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 +// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK12-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 +// CHECK12-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK12: omp_offload.failed16: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK12: omp_offload.cont17: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK12-NEXT: [[TMP88:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP88]], i32* [[A_CASTED19]], align 4 +// CHECK12-NEXT: [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4 +// CHECK12-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK12-NEXT: store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK12-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK12-NEXT: [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20 +// CHECK12-NEXT: br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]] +// CHECK12: omp_if.then22: +// CHECK12-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK12-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 +// CHECK12-NEXT: [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK12-NEXT: [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8 +// CHECK12-NEXT: [[TMP97:%.*]] = sext i32 [[TMP96]] to i64 +// CHECK12-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* +// CHECK12-NEXT: store i32 [[TMP89]], i32* [[TMP99]], align 4 +// CHECK12-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* +// CHECK12-NEXT: store i32 [[TMP89]], i32* [[TMP101]], align 4 +// CHECK12-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP102]], align 4 +// CHECK12-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP103]], align 4 +// CHECK12-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4 +// CHECK12-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4 +// CHECK12-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 40, i64* [[TMP108]], align 4 +// CHECK12-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP109]], align 4 +// CHECK12-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP111]], align 4 +// CHECK12-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP113]], align 4 +// CHECK12-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP114]], align 4 +// CHECK12-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP115]], align 4 +// CHECK12-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** +// CHECK12-NEXT: store float* [[VLA]], float** [[TMP117]], align 4 +// CHECK12-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float** +// CHECK12-NEXT: store float* [[VLA]], float** [[TMP119]], align 4 +// CHECK12-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK12-NEXT: store i64 [[TMP94]], i64* [[TMP120]], align 4 +// CHECK12-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP121]], align 4 +// CHECK12-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4 +// CHECK12-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]** +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 4 +// CHECK12-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK12-NEXT: store i64 400, i64* [[TMP126]], align 4 +// CHECK12-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP127]], align 4 +// CHECK12-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32* +// CHECK12-NEXT: store i32 5, i32* [[TMP129]], align 4 +// CHECK12-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32* +// CHECK12-NEXT: store i32 5, i32* [[TMP131]], align 4 +// CHECK12-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK12-NEXT: store i64 4, i64* [[TMP132]], align 4 +// CHECK12-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5 +// CHECK12-NEXT: store i8* null, i8** [[TMP133]], align 4 +// CHECK12-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP135]], align 4 +// CHECK12-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP137]], align 4 +// CHECK12-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK12-NEXT: store i64 4, i64* [[TMP138]], align 4 +// CHECK12-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6 +// CHECK12-NEXT: store i8* null, i8** [[TMP139]], align 4 +// CHECK12-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double** +// CHECK12-NEXT: store double* [[VLA1]], double** [[TMP141]], align 4 +// CHECK12-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double** +// CHECK12-NEXT: store double* [[VLA1]], double** [[TMP143]], align 4 +// CHECK12-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK12-NEXT: store i64 [[TMP97]], i64* [[TMP144]], align 4 +// CHECK12-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7 +// CHECK12-NEXT: store i8* null, i8** [[TMP145]], align 4 +// CHECK12-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8 +// CHECK12-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT** +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 4 +// CHECK12-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8 +// CHECK12-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT** +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 4 +// CHECK12-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK12-NEXT: store i64 12, i64* [[TMP150]], align 4 +// CHECK12-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8 +// CHECK12-NEXT: store i8* null, i8** [[TMP151]], align 4 +// CHECK12-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9 +// CHECK12-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* +// CHECK12-NEXT: store i32 [[TMP91]], i32* [[TMP153]], align 4 +// CHECK12-NEXT: [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9 +// CHECK12-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32* +// CHECK12-NEXT: store i32 [[TMP91]], i32* [[TMP155]], align 4 +// CHECK12-NEXT: [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK12-NEXT: store i64 4, i64* [[TMP156]], align 4 +// CHECK12-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9 +// CHECK12-NEXT: store i8* null, i8** [[TMP157]], align 4 +// CHECK12-NEXT: [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0 +// CHECK12-NEXT: br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] +// CHECK12: omp_offload.failed27: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT28]] +// CHECK12: omp_offload.cont28: +// CHECK12-NEXT: br label [[OMP_IF_END30:%.*]] +// CHECK12: omp_if.else29: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END30]] +// CHECK12: omp_if.end30: +// CHECK12-NEXT: [[TMP163:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP164]]) +// CHECK12-NEXT: ret i32 [[TMP163]] +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 @@ -11049,7 +15924,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11111,8 +15986,192 @@ // CHECK12-NEXT: ret void // // +// CHECK12-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK12-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK12-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK12-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK12-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK12-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK12-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK12-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK12-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK12-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK12-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK12-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK12-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK12-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK12-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK12-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK12-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK12-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK12-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK12-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK12-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK12-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK12-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] +// CHECK12-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] +// CHECK12-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK12-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK12: omp_offload.failed.i: +// CHECK12-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK12-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK12-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21 +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK12-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK12-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21 +// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21 +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK12: .omp_outlined..1.exit: +// CHECK12-NEXT: ret i32 0 +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 +// CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -11122,12 +16181,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11195,7 +16254,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11211,12 +16270,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11289,7 +16348,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -11327,12 +16386,12 @@ // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11403,78 +16462,523 @@ // CHECK12: omp.dispatch.body: // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double // CHECK12-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 // CHECK12-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float -// CHECK12-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK12-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double // CHECK12-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK12-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK12-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 // CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !22 // CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22 // CHECK12-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] // CHECK12-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] // CHECK12-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 -// CHECK12-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !22 // CHECK12-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK12-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK12-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22 // CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK12-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !22 // CHECK12-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 // CHECK12-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 // CHECK12-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 -// CHECK12-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK12-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK12-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK12-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z3bari +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP8]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK12-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK12-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK12-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** +// CHECK12-NEXT: store double* [[A]], double** [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 8, i64* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK12-NEXT: store i32 2, i32* [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK12-NEXT: store i32 2, i32* [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK12-NEXT: store i64 4, i64* [[TMP32]], align 4 +// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** +// CHECK12-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** +// CHECK12-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 +// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK12-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK12-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] +// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK12-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 +// CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] +// CHECK12-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) +// CHECK12-NEXT: ret i32 [[ADD3]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK12-NEXT: store i8 [[TMP6]], i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4 +// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] +// CHECK12-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK12-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK12-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK12-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add i32 [[TMP40]], 1 +// CHECK12-NEXT: [[TMP41:%.*]] = zext i32 [[ADD6]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) +// CHECK12-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK12-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP44]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK12-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP24]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK12-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK12-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK12-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK12-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK12-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK12-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK12-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK12-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK12-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -11507,12 +17011,12 @@ // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK12-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11633,121 +17137,8 @@ // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK12-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK12-NEXT: store double [[ADD4]], double* [[A]], align 4 -// CHECK12-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK12-NEXT: store double [[INC]], double* [[A5]], align 4 -// CHECK12-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK12-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK12-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK12-NEXT: ret void -// -// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11766,12 +17157,12 @@ // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11850,14370 +17241,3355 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK12-SAME: () #[[ATTR4]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK12-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK13-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK13-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK13-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK13-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK13-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK13-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK13-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK13-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK13-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK13-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK13-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK13-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK13: omp.dispatch.cond: +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK13: omp.dispatch.body: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK13-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK13-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK13-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK13-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK13-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK13-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK13-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK13-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK13-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK13-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK13-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK13-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK13-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK13-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK13-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK13-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK13-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11 +// CHECK13-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK13-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11 +// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK13-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK13-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK13-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK13-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK13-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK13-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK13: omp.dispatch.inc: +// CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK13-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK13-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK13: omp.dispatch.end: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 +// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK13-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK13-NEXT: br label [[FOR_COND4:%.*]] -// CHECK13: for.cond4: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK13-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK13-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body6: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK13-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK13-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20:%.*]] -// CHECK13: for.cond20: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK13-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK13: for.body22: -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK13-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK13-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK13-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK13-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK13-NEXT: br label [[FOR_INC27:%.*]] -// CHECK13: for.inc27: -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK13-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end29: -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK13-NEXT: br label [[FOR_COND32:%.*]] -// CHECK13: for.cond32: -// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK13-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK13-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK13: for.body34: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK13-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK13-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK13-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK13-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK13-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK13-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK13-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK13-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK13-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK13-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK13-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK13-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK13-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK13-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK13-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK13-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK13-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK13-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK13-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK13-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK13-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK13-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK13-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK13-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK13-NEXT: br label [[FOR_INC53:%.*]] -// CHECK13: for.inc53: -// CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK13-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK13-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK13-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end55: -// CHECK13-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK13-NEXT: ret i32 [[TMP31]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK13-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK13-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK13-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK13-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK13: omp.precond.then: +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK13-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK13-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK13-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK13-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK13-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK13-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK13-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 +// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK13-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 +// CHECK13-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK13-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK13-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK13-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 +// CHECK13-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 +// CHECK13-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK13-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK13-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK13-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK13-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK13-NEXT: br label [[OMP_PRECOND_END]] +// CHECK13: omp.precond.end: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP8]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK13-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK13-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK13-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK13-NEXT: ret i32 [[ADD10]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK13-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK13-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: store double [[ADD5]], double* [[A]], align 8 +// CHECK13-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 +// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK13-NEXT: store double [[INC]], double* [[A6]], align 8 +// CHECK13-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK13-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK13-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK13-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK13-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP8]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK13-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK13-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK13-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK13-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK13-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK13-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK14-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK14-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK14-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK14-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK14-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK14-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK14-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK14-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK14-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK14-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK14-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK14-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK14: omp.dispatch.cond: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK14: omp.dispatch.body: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK14-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK14-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK14-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK14-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK14-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK14-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK14-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK14-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK14-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK14-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK14-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 +// CHECK14-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK14-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK14-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK14-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 +// CHECK14-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK14-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK14-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK14-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK14-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK14-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 +// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11 +// CHECK14-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK14-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11 +// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK14-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK14-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK14-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK14-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK14-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK14-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK14: omp.dispatch.inc: +// CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK14-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK14-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK14: omp.dispatch.end: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 +// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK14-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK14-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK14-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK14-NEXT: br label [[FOR_COND4:%.*]] -// CHECK14: for.cond4: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK14-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK14-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body6: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK14-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK14-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK14-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20:%.*]] -// CHECK14: for.cond20: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK14-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK14: for.body22: -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK14-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK14-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK14-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK14-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK14-NEXT: br label [[FOR_INC27:%.*]] -// CHECK14: for.inc27: -// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK14-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end29: -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK14-NEXT: br label [[FOR_COND32:%.*]] -// CHECK14: for.cond32: -// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK14-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK14-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK14: for.body34: -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK14-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK14-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK14-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK14-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK14-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK14-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK14-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK14-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK14-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK14-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK14-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK14-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK14-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK14-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK14-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK14-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK14-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK14-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK14-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK14-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK14-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK14-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK14-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK14-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK14-NEXT: br label [[FOR_INC53:%.*]] -// CHECK14: for.inc53: -// CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK14-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK14-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK14-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end55: -// CHECK14-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK14-NEXT: ret i32 [[TMP31]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK14-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK14-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK14-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK14-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK14: omp.precond.then: +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK14-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK14-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK14-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK14-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK14-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK14-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK14-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 +// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK14-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 +// CHECK14-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK14-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK14-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK14-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK14-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 +// CHECK14-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 +// CHECK14-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK14-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK14-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK14-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK14-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK14-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK14-NEXT: br label [[OMP_PRECOND_END]] +// CHECK14: omp.precond.end: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP8]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK14-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK14-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK14-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK14-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK14-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK14-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK14-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK14-NEXT: ret i32 [[ADD10]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK14-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK14-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: store double [[ADD5]], double* [[A]], align 8 +// CHECK14-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 +// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK14-NEXT: store double [[INC]], double* [[A6]], align 8 +// CHECK14-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK14-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK14-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK14-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK14-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK14-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP8]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK14-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK14-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK14-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK14-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK14-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK14-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK15-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK15-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK15-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK15-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK15-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK15-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK15-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK15-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK15-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK15: omp.dispatch.cond: +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK15-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK15: omp.dispatch.body: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK15-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double +// CHECK15-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK15-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK15-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK15-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK15-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK15-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK15-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK15-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK15-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK15-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK15-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK15-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK15-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK15-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK15-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK15-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK15-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK15-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK15-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK15-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK15-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK15: omp.dispatch.inc: +// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK15-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK15-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK15: omp.dispatch.end: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK15-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK15-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I31:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4:%.*]] -// CHECK15: for.cond4: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK15-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK15: for.body6: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: br label [[FOR_INC7:%.*]] -// CHECK15: for.inc7: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end9: -// CHECK15-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK15-NEXT: br label [[FOR_COND11:%.*]] -// CHECK15: for.cond11: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK15-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK15-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK15: for.body13: -// CHECK15-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK15-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK15-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK15-NEXT: br label [[FOR_INC16:%.*]] -// CHECK15: for.inc16: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK15-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK15-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK15-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end18: -// CHECK15-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK15-NEXT: br label [[FOR_COND20:%.*]] -// CHECK15: for.cond20: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK15-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK15-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK15: for.body22: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK15-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK15-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK15-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK15-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK15-NEXT: br label [[FOR_INC27:%.*]] -// CHECK15: for.inc27: -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK15-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK15-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK15-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end29: -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK15-NEXT: br label [[FOR_COND32:%.*]] -// CHECK15: for.cond32: -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK15-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK15-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK15: for.body34: -// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK15-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK15-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK15-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK15-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK15-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK15-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK15-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK15-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK15-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK15-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK15-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK15-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK15-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK15-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK15-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK15-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK15-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK15-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK15-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK15-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK15-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK15-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK15-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK15-NEXT: br label [[FOR_INC53:%.*]] -// CHECK15: for.inc53: -// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK15-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK15-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK15-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end55: -// CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK15-NEXT: ret i32 [[TMP29]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK15-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK15-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK15-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK15-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK15: omp.precond.then: +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK15-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK15-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK15-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK15-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK15-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK15-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK15-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 +// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK15-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK15-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK15-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK15-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 +// CHECK15-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK15-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK15-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK15-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK15-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK15-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK15-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK15-NEXT: br label [[OMP_PRECOND_END]] +// CHECK15: omp.precond.end: +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK15-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK15-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK15-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK15-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK15-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK15-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK15-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK15-NEXT: ret i32 [[ADD10]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK15-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK15-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK15-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK15-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK15-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK15-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK15-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK15-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK15-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP5]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK15-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK15-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK16-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK16-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK16-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK16-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK16-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK16-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK16-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK16-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK16-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK16-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK16: omp.dispatch.cond: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK16-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK16: omp.dispatch.body: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK16-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double +// CHECK16-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK16-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK16-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK16-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK16-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK16-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK16-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK16-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK16-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK16-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 +// CHECK16-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK16-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK16-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK16-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK16-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK16-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 +// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK16-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK16-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK16-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK16-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK16-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK16: omp.dispatch.inc: +// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK16-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK16-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK16: omp.dispatch.end: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK16-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK16-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I31:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK16-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4:%.*]] -// CHECK16: for.cond4: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK16-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK16: for.body6: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: br label [[FOR_INC7:%.*]] -// CHECK16: for.inc7: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK16-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end9: -// CHECK16-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK16-NEXT: br label [[FOR_COND11:%.*]] -// CHECK16: for.cond11: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK16-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK16-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK16: for.body13: -// CHECK16-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK16-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK16-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK16-NEXT: br label [[FOR_INC16:%.*]] -// CHECK16: for.inc16: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK16-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK16-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK16-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end18: -// CHECK16-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK16-NEXT: br label [[FOR_COND20:%.*]] -// CHECK16: for.cond20: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK16-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK16-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK16: for.body22: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK16-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK16-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK16-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK16-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK16-NEXT: br label [[FOR_INC27:%.*]] -// CHECK16: for.inc27: -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK16-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK16-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK16-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end29: -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK16-NEXT: br label [[FOR_COND32:%.*]] -// CHECK16: for.cond32: -// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK16-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK16-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK16: for.body34: -// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK16-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK16-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK16-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK16-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK16-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK16-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK16-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK16-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK16-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK16-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK16-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK16-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK16-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK16-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK16-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK16-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK16-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK16-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK16-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK16-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK16-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK16-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK16-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK16-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK16-NEXT: br label [[FOR_INC53:%.*]] -// CHECK16: for.inc53: -// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK16-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK16-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK16-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end55: -// CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK16-NEXT: ret i32 [[TMP29]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK16-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK16-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK16-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK16-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK16: omp.precond.then: +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK16-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK16-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK16-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK16-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK16-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK16-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK16-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK16-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK16-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK16-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK16-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 +// CHECK16-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 +// CHECK16-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK16-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK16-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK16-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK16-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK16-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK16-NEXT: br label [[OMP_PRECOND_END]] +// CHECK16: omp.precond.end: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK16-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK16-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK16-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK16-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK16-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK16-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK16-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK16-NEXT: ret i32 [[ADD10]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK16-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK16-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK16-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK16-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK16-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK16-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK16-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK16-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK16-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK16-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK16-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP5]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[_TMP19:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A_CASTED23:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 -// CHECK17-NEXT: [[_TMP32:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 -// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* -// CHECK17-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 -// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 -// CHECK17-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 -// CHECK17-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) -// CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* -// CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* -// CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) -// CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* -// CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) -// CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) -// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 -// CHECK17-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) -// CHECK17-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 -// CHECK17-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* -// CHECK17-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 -// CHECK17-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 -// CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* -// CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 -// CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* -// CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 -// CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP65]], align 8 -// CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 -// CHECK17-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* -// CHECK17-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 -// CHECK17-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 -// CHECK17-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* -// CHECK17-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 -// CHECK17-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 -// CHECK17-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 -// CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 -// CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP79]], align 8 -// CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 -// CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* -// CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 -// CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP84]], align 8 -// CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 -// CHECK17-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]] -// CHECK17: omp_offload.failed20: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT21]] -// CHECK17: omp_offload.cont21: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK17-NEXT: [[TMP90:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32* -// CHECK17-NEXT: store i32 [[TMP90]], i32* [[CONV24]], align 4 -// CHECK17-NEXT: [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8 -// CHECK17-NEXT: [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK17-NEXT: [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32* -// CHECK17-NEXT: store i32 [[TMP92]], i32* [[CONV26]], align 4 -// CHECK17-NEXT: [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8 -// CHECK17-NEXT: [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20 -// CHECK17-NEXT: br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]] -// CHECK17: omp_if.then28: -// CHECK17-NEXT: [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4 -// CHECK17-NEXT: [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK17-NEXT: [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8 -// CHECK17-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* -// CHECK17-NEXT: store i64 [[TMP91]], i64* [[TMP99]], align 8 -// CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* -// CHECK17-NEXT: store i64 [[TMP91]], i64* [[TMP101]], align 8 -// CHECK17-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP102]], align 8 -// CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP103]], align 8 -// CHECK17-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8 -// CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8 -// CHECK17-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 40, i64* [[TMP108]], align 8 -// CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP109]], align 8 -// CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP111]], align 8 -// CHECK17-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP113]], align 8 -// CHECK17-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP114]], align 8 -// CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP115]], align 8 -// CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** -// CHECK17-NEXT: store float* [[VLA]], float** [[TMP117]], align 8 -// CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float** -// CHECK17-NEXT: store float* [[VLA]], float** [[TMP119]], align 8 -// CHECK17-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK17-NEXT: store i64 [[TMP95]], i64* [[TMP120]], align 8 -// CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP121]], align 8 -// CHECK17-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8 -// CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]** -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 8 -// CHECK17-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK17-NEXT: store i64 400, i64* [[TMP126]], align 8 -// CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP127]], align 8 -// CHECK17-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i64* -// CHECK17-NEXT: store i64 5, i64* [[TMP129]], align 8 -// CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64* -// CHECK17-NEXT: store i64 5, i64* [[TMP131]], align 8 -// CHECK17-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK17-NEXT: store i64 8, i64* [[TMP132]], align 8 -// CHECK17-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5 -// CHECK17-NEXT: store i8* null, i8** [[TMP133]], align 8 -// CHECK17-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP135]], align 8 -// CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP137]], align 8 -// CHECK17-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK17-NEXT: store i64 8, i64* [[TMP138]], align 8 -// CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6 -// CHECK17-NEXT: store i8* null, i8** [[TMP139]], align 8 -// CHECK17-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double** -// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP141]], align 8 -// CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double** -// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP143]], align 8 -// CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK17-NEXT: store i64 [[TMP97]], i64* [[TMP144]], align 8 -// CHECK17-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7 -// CHECK17-NEXT: store i8* null, i8** [[TMP145]], align 8 -// CHECK17-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8 -// CHECK17-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT** -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 8 -// CHECK17-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8 -// CHECK17-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT** -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 8 -// CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK17-NEXT: store i64 16, i64* [[TMP150]], align 8 -// CHECK17-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8 -// CHECK17-NEXT: store i8* null, i8** [[TMP151]], align 8 -// CHECK17-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9 -// CHECK17-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* -// CHECK17-NEXT: store i64 [[TMP93]], i64* [[TMP153]], align 8 -// CHECK17-NEXT: [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9 -// CHECK17-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i64* -// CHECK17-NEXT: store i64 [[TMP93]], i64* [[TMP155]], align 8 -// CHECK17-NEXT: [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK17-NEXT: store i64 4, i64* [[TMP156]], align 8 -// CHECK17-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9 -// CHECK17-NEXT: store i8* null, i8** [[TMP157]], align 8 -// CHECK17-NEXT: [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0 -// CHECK17-NEXT: br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] -// CHECK17: omp_offload.failed33: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT34]] -// CHECK17: omp_offload.cont34: -// CHECK17-NEXT: br label [[OMP_IF_END36:%.*]] -// CHECK17: omp_if.else35: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END36]] -// CHECK17: omp_if.end36: -// CHECK17-NEXT: [[TMP163:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP164]]) -// CHECK17-NEXT: ret i32 [[TMP163]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 -// CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 -// CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 -// CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 -// CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 -// CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) -// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20 -// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] -// CHECK17-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] -// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK17: omp_offload.failed.i: -// CHECK17-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* -// CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20 -// CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* -// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20 -// CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20 -// CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK17-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* -// CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20 -// CHECK17-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20 -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK17: .omp_outlined..1.exit: -// CHECK17-NEXT: ret i32 0 -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21 -// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK17-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !21 -// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double -// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21 -// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !21 -// CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double -// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21 -// CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !21 -// CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21 -// CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] -// CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !21 -// CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21 -// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !21 -// CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21 -// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !21 -// CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP8]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK17-NEXT: store double* [[A]], double** [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 8, i64* [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 4, i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK17-NEXT: store i64 2, i64* [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK17-NEXT: store i64 2, i64* [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8 -// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 -// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK17-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] -// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK17-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK17-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] -// CHECK17-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK17-NEXT: ret i32 [[ADD4]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK17-NEXT: store i8 [[TMP6]], i8* [[CONV3]], align 1 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK17-NEXT: store i64 [[TMP7]], i64* [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK17-NEXT: store i64 [[TMP7]], i64* [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8 -// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK17-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK17-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] -// CHECK17-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 -// CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK17-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK17-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK17-NEXT: [[ADD8:%.*]] = add i32 [[TMP40]], 1 -// CHECK17-NEXT: [[TMP41:%.*]] = zext i32 [[ADD8]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) -// CHECK17-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 -// CHECK17-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP44]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK17: omp_if.then: -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_IF_END]] -// CHECK17: omp_if.end: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP24]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK17-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double [[ADD5]], double* [[A]], align 8 -// CHECK17-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 -// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK17-NEXT: store double [[INC]], double* [[A6]], align 8 -// CHECK17-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 -// CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] -// CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK17-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK17-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK17-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 -// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK17-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] -// CHECK17-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 -// CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK17-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK17-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 -// CHECK17-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] -// CHECK17-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 -// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK17-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 -// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 -// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 -// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 -// CHECK17-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 -// CHECK17-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 -// CHECK17-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 -// CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK17-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 -// CHECK17-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR4]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[_TMP19:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A_CASTED23:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 -// CHECK18-NEXT: [[_TMP32:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 -// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* -// CHECK18-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 -// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 -// CHECK18-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK18-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 -// CHECK18-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) -// CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* -// CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* -// CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) -// CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* -// CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) -// CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) -// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 -// CHECK18-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) -// CHECK18-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 -// CHECK18-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] -// CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* -// CHECK18-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 -// CHECK18-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 -// CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* -// CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 -// CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* -// CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 -// CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP65]], align 8 -// CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 -// CHECK18-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* -// CHECK18-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 -// CHECK18-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 -// CHECK18-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* -// CHECK18-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 -// CHECK18-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 -// CHECK18-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 -// CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 -// CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP79]], align 8 -// CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 -// CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* -// CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 -// CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP84]], align 8 -// CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 -// CHECK18-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]] -// CHECK18: omp_offload.failed20: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT21]] -// CHECK18: omp_offload.cont21: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK18-NEXT: [[TMP90:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32* -// CHECK18-NEXT: store i32 [[TMP90]], i32* [[CONV24]], align 4 -// CHECK18-NEXT: [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8 -// CHECK18-NEXT: [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 -// CHECK18-NEXT: [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32* -// CHECK18-NEXT: store i32 [[TMP92]], i32* [[CONV26]], align 4 -// CHECK18-NEXT: [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8 -// CHECK18-NEXT: [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20 -// CHECK18-NEXT: br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]] -// CHECK18: omp_if.then28: -// CHECK18-NEXT: [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4 -// CHECK18-NEXT: [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]] -// CHECK18-NEXT: [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8 -// CHECK18-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* -// CHECK18-NEXT: store i64 [[TMP91]], i64* [[TMP99]], align 8 -// CHECK18-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* -// CHECK18-NEXT: store i64 [[TMP91]], i64* [[TMP101]], align 8 -// CHECK18-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP102]], align 8 -// CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP103]], align 8 -// CHECK18-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8 -// CHECK18-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8 -// CHECK18-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 40, i64* [[TMP108]], align 8 -// CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP109]], align 8 -// CHECK18-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP111]], align 8 -// CHECK18-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP113]], align 8 -// CHECK18-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP114]], align 8 -// CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP115]], align 8 -// CHECK18-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** -// CHECK18-NEXT: store float* [[VLA]], float** [[TMP117]], align 8 -// CHECK18-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float** -// CHECK18-NEXT: store float* [[VLA]], float** [[TMP119]], align 8 -// CHECK18-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK18-NEXT: store i64 [[TMP95]], i64* [[TMP120]], align 8 -// CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP121]], align 8 -// CHECK18-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8 -// CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]** -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 8 -// CHECK18-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK18-NEXT: store i64 400, i64* [[TMP126]], align 8 -// CHECK18-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP127]], align 8 -// CHECK18-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i64* -// CHECK18-NEXT: store i64 5, i64* [[TMP129]], align 8 -// CHECK18-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64* -// CHECK18-NEXT: store i64 5, i64* [[TMP131]], align 8 -// CHECK18-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK18-NEXT: store i64 8, i64* [[TMP132]], align 8 -// CHECK18-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5 -// CHECK18-NEXT: store i8* null, i8** [[TMP133]], align 8 -// CHECK18-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP135]], align 8 -// CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP137]], align 8 -// CHECK18-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK18-NEXT: store i64 8, i64* [[TMP138]], align 8 -// CHECK18-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6 -// CHECK18-NEXT: store i8* null, i8** [[TMP139]], align 8 -// CHECK18-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double** -// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP141]], align 8 -// CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double** -// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP143]], align 8 -// CHECK18-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK18-NEXT: store i64 [[TMP97]], i64* [[TMP144]], align 8 -// CHECK18-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7 -// CHECK18-NEXT: store i8* null, i8** [[TMP145]], align 8 -// CHECK18-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8 -// CHECK18-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT** -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 8 -// CHECK18-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8 -// CHECK18-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT** -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 8 -// CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK18-NEXT: store i64 16, i64* [[TMP150]], align 8 -// CHECK18-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8 -// CHECK18-NEXT: store i8* null, i8** [[TMP151]], align 8 -// CHECK18-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9 -// CHECK18-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* -// CHECK18-NEXT: store i64 [[TMP93]], i64* [[TMP153]], align 8 -// CHECK18-NEXT: [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9 -// CHECK18-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i64* -// CHECK18-NEXT: store i64 [[TMP93]], i64* [[TMP155]], align 8 -// CHECK18-NEXT: [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK18-NEXT: store i64 4, i64* [[TMP156]], align 8 -// CHECK18-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9 -// CHECK18-NEXT: store i8* null, i8** [[TMP157]], align 8 -// CHECK18-NEXT: [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0 -// CHECK18-NEXT: br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] -// CHECK18: omp_offload.failed33: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT34]] -// CHECK18: omp_offload.cont34: -// CHECK18-NEXT: br label [[OMP_IF_END36:%.*]] -// CHECK18: omp_if.else35: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END36]] -// CHECK18: omp_if.end36: -// CHECK18-NEXT: [[TMP163:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP164]]) -// CHECK18-NEXT: ret i32 [[TMP163]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 -// CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 -// CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 -// CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 -// CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 -// CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 -// CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 -// CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 -// CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 -// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 -// CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) -// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20 -// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] -// CHECK18-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] -// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK18: omp_offload.failed.i: -// CHECK18-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* -// CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20 -// CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* -// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20 -// CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20 -// CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK18-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* -// CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20 -// CHECK18-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20 -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK18: .omp_outlined..1.exit: -// CHECK18-NEXT: ret i32 0 -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21 -// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK18-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !21 -// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double -// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21 -// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !21 -// CHECK18-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double -// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK18-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK18-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21 -// CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK18-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !21 -// CHECK18-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK18-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21 -// CHECK18-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK18-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] -// CHECK18-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK18-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !21 -// CHECK18-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK18-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21 -// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !21 -// CHECK18-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK18-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21 -// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !21 -// CHECK18-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK18-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK18-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK18-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK18-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK18-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK18-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP8]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK18-NEXT: store double* [[A]], double** [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 8, i64* [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 4, i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK18-NEXT: store i64 2, i64* [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK18-NEXT: store i64 2, i64* [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8 -// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 -// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK18-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] -// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK18-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK18-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] -// CHECK18-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK18-NEXT: ret i32 [[ADD4]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK18-NEXT: store i8 [[TMP6]], i8* [[CONV3]], align 1 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK18-NEXT: store i64 [[TMP7]], i64* [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK18-NEXT: store i64 [[TMP7]], i64* [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8 -// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK18-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK18-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] -// CHECK18-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 -// CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK18-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK18-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK18-NEXT: [[ADD8:%.*]] = add i32 [[TMP40]], 1 -// CHECK18-NEXT: [[TMP41:%.*]] = zext i32 [[ADD8]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) -// CHECK18-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 -// CHECK18-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP44]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK18: omp_if.then: -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK18: omp_if.else: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_IF_END]] -// CHECK18: omp_if.end: -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP24]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK18-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double [[ADD5]], double* [[A]], align 8 -// CHECK18-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 -// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK18-NEXT: store double [[INC]], double* [[A6]], align 8 -// CHECK18-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 -// CHECK18-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] -// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK18-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK18-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK18-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 -// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK18-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] -// CHECK18-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 -// CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK18-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK18-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] -// CHECK18-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 -// CHECK18-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] -// CHECK18-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 -// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK18-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 -// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 -// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 -// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 -// CHECK18-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 -// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 -// CHECK18-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 -// CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK18-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 -// CHECK18-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR4]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED19:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 -// CHECK19-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* -// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 -// CHECK19-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) -// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* -// CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) -// CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* -// CHECK19-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) -// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* -// CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) -// CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 -// CHECK19-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]]) -// CHECK19-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] -// CHECK19-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* -// CHECK19-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 -// CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 -// CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* -// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 -// CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* -// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 -// CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP63]], align 4 -// CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 -// CHECK19-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 -// CHECK19-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 -// CHECK19-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* -// CHECK19-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 -// CHECK19-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 -// CHECK19-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 -// CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* -// CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 -// CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP77]], align 4 -// CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 -// CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* -// CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 -// CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 -// CHECK19-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK19: omp_offload.failed16: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK19: omp_offload.cont17: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK19-NEXT: [[TMP88:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP88]], i32* [[A_CASTED19]], align 4 -// CHECK19-NEXT: [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4 -// CHECK19-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK19-NEXT: store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 -// CHECK19-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 -// CHECK19-NEXT: [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20 -// CHECK19-NEXT: br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]] -// CHECK19: omp_if.then22: -// CHECK19-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4 -// CHECK19-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 -// CHECK19-NEXT: [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK19-NEXT: [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8 -// CHECK19-NEXT: [[TMP97:%.*]] = sext i32 [[TMP96]] to i64 -// CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* -// CHECK19-NEXT: store i32 [[TMP89]], i32* [[TMP99]], align 4 -// CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* -// CHECK19-NEXT: store i32 [[TMP89]], i32* [[TMP101]], align 4 -// CHECK19-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP102]], align 4 -// CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP103]], align 4 -// CHECK19-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4 -// CHECK19-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4 -// CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 40, i64* [[TMP108]], align 4 -// CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP109]], align 4 -// CHECK19-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP111]], align 4 -// CHECK19-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP113]], align 4 -// CHECK19-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP114]], align 4 -// CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP115]], align 4 -// CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** -// CHECK19-NEXT: store float* [[VLA]], float** [[TMP117]], align 4 -// CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float** -// CHECK19-NEXT: store float* [[VLA]], float** [[TMP119]], align 4 -// CHECK19-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK19-NEXT: store i64 [[TMP94]], i64* [[TMP120]], align 4 -// CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP121]], align 4 -// CHECK19-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4 -// CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]** -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 4 -// CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK19-NEXT: store i64 400, i64* [[TMP126]], align 4 -// CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP127]], align 4 -// CHECK19-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32* -// CHECK19-NEXT: store i32 5, i32* [[TMP129]], align 4 -// CHECK19-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32* -// CHECK19-NEXT: store i32 5, i32* [[TMP131]], align 4 -// CHECK19-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK19-NEXT: store i64 4, i64* [[TMP132]], align 4 -// CHECK19-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5 -// CHECK19-NEXT: store i8* null, i8** [[TMP133]], align 4 -// CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP135]], align 4 -// CHECK19-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP137]], align 4 -// CHECK19-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK19-NEXT: store i64 4, i64* [[TMP138]], align 4 -// CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6 -// CHECK19-NEXT: store i8* null, i8** [[TMP139]], align 4 -// CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double** -// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP141]], align 4 -// CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double** -// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP143]], align 4 -// CHECK19-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK19-NEXT: store i64 [[TMP97]], i64* [[TMP144]], align 4 -// CHECK19-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7 -// CHECK19-NEXT: store i8* null, i8** [[TMP145]], align 4 -// CHECK19-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8 -// CHECK19-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT** -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 4 -// CHECK19-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8 -// CHECK19-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT** -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 4 -// CHECK19-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK19-NEXT: store i64 12, i64* [[TMP150]], align 4 -// CHECK19-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8 -// CHECK19-NEXT: store i8* null, i8** [[TMP151]], align 4 -// CHECK19-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9 -// CHECK19-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* -// CHECK19-NEXT: store i32 [[TMP91]], i32* [[TMP153]], align 4 -// CHECK19-NEXT: [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9 -// CHECK19-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32* -// CHECK19-NEXT: store i32 [[TMP91]], i32* [[TMP155]], align 4 -// CHECK19-NEXT: [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK19-NEXT: store i64 4, i64* [[TMP156]], align 4 -// CHECK19-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9 -// CHECK19-NEXT: store i8* null, i8** [[TMP157]], align 4 -// CHECK19-NEXT: [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0 -// CHECK19-NEXT: br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] -// CHECK19: omp_offload.failed27: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT28]] -// CHECK19: omp_offload.cont28: -// CHECK19-NEXT: br label [[OMP_IF_END30:%.*]] -// CHECK19: omp_if.else29: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END30]] -// CHECK19: omp_if.end30: -// CHECK19-NEXT: [[TMP163:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP164]]) -// CHECK19-NEXT: ret i32 [[TMP163]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK19-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 -// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 -// CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 -// CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 -// CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 -// CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 -// CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 -// CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) -// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] -// CHECK19-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] -// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK19: omp_offload.failed.i: -// CHECK19-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* -// CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21 -// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21 -// CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21 -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK19: .omp_outlined..1.exit: -// CHECK19-NEXT: ret i32 0 -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK19-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double -// CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float -// CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double -// CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 -// CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !22 -// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22 -// CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] -// CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 -// CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !22 -// CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22 -// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 -// CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 -// CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP8]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 -// CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK19-NEXT: store double* [[A]], double** [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 8, i64* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK19-NEXT: store i32 2, i32* [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK19-NEXT: store i32 2, i32* [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK19-NEXT: store i64 4, i64* [[TMP32]], align 4 -// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 -// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK19-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK19-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK19-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] -// CHECK19-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK19-NEXT: ret i32 [[ADD3]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK19-NEXT: store i8 [[TMP6]], i8* [[CONV1]], align 1 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4 -// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] -// CHECK19-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 -// CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK19-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK19-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add i32 [[TMP40]], 1 -// CHECK19-NEXT: [[TMP41:%.*]] = zext i32 [[ADD6]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) -// CHECK19-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 -// CHECK19-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP44]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK19: omp_if.then: -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_IF_END]] -// CHECK19: omp_if.end: -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP24]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK19-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double [[ADD4]], double* [[A]], align 4 -// CHECK19-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK19-NEXT: store double [[INC]], double* [[A5]], align 4 -// CHECK19-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] -// CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK19-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK19-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK19-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] -// CHECK19-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 -// CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK19-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK19-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] -// CHECK19-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 -// CHECK19-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] -// CHECK19-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 -// CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK19-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK19-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 -// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 -// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 -// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK19-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 -// CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 -// CHECK19-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 -// CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK19-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 -// CHECK19-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR4]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED19:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 -// CHECK20-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) -// CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* -// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 -// CHECK20-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) -// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* -// CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) -// CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* -// CHECK20-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) -// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* -// CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) -// CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 -// CHECK20-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]]) -// CHECK20-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] -// CHECK20-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* -// CHECK20-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 -// CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 -// CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* -// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 -// CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* -// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 -// CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP63]], align 4 -// CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 -// CHECK20-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 -// CHECK20-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 -// CHECK20-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* -// CHECK20-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 -// CHECK20-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 -// CHECK20-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 -// CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* -// CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 -// CHECK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP77]], align 4 -// CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 -// CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* -// CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 -// CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 -// CHECK20-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK20: omp_offload.failed16: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK20: omp_offload.cont17: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK20-NEXT: [[TMP88:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP88]], i32* [[A_CASTED19]], align 4 -// CHECK20-NEXT: [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4 -// CHECK20-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK20-NEXT: store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 -// CHECK20-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 -// CHECK20-NEXT: [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20 -// CHECK20-NEXT: br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]] -// CHECK20: omp_if.then22: -// CHECK20-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4 -// CHECK20-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 -// CHECK20-NEXT: [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]] -// CHECK20-NEXT: [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8 -// CHECK20-NEXT: [[TMP97:%.*]] = sext i32 [[TMP96]] to i64 -// CHECK20-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* -// CHECK20-NEXT: store i32 [[TMP89]], i32* [[TMP99]], align 4 -// CHECK20-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* -// CHECK20-NEXT: store i32 [[TMP89]], i32* [[TMP101]], align 4 -// CHECK20-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP102]], align 4 -// CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP103]], align 4 -// CHECK20-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4 -// CHECK20-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4 -// CHECK20-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 40, i64* [[TMP108]], align 4 -// CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP109]], align 4 -// CHECK20-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP111]], align 4 -// CHECK20-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP113]], align 4 -// CHECK20-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP114]], align 4 -// CHECK20-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP115]], align 4 -// CHECK20-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** -// CHECK20-NEXT: store float* [[VLA]], float** [[TMP117]], align 4 -// CHECK20-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float** -// CHECK20-NEXT: store float* [[VLA]], float** [[TMP119]], align 4 -// CHECK20-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK20-NEXT: store i64 [[TMP94]], i64* [[TMP120]], align 4 -// CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP121]], align 4 -// CHECK20-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4 -// CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]** -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 4 -// CHECK20-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK20-NEXT: store i64 400, i64* [[TMP126]], align 4 -// CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP127]], align 4 -// CHECK20-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32* -// CHECK20-NEXT: store i32 5, i32* [[TMP129]], align 4 -// CHECK20-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32* -// CHECK20-NEXT: store i32 5, i32* [[TMP131]], align 4 -// CHECK20-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK20-NEXT: store i64 4, i64* [[TMP132]], align 4 -// CHECK20-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5 -// CHECK20-NEXT: store i8* null, i8** [[TMP133]], align 4 -// CHECK20-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP135]], align 4 -// CHECK20-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP137]], align 4 -// CHECK20-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK20-NEXT: store i64 4, i64* [[TMP138]], align 4 -// CHECK20-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6 -// CHECK20-NEXT: store i8* null, i8** [[TMP139]], align 4 -// CHECK20-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double** -// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP141]], align 4 -// CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double** -// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP143]], align 4 -// CHECK20-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK20-NEXT: store i64 [[TMP97]], i64* [[TMP144]], align 4 -// CHECK20-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7 -// CHECK20-NEXT: store i8* null, i8** [[TMP145]], align 4 -// CHECK20-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8 -// CHECK20-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT** -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 4 -// CHECK20-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8 -// CHECK20-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT** -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 4 -// CHECK20-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK20-NEXT: store i64 12, i64* [[TMP150]], align 4 -// CHECK20-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8 -// CHECK20-NEXT: store i8* null, i8** [[TMP151]], align 4 -// CHECK20-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9 -// CHECK20-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* -// CHECK20-NEXT: store i32 [[TMP91]], i32* [[TMP153]], align 4 -// CHECK20-NEXT: [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9 -// CHECK20-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32* -// CHECK20-NEXT: store i32 [[TMP91]], i32* [[TMP155]], align 4 -// CHECK20-NEXT: [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK20-NEXT: store i64 4, i64* [[TMP156]], align 4 -// CHECK20-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9 -// CHECK20-NEXT: store i8* null, i8** [[TMP157]], align 4 -// CHECK20-NEXT: [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0 -// CHECK20-NEXT: br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] -// CHECK20: omp_offload.failed27: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT28]] -// CHECK20: omp_offload.cont28: -// CHECK20-NEXT: br label [[OMP_IF_END30:%.*]] -// CHECK20: omp_if.else29: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END30]] -// CHECK20: omp_if.end30: -// CHECK20-NEXT: [[TMP163:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP164]]) -// CHECK20-NEXT: ret i32 [[TMP163]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK20-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 -// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 -// CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 -// CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 -// CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 -// CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 -// CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 -// CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 -// CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 -// CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 -// CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 -// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 -// CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) -// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* -// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] -// CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] -// CHECK20-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] -// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] -// CHECK20: omp_offload.failed.i: -// CHECK20-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 -// CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* -// CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21 -// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21 -// CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21 -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] -// CHECK20: .omp_outlined..1.exit: -// CHECK20-NEXT: ret i32 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK20-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double -// CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float -// CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double -// CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 -// CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !22 -// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22 -// CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK20-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] -// CHECK20-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 -// CHECK20-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !22 -// CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22 -// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 -// CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 -// CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK20-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP8]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 -// CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK20-NEXT: store double* [[A]], double** [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 8, i64* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK20-NEXT: store i32 2, i32* [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK20-NEXT: store i32 2, i32* [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK20-NEXT: store i64 4, i64* [[TMP32]], align 4 -// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** -// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** -// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 -// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK20-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] -// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK20-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 -// CHECK20-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] -// CHECK20-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) -// CHECK20-NEXT: ret i32 [[ADD3]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK20-NEXT: store i8 [[TMP6]], i8* [[CONV1]], align 1 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4 -// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] -// CHECK20-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 -// CHECK20-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK20-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK20-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add i32 [[TMP40]], 1 -// CHECK20-NEXT: [[TMP41:%.*]] = zext i32 [[ADD6]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) -// CHECK20-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 -// CHECK20-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP44]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK20: omp_if.then: -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK20: omp_if.else: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_IF_END]] -// CHECK20: omp_if.end: -// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP24]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK20-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double [[ADD4]], double* [[A]], align 4 -// CHECK20-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK20-NEXT: store double [[INC]], double* [[A5]], align 4 -// CHECK20-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK20-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] -// CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK20-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK20-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK20-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] -// CHECK20-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 -// CHECK20-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK20-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK20-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] -// CHECK20-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 -// CHECK20-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] -// CHECK20-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 -// CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK20-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK20-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 -// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 -// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 -// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK20-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 -// CHECK20-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 -// CHECK20-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 -// CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK20-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 -// CHECK20-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR4]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK21-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK21-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK21-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK21-NEXT: br label [[FOR_COND4:%.*]] -// CHECK21: for.cond4: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK21-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK21-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK21: for.body6: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK21-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK21-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK21: for.end9: -// CHECK21-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11:%.*]] -// CHECK21: for.cond11: -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK21-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK21: for.body13: -// CHECK21-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK21-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK21-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK21-NEXT: br label [[FOR_INC16:%.*]] -// CHECK21: for.inc16: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK21-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end18: -// CHECK21-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20:%.*]] -// CHECK21: for.cond20: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK21-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK21: for.body22: -// CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK21-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK21-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK21-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK21-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK21-NEXT: br label [[FOR_INC27:%.*]] -// CHECK21: for.inc27: -// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK21-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK21: for.end29: -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK21-NEXT: br label [[FOR_COND32:%.*]] -// CHECK21: for.cond32: -// CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK21-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK21-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK21: for.body34: -// CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK21-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK21-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK21-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK21-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK21-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK21-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK21-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK21-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK21-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK21-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK21-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK21-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK21-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK21-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK21-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK21-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK21-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK21-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK21-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK21-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK21-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK21-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK21-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK21-NEXT: br label [[FOR_INC53:%.*]] -// CHECK21: for.inc53: -// CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK21-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK21-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK21-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK21: for.end55: -// CHECK21-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK21-NEXT: ret i32 [[TMP31]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP8]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK21-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK21-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK21-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK21-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK21-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK21-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK21-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK21-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK21-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK21-NEXT: ret i32 [[ADD10]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK21-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP8]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP5]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK22-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK22-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK22-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK22-NEXT: br label [[FOR_COND4:%.*]] -// CHECK22: for.cond4: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK22-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK22-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK22: for.body6: -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK22-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK22-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK22-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK22: for.end9: -// CHECK22-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11:%.*]] -// CHECK22: for.cond11: -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK22-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK22: for.body13: -// CHECK22-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK22-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK22-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK22-NEXT: br label [[FOR_INC16:%.*]] -// CHECK22: for.inc16: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK22-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK22: for.end18: -// CHECK22-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20:%.*]] -// CHECK22: for.cond20: -// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK22-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK22: for.body22: -// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK22-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK22-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK22-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK22-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK22-NEXT: br label [[FOR_INC27:%.*]] -// CHECK22: for.inc27: -// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK22-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK22: for.end29: -// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK22-NEXT: br label [[FOR_COND32:%.*]] -// CHECK22: for.cond32: -// CHECK22-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK22-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK22-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK22: for.body34: -// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK22-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK22-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK22-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK22-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK22-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK22-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK22-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK22-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK22-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK22-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK22-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK22-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK22-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK22-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK22-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK22-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK22-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK22-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK22-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK22-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK22-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK22-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK22-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK22-NEXT: br label [[FOR_INC53:%.*]] -// CHECK22: for.inc53: -// CHECK22-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK22-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK22-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK22-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK22: for.end55: -// CHECK22-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK22-NEXT: ret i32 [[TMP31]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP8]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK22-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK22-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK22-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK22-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK22-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK22-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK22-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK22-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK22-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK22-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK22-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK22-NEXT: ret i32 [[ADD10]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK22-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK22-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP8]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP5]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK23-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK23-NEXT: br label [[FOR_COND4:%.*]] -// CHECK23: for.cond4: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK23-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK23-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK23: for.body6: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: br label [[FOR_INC7:%.*]] -// CHECK23: for.inc7: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK23-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK23-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK23-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK23: for.end9: -// CHECK23-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK23-NEXT: br label [[FOR_COND11:%.*]] -// CHECK23: for.cond11: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK23-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK23-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK23: for.body13: -// CHECK23-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK23-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK23-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK23-NEXT: br label [[FOR_INC16:%.*]] -// CHECK23: for.inc16: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK23-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK23-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK23-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK23: for.end18: -// CHECK23-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK23-NEXT: br label [[FOR_COND20:%.*]] -// CHECK23: for.cond20: -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK23-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK23-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK23: for.body22: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK23-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK23-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK23-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK23-NEXT: br label [[FOR_INC27:%.*]] -// CHECK23: for.inc27: -// CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK23-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK23-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK23-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK23: for.end29: -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK23-NEXT: br label [[FOR_COND32:%.*]] -// CHECK23: for.cond32: -// CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK23-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK23-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK23: for.body34: -// CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK23-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK23-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK23-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK23-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK23-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK23-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK23-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK23-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK23-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK23-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK23-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK23-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK23-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK23-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK23-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK23-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK23-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK23-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK23-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK23-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK23-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK23-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK23-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK23-NEXT: br label [[FOR_INC53:%.*]] -// CHECK23: for.inc53: -// CHECK23-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK23-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK23-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK23-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK23: for.end55: -// CHECK23-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK23-NEXT: ret i32 [[TMP29]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP8]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK23-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK23-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK23-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK23-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK23-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK23-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK23-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK23-NEXT: ret i32 [[ADD10]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK23-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP8]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP5]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK24-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK24-NEXT: br label [[FOR_COND4:%.*]] -// CHECK24: for.cond4: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK24-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK24-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK24: for.body6: -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: br label [[FOR_INC7:%.*]] -// CHECK24: for.inc7: -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK24-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK24-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK24-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK24: for.end9: -// CHECK24-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK24-NEXT: br label [[FOR_COND11:%.*]] -// CHECK24: for.cond11: -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK24-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK24-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK24: for.body13: -// CHECK24-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK24-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK24-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK24-NEXT: br label [[FOR_INC16:%.*]] -// CHECK24: for.inc16: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK24-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK24-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK24-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK24: for.end18: -// CHECK24-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK24-NEXT: br label [[FOR_COND20:%.*]] -// CHECK24: for.cond20: -// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK24-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK24-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK24: for.body22: -// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK24-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK24-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK24-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK24-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK24-NEXT: br label [[FOR_INC27:%.*]] -// CHECK24: for.inc27: -// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK24-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK24-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK24-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK24: for.end29: -// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK24-NEXT: br label [[FOR_COND32:%.*]] -// CHECK24: for.cond32: -// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK24-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK24-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK24: for.body34: -// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK24-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK24-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK24-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK24-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK24-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK24-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK24-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK24-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK24-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK24-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK24-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK24-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK24-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK24-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK24-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK24-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK24-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK24-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK24-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK24-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK24-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK24-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK24-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK24-NEXT: br label [[FOR_INC53:%.*]] -// CHECK24: for.inc53: -// CHECK24-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK24-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK24-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK24-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK24: for.end55: -// CHECK24-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK24-NEXT: ret i32 [[TMP29]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP8]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK24-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK24-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK24-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK24-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK24-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK24-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK24-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK24-NEXT: ret i32 [[ADD10]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK24-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP8]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP5]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK25-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK25-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK25-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 -// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK25: omp.dispatch.cond: -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK25: omp.dispatch.body: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 -// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK25-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double -// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double -// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK25-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK25-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK25-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 -// CHECK25-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK25-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 -// CHECK25-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK25-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] -// CHECK25-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK25-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 -// CHECK25-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK25-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 -// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11 -// CHECK25-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK25-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11 -// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11 -// CHECK25-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK25-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK25-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK25-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK25-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK25: omp.dispatch.inc: -// CHECK25-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK25-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK25-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK25: omp.dispatch.end: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK25-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 -// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 -// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK25-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 -// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] -// CHECK25-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 -// CHECK25-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK25-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 -// CHECK25-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK25: omp.precond.then: -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK25-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK25-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] -// CHECK25-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 -// CHECK25-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] -// CHECK25-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 -// CHECK25-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK25-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 -// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK25-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK25-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 -// CHECK25-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 -// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 -// CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 -// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 -// CHECK25-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 -// CHECK25-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 -// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 -// CHECK25-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 -// CHECK25-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK25-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 -// CHECK25-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK25-NEXT: br label [[OMP_PRECOND_END]] -// CHECK25: omp.precond.end: -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK25-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double [[ADD5]], double* [[A]], align 8 -// CHECK25-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 -// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK25-NEXT: store double [[INC]], double* [[A6]], align 8 -// CHECK25-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 -// CHECK25-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] -// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK25-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK25-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK25-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK26-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK26-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 -// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK26-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 -// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 -// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 -// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK26: omp.dispatch.cond: -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK26: omp.dispatch.body: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 -// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK26-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double -// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 -// CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double -// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK26-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK26-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 -// CHECK26-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 -// CHECK26-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK26-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11 -// CHECK26-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK26-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] -// CHECK26-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK26-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 -// CHECK26-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK26-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11 -// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11 -// CHECK26-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK26-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11 -// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11 -// CHECK26-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK26-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK26-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK26-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK26-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK26: omp.dispatch.inc: -// CHECK26-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK26-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK26-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK26: omp.dispatch.end: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK26-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 -// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 -// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK26-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 -// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] -// CHECK26-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 -// CHECK26-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK26-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 -// CHECK26-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK26: omp.precond.then: -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK26-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK26-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] -// CHECK26-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 -// CHECK26-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] -// CHECK26-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 -// CHECK26-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK26-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 -// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK26-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK26-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 -// CHECK26-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 -// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 -// CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 -// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 -// CHECK26-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 -// CHECK26-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 -// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 -// CHECK26-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 -// CHECK26-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK26-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 -// CHECK26-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK26-NEXT: br label [[OMP_PRECOND_END]] -// CHECK26: omp.precond.end: -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK26-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double [[ADD5]], double* [[A]], align 8 -// CHECK26-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 -// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK26-NEXT: store double [[INC]], double* [[A6]], align 8 -// CHECK26-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 -// CHECK26-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] -// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK26-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK26-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 -// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK26-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK27-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK27-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK27-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK27-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK27: omp.dispatch.cond: -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK27: omp.dispatch.body: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK27-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK27-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double -// CHECK27-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK27-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float -// CHECK27-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK27-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double -// CHECK27-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 -// CHECK27-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK27-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 -// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 -// CHECK27-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK27-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] -// CHECK27-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 -// CHECK27-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 -// CHECK27-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK27-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 -// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK27-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK27-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 -// CHECK27-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 -// CHECK27-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK27-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK27: omp.dispatch.inc: -// CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK27-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK27-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK27: omp.dispatch.end: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK27-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK27-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] -// CHECK27-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 -// CHECK27-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK27-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 -// CHECK27-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK27: omp.precond.then: -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK27-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK27-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] -// CHECK27-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 -// CHECK27-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] -// CHECK27-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 -// CHECK27-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK27-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 -// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK27-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 -// CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 -// CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 -// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 -// CHECK27-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK27-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 -// CHECK27-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 -// CHECK27-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 -// CHECK27-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK27-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 -// CHECK27-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK27-NEXT: br label [[OMP_PRECOND_END]] -// CHECK27: omp.precond.end: -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK27-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK27-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double [[ADD4]], double* [[A]], align 4 -// CHECK27-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 -// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK27-NEXT: store double [[INC]], double* [[A5]], align 4 -// CHECK27-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK27-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] -// CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK27-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK27-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK27-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK28-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK28-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK28-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) -// CHECK28-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK28: omp.dispatch.cond: -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK28: omp.dispatch.body: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK28-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK28-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double -// CHECK28-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 -// CHECK28-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float -// CHECK28-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 -// CHECK28-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double -// CHECK28-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 -// CHECK28-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK28-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 -// CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 -// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 -// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12 -// CHECK28-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK28-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] -// CHECK28-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 -// CHECK28-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 -// CHECK28-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 -// CHECK28-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12 -// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 -// CHECK28-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 -// CHECK28-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 -// CHECK28-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 -// CHECK28-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 -// CHECK28-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK28: omp.dispatch.inc: -// CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK28-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK28-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK28: omp.dispatch.end: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK28-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK28-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] -// CHECK28-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 -// CHECK28-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 -// CHECK28-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 -// CHECK28-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK28: omp.precond.then: -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK28-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK28-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] -// CHECK28-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 -// CHECK28-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] -// CHECK28-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 -// CHECK28-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK28-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 -// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK28-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 -// CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 -// CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 -// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 -// CHECK28-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 -// CHECK28-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 -// CHECK28-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 -// CHECK28-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 -// CHECK28-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK28-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 -// CHECK28-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK28-NEXT: br label [[OMP_PRECOND_END]] -// CHECK28: omp.precond.end: -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK28-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK28-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double [[ADD4]], double* [[A]], align 4 -// CHECK28-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 -// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK28-NEXT: store double [[INC]], double* [[A5]], align 4 -// CHECK28-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK28-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] -// CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK28-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK28-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 -// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK29-NEXT: br label [[FOR_COND4:%.*]] -// CHECK29: for.cond4: -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK29-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK29-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK29: for.body6: -// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: br label [[FOR_INC7:%.*]] -// CHECK29: for.inc7: -// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK29-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK29-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK29-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK29: for.end9: -// CHECK29-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK29-NEXT: br label [[FOR_COND11:%.*]] -// CHECK29: for.cond11: -// CHECK29-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK29-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK29-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK29: for.body13: -// CHECK29-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK29-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK29-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK29-NEXT: br label [[FOR_INC16:%.*]] -// CHECK29: for.inc16: -// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK29-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK29-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK29-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK29: for.end18: -// CHECK29-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK29-NEXT: br label [[FOR_COND20:%.*]] -// CHECK29: for.cond20: -// CHECK29-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK29-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK29-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK29: for.body22: -// CHECK29-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK29-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK29-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK29-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK29-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK29-NEXT: br label [[FOR_INC27:%.*]] -// CHECK29: for.inc27: -// CHECK29-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK29-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK29-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK29-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK29: for.end29: -// CHECK29-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK29-NEXT: br label [[FOR_COND32:%.*]] -// CHECK29: for.cond32: -// CHECK29-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK29-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK29-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK29: for.body34: -// CHECK29-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK29-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK29-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK29-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK29-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK29-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK29-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK29-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK29-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK29-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK29-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK29-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK29-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK29-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK29-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK29-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK29-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK29-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK29-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK29-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK29-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK29-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK29-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK29-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK29-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK29-NEXT: br label [[FOR_INC53:%.*]] -// CHECK29: for.inc53: -// CHECK29-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK29-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK29-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK29-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK29: for.end55: -// CHECK29-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK29-NEXT: ret i32 [[TMP31]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP8]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK29-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK29-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK29-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK29-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK29-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK29-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK29-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK29-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK29-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK29-NEXT: ret i32 [[ADD10]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK29-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK29-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP8]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP5]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK30-NEXT: br label [[FOR_COND4:%.*]] -// CHECK30: for.cond4: -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK30-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK30-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK30: for.body6: -// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: br label [[FOR_INC7:%.*]] -// CHECK30: for.inc7: -// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK30-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK30-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK30-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK30: for.end9: -// CHECK30-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK30-NEXT: br label [[FOR_COND11:%.*]] -// CHECK30: for.cond11: -// CHECK30-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK30-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK30-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK30: for.body13: -// CHECK30-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK30-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK30-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK30-NEXT: br label [[FOR_INC16:%.*]] -// CHECK30: for.inc16: -// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK30-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK30-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK30-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK30: for.end18: -// CHECK30-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK30-NEXT: br label [[FOR_COND20:%.*]] -// CHECK30: for.cond20: -// CHECK30-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK30-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK30-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK30: for.body22: -// CHECK30-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK30-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK30-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK30-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK30-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK30-NEXT: br label [[FOR_INC27:%.*]] -// CHECK30: for.inc27: -// CHECK30-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK30-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK30-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK30-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK30: for.end29: -// CHECK30-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK30-NEXT: br label [[FOR_COND32:%.*]] -// CHECK30: for.cond32: -// CHECK30-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK30-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK30-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK30: for.body34: -// CHECK30-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK30-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK30-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK30-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK30-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK30-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK30-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK30-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK30-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK30-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK30-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK30-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK30-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK30-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK30-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK30-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK30-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK30-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK30-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK30-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK30-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK30-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK30-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK30-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK30-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK30-NEXT: br label [[FOR_INC53:%.*]] -// CHECK30: for.inc53: -// CHECK30-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK30-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK30-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK30-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK30: for.end55: -// CHECK30-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK30-NEXT: ret i32 [[TMP31]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP8]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK30-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK30-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK30-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK30-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK30-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK30-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK30-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK30-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK30-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK30-NEXT: ret i32 [[ADD10]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK30-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK30-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP8]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP5]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK31-NEXT: br label [[FOR_COND4:%.*]] -// CHECK31: for.cond4: -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK31-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK31-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK31: for.body6: -// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: br label [[FOR_INC7:%.*]] -// CHECK31: for.inc7: -// CHECK31-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK31-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK31-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK31-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK31: for.end9: -// CHECK31-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK31-NEXT: br label [[FOR_COND11:%.*]] -// CHECK31: for.cond11: -// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK31-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK31-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK31: for.body13: -// CHECK31-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK31-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK31-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK31-NEXT: br label [[FOR_INC16:%.*]] -// CHECK31: for.inc16: -// CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK31-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK31-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK31-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK31: for.end18: -// CHECK31-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK31-NEXT: br label [[FOR_COND20:%.*]] -// CHECK31: for.cond20: -// CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK31-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK31-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK31: for.body22: -// CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK31-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK31-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK31-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK31-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK31-NEXT: br label [[FOR_INC27:%.*]] -// CHECK31: for.inc27: -// CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK31-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK31-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK31-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK31: for.end29: -// CHECK31-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK31-NEXT: br label [[FOR_COND32:%.*]] -// CHECK31: for.cond32: -// CHECK31-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK31-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK31-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK31: for.body34: -// CHECK31-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK31-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK31-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK31-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK31-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK31-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK31-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK31-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK31-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK31-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK31-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK31-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK31-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK31-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK31-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK31-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK31-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK31-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK31-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK31-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK31-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK31-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK31-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK31-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK31-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK31-NEXT: br label [[FOR_INC53:%.*]] -// CHECK31: for.inc53: -// CHECK31-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK31-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK31-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK31-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK31: for.end55: -// CHECK31-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK31-NEXT: ret i32 [[TMP29]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK31-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK31-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK31-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK31-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK31-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK31-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK31-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK31-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK31-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK31-NEXT: ret i32 [[ADD10]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK31-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK31-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP5]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK32-NEXT: br label [[FOR_COND4:%.*]] -// CHECK32: for.cond4: -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK32-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK32-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK32: for.body6: -// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: br label [[FOR_INC7:%.*]] -// CHECK32: for.inc7: -// CHECK32-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK32-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK32-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK32-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK32: for.end9: -// CHECK32-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK32-NEXT: br label [[FOR_COND11:%.*]] -// CHECK32: for.cond11: -// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK32-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK32-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK32: for.body13: -// CHECK32-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK32-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK32-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK32-NEXT: br label [[FOR_INC16:%.*]] -// CHECK32: for.inc16: -// CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK32-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK32-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK32-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK32: for.end18: -// CHECK32-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK32-NEXT: br label [[FOR_COND20:%.*]] -// CHECK32: for.cond20: -// CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK32-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK32-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK32: for.body22: -// CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK32-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK32-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK32-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK32-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK32-NEXT: br label [[FOR_INC27:%.*]] -// CHECK32: for.inc27: -// CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK32-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK32-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK32-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK32: for.end29: -// CHECK32-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK32-NEXT: br label [[FOR_COND32:%.*]] -// CHECK32: for.cond32: -// CHECK32-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK32-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK32-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK32: for.body34: -// CHECK32-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK32-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK32-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK32-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK32-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK32-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK32-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK32-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK32-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK32-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK32-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK32-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK32-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK32-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK32-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK32-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK32-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK32-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK32-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK32-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK32-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK32-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK32-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK32-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK32-NEXT: br label [[FOR_INC53:%.*]] -// CHECK32: for.inc53: -// CHECK32-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK32-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK32-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK32-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK32: for.end55: -// CHECK32-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK32-NEXT: ret i32 [[TMP29]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK32-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK32-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK32-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK32-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK32-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK32-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK32-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK32-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK32-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK32-NEXT: ret i32 [[ADD10]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK32-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK32-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP5]] +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK16-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK16-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -46,19 +46,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -666,2460 +666,1752 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK5-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK5-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() +// CHECK5-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK5-NEXT: store i64 4, i64* [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK5-NEXT: store i64 8, i64* [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK5-NEXT: store i64 8, i64* [[TMP34]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP35]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK5-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 +// CHECK5-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 +// CHECK5-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK5-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] +// CHECK5-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK5-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK5-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK5-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 +// CHECK5-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) +// CHECK5-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP54]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J14:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK5-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 +// CHECK5-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] +// CHECK5-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK5-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body: // CHECK5-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: land.lhs.true: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK5-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 +// CHECK5-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 +// CHECK5-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] +// CHECK5-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 +// CHECK5-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] +// CHECK5-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] +// CHECK5-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK5-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 +// CHECK5-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 +// CHECK5-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] +// CHECK5-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 +// CHECK5-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK5-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK5-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] +// CHECK5-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 +// CHECK5-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] +// CHECK5-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] +// CHECK5-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 +// CHECK5-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] +// CHECK5-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK5-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK5-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4 +// CHECK5-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 +// CHECK5-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK5-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) +// CHECK5-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK5-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 +// CHECK5-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] +// CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 +// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK6-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK6-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() +// CHECK6-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK6-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK6-NEXT: store i64 4, i64* [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK6-NEXT: store i64 8, i64* [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK6-NEXT: store i64 8, i64* [[TMP34]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP35]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK6-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 +// CHECK6-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 +// CHECK6-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK6-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] +// CHECK6-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK6-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK6-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK6-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 +// CHECK6-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) +// CHECK6-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP54]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J14:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK6-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 +// CHECK6-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] +// CHECK6-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK6-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body: // CHECK6-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: land.lhs.true: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK6-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 +// CHECK6-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 +// CHECK6-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] +// CHECK6-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 +// CHECK6-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] +// CHECK6-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] +// CHECK6-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK6-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 +// CHECK6-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 +// CHECK6-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] +// CHECK6-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 +// CHECK6-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK6-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK6-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] +// CHECK6-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 +// CHECK6-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] +// CHECK6-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] +// CHECK6-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 +// CHECK6-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] +// CHECK6-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK6-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK6-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4 +// CHECK6-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 +// CHECK6-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK6-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) +// CHECK6-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK6-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 +// CHECK6-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] +// CHECK6-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 +// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@main +// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK7-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK7-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 +// CHECK7-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK7-NEXT: store i64 4, i64* [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK7-NEXT: store i64 4, i64* [[TMP33]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 +// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 +// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK7-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 +// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK7-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 +// CHECK7-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] +// CHECK7-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK7-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 +// CHECK7-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) +// CHECK7-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP53]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK7-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK7-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body: // CHECK7-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: land.lhs.true: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 +// CHECK7-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK7-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// CHECK7-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// CHECK7-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] +// CHECK7-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// CHECK7-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK7-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 +// CHECK7-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// CHECK7-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// CHECK7-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// CHECK7-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK7-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK7-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// CHECK7-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// CHECK7-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// CHECK7-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] +// CHECK7-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// CHECK7-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// CHECK7-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// CHECK7-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4 +// CHECK7-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 +// CHECK7-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK7-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 +// CHECK7-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] +// CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@main +// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK8-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK8-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 +// CHECK8-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK8-NEXT: store i64 4, i64* [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK8-NEXT: store i64 4, i64* [[TMP33]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 +// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 +// CHECK8-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK8-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 +// CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK8-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK8-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 +// CHECK8-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] +// CHECK8-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK8-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 +// CHECK8-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) +// CHECK8-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP53]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK8-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK8-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK8-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body: // CHECK8-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK9-NEXT: store i64 4, i64* [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK9-NEXT: store i64 8, i64* [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK9-NEXT: store i64 8, i64* [[TMP34]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 -// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 -// CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] -// CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK9-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK9-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 -// CHECK9-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) -// CHECK9-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP54]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 -// CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] -// CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: land.lhs.true: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 -// CHECK9-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 -// CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] -// CHECK9-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 -// CHECK9-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] -// CHECK9-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] -// CHECK9-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK9-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 -// CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 -// CHECK9-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] -// CHECK9-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 -// CHECK9-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 -// CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] -// CHECK9-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 -// CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] -// CHECK9-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] -// CHECK9-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 -// CHECK9-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] -// CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK9-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK9-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4 -// CHECK9-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK9-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] -// CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK10-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK10-NEXT: store i64 4, i64* [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK10-NEXT: store i64 8, i64* [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 -// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK10-NEXT: store i64 8, i64* [[TMP34]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK10-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 -// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 -// CHECK10-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 -// CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] -// CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK10-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK10-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 -// CHECK10-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) -// CHECK10-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP54]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 -// CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] -// CHECK10-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK10-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: land.lhs.true: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK10-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 -// CHECK10-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 -// CHECK10-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] -// CHECK10-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 -// CHECK10-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] -// CHECK10-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] -// CHECK10-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK10-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 -// CHECK10-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 -// CHECK10-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] -// CHECK10-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 -// CHECK10-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 -// CHECK10-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] -// CHECK10-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 -// CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] -// CHECK10-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] -// CHECK10-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 -// CHECK10-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] -// CHECK10-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK10-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK10-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4 -// CHECK10-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK10-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] -// CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 -// CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK11-NEXT: store i64 4, i64* [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK11-NEXT: store i64 4, i64* [[TMP33]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP34]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 -// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 -// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 -// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 -// CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] -// CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK11-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 -// CHECK11-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) -// CHECK11-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP53]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: land.lhs.true: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 -// CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 -// CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] -// CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 -// CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] -// CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] -// CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 -// CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 -// CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] -// CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 -// CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 -// CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 -// CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] -// CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 -// CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] -// CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] -// CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 -// CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] -// CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4 -// CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) -// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] -// CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 -// CHECK12-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK12-NEXT: store i64 4, i64* [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK12-NEXT: store i64 4, i64* [[TMP33]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP34]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 -// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 -// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK12-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 -// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK12-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 -// CHECK12-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] -// CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK12-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 -// CHECK12-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) -// CHECK12-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP53]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: land.lhs.true: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 -// CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 -// CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] -// CHECK12-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 -// CHECK12-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] -// CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] -// CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 -// CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 -// CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] -// CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 -// CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 -// CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 -// CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] -// CHECK12-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 -// CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] -// CHECK12-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] -// CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 -// CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] -// CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4 -// CHECK12-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) -// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] -// CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP17]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP17]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP15]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP15]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: land.lhs.true: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 +// CHECK8-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK8-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// CHECK8-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// CHECK8-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] +// CHECK8-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// CHECK8-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK8-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 +// CHECK8-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// CHECK8-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// CHECK8-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// CHECK8-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK8-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK8-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// CHECK8-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// CHECK8-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// CHECK8-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] +// CHECK8-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// CHECK8-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// CHECK8-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// CHECK8-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4 +// CHECK8-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 +// CHECK8-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK8-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 +// CHECK8-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK8-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] +// CHECK8-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 +// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -55,19 +55,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -1504,4670 +1504,3742 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 +// CHECK5-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK5-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK5-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK5-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK5-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK5-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK5-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK5-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP60]]) +// CHECK5-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK5-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK5: omp_offload.failed16: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK5: omp_offload.cont17: +// CHECK5-NEXT: [[TMP63:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK5-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* +// CHECK5-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 +// CHECK5-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 +// CHECK5-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK5-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 +// CHECK5-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* +// CHECK5-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 +// CHECK5-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* +// CHECK5-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 +// CHECK5-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP73]], align 8 +// CHECK5-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP74]], align 8 +// CHECK5-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 +// CHECK5-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 +// CHECK5-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP79]], align 8 +// CHECK5-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP80]], align 8 +// CHECK5-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 +// CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 +// CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 +// CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP86]], align 8 +// CHECK5-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* +// CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 +// CHECK5-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* +// CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 +// CHECK5-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 +// CHECK5-NEXT: store i64 4, i64* [[TMP91]], align 8 +// CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP92]], align 8 +// CHECK5-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK5-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK5-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 +// CHECK5-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK5-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 +// CHECK5-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK5-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK5-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 +// CHECK5-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP99]]) +// CHECK5-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 +// CHECK5-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK5: omp_offload.failed33: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK5: omp_offload.cont34: +// CHECK5-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) +// CHECK5-NEXT: [[TMP104:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP104]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK5-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK5-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK5-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK5: omp_offload.failed5: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK5: omp_offload.cont6: +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK5-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK5: omp_offload.failed11: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK5: omp_offload.cont12: +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3:%.*]] -// CHECK5: for.cond3: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK5: for.body5: -// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK5-NEXT: br label [[FOR_INC9:%.*]] -// CHECK5: for.inc9: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end11: -// CHECK5-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13:%.*]] -// CHECK5: for.cond13: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK5-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK5: for.body15: -// CHECK5-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK5-NEXT: br label [[FOR_INC19:%.*]] -// CHECK5: for.inc19: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end21: -// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void +// // +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void // -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 +// CHECK6-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK6-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK6-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK6-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK6-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK6-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK6-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK6-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK6-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK6-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK6-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK6-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK6-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK6-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK6-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK6-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK6-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK6-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP60]]) +// CHECK6-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK6-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK6: omp_offload.failed16: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK6: omp_offload.cont17: +// CHECK6-NEXT: [[TMP63:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK6-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* +// CHECK6-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 +// CHECK6-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 +// CHECK6-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK6-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 +// CHECK6-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* +// CHECK6-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 +// CHECK6-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* +// CHECK6-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 +// CHECK6-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP73]], align 8 +// CHECK6-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP74]], align 8 +// CHECK6-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 +// CHECK6-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 +// CHECK6-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP79]], align 8 +// CHECK6-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP80]], align 8 +// CHECK6-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 +// CHECK6-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 +// CHECK6-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 +// CHECK6-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP86]], align 8 +// CHECK6-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* +// CHECK6-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 +// CHECK6-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* +// CHECK6-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 +// CHECK6-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 +// CHECK6-NEXT: store i64 4, i64* [[TMP91]], align 8 +// CHECK6-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP92]], align 8 +// CHECK6-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK6-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK6-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 +// CHECK6-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK6-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 +// CHECK6-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK6-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK6-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 +// CHECK6-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP99]]) +// CHECK6-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 +// CHECK6-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK6: omp_offload.failed33: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK6: omp_offload.cont34: +// CHECK6-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) +// CHECK6-NEXT: [[TMP104:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP104]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] // CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC9:%.*]] -// CHECK6: for.inc9: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end11: -// CHECK6-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13:%.*]] -// CHECK6: for.cond13: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK6-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK6: for.body15: -// CHECK6-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK6-NEXT: br label [[FOR_INC19:%.*]] -// CHECK6: for.inc19: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end21: -// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK6-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK6-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK6-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK6: omp_offload.failed5: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK6: omp_offload.cont6: +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK6-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK6: omp_offload.failed11: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK6: omp_offload.cont12: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@main +// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 +// CHECK7-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK7-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK7-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK7-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK7-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK7-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK7-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP61]]) +// CHECK7-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK7-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK7: omp_offload.failed15: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK7: omp_offload.cont16: +// CHECK7-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK7-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 +// CHECK7-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 +// CHECK7-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK7-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 +// CHECK7-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* +// CHECK7-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 +// CHECK7-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK7-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 +// CHECK7-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP75]], align 4 +// CHECK7-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP76]], align 4 +// CHECK7-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 +// CHECK7-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 +// CHECK7-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP81]], align 4 +// CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 +// CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 +// CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 +// CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP88]], align 4 +// CHECK7-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* +// CHECK7-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 +// CHECK7-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* +// CHECK7-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 +// CHECK7-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 +// CHECK7-NEXT: store i64 4, i64* [[TMP93]], align 4 +// CHECK7-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP94]], align 4 +// CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK7-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK7-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 +// CHECK7-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// CHECK7-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 +// CHECK7-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK7-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK7-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 +// CHECK7-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP101]]) +// CHECK7-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 +// CHECK7-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK7: omp_offload.failed30: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK7: omp_offload.cont31: +// CHECK7-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) +// CHECK7-NEXT: [[TMP106:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP106]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP16]] // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC8:%.*]] -// CHECK7: for.inc8: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end10: -// CHECK7-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12:%.*]] -// CHECK7: for.cond12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK7-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK7: for.body14: -// CHECK7-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK7-NEXT: br label [[FOR_INC17:%.*]] -// CHECK7: for.inc17: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end19: -// CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP16]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP19]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK7-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK7-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK7: omp_offload.failed5: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK7: omp_offload.cont6: +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK7-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK7: omp_offload.failed11: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK7: omp_offload.cont12: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@main +// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 +// CHECK8-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK8-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK8-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK8-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK8-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK8-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK8-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK8-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK8-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK8-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK8-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK8-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK8-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK8-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK8-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK8-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK8-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK8-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP61]]) +// CHECK8-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK8-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK8: omp_offload.failed15: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK8: omp_offload.cont16: +// CHECK8-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK8-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 +// CHECK8-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 +// CHECK8-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK8-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 +// CHECK8-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* +// CHECK8-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 +// CHECK8-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK8-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 +// CHECK8-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP75]], align 4 +// CHECK8-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP76]], align 4 +// CHECK8-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 +// CHECK8-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 +// CHECK8-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP81]], align 4 +// CHECK8-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK8-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 +// CHECK8-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 +// CHECK8-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 +// CHECK8-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP88]], align 4 +// CHECK8-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* +// CHECK8-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 +// CHECK8-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* +// CHECK8-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 +// CHECK8-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 +// CHECK8-NEXT: store i64 4, i64* [[TMP93]], align 4 +// CHECK8-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP94]], align 4 +// CHECK8-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK8-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK8-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 +// CHECK8-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// CHECK8-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 +// CHECK8-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK8-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK8-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 +// CHECK8-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP101]]) +// CHECK8-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 +// CHECK8-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK8: omp_offload.failed30: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK8: omp_offload.cont31: +// CHECK8-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) +// CHECK8-NEXT: [[TMP106:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP106]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP16]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP16]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP19]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK8-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK8-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK8: omp_offload.failed5: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK8: omp_offload.cont6: +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK8-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK8: omp_offload.failed11: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK8: omp_offload.cont12: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] // CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC8:%.*]] -// CHECK8: for.inc8: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end10: -// CHECK8-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12:%.*]] -// CHECK8: for.cond12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK8-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK8: for.body14: -// CHECK8-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK8-NEXT: br label [[FOR_INC17:%.*]] -// CHECK8: for.inc17: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end19: -// CHECK8-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK9-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 -// CHECK9-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK9-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK9-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK9-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK9-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP60]]) -// CHECK9-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK9-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK9: omp_offload.failed16: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK9: omp_offload.cont17: -// CHECK9-NEXT: [[TMP63:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK9-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* -// CHECK9-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 -// CHECK9-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 -// CHECK9-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK9-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 -// CHECK9-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* -// CHECK9-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 -// CHECK9-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* -// CHECK9-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 -// CHECK9-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP73]], align 8 -// CHECK9-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP74]], align 8 -// CHECK9-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 -// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 -// CHECK9-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP79]], align 8 -// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP80]], align 8 -// CHECK9-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 -// CHECK9-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 -// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 -// CHECK9-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP86]], align 8 -// CHECK9-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* -// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 -// CHECK9-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* -// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 -// CHECK9-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 -// CHECK9-NEXT: store i64 4, i64* [[TMP91]], align 8 -// CHECK9-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK9-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK9-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 -// CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK9-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 -// CHECK9-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK9-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK9-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 -// CHECK9-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP99]]) -// CHECK9-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 -// CHECK9-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] -// CHECK9: omp_offload.failed33: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT34]] -// CHECK9: omp_offload.cont34: -// CHECK9-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) -// CHECK9-NEXT: [[TMP104:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP104]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK9: omp.dispatch.cond: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK9: omp.dispatch.body: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK9: omp.dispatch.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK9: omp.dispatch.end: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK9: omp_offload.failed5: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK9: omp_offload.cont6: -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK9-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK9: omp_offload.failed11: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK9: omp_offload.cont12: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK9: omp.dispatch.cond: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK9: omp.dispatch.body: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK9: omp.dispatch.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK9: omp.dispatch.end: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK10-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 -// CHECK10-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK10-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK10-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK10-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK10-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP60]]) -// CHECK10-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK10-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK10: omp_offload.failed16: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK10: omp_offload.cont17: -// CHECK10-NEXT: [[TMP63:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK10-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* -// CHECK10-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 -// CHECK10-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 -// CHECK10-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK10-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 -// CHECK10-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* -// CHECK10-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 -// CHECK10-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* -// CHECK10-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 -// CHECK10-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP73]], align 8 -// CHECK10-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP74]], align 8 -// CHECK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 -// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 -// CHECK10-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP79]], align 8 -// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP80]], align 8 -// CHECK10-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 -// CHECK10-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 -// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 -// CHECK10-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP86]], align 8 -// CHECK10-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* -// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 -// CHECK10-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* -// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 -// CHECK10-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 -// CHECK10-NEXT: store i64 4, i64* [[TMP91]], align 8 -// CHECK10-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK10-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK10-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 -// CHECK10-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK10-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 -// CHECK10-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK10-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK10-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 -// CHECK10-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP99]]) -// CHECK10-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 -// CHECK10-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] -// CHECK10: omp_offload.failed33: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT34]] -// CHECK10: omp_offload.cont34: -// CHECK10-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) -// CHECK10-NEXT: [[TMP104:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP104]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK10: omp.dispatch.cond: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK10: omp.dispatch.body: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK10: omp.dispatch.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK10: omp.dispatch.end: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK10-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK10: omp_offload.failed5: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK10: omp_offload.cont6: -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK10-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK10: omp_offload.failed11: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK10: omp_offload.cont12: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK10: omp.dispatch.cond: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK10: omp.dispatch.body: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK10: omp.dispatch.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK10: omp.dispatch.end: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK11-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 -// CHECK11-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK11-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK11-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK11-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK11-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK11-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP61]]) -// CHECK11-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK11-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK11: omp_offload.failed15: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK11: omp_offload.cont16: -// CHECK11-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK11-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 -// CHECK11-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 -// CHECK11-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK11-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 -// CHECK11-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* -// CHECK11-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 -// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK11-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 -// CHECK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP75]], align 4 -// CHECK11-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP76]], align 4 -// CHECK11-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 -// CHECK11-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 -// CHECK11-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP81]], align 4 -// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK11-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 -// CHECK11-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 -// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 -// CHECK11-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP88]], align 4 -// CHECK11-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* -// CHECK11-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 -// CHECK11-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* -// CHECK11-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 -// CHECK11-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 -// CHECK11-NEXT: store i64 4, i64* [[TMP93]], align 4 -// CHECK11-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP94]], align 4 -// CHECK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK11-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK11-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 -// CHECK11-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// CHECK11-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 -// CHECK11-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK11-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK11-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 -// CHECK11-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP101]]) -// CHECK11-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 -// CHECK11-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK11: omp_offload.failed30: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK11: omp_offload.cont31: -// CHECK11-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) -// CHECK11-NEXT: [[TMP106:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP106]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP16]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP16]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK11: omp.dispatch.cond: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK11: omp.dispatch.body: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP19]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK11: omp.dispatch.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK11: omp.dispatch.end: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK11-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK11: omp_offload.failed5: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK11: omp_offload.cont6: -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK11-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK11: omp_offload.failed11: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK11: omp_offload.cont12: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK11: omp.dispatch.cond: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK11: omp.dispatch.body: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK11: omp.dispatch.inc: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK11: omp.dispatch.end: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 -// CHECK12-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK12-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK12-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK12-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK12-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK12-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK12-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP61]]) -// CHECK12-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK12-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK12: omp_offload.failed15: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK12: omp_offload.cont16: -// CHECK12-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK12-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 -// CHECK12-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 -// CHECK12-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK12-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 -// CHECK12-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* -// CHECK12-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 -// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK12-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 -// CHECK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP75]], align 4 -// CHECK12-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP76]], align 4 -// CHECK12-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 -// CHECK12-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 -// CHECK12-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP81]], align 4 -// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK12-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 -// CHECK12-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 -// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 -// CHECK12-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP88]], align 4 -// CHECK12-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* -// CHECK12-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 -// CHECK12-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* -// CHECK12-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 -// CHECK12-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 -// CHECK12-NEXT: store i64 4, i64* [[TMP93]], align 4 -// CHECK12-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP94]], align 4 -// CHECK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK12-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK12-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 -// CHECK12-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// CHECK12-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 -// CHECK12-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK12-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK12-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 -// CHECK12-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP101]]) -// CHECK12-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 -// CHECK12-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK12: omp_offload.failed30: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK12: omp_offload.cont31: -// CHECK12-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) -// CHECK12-NEXT: [[TMP106:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP106]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP16]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP16]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK12: omp.dispatch.cond: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK12: omp.dispatch.body: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP19]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK12-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK12: omp_offload.failed5: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK12: omp_offload.cont6: -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK12-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK12: omp_offload.failed11: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK12: omp_offload.cont12: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK12: omp.dispatch.cond: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK12: omp.dispatch.body: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP17]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP17]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: ret i32 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -3295,6 +3295,28 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: @@ -3333,140 +3355,6 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done3: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP13]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: @@ -3484,73 +3372,139 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 +// CHECK5-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK5-NEXT: ret void // // @@ -3563,6 +3517,13 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: @@ -3591,6 +3552,28 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: @@ -3629,140 +3612,6 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done3: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP13]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: @@ -3780,73 +3629,139 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK6-NEXT: ret i32 0 // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 +// CHECK6-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK6-NEXT: ret void // // @@ -3859,1364 +3774,9 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP13]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP13]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK9-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 -// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init() -// CHECK9-NEXT: call void @__cxx_global_var_init.1() -// CHECK9-NEXT: call void @__cxx_global_var_init.2() -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK10-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 -// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__cxx_global_var_init() -// CHECK10-NEXT: call void @__cxx_global_var_init.1() -// CHECK10-NEXT: call void @__cxx_global_var_init.2() -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp @@ -6,26 +6,26 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -830,16 +830,704 @@ // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP31]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 +// CHECK5-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done3: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP37]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK5-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK5-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK5-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[TMP14]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK5-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP27]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done14: +// CHECK5-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8* +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK5-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8 +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done16: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK5-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP30]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK5-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK5-NEXT: [[TMP16:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[TMP14]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK5-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP27]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done12: +// CHECK5-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done14: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -848,16 +1536,704 @@ // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP31]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 +// CHECK6-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done3: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP37]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK6-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK6-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK6-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[TMP14]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK6-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP27]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done14: +// CHECK6-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8* +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK6-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8 +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done16: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK6-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP30]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK6-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK6-NEXT: [[TMP16:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[TMP14]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK6-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP27]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done12: +// CHECK6-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done14: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main @@ -866,16 +2242,688 @@ // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP31]], align 4 +// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 +// CHECK7-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP37]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK7-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i32 [[TMP7]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP13]] +// CHECK7-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* +// CHECK7-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[TMP14]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK7-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP23]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP27]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done12: +// CHECK7-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8* +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK7-NEXT: store i32 [[TMP33]], i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done14: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK7-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP30]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK7-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP13]] +// CHECK7-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: [[TMP16:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* +// CHECK7-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[TMP14]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK7-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP23]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP27]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done11: +// CHECK7-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done13: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main @@ -884,3886 +2932,686 @@ // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP31]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 -// CHECK9-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP37]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK9-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK9-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[TMP14]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK9-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP27]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done14: -// CHECK9-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8* -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8 -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done16: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK9-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP30]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM8]] -// CHECK9-NEXT: [[TMP16:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[TMP14]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK9-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP27]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done12: -// CHECK9-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done14: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP31]], align 8 -// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 -// CHECK10-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP37]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK10-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK10-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[TMP14]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK10-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP27]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done14: -// CHECK10-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8* -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8 -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done16: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK10-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP30]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM8]] -// CHECK10-NEXT: [[TMP16:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[TMP14]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK10-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP27]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done12: -// CHECK10-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done14: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP31]], align 4 -// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 -// CHECK11-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP37]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK11-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i32 [[TMP7]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP15]] -// CHECK11-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* -// CHECK11-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[TMP14]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK11-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: store i32 [[TMP23]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP27]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done12: -// CHECK11-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8* -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK11-NEXT: store i32 [[TMP33]], i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done14: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK11-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP30]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP15]] -// CHECK11-NEXT: [[TMP16:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* -// CHECK11-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[TMP14]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK11-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: store i32 [[TMP23]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP27]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done11: -// CHECK11-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done13: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP31]], align 4 -// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 -// CHECK12-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP37]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK12-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i32 [[TMP7]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP15]] -// CHECK12-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[TMP14]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK12-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: store i32 [[TMP23]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP27]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done12: -// CHECK12-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8* -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK12-NEXT: store i32 [[TMP33]], i32* [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done14: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK12-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP30]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP15]] -// CHECK12-NEXT: [[TMP16:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[TMP14]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK12-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: store i32 [[TMP23]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP27]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done11: -// CHECK12-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done13: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done4: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP13]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done3: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP13]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done3: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done3: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done2: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done3: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done2: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP31]], align 4 +// CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 +// CHECK8-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP37]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 +// CHECK8-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i32 [[TMP7]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP13]] +// CHECK8-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK8-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* +// CHECK8-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[TMP14]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK8-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP23]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP27]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done12: +// CHECK8-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8* +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK8-NEXT: store i32 [[TMP33]], i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done14: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK8-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP30]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK8-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP13]] +// CHECK8-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK8-NEXT: [[TMP16:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* +// CHECK8-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[TMP14]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK8-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP23]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP27]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done11: +// CHECK8-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done13: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp @@ -11,31 +11,31 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK6 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK8 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 @@ -3029,2342 +3029,1806 @@ // CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK6-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 +// CHECK6-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) +// CHECK6-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK6-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK6: .cancel.exit: +// CHECK6-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK6: .cancel.continue: +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: cancel.exit: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK6-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: br label [[CANCEL_CONT]] +// CHECK6: cancel.cont: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 +// CHECK6-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK6-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK6-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK6-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK6-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i64 0 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC9:%.*]] -// CHECK6: for.inc9: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end11: -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: ret i32 [[TMP13]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK7-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 +// CHECK7-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) +// CHECK7-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK7-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK7-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK7-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK7-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK7-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK7-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK7-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK7-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) +// CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK7-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK7: .cancel.exit: +// CHECK7-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK7: .cancel.continue: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: cancel.exit: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK7-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: br label [[CANCEL_CONT]] +// CHECK7: cancel.cont: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 +// CHECK7-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK7-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK7-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK7-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK7-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK7-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK7-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK7-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK7-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK7-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK7-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i64 0 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM7]] -// CHECK7-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX8]], align 4 -// CHECK7-NEXT: br label [[FOR_INC9:%.*]] -// CHECK7: for.inc9: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK7-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end11: -// CHECK7-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK7-NEXT: ret i32 [[TMP13]] +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK7-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK7-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK7-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK7-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 +// CHECK8-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP5]], [1000 x i32]* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) +// CHECK8-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK8-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK8: .cancel.exit: +// CHECK8-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK8: .cancel.continue: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: cancel.exit: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK8-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: br label [[CANCEL_CONT]] +// CHECK8: cancel.cont: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 +// CHECK8-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK8-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) +// CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK8-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 // CHECK8-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK8-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 // CHECK8-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK8-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK8-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP5]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK8-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC8:%.*]] -// CHECK8: for.inc8: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end10: -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: ret i32 [[TMP13]] +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK8-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK8-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 +// CHECK9-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP5]], [1000 x i32]* [[TMP1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) +// CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK9-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK9: .cancel.exit: +// CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK9: .cancel.continue: +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: cancel.exit: +// CHECK9-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK9-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: br label [[CANCEL_CONT]] +// CHECK9: cancel.cont: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 +// CHECK9-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) +// CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK9-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK9-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 // CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK9-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK9-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK9-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP5]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3:%.*]] -// CHECK9: for.cond3: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK9: for.body5: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX7]], align 4 -// CHECK9-NEXT: br label [[FOR_INC8:%.*]] -// CHECK9: for.inc8: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end10: -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK9-NEXT: ret i32 [[TMP13]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) -// CHECK10-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK10-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK10: .cancel.exit: -// CHECK10-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK10: .cancel.continue: -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: cancel.exit: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK10-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: br label [[CANCEL_CONT]] -// CHECK10: cancel.cont: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK11-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) -// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK11-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK11-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK11-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK11-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK11-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK11-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK11-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) -// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK11-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK11: .cancel.exit: -// CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK11: .cancel.continue: -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: cancel.exit: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK11-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: br label [[CANCEL_CONT]] -// CHECK11: cancel.cont: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK11-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 -// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK11-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK11-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK11-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK11-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK12-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP5]], [1000 x i32]* [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) -// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK12-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK12: .cancel.exit: -// CHECK12-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK12: .cancel.continue: -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: cancel.exit: -// CHECK12-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK12-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: br label [[CANCEL_CONT]] -// CHECK12: cancel.cont: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK12-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] -// CHECK12-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK13-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP5]], [1000 x i32]* [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK13: omp.precond.then: -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK13-NEXT: br label [[OMP_PRECOND_END]] -// CHECK13: omp.precond.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK13: omp.precond.then: -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK13-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) -// CHECK13-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK13-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] -// CHECK13: .cancel.exit: -// CHECK13-NEXT: br label [[CANCEL_EXIT:%.*]] -// CHECK13: .cancel.continue: -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK13-NEXT: br label [[OMP_PRECOND_END]] -// CHECK13: cancel.exit: -// CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK13-NEXT: br label [[CANCEL_CONT:%.*]] -// CHECK13: omp.precond.end: -// CHECK13-NEXT: br label [[CANCEL_CONT]] -// CHECK13: cancel.cont: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK13-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK13: omp.precond.then: -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK13-NEXT: br label [[OMP_PRECOND_END]] -// CHECK13: omp.precond.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 -// CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK13: omp.precond.then: -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] -// CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK13-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK13-NEXT: br label [[OMP_PRECOND_END]] -// CHECK13: omp.precond.end: -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK14-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK14-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK14-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK14-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK14-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK14-NEXT: br label [[FOR_COND3:%.*]] -// CHECK14: for.cond3: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK14: for.body5: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i64 0 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK14-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM7]] -// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX8]], align 4 -// CHECK14-NEXT: br label [[FOR_INC9:%.*]] -// CHECK14: for.inc9: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK14-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK14-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end11: -// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK15-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK15-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK15-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK15-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK15-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3:%.*]] -// CHECK15: for.cond3: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK15-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK15: for.body5: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i64 0 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM7]] -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX8]], align 4 -// CHECK15-NEXT: br label [[FOR_INC9:%.*]] -// CHECK15: for.inc9: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK15: for.end11: -// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK16-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK16-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK16-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK16-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK16-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP5]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3:%.*]] -// CHECK16: for.cond3: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK16-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK16: for.body5: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX7]], align 4 -// CHECK16-NEXT: br label [[FOR_INC8:%.*]] -// CHECK16: for.inc8: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end10: -// CHECK16-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK17-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK17-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK17-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK17-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK17-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK17-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: br label [[FOR_COND:%.*]] -// CHECK17: for.cond: -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK17: for.body: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP5]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[FOR_INC:%.*]] -// CHECK17: for.inc: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK17-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK17-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK17: for.end: -// CHECK17-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK17-NEXT: br label [[FOR_COND3:%.*]] -// CHECK17: for.cond3: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK17: for.body5: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK17-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX7]], align 4 -// CHECK17-NEXT: br label [[FOR_INC8:%.*]] -// CHECK17: for.inc8: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK17-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK17-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK17: for.end10: -// CHECK17-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK17-NEXT: ret i32 [[TMP13]] +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK9-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -47,19 +47,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -963,3272 +963,2564 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK5-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK5-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() +// CHECK5-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK5-NEXT: store i64 4, i64* [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK5-NEXT: store i64 8, i64* [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK5-NEXT: store i64 8, i64* [[TMP34]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP35]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK5-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 +// CHECK5-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 +// CHECK5-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK5-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] +// CHECK5-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK5-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK5-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK5-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 +// CHECK5-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) +// CHECK5-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP54]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J14:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK5-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 +// CHECK5-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] +// CHECK5-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK5-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[J]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: land.lhs.true: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK5-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK5-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] +// CHECK5-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J14:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK5-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 +// CHECK5-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] +// CHECK5-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK5-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body: // CHECK5-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: land.lhs.true: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK5-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK5-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 +// CHECK5-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 +// CHECK5-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] +// CHECK5-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 +// CHECK5-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]] +// CHECK5-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] +// CHECK5-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK5-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK5-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 +// CHECK5-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] +// CHECK5-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 +// CHECK5-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK5-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 +// CHECK5-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK5-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] +// CHECK5-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 +// CHECK5-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] +// CHECK5-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]] +// CHECK5-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 +// CHECK5-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] +// CHECK5-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK5-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP28]] +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 +// CHECK5-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP30]], 1 +// CHECK5-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK5-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) +// CHECK5-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK5-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 +// CHECK5-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 +// CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] +// CHECK5-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 +// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK6-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK6-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() +// CHECK6-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK6-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK6-NEXT: store i64 4, i64* [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK6-NEXT: store i64 8, i64* [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK6-NEXT: store i64 8, i64* [[TMP34]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP35]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK6-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 +// CHECK6-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 +// CHECK6-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK6-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] +// CHECK6-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK6-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK6-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK6-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 +// CHECK6-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) +// CHECK6-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP54]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J14:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK6-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 +// CHECK6-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] +// CHECK6-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK6-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body: // CHECK6-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: land.lhs.true: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK6-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK6-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] +// CHECK6-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J14:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK6-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 +// CHECK6-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] +// CHECK6-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK6-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[J]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: land.lhs.true: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK6-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK6-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 +// CHECK6-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 +// CHECK6-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] +// CHECK6-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 +// CHECK6-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]] +// CHECK6-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] +// CHECK6-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK6-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK6-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 +// CHECK6-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] +// CHECK6-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 +// CHECK6-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK6-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 +// CHECK6-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK6-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] +// CHECK6-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 +// CHECK6-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] +// CHECK6-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]] +// CHECK6-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 +// CHECK6-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] +// CHECK6-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK6-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP28]] +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 +// CHECK6-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK6-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP30]], 1 +// CHECK6-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK6-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) +// CHECK6-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK6-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 +// CHECK6-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 +// CHECK6-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] +// CHECK6-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 +// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@main +// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK7-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK7-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 +// CHECK7-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK7-NEXT: store i64 4, i64* [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK7-NEXT: store i64 4, i64* [[TMP33]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 +// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 +// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK7-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 +// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK7-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 +// CHECK7-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] +// CHECK7-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK7-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 +// CHECK7-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) +// CHECK7-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP53]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK7-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK7-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body: // CHECK7-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: land.lhs.true: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK7-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32 +// CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP23]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP25]], i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP26]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP27]], [[TMP28]] +// CHECK7-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J14:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK7-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK7-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[J]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: land.lhs.true: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[CONV11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: [[CONV12:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK7-NEXT: store i64 [[CONV11]], i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[CONV12]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 +// CHECK7-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 +// CHECK7-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] +// CHECK7-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 +// CHECK7-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]] +// CHECK7-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] +// CHECK7-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK7-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK7-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 +// CHECK7-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] +// CHECK7-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 +// CHECK7-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 +// CHECK7-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK7-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] +// CHECK7-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 +// CHECK7-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] +// CHECK7-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]] +// CHECK7-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 +// CHECK7-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] +// CHECK7-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK7-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP1]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP28]] +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 +// CHECK7-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP30]], 1 +// CHECK7-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK7-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 +// CHECK7-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 +// CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] +// CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@main +// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK8-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK8-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 +// CHECK8-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK8-NEXT: store i64 4, i64* [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK8-NEXT: store i64 4, i64* [[TMP33]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 +// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 +// CHECK8-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK8-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 +// CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK8-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK8-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 +// CHECK8-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] +// CHECK8-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK8-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 +// CHECK8-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) +// CHECK8-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP53]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK8-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK8-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK8-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body: // CHECK8-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK9-NEXT: store i64 4, i64* [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK9-NEXT: store i64 8, i64* [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK9-NEXT: store i64 8, i64* [[TMP34]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 -// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 -// CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] -// CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK9-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK9-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 -// CHECK9-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) -// CHECK9-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP54]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 -// CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] -// CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: land.lhs.true: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK9-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] -// CHECK9-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 -// CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] -// CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: land.lhs.true: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 -// CHECK9-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 -// CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] -// CHECK9-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 -// CHECK9-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]] -// CHECK9-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] -// CHECK9-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK9-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 -// CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 -// CHECK9-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] -// CHECK9-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 -// CHECK9-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 -// CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] -// CHECK9-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 -// CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] -// CHECK9-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]] -// CHECK9-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 -// CHECK9-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] -// CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK9-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP28]] -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 -// CHECK9-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK9-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK9-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 -// CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] -// CHECK9-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 -// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK10-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK10-NEXT: store i64 4, i64* [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK10-NEXT: store i64 8, i64* [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 -// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK10-NEXT: store i64 8, i64* [[TMP34]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK10-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 -// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 -// CHECK10-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 -// CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] -// CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK10-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK10-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 -// CHECK10-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) -// CHECK10-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP54]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 -// CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] -// CHECK10-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK10-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: land.lhs.true: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK10-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] -// CHECK10-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 -// CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] -// CHECK10-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK10-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: land.lhs.true: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_LB]], align 8 -// CHECK10-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 -// CHECK10-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 -// CHECK10-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] -// CHECK10-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 -// CHECK10-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]] -// CHECK10-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] -// CHECK10-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK10-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 -// CHECK10-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 -// CHECK10-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] -// CHECK10-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 -// CHECK10-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 -// CHECK10-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] -// CHECK10-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 -// CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] -// CHECK10-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]] -// CHECK10-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 -// CHECK10-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] -// CHECK10-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK10-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP28]] -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 -// CHECK10-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK10-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK10-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 -// CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] -// CHECK10-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 -// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 -// CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK11-NEXT: store i64 4, i64* [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK11-NEXT: store i64 4, i64* [[TMP33]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP34]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 -// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 -// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 -// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 -// CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] -// CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK11-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 -// CHECK11-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) -// CHECK11-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP53]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: land.lhs.true: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK11-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32 -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP23]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP25]], i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP26]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP27]], [[TMP28]] -// CHECK11-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: land.lhs.true: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[CONV11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: [[CONV12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK11-NEXT: store i64 [[CONV11]], i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: store i64 [[CONV12]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 -// CHECK11-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 -// CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] -// CHECK11-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 -// CHECK11-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]] -// CHECK11-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] -// CHECK11-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK11-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 -// CHECK11-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 -// CHECK11-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] -// CHECK11-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 -// CHECK11-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 -// CHECK11-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] -// CHECK11-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 -// CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] -// CHECK11-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]] -// CHECK11-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 -// CHECK11-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] -// CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK11-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP1]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP28]] -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 -// CHECK11-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK11-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) -// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 -// CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] -// CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 -// CHECK12-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK12-NEXT: store i64 4, i64* [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK12-NEXT: store i64 4, i64* [[TMP33]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP34]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 -// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 -// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK12-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 -// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK12-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 -// CHECK12-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] -// CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK12-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 -// CHECK12-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) -// CHECK12-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP53]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: land.lhs.true: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK12-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK12-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32 -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP23]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP25]], i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP26]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP27]], [[TMP28]] -// CHECK12-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 -// CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: land.lhs.true: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[CONV11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: [[CONV12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK12-NEXT: store i64 [[CONV11]], i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: store i64 [[CONV12]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 -// CHECK12-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 -// CHECK12-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] -// CHECK12-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 -// CHECK12-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]] -// CHECK12-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] -// CHECK12-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK12-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 -// CHECK12-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 -// CHECK12-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] -// CHECK12-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 -// CHECK12-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 -// CHECK12-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] -// CHECK12-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 -// CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] -// CHECK12-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]] -// CHECK12-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 -// CHECK12-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] -// CHECK12-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK12-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP1]] -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP28]] -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 -// CHECK12-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK12-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) -// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 -// CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] -// CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP17]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP17]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP15]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP15]] +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: land.lhs.true: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK8-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32 +// CHECK8-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP23]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP25]], i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP26]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP27]], [[TMP28]] +// CHECK8-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J14:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK8-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK8-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK8-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[J]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: land.lhs.true: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[CONV11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: [[CONV12:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK8-NEXT: store i64 [[CONV11]], i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[CONV12]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 +// CHECK8-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 +// CHECK8-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] +// CHECK8-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 +// CHECK8-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]] +// CHECK8-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] +// CHECK8-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK8-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK8-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 +// CHECK8-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] +// CHECK8-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 +// CHECK8-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 +// CHECK8-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK8-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] +// CHECK8-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 +// CHECK8-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] +// CHECK8-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]] +// CHECK8-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 +// CHECK8-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] +// CHECK8-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK8-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP1]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP28]] +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 +// CHECK8-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP30]], 1 +// CHECK8-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK8-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 +// CHECK8-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK8-NEXT: ret void // // -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret i32 0 +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 +// CHECK8-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] +// CHECK8-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 +// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -59,19 +59,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -2380,7002 +2380,6046 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 +// CHECK5-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK5-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK5-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK5-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK5-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK5-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK5-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK5-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK5-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) +// CHECK5-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK5-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK5: omp_offload.failed16: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK5: omp_offload.cont17: +// CHECK5-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK5-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* +// CHECK5-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 +// CHECK5-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 +// CHECK5-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK5-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 +// CHECK5-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* +// CHECK5-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 +// CHECK5-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* +// CHECK5-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 +// CHECK5-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP73]], align 8 +// CHECK5-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP74]], align 8 +// CHECK5-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 +// CHECK5-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 +// CHECK5-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP79]], align 8 +// CHECK5-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP80]], align 8 +// CHECK5-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 +// CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 +// CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 +// CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP86]], align 8 +// CHECK5-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* +// CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 +// CHECK5-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* +// CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 +// CHECK5-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 +// CHECK5-NEXT: store i64 4, i64* [[TMP91]], align 8 +// CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP92]], align 8 +// CHECK5-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK5-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK5-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 +// CHECK5-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK5-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 +// CHECK5-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK5-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK5-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 +// CHECK5-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP99]]) +// CHECK5-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 +// CHECK5-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK5: omp_offload.failed33: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK5: omp_offload.cont34: +// CHECK5-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) +// CHECK5-NEXT: [[TMP104:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP104]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP30]], [[TMP31]] +// CHECK5-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] +// CHECK5: cond.true14: +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: br label [[COND_END16:%.*]] +// CHECK5: cond.false15: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END16]] +// CHECK5: cond.end16: +// CHECK5-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE14]] ], [ [[TMP33]], [[COND_FALSE15]] ] +// CHECK5-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK5-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK5-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK5-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK5-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK5-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK5-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK5: omp_offload.failed5: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK5: omp_offload.cont6: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP19]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK5-NEXT: store i64 [[TMP20]], i64* [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK5-NEXT: store i64 [[TMP20]], i64* [[TMP29]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK5-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK5: omp_offload.failed11: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]], i64 [[TMP20]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK5: omp_offload.cont12: +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3:%.*]] -// CHECK5: for.cond3: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK5: for.body5: -// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK5-NEXT: br label [[FOR_INC9:%.*]] -// CHECK5: for.inc9: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end11: -// CHECK5-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13:%.*]] -// CHECK5: for.cond13: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK5-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK5: for.body15: -// CHECK5-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK5-NEXT: br label [[FOR_INC19:%.*]] -// CHECK5: for.inc19: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end21: -// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK5: cond.true6: +// CHECK5-NEXT: br label [[COND_END8:%.*]] +// CHECK5: cond.false7: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END8]] +// CHECK5: cond.end8: +// CHECK5-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] +// CHECK5-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 +// CHECK6-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK6-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK6-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK6-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK6-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK6-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK6-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK6-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK6-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK6-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK6-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK6-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK6-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK6-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK6-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK6-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK6-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK6-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) +// CHECK6-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK6-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK6: omp_offload.failed16: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK6: omp_offload.cont17: +// CHECK6-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK6-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* +// CHECK6-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 +// CHECK6-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 +// CHECK6-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK6-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 +// CHECK6-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* +// CHECK6-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 +// CHECK6-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* +// CHECK6-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 +// CHECK6-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP73]], align 8 +// CHECK6-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP74]], align 8 +// CHECK6-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 +// CHECK6-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 +// CHECK6-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP79]], align 8 +// CHECK6-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP80]], align 8 +// CHECK6-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 +// CHECK6-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 +// CHECK6-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 +// CHECK6-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP86]], align 8 +// CHECK6-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* +// CHECK6-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 +// CHECK6-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* +// CHECK6-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 +// CHECK6-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 +// CHECK6-NEXT: store i64 4, i64* [[TMP91]], align 8 +// CHECK6-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP92]], align 8 +// CHECK6-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK6-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK6-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 +// CHECK6-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK6-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 +// CHECK6-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK6-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK6-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 +// CHECK6-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP99]]) +// CHECK6-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 +// CHECK6-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK6: omp_offload.failed33: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK6: omp_offload.cont34: +// CHECK6-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) +// CHECK6-NEXT: [[TMP104:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP104]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] // CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC9:%.*]] -// CHECK6: for.inc9: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end11: -// CHECK6-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13:%.*]] -// CHECK6: for.cond13: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK6-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK6: for.body15: -// CHECK6-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK6-NEXT: br label [[FOR_INC19:%.*]] -// CHECK6: for.inc19: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end21: -// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP30]], [[TMP31]] +// CHECK6-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] +// CHECK6: cond.true14: +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: br label [[COND_END16:%.*]] +// CHECK6: cond.false15: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END16]] +// CHECK6: cond.end16: +// CHECK6-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE14]] ], [ [[TMP33]], [[COND_FALSE15]] ] +// CHECK6-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK6-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK6-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK6-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK6-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK6-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK6-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK6: omp_offload.failed5: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK6: omp_offload.cont6: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP19]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK6-NEXT: store i64 [[TMP20]], i64* [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK6-NEXT: store i64 [[TMP20]], i64* [[TMP29]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK6-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK6: omp_offload.failed11: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]], i64 [[TMP20]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK6: omp_offload.cont12: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK6: cond.true6: +// CHECK6-NEXT: br label [[COND_END8:%.*]] +// CHECK6: cond.false7: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END8]] +// CHECK6: cond.end8: +// CHECK6-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] +// CHECK6-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@main +// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 +// CHECK7-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK7-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK7-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK7-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK7-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK7-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK7-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) +// CHECK7-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK7-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK7: omp_offload.failed15: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK7: omp_offload.cont16: +// CHECK7-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK7-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 +// CHECK7-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 +// CHECK7-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK7-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 +// CHECK7-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* +// CHECK7-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 +// CHECK7-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK7-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 +// CHECK7-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP75]], align 4 +// CHECK7-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP76]], align 4 +// CHECK7-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 +// CHECK7-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 +// CHECK7-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP81]], align 4 +// CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 +// CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 +// CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 +// CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP88]], align 4 +// CHECK7-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* +// CHECK7-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 +// CHECK7-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* +// CHECK7-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 +// CHECK7-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 +// CHECK7-NEXT: store i64 4, i64* [[TMP93]], align 4 +// CHECK7-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP94]], align 4 +// CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK7-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK7-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 +// CHECK7-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// CHECK7-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 +// CHECK7-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK7-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK7-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 +// CHECK7-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP101]]) +// CHECK7-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 +// CHECK7-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK7: omp_offload.failed30: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK7: omp_offload.cont31: +// CHECK7-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) +// CHECK7-NEXT: [[TMP106:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP106]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC8:%.*]] -// CHECK7: for.inc8: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end10: -// CHECK7-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12:%.*]] -// CHECK7: for.cond12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK7-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK7: for.body14: -// CHECK7-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK7-NEXT: br label [[FOR_INC17:%.*]] -// CHECK7: for.inc17: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end19: -// CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP28]], [[TMP29]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK7: cond.true11: +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END13:%.*]] +// CHECK7: cond.false12: +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END13]] +// CHECK7: cond.end13: +// CHECK7-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE11]] ], [ [[TMP31]], [[COND_FALSE12]] ] +// CHECK7-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK7-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK7-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 +// CHECK7-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK7-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK7: omp_offload.failed5: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK7: omp_offload.cont6: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK7-NEXT: store i32 [[TMP20]], i32* [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK7-NEXT: store i32 [[TMP20]], i32* [[TMP29]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK7-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK7: omp_offload.failed11: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]], i32 [[TMP20]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK7: omp_offload.cont12: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] +// CHECK7: cond.true5: +// CHECK7-NEXT: br label [[COND_END7:%.*]] +// CHECK7: cond.false6: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END7]] +// CHECK7: cond.end7: +// CHECK7-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] +// CHECK7-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@main +// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 +// CHECK8-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK8-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK8-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK8-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK8-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK8-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK8-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK8-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK8-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK8-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK8-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK8-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK8-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK8-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK8-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK8-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK8-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK8-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) +// CHECK8-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK8-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK8: omp_offload.failed15: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK8: omp_offload.cont16: +// CHECK8-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK8-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 +// CHECK8-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 +// CHECK8-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK8-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 +// CHECK8-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* +// CHECK8-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 +// CHECK8-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK8-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 +// CHECK8-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP75]], align 4 +// CHECK8-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP76]], align 4 +// CHECK8-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 +// CHECK8-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 +// CHECK8-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP81]], align 4 +// CHECK8-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK8-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 +// CHECK8-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 +// CHECK8-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 +// CHECK8-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP88]], align 4 +// CHECK8-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* +// CHECK8-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 +// CHECK8-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* +// CHECK8-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 +// CHECK8-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 +// CHECK8-NEXT: store i64 4, i64* [[TMP93]], align 4 +// CHECK8-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP94]], align 4 +// CHECK8-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK8-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK8-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 +// CHECK8-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// CHECK8-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 +// CHECK8-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK8-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK8-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 +// CHECK8-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP101]]) +// CHECK8-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 +// CHECK8-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK8: omp_offload.failed30: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK8: omp_offload.cont31: +// CHECK8-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) +// CHECK8-NEXT: [[TMP106:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP106]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] // CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC8:%.*]] -// CHECK8: for.inc8: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end10: -// CHECK8-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12:%.*]] -// CHECK8: for.cond12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK8-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK8: for.body14: -// CHECK8-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK8-NEXT: br label [[FOR_INC17:%.*]] -// CHECK8: for.inc17: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end19: -// CHECK8-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK9-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 -// CHECK9-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK9-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK9-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK9-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK9-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK9-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) -// CHECK9-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK9-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK9: omp_offload.failed16: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK9: omp_offload.cont17: -// CHECK9-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK9-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* -// CHECK9-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 -// CHECK9-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 -// CHECK9-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK9-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 -// CHECK9-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* -// CHECK9-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 -// CHECK9-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* -// CHECK9-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 -// CHECK9-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP73]], align 8 -// CHECK9-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP74]], align 8 -// CHECK9-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 -// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 -// CHECK9-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP79]], align 8 -// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP80]], align 8 -// CHECK9-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 -// CHECK9-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 -// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 -// CHECK9-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP86]], align 8 -// CHECK9-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* -// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 -// CHECK9-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* -// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 -// CHECK9-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 -// CHECK9-NEXT: store i64 4, i64* [[TMP91]], align 8 -// CHECK9-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK9-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK9-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 -// CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK9-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 -// CHECK9-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK9-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK9-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 -// CHECK9-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP99]]) -// CHECK9-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 -// CHECK9-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] -// CHECK9: omp_offload.failed33: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT34]] -// CHECK9: omp_offload.cont34: -// CHECK9-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) -// CHECK9-NEXT: [[TMP104:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP104]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP30]], [[TMP31]] -// CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] -// CHECK9: cond.true14: -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: br label [[COND_END16:%.*]] -// CHECK9: cond.false15: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END16]] -// CHECK9: cond.end16: -// CHECK9-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE14]] ], [ [[TMP33]], [[COND_FALSE15]] ] -// CHECK9-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I7:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 -// CHECK9-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK9: omp_offload.failed5: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK9: omp_offload.cont6: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK9-NEXT: store i64 [[TMP20]], i64* [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK9-NEXT: store i64 [[TMP20]], i64* [[TMP29]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK9-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK9: omp_offload.failed11: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]], i64 [[TMP20]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK9: omp_offload.cont12: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] -// CHECK9: cond.true6: -// CHECK9-NEXT: br label [[COND_END8:%.*]] -// CHECK9: cond.false7: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END8]] -// CHECK9: cond.end8: -// CHECK9-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] -// CHECK9-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK10-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 -// CHECK10-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK10-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK10-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK10-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK10-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) -// CHECK10-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK10-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK10: omp_offload.failed16: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK10: omp_offload.cont17: -// CHECK10-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK10-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* -// CHECK10-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 -// CHECK10-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 -// CHECK10-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK10-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 -// CHECK10-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* -// CHECK10-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 -// CHECK10-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* -// CHECK10-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 -// CHECK10-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP73]], align 8 -// CHECK10-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP74]], align 8 -// CHECK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 -// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 -// CHECK10-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP79]], align 8 -// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP80]], align 8 -// CHECK10-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 -// CHECK10-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 -// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 -// CHECK10-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP86]], align 8 -// CHECK10-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* -// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 -// CHECK10-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* -// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 -// CHECK10-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 -// CHECK10-NEXT: store i64 4, i64* [[TMP91]], align 8 -// CHECK10-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK10-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK10-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 -// CHECK10-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK10-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 -// CHECK10-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK10-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK10-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 -// CHECK10-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP99]]) -// CHECK10-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 -// CHECK10-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] -// CHECK10: omp_offload.failed33: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT34]] -// CHECK10: omp_offload.cont34: -// CHECK10-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) -// CHECK10-NEXT: [[TMP104:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP104]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP30]], [[TMP31]] -// CHECK10-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] -// CHECK10: cond.true14: -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: br label [[COND_END16:%.*]] -// CHECK10: cond.false15: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END16]] -// CHECK10: cond.end16: -// CHECK10-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE14]] ], [ [[TMP33]], [[COND_FALSE15]] ] -// CHECK10-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I7:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 -// CHECK10-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK10-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK10: omp_offload.failed5: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK10: omp_offload.cont6: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 8 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK10-NEXT: store i64 [[TMP20]], i64* [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK10-NEXT: store i64 [[TMP20]], i64* [[TMP29]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK10-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK10: omp_offload.failed11: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]], i64 [[TMP20]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK10: omp_offload.cont12: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] -// CHECK10: cond.true6: -// CHECK10-NEXT: br label [[COND_END8:%.*]] -// CHECK10: cond.false7: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END8]] -// CHECK10: cond.end8: -// CHECK10-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] -// CHECK10-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK11-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 -// CHECK11-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK11-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK11-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK11-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK11-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK11-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK11-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) -// CHECK11-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK11-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK11: omp_offload.failed15: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK11: omp_offload.cont16: -// CHECK11-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK11-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 -// CHECK11-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 -// CHECK11-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK11-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 -// CHECK11-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* -// CHECK11-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 -// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK11-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 -// CHECK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP75]], align 4 -// CHECK11-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP76]], align 4 -// CHECK11-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 -// CHECK11-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 -// CHECK11-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP81]], align 4 -// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK11-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 -// CHECK11-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 -// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 -// CHECK11-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP88]], align 4 -// CHECK11-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* -// CHECK11-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 -// CHECK11-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* -// CHECK11-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 -// CHECK11-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 -// CHECK11-NEXT: store i64 4, i64* [[TMP93]], align 4 -// CHECK11-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP94]], align 4 -// CHECK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK11-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK11-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 -// CHECK11-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// CHECK11-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 -// CHECK11-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK11-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK11-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 -// CHECK11-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP101]]) -// CHECK11-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 -// CHECK11-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK11: omp_offload.failed30: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK11: omp_offload.cont31: -// CHECK11-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) -// CHECK11-NEXT: [[TMP106:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP106]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP28]], [[TMP29]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK11: cond.true11: -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END13:%.*]] -// CHECK11: cond.false12: -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END13]] -// CHECK11: cond.end13: -// CHECK11-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE11]] ], [ [[TMP31]], [[COND_FALSE12]] ] -// CHECK11-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 -// CHECK11-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK11-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK11: omp_offload.failed5: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK11: omp_offload.cont6: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* -// CHECK11-NEXT: store i32 [[TMP20]], i32* [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK11-NEXT: store i32 [[TMP20]], i32* [[TMP29]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK11-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK11: omp_offload.failed11: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]], i32 [[TMP20]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK11: omp_offload.cont12: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] -// CHECK11: cond.true5: -// CHECK11-NEXT: br label [[COND_END7:%.*]] -// CHECK11: cond.false6: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END7]] -// CHECK11: cond.end7: -// CHECK11-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] -// CHECK11-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 -// CHECK12-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK12-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK12-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK12-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK12-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK12-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK12-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK12-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) -// CHECK12-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK12-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK12: omp_offload.failed15: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK12: omp_offload.cont16: -// CHECK12-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK12-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 -// CHECK12-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 -// CHECK12-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK12-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 -// CHECK12-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* -// CHECK12-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 -// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK12-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 -// CHECK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP75]], align 4 -// CHECK12-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP76]], align 4 -// CHECK12-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 -// CHECK12-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 -// CHECK12-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP81]], align 4 -// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK12-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 -// CHECK12-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 -// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 -// CHECK12-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP88]], align 4 -// CHECK12-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* -// CHECK12-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 -// CHECK12-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* -// CHECK12-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 -// CHECK12-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 -// CHECK12-NEXT: store i64 4, i64* [[TMP93]], align 4 -// CHECK12-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP94]], align 4 -// CHECK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK12-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK12-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 -// CHECK12-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// CHECK12-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 -// CHECK12-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK12-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK12-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 -// CHECK12-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP101]]) -// CHECK12-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 -// CHECK12-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK12: omp_offload.failed30: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK12: omp_offload.cont31: -// CHECK12-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) -// CHECK12-NEXT: [[TMP106:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP106]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP28]], [[TMP29]] -// CHECK12-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK12: cond.true11: -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END13:%.*]] -// CHECK12: cond.false12: -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END13]] -// CHECK12: cond.end13: -// CHECK12-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE11]] ], [ [[TMP31]], [[COND_FALSE12]] ] -// CHECK12-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 -// CHECK12-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK12-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK12: omp_offload.failed5: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK12: omp_offload.cont6: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* -// CHECK12-NEXT: store i32 [[TMP20]], i32* [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK12-NEXT: store i32 [[TMP20]], i32* [[TMP29]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK12-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK12: omp_offload.failed11: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]], i32 [[TMP20]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK12: omp_offload.cont12: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] -// CHECK12: cond.true5: -// CHECK12-NEXT: br label [[COND_END7:%.*]] -// CHECK12: cond.false6: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END7]] -// CHECK12: cond.end7: -// CHECK12-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] -// CHECK12-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP17]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP17]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: ret i32 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP28]], [[TMP29]] +// CHECK8-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK8: cond.true11: +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END13:%.*]] +// CHECK8: cond.false12: +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END13]] +// CHECK8: cond.end13: +// CHECK8-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE11]] ], [ [[TMP31]], [[COND_FALSE12]] ] +// CHECK8-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK8-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK8-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 +// CHECK8-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK8-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK8: omp_offload.failed5: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK8: omp_offload.cont6: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK8-NEXT: store i32 [[TMP20]], i32* [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK8-NEXT: store i32 [[TMP20]], i32* [[TMP29]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK8-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK8: omp_offload.failed11: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]], i32 [[TMP20]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK8: omp_offload.cont12: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] +// CHECK8: cond.true5: +// CHECK8-NEXT: br label [[COND_END7:%.*]] +// CHECK8: cond.false6: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END7]] +// CHECK8: cond.end7: +// CHECK8-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] +// CHECK8-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -10,41 +10,41 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK18 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK22 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -5096,1170 +5096,2882 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 +// CHECK7-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK7-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK7-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK7-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done4: +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK7-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done11: // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK7-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK7-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK7-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK7-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK7-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK7-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK7-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK7-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK7-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done6: +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK7-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] +// CHECK7-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK7-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done15: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK7-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK7-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK7-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done4: +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK7-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done11: // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK7-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK7-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK7-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK7-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK7-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done6: +// CHECK7-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK7-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK7-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK7-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK7-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP14]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done15: // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK7-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK7-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK7-NEXT: store i32 0, i32* [[B]], align 4 // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK7-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK7-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK7-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK7-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK7-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 +// CHECK8-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) +// CHECK8-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK8-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done4: +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK8-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done11: +// CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK8-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK8-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK8-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK8-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK8-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK8-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK8-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done6: +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK8-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] +// CHECK8-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK8-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done15: // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK8-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK8-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK8-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done4: +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK8-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done11: // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK8-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK8-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK8-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK8-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK8-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done6: +// CHECK8-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK8-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK8-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK8-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK8-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP14]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done15: // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK8-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK8-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK8-NEXT: store i32 0, i32* [[B]], align 4 // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK8-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK8-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK8-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK8-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 +// CHECK9-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) +// CHECK9-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 +// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* +// CHECK9-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK9: omp.arraycpy.body: +// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] +// CHECK9: omp.arraycpy.done3: +// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK9: omp.inner.for.cond.cleanup: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 +// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK9: arraydestroy.body: +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done8: +// CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 +// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* +// CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK9: omp.arraycpy.body: +// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] +// CHECK9: omp.arraycpy.done3: +// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK9: omp.inner.for.cond.cleanup: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] +// CHECK9-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] +// CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* +// CHECK9-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 +// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK9: arraydestroy.body: +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done11: // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK9-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 +// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK9-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK9: omp.arraycpy.body: +// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK9: omp.arraycpy.done4: +// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK9: omp.inner.for.cond.cleanup: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done10: // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK9-SAME: () #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK9-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK9-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK9: omp.arraycpy.body: +// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK9: omp.arraycpy.done4: +// CHECK9-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK9: omp.inner.for.cond.cleanup: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] +// CHECK9-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] +// CHECK9-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP14]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done12: // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK9-NEXT: store i32 0, i32* [[B]], align 4 // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] +// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: ret void +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 +// CHECK10-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) +// CHECK10-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init() -// CHECK9-NEXT: call void @__cxx_global_var_init.1() -// CHECK9-NEXT: call void @__cxx_global_var_init.2() -// CHECK9-NEXT: ret void +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 +// CHECK10-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK10-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK10-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* +// CHECK10-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK10: omp.arraycpy.body: +// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] +// CHECK10: omp.arraycpy.done3: +// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK10: omp.inner.for.cond.cleanup: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 +// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK10: arraydestroy.body: +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK10: arraydestroy.done8: +// CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK10-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK10-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 +// CHECK10-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK10-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK10-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* +// CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK10: omp.arraycpy.body: +// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] +// CHECK10: omp.arraycpy.done3: +// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK10: omp.inner.for.cond.cleanup: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] +// CHECK10-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] +// CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* +// CHECK10-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 +// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK10: arraydestroy.body: +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK10: arraydestroy.done11: // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK10-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] +// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK10-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK10-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK10-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK10: omp.arraycpy.body: +// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK10: omp.arraycpy.done4: +// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK10: omp.inner.for.cond.cleanup: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP14]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] +// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK10: arraydestroy.done10: // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK10-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK10: omp.arraycpy.body: +// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK10: omp.arraycpy.done4: +// CHECK10-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK10: omp.inner.for.cond.cleanup: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] +// CHECK10-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] +// CHECK10-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 +// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK10: arraydestroy.body: +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK10: arraydestroy.done12: // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK10-NEXT: store i32 0, i32* [[B]], align 4 // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6267,4704 +7979,236 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__cxx_global_var_init() -// CHECK10-NEXT: call void @__cxx_global_var_init.1() -// CHECK10-NEXT: call void @__cxx_global_var_init.2() +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 +// CHECK11-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK11-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK11-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK11-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK11-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 +// CHECK11-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK11-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK11-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK11-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK11-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK11-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK11-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK11-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK11-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK11-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK11-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK11-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK11-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK11-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK11-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK11-NEXT: store i32 2, i32* [[CONV2]], align 8 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 +// CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK11-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 +// CHECK11-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 +// CHECK11-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK11-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK13-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK13: omp.arraycpy.body: -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK13: omp.arraycpy.done4: -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] -// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK13: omp.inner.for.cond.cleanup: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 -// CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 -// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done11: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK13-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK13-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK13: omp.arraycpy.body: -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK13: omp.arraycpy.done6: -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] -// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK13: omp.inner.for.cond.cleanup: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK13-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK13-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done15: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK13-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK13-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK13: omp.arraycpy.body: -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK13: omp.arraycpy.done4: -// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] -// CHECK13-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK13: omp.inner.for.cond.cleanup: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 -// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK13-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done11: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK13-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK13: omp.arraycpy.body: -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK13: omp.arraycpy.done6: -// CHECK13-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] -// CHECK13-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK13: omp.inner.for.cond.cleanup: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 -// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] -// CHECK13-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* -// CHECK13-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done15: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK13-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK13-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK13-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float -// CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] -// CHECK13-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK14-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK14: omp.arraycpy.body: -// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] -// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK14: omp.arraycpy.done4: -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] -// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK14: omp.inner.for.cond.cleanup: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 -// CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 -// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done11: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK14-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK14-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK14-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 -// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK14: omp.arraycpy.body: -// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK14: omp.arraycpy.done6: -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] -// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK14: omp.inner.for.cond.cleanup: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK14-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK14-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done15: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK14-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK14-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK14: omp.arraycpy.body: -// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK14: omp.arraycpy.done4: -// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] -// CHECK14-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK14: omp.inner.for.cond.cleanup: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 -// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK14-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done11: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK14-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK14-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 -// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK14: omp.arraycpy.body: -// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] -// CHECK14: omp.arraycpy.done6: -// CHECK14-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] -// CHECK14-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK14: omp.inner.for.cond.cleanup: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 -// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] -// CHECK14-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* -// CHECK14-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR7]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done15: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK14-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK14-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK14-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK14-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float -// CHECK14-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] -// CHECK14-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK14-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* -// CHECK15-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK15: omp.arraycpy.body: -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] -// CHECK15: omp.arraycpy.done3: -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] -// CHECK15-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK15: cond.true: -// CHECK15-NEXT: br label [[COND_END:%.*]] -// CHECK15: cond.false: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: br label [[COND_END]] -// CHECK15: cond.end: -// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK15: omp.inner.for.cond.cleanup: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) -// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK15: omp.inner.for.end: -// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done8: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK15-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK15-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR5]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* -// CHECK15-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK15: omp.arraycpy.body: -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] -// CHECK15: omp.arraycpy.done3: -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] -// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 -// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK15: cond.true: -// CHECK15-NEXT: br label [[COND_END:%.*]] -// CHECK15: cond.false: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: br label [[COND_END]] -// CHECK15: cond.end: -// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK15: omp.inner.for.cond.cleanup: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] -// CHECK15-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] -// CHECK15-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* -// CHECK15-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) -// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK15-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK15: omp.body.continue: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK15-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK15: omp.inner.for.end: -// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done11: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK15-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK15-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK15: omp.arraycpy.body: -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK15: omp.arraycpy.done4: -// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] -// CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK15: cond.true: -// CHECK15-NEXT: br label [[COND_END:%.*]] -// CHECK15: cond.false: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: br label [[COND_END]] -// CHECK15: cond.end: -// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK15: omp.inner.for.cond.cleanup: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) -// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK15: omp.inner.for.end: -// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done10: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK15-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK15-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK15: omp.arraycpy.body: -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK15: omp.arraycpy.done4: -// CHECK15-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] -// CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 -// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK15: cond.true: -// CHECK15-NEXT: br label [[COND_END:%.*]] -// CHECK15: cond.false: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: br label [[COND_END]] -// CHECK15: cond.end: -// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK15: omp.inner.for.cond.cleanup: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] -// CHECK15-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] -// CHECK15-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* -// CHECK15-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) -// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK15: omp.body.continue: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK15-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK15: omp.inner.for.end: -// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done12: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK15-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK15-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float -// CHECK15-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] -// CHECK15-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* -// CHECK16-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK16-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK16: omp.arraycpy.body: -// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] -// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] -// CHECK16: omp.arraycpy.done3: -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] -// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK16: cond.true: -// CHECK16-NEXT: br label [[COND_END:%.*]] -// CHECK16: cond.false: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: br label [[COND_END]] -// CHECK16: cond.end: -// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK16: omp.inner.for.cond.cleanup: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 -// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) -// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK16: omp.inner.for.end: -// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK16: omp.loop.exit: -// CHECK16-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done8: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK16-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK16-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR5]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK16: omp.arraycpy.body: -// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] -// CHECK16: omp.arraycpy.done3: -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] -// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 -// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK16: cond.true: -// CHECK16-NEXT: br label [[COND_END:%.*]] -// CHECK16: cond.false: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: br label [[COND_END]] -// CHECK16: cond.end: -// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK16: omp.inner.for.cond.cleanup: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] -// CHECK16-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] -// CHECK16-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* -// CHECK16-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) -// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 -// CHECK16-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK16-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 -// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK16: omp.body.continue: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK16-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK16: omp.inner.for.end: -// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK16: omp.loop.exit: -// CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done11: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK16-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK16-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK16-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK16: omp.arraycpy.body: -// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK16: omp.arraycpy.done4: -// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] -// CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK16: cond.true: -// CHECK16-NEXT: br label [[COND_END:%.*]] -// CHECK16: cond.false: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: br label [[COND_END]] -// CHECK16: cond.end: -// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK16: omp.inner.for.cond.cleanup: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK16-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) -// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK16: omp.inner.for.end: -// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK16: omp.loop.exit: -// CHECK16-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done10: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK16-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK16: omp.arraycpy.body: -// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK16: omp.arraycpy.done4: -// CHECK16-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] -// CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 -// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK16: cond.true: -// CHECK16-NEXT: br label [[COND_END:%.*]] -// CHECK16: cond.false: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: br label [[COND_END]] -// CHECK16: cond.end: -// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK16: omp.inner.for.cond.cleanup: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] -// CHECK16-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 -// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] -// CHECK16-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* -// CHECK16-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) -// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK16: omp.body.continue: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK16-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK16: omp.inner.for.end: -// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK16: omp.loop.exit: -// CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done12: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK16-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK16-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK16-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK16-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float -// CHECK16-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] -// CHECK16-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK16-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK17-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 -// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 -// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done1: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND:%.*]] -// CHECK18: for.cond: -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK18-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK18: for.body: -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK18-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK18-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK18-NEXT: br label [[FOR_INC:%.*]] -// CHECK18: for.inc: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK18: for.end: -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK18-NEXT: ret i32 [[CALL]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK18-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK18-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK18-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK18-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK18-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK18-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK18-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK18-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND:%.*]] -// CHECK18: for.cond: -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK18-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK18: for.body: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK18-NEXT: br label [[FOR_INC:%.*]] -// CHECK18: for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK18: for.end: -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done3: -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: ret i32 [[TMP14]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK18-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK18-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK18-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__cxx_global_var_init() -// CHECK18-NEXT: call void @__cxx_global_var_init.1() -// CHECK18-NEXT: call void @__cxx_global_var_init.2() -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK19-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK19-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK19: arraydestroy.body: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK19: arraydestroy.done1: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND:%.*]] -// CHECK19: for.cond: -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK19-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK19: for.body: -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK19-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK19-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK19-NEXT: br label [[FOR_INC:%.*]] -// CHECK19: for.inc: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK19: for.end: -// CHECK19-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK19-NEXT: ret i32 [[CALL]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK19-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK19-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK19-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK19-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK19-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK19-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK19-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK19-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK19-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND:%.*]] -// CHECK19: for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK19-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK19: for.body: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK19-NEXT: br label [[FOR_INC:%.*]] -// CHECK19: for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK19: for.end: -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK19: arraydestroy.body: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK19: arraydestroy.done3: -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: ret i32 [[TMP14]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK19-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK19-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK19-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__cxx_global_var_init() -// CHECK19-NEXT: call void @__cxx_global_var_init.1() -// CHECK19-NEXT: call void @__cxx_global_var_init.2() -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK20-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK20: arraydestroy.body: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK20: arraydestroy.done1: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND:%.*]] -// CHECK20: for.cond: -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK20-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK20: for.body: -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK20-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK20-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK20-NEXT: br label [[FOR_INC:%.*]] -// CHECK20: for.inc: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK20: for.end: -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK20-NEXT: ret i32 [[CALL]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK20-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK20-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK20-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK20-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK20-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK20-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK20-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK20-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND:%.*]] -// CHECK20: for.cond: -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK20-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK20: for.body: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK20-NEXT: br label [[FOR_INC:%.*]] -// CHECK20: for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK20: for.end: -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK20: arraydestroy.body: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK20: arraydestroy.done2: -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: ret i32 [[TMP14]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK20-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK20-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK20-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__cxx_global_var_init() -// CHECK20-NEXT: call void @__cxx_global_var_init.1() -// CHECK20-NEXT: call void @__cxx_global_var_init.2() -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK21-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK21-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done1: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@main -// CHECK21-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK21-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK21-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK21-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK21-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK21-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK21-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK21-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK21-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK21-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK21-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK21-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK21-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK21-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK21-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done2: -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: ret i32 [[TMP14]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK21-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK21-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK21-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @__cxx_global_var_init() -// CHECK21-NEXT: call void @__cxx_global_var_init.1() -// CHECK21-NEXT: call void @__cxx_global_var_init.2() -// CHECK21-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK22-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK22-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK22: arraydestroy.body: -// CHECK22-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK22-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK22-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK22-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK22-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK22: arraydestroy.done1: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@main -// CHECK22-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK22-NEXT: ret i32 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK22-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK22-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK22-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @__cxx_global_var_init() -// CHECK22-NEXT: call void @__cxx_global_var_init.1() -// CHECK22-NEXT: call void @__cxx_global_var_init.2() -// CHECK22-NEXT: ret void -// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp @@ -3,33 +3,33 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2756,323 +2756,2649 @@ // CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 +// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z9gtid_testv() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: () #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83() #[[ATTR2]] +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK3-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK3-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP5]] to i1 +// CHECK3-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK3-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK3-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK3-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP13]] to i1 +// CHECK3-NEXT: [[TMP14:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP14]]) +// CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK3-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK3: omp_offload.failed6: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK3: omp_offload.cont7: +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) +// CHECK3-NEXT: ret i32 [[CALL]] +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn4v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn5v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 +// CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 +// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: +// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn6v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK3-NEXT: ret i32 [[CALL]] +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64() #[[ATTR2]] +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK3-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK3-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK3-NEXT: store i64 [[TMP4]], i64* [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK3-NEXT: store i64 [[TMP4]], i64* [[TMP8]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP12]] to i1 +// CHECK3-NEXT: [[TMP13:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.region_id, i32 1, i8** [[TMP10]], i8** [[TMP11]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP13]]) +// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK3-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK3: omp_offload.failed5: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68(i64 [[TMP4]]) #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK3: omp_offload.cont6: +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn1v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn2v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 +// CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 +// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: +// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn3v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: ret i32 0 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK3-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK3-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 +// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z9gtid_testv() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: () #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83() #[[ATTR2]] +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK4-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK4-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP5]] to i1 +// CHECK4-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK4-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK4-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK4-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP13]] to i1 +// CHECK4-NEXT: [[TMP14:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP14]]) +// CHECK4-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK4-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK4: omp_offload.failed6: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK4: omp_offload.cont7: +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) +// CHECK4-NEXT: ret i32 [[CALL]] +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn4v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn5v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 +// CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 +// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: +// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn6v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK4-NEXT: ret i32 [[CALL]] +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64() #[[ATTR2]] +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK4-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK4-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK4-NEXT: store i64 [[TMP4]], i64* [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK4-NEXT: store i64 [[TMP4]], i64* [[TMP8]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP12]] to i1 +// CHECK4-NEXT: [[TMP13:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.region_id, i32 1, i8** [[TMP10]], i8** [[TMP11]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP13]]) +// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK4-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK4: omp_offload.failed5: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68(i64 [[TMP4]]) #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK4: omp_offload.cont6: +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn1v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn2v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 +// CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 +// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: +// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn3v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: ret i32 0 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK4-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK4-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv @@ -5726,6261 +8052,2647 @@ // CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK7: omp_offload.failed2: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK7: omp_offload.cont3: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 +// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z9gtid_testv() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end7: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83() #[[ATTR2]] +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK7-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK7-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP5]] to i1 +// CHECK7-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK7-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK7-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP13]] to i1 +// CHECK7-NEXT: [[TMP14:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP14]]) +// CHECK7-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK7-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK7: omp_offload.failed6: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK7: omp_offload.cont7: +// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.else: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) +// CHECK7-NEXT: ret i32 [[CALL]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn4v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn5v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 +// CHECK7-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: +// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.else: +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn6v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64() #[[ATTR2]] +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK7-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK7-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK7-NEXT: store i64 [[TMP4]], i64* [[TMP6]], align 8 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK7-NEXT: store i64 [[TMP4]], i64* [[TMP8]], align 8 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP12]] to i1 +// CHECK7-NEXT: [[TMP13:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.region_id, i32 1, i8** [[TMP10]], i8** [[TMP11]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP13]]) +// CHECK7-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK7-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK7: omp_offload.failed5: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68(i64 [[TMP4]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK7: omp_offload.cont6: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn1v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn2v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 +// CHECK7-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: +// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.else: +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn3v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK8: omp_offload.failed2: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK8: omp_offload.cont3: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 +// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z9gtid_testv() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end7: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83() #[[ATTR2]] +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK8-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK8-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP5]] to i1 +// CHECK8-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK8-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK8-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP13]] to i1 +// CHECK8-NEXT: [[TMP14:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP14]]) +// CHECK8-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK8-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK8: omp_offload.failed6: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK8: omp_offload.cont7: +// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.else: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) +// CHECK8-NEXT: ret i32 [[CALL]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn4v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn5v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 +// CHECK8-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK8-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: +// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.else: +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn6v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64() #[[ATTR2]] +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK8-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK8-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK8-NEXT: store i64 [[TMP4]], i64* [[TMP6]], align 8 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK8-NEXT: store i64 [[TMP4]], i64* [[TMP8]], align 8 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP12]] to i1 +// CHECK8-NEXT: [[TMP13:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.region_id, i32 1, i8** [[TMP10]], i8** [[TMP11]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP13]]) +// CHECK8-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK8-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK8: omp_offload.failed5: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68(i64 [[TMP4]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK8: omp_offload.cont6: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn1v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn2v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 +// CHECK8-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK8-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: +// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.else: +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn3v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: ret i32 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK9: omp_offload.failed2: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK9: omp_offload.cont3: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 -// CHECK9-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z9gtid_testv() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83() #[[ATTR2]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK9-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP5]] to i1 -// CHECK9-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK9: omp_if.then: -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP13]] to i1 -// CHECK9-NEXT: [[TMP14:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP14]]) -// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK9-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK9: omp_offload.failed6: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK9: omp_offload.cont7: -// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK9: omp_if.else: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_IF_END]] -// CHECK9: omp_if.end: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn4v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn5v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_IF_END]] -// CHECK9: omp_if.end: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn6v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64() #[[ATTR2]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK9-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP12]] to i1 -// CHECK9-NEXT: [[TMP13:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.region_id, i32 1, i8** [[TMP10]], i8** [[TMP11]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP13]]) -// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK9-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK9: omp_offload.failed5: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68(i64 [[TMP4]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK9: omp_offload.cont6: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn1v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn2v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_IF_END]] -// CHECK9: omp_if.end: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn3v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK10: omp_offload.failed2: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK10: omp_offload.cont3: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 -// CHECK10-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z9gtid_testv() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83() #[[ATTR2]] -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK10-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP5]] to i1 -// CHECK10-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK10: omp_if.then: -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP13]] to i1 -// CHECK10-NEXT: [[TMP14:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP14]]) -// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK10-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK10: omp_offload.failed6: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK10: omp_offload.cont7: -// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK10: omp_if.else: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_IF_END]] -// CHECK10: omp_if.end: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn4v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn5v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_IF_END]] -// CHECK10: omp_if.end: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn6v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK10-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64() #[[ATTR2]] -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK10-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP12]] to i1 -// CHECK10-NEXT: [[TMP13:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.region_id, i32 1, i8** [[TMP10]], i8** [[TMP11]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP13]]) -// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK10-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK10: omp_offload.failed5: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68(i64 [[TMP4]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK10: omp_offload.cont6: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn1v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn2v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_IF_END]] -// CHECK10: omp_if.end: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn3v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z9gtid_testv() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn4v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn5v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn6v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK11-NEXT: ret i32 [[CALL]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK11-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn1v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn2v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn3v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z9gtid_testv() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn4v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn5v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn6v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK12-NEXT: ret i32 [[CALL]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK12-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn1v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn2v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn3v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK13: omp_offload.failed2: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK13: omp_offload.cont3: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 -// CHECK13-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z9gtid_testv() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83() #[[ATTR2]] -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK13-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP5]] to i1 -// CHECK13-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK13: omp_if.then: -// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK13-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP13]] to i1 -// CHECK13-NEXT: [[TMP14:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP14]]) -// CHECK13-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK13-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK13: omp_offload.failed6: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK13: omp_offload.cont7: -// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK13: omp_if.else: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_IF_END]] -// CHECK13: omp_if.end: -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) -// CHECK13-NEXT: ret i32 [[CALL]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn4v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn5v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 -// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK13: omp_if.then: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK13: omp_if.else: -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_IF_END]] -// CHECK13: omp_if.end: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn6v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK13-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64() #[[ATTR2]] -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK13-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[TMP6]], align 8 -// CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[TMP8]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK13-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP12]] to i1 -// CHECK13-NEXT: [[TMP13:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.region_id, i32 1, i8** [[TMP10]], i8** [[TMP11]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP13]]) -// CHECK13-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK13-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK13: omp_offload.failed5: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68(i64 [[TMP4]]) #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK13: omp_offload.cont6: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn1v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn2v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 -// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK13: omp_if.then: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK13: omp_if.else: -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_IF_END]] -// CHECK13: omp_if.end: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn3v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK13-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK14: omp_offload.failed2: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK14: omp_offload.cont3: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 -// CHECK14-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z9gtid_testv() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83() #[[ATTR2]] -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK14-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 -// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP5]] to i1 -// CHECK14-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK14: omp_if.then: -// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK14-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP13]] to i1 -// CHECK14-NEXT: [[TMP14:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP14]]) -// CHECK14-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK14-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK14: omp_offload.failed6: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK14: omp_offload.cont7: -// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK14: omp_if.else: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90(i64 [[TMP4]]) #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_IF_END]] -// CHECK14: omp_if.end: -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) -// CHECK14-NEXT: ret i32 [[CALL]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn4v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn5v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 -// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK14: omp_if.then: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK14: omp_if.else: -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_IF_END]] -// CHECK14: omp_if.end: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn6v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK14-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64() #[[ATTR2]] -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK14-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 -// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[TMP6]], align 8 -// CHECK14-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[TMP8]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK14-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP12]] to i1 -// CHECK14-NEXT: [[TMP13:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.region_id, i32 1, i8** [[TMP10]], i8** [[TMP11]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP13]]) -// CHECK14-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK14-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK14: omp_offload.failed5: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68(i64 [[TMP4]]) #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK14: omp_offload.cont6: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn1v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn2v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 -// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK14: omp_if.then: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK14: omp_if.else: -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_IF_END]] -// CHECK14: omp_if.end: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn3v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK14-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z9gtid_testv() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn4v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn5v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn6v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK15-NEXT: ret i32 [[CALL]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK15-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn1v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn2v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn3v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z9gtid_testv() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn4v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn5v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn6v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK16-NEXT: ret i32 [[CALL]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK16-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn1v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn2v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn3v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: ret i32 0 +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp @@ -13,19 +13,19 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -5370,1163 +5370,3 @@ // CHECK8-NEXT: call void @__tgt_register_requires(i64 1) // CHECK8-NEXT: ret void // -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK9-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK10-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK11-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK12-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK12-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done4: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done3: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done3: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done3: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done2: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done3: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done2: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // REQUIRES: powerpc-registered-target // expected-no-diagnostics @@ -338,45 +338,3 @@ // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret void -// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp @@ -10,40 +10,40 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK22 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -3534,233 +3534,475 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done3: // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 +// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] +// CHECK7-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done8: // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK7-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done4: -// CHECK7-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done5: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK7-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK7-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done8: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK7: arraydestroy.body10: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK7: arraydestroy.done14: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP11]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done9: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev @@ -3785,56 +4027,6 @@ // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: @@ -3847,22 +4039,6 @@ // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: @@ -3872,242 +4048,475 @@ // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done3: // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 +// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] +// CHECK8-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done8: // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done4: -// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done5: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK8-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done8: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK8: arraydestroy.body10: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK8: arraydestroy.done14: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP11]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done9: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev @@ -4132,325 +4541,484 @@ // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK9: arrayctor.loop: +// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK9: arrayctor.cont: +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK9: omp.inner.for.cond.cleanup: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 +// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK9: arraydestroy.body: +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done3: // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK9: arrayctor.loop: +// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK9: arrayctor.cont: +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK9: omp.inner.for.cond.cleanup: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* +// CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 +// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK9: arraydestroy.body: +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done6: // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK9-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK9: omp.inner.for.cond.cleanup: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: ret i32 [[CALL]] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done5: +// CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK9: omp.inner.for.cond.cleanup: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK9-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done7: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK9: arraydestroy.body9: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK9: arraydestroy.done13: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP11]] +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev @@ -4475,56 +5043,6 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: @@ -4537,22 +5055,6 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: @@ -4562,238 +5064,463 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init() -// CHECK9-NEXT: call void @__cxx_global_var_init.1() -// CHECK9-NEXT: call void @__cxx_global_var_init.2() -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK10: arrayctor.loop: +// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK10: arrayctor.cont: +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK10: omp.inner.for.cond.cleanup: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK10-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 +// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK10: arraydestroy.body: +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK10: arraydestroy.done3: // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK10: arrayctor.loop: +// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK10: arrayctor.cont: +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK10: omp.inner.for.cond.cleanup: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* +// CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 +// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK10: arraydestroy.body: +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] +// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK10: arraydestroy.done6: // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK10-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK10-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK10: omp.inner.for.cond.cleanup: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: ret i32 [[CALL]] +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK10: arraydestroy.done5: +// CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK10-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK10: omp.inner.for.cond.cleanup: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK10-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done7: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK10: arraydestroy.body9: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK10: arraydestroy.done13: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP11]] +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev @@ -4818,56 +5545,6 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: @@ -4880,22 +5557,6 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: @@ -4905,3983 +5566,166 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__cxx_global_var_init() -// CHECK10-NEXT: call void @__cxx_global_var_init.1() -// CHECK10-NEXT: call void @__cxx_global_var_init.2() -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32* undef, i32** [[_TMP1]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK11-NEXT: store i32* undef, i32** [[_TMP1]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK11-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK11-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK11-NEXT: store i32 2, i32* [[SIVAR]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 +// CHECK11-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK11-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 +// CHECK11-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 +// CHECK11-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK11-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK13: omp.inner.for.cond.cleanup: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done3: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK13: omp.inner.for.cond.cleanup: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK13-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done8: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK13: omp.inner.for.cond.cleanup: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK13: omp.inner.for.cond.cleanup: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK13-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK13-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done9: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK13-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK14: omp.inner.for.cond.cleanup: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done3: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK14: omp.inner.for.cond.cleanup: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK14-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done8: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK14: omp.inner.for.cond.cleanup: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK14: omp.inner.for.cond.cleanup: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK14-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK14-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done9: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK14-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK15: cond.true: -// CHECK15-NEXT: br label [[COND_END:%.*]] -// CHECK15: cond.false: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: br label [[COND_END]] -// CHECK15: cond.end: -// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK15: omp.inner.for.cond.cleanup: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) -// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK15: omp.inner.for.end: -// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done3: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK15: cond.true: -// CHECK15-NEXT: br label [[COND_END:%.*]] -// CHECK15: cond.false: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: br label [[COND_END]] -// CHECK15: cond.end: -// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK15: omp.inner.for.cond.cleanup: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] -// CHECK15-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK15-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK15-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 -// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK15: omp.body.continue: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK15: omp.inner.for.end: -// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done6: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 -// CHECK15-SAME: () #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK15-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK15: cond.true: -// CHECK15-NEXT: br label [[COND_END:%.*]] -// CHECK15: cond.false: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: br label [[COND_END]] -// CHECK15: cond.end: -// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK15: omp.inner.for.cond.cleanup: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) -// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK15: omp.inner.for.end: -// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done5: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK15: cond.true: -// CHECK15-NEXT: br label [[COND_END:%.*]] -// CHECK15: cond.false: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: br label [[COND_END]] -// CHECK15: cond.end: -// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK15: omp.inner.for.cond.cleanup: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] -// CHECK15-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK15-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) -// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK15: omp.body.continue: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK15-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK15: omp.inner.for.end: -// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK15-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK16: cond.true: -// CHECK16-NEXT: br label [[COND_END:%.*]] -// CHECK16: cond.false: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: br label [[COND_END]] -// CHECK16: cond.end: -// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK16: omp.inner.for.cond.cleanup: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) -// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK16: omp.inner.for.end: -// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK16: omp.loop.exit: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK16-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done3: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK16: cond.true: -// CHECK16-NEXT: br label [[COND_END:%.*]] -// CHECK16: cond.false: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: br label [[COND_END]] -// CHECK16: cond.end: -// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK16: omp.inner.for.cond.cleanup: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] -// CHECK16-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK16-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK16-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 -// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK16: omp.body.continue: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK16: omp.inner.for.end: -// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK16: omp.loop.exit: -// CHECK16-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done6: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 -// CHECK16-SAME: () #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK16-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK16: cond.true: -// CHECK16-NEXT: br label [[COND_END:%.*]] -// CHECK16: cond.false: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: br label [[COND_END]] -// CHECK16: cond.end: -// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK16-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK16: omp.inner.for.cond.cleanup: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) -// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK16: omp.inner.for.end: -// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK16: omp.loop.exit: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done5: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK16-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK16: cond.true: -// CHECK16-NEXT: br label [[COND_END:%.*]] -// CHECK16: cond.false: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: br label [[COND_END]] -// CHECK16: cond.end: -// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK16-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK16: omp.inner.for.cond.cleanup: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] -// CHECK16-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK16-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) -// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK16: omp.body.continue: -// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK16-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK16: omp.inner.for.end: -// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK16: omp.loop.exit: -// CHECK16-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK16-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* undef, i32** [[_TMP1]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i32* undef, i32** [[_TMP1]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 -// CHECK17-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK17-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK17-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 -// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done1: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK18-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK18-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK18-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK18-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK18-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK18: arrayctor.loop: -// CHECK18-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK18-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK18-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK18-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK18: arrayctor.cont: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND:%.*]] -// CHECK18: for.cond: -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK18-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK18: for.body: -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK18-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK18-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK18-NEXT: br label [[FOR_INC:%.*]] -// CHECK18: for.inc: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK18: for.end: -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done4: -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK18-NEXT: ret i32 [[CALL]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK18-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK18-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK18-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK18-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK18-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK18-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK18-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK18-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK18-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK18-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK18-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK18-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK18: arrayctor.loop: -// CHECK18-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK18-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK18-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK18-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK18: arrayctor.cont: -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK18-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND:%.*]] -// CHECK18: for.cond: -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK18-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK18: for.body: -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK18-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK18-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK18-NEXT: br label [[FOR_INC:%.*]] -// CHECK18: for.inc: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK18: for.end: -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done8: -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK18: arraydestroy.body10: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK18: arraydestroy.done14: -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: ret i32 [[TMP11]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK18-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK18-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK18-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK18-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK18-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__cxx_global_var_init() -// CHECK18-NEXT: call void @__cxx_global_var_init.1() -// CHECK18-NEXT: call void @__cxx_global_var_init.2() -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK19-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK19-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK19: arraydestroy.body: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK19: arraydestroy.done1: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK19-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK19-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK19-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK19-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK19-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK19: arrayctor.loop: -// CHECK19-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK19-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK19-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK19-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK19: arrayctor.cont: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND:%.*]] -// CHECK19: for.cond: -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK19-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK19: for.body: -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK19-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK19-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK19-NEXT: br label [[FOR_INC:%.*]] -// CHECK19: for.inc: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK19: for.end: -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK19: arraydestroy.body: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK19: arraydestroy.done4: -// CHECK19-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK19-NEXT: ret i32 [[CALL]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK19-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK19-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK19-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK19-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK19-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK19-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK19-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK19-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK19-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK19-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK19-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK19-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK19: arrayctor.loop: -// CHECK19-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK19-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK19-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK19-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK19: arrayctor.cont: -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK19-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND:%.*]] -// CHECK19: for.cond: -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK19-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK19: for.body: -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK19-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK19-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK19-NEXT: br label [[FOR_INC:%.*]] -// CHECK19: for.inc: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK19: for.end: -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK19: arraydestroy.body: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK19: arraydestroy.done8: -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK19: arraydestroy.body10: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK19: arraydestroy.done14: -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: ret i32 [[TMP11]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK19-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK19-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK19-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK19-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK19-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__cxx_global_var_init() -// CHECK19-NEXT: call void @__cxx_global_var_init.1() -// CHECK19-NEXT: call void @__cxx_global_var_init.2() -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK20-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK20: arraydestroy.body: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK20: arraydestroy.done1: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK20-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK20-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK20-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK20-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK20: arrayctor.loop: -// CHECK20-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK20-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK20-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK20-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK20: arrayctor.cont: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND:%.*]] -// CHECK20: for.cond: -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK20-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK20: for.body: -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK20-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK20-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK20-NEXT: br label [[FOR_INC:%.*]] -// CHECK20: for.inc: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK20: for.end: -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK20: arraydestroy.body: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK20: arraydestroy.done3: -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK20-NEXT: ret i32 [[CALL]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK20-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK20-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK20-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK20-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK20-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK20-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK20-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK20-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK20-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK20-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK20-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK20-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK20: arrayctor.loop: -// CHECK20-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK20-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK20-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK20-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK20: arrayctor.cont: -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK20-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND:%.*]] -// CHECK20: for.cond: -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK20-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK20: for.body: -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK20-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK20-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK20-NEXT: br label [[FOR_INC:%.*]] -// CHECK20: for.inc: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK20: for.end: -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK20: arraydestroy.body: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK20: arraydestroy.done7: -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK20: arraydestroy.body9: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK20: arraydestroy.done13: -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: ret i32 [[TMP11]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK20-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK20-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK20-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK20-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK20-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__cxx_global_var_init() -// CHECK20-NEXT: call void @__cxx_global_var_init.1() -// CHECK20-NEXT: call void @__cxx_global_var_init.2() -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK21-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK21-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done1: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@main -// CHECK21-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK21-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK21-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK21-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK21-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK21: arrayctor.loop: -// CHECK21-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK21-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK21-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK21-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK21: arrayctor.cont: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK21-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK21-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK21-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done3: -// CHECK21-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK21-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK21-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK21-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK21-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK21-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK21-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK21-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK21-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK21-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK21-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK21-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK21-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK21-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK21: arrayctor.loop: -// CHECK21-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK21-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK21-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK21-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK21: arrayctor.cont: -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK21-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK21-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK21-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK21-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done7: -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK21: arraydestroy.body9: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK21: arraydestroy.done13: -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: ret i32 [[TMP11]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK21-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK21-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK21-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK21-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK21-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @__cxx_global_var_init() -// CHECK21-NEXT: call void @__cxx_global_var_init.1() -// CHECK21-NEXT: call void @__cxx_global_var_init.2() -// CHECK21-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK22-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK22-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK22: arraydestroy.body: -// CHECK22-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK22-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK22-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK22-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK22-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK22: arraydestroy.done1: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@main -// CHECK22-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK22-NEXT: ret i32 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK22-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK22-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK22-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK22-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @__cxx_global_var_init() -// CHECK22-NEXT: call void @__cxx_global_var_init.1() -// CHECK22-NEXT: call void @__cxx_global_var_init.2() -// CHECK22-NEXT: ret void -// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp @@ -5,9 +5,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -973,123 +973,3 @@ // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret i32 0 -// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp @@ -10,16 +10,16 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2859,255 +2859,3 @@ // CHECK6-NEXT: call void @__tgt_register_requires(i64 1) // CHECK6-NEXT: ret void // -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK9-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK10-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1898,62 +1898,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG22:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG22]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG23:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG24:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG26:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG27:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG30:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG30]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG30]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG31:![0-9]+]], !llvm.loop [[LOOP32:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG35:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG35]] -// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp @@ -18,12 +18,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 @@ -83,26 +83,26 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -7402,474 +7402,9878 @@ // CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@main +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK9-NEXT: ret i32 [[CALL]] +// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK9-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 +// CHECK9-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED35:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS37:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS38:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS39:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES40:%.*]] = alloca [3 x i64], align 8 +// CHECK9-NEXT: [[_TMP41:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_42:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_43:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_50:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED51:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED53:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS55:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS56:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS57:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES58:%.*]] = alloca [4 x i64], align 8 +// CHECK9-NEXT: [[_TMP59:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_60:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK9-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK9-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK9-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK9-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK9-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK9-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK9-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) +// CHECK9-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK9-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK9: omp_offload.failed16: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK9: omp_offload.cont17: +// CHECK9-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 +// CHECK9-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK9-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* +// CHECK9-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 +// CHECK9-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 +// CHECK9-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK9-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 +// CHECK9-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK9-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* +// CHECK9-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 +// CHECK9-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* +// CHECK9-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 +// CHECK9-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP73]], align 8 +// CHECK9-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP74]], align 8 +// CHECK9-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 +// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 +// CHECK9-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 +// CHECK9-NEXT: store i64 8, i64* [[TMP79]], align 8 +// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP80]], align 8 +// CHECK9-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 +// CHECK9-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 +// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 +// CHECK9-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 +// CHECK9-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP86]], align 8 +// CHECK9-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* +// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 +// CHECK9-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* +// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 +// CHECK9-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 +// CHECK9-NEXT: store i64 4, i64* [[TMP91]], align 8 +// CHECK9-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP92]], align 8 +// CHECK9-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK9-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 +// CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK9-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 +// CHECK9-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK9-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK9-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 +// CHECK9-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP99]]) +// CHECK9-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 +// CHECK9-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK9: omp_offload.failed33: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK9: omp_offload.cont34: +// CHECK9-NEXT: [[TMP102:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[CONV36:%.*]] = bitcast i64* [[N_CASTED35]] to i32* +// CHECK9-NEXT: store i32 [[TMP102]], i32* [[CONV36]], align 4 +// CHECK9-NEXT: [[TMP103:%.*]] = load i64, i64* [[N_CASTED35]], align 8 +// CHECK9-NEXT: [[TMP104:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK9-NEXT: [[TMP105:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to i64* +// CHECK9-NEXT: store i64 [[TMP103]], i64* [[TMP106]], align 8 +// CHECK9-NEXT: [[TMP107:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* +// CHECK9-NEXT: store i64 [[TMP103]], i64* [[TMP108]], align 8 +// CHECK9-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP109]], align 8 +// CHECK9-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP110]], align 8 +// CHECK9-NEXT: [[TMP111:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP112]], align 8 +// CHECK9-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP114]], align 8 +// CHECK9-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 1 +// CHECK9-NEXT: store i64 8, i64* [[TMP115]], align 8 +// CHECK9-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP116]], align 8 +// CHECK9-NEXT: [[TMP117:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP118]], align 8 +// CHECK9-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP120]], align 8 +// CHECK9-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 2 +// CHECK9-NEXT: store i64 [[TMP104]], i64* [[TMP121]], align 8 +// CHECK9-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP122]], align 8 +// CHECK9-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP126:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP126]], i32* [[DOTCAPTURE_EXPR_42]], align 4 +// CHECK9-NEXT: [[TMP127:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_42]], align 4 +// CHECK9-NEXT: [[SUB44:%.*]] = sub nsw i32 [[TMP127]], 0 +// CHECK9-NEXT: [[DIV45:%.*]] = sdiv i32 [[SUB44]], 1 +// CHECK9-NEXT: [[SUB46:%.*]] = sub nsw i32 [[DIV45]], 1 +// CHECK9-NEXT: store i32 [[SUB46]], i32* [[DOTCAPTURE_EXPR_43]], align 4 +// CHECK9-NEXT: [[TMP128:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_43]], align 4 +// CHECK9-NEXT: [[ADD47:%.*]] = add nsw i32 [[TMP128]], 1 +// CHECK9-NEXT: [[TMP129:%.*]] = zext i32 [[ADD47]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP129]]) +// CHECK9-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151.region_id, i32 3, i8** [[TMP123]], i8** [[TMP124]], i64* [[TMP125]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0 +// CHECK9-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED48:%.*]], label [[OMP_OFFLOAD_CONT49:%.*]] +// CHECK9: omp_offload.failed48: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151(i64 [[TMP103]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT49]] +// CHECK9: omp_offload.cont49: +// CHECK9-NEXT: [[TMP132:%.*]] = load i32, i32* [[M]], align 4 +// CHECK9-NEXT: store i32 [[TMP132]], i32* [[DOTCAPTURE_EXPR_50]], align 4 +// CHECK9-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[CONV52:%.*]] = bitcast i64* [[N_CASTED51]] to i32* +// CHECK9-NEXT: store i32 [[TMP133]], i32* [[CONV52]], align 4 +// CHECK9-NEXT: [[TMP134:%.*]] = load i64, i64* [[N_CASTED51]], align 8 +// CHECK9-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_50]], align 4 +// CHECK9-NEXT: [[CONV54:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED53]] to i32* +// CHECK9-NEXT: store i32 [[TMP135]], i32* [[CONV54]], align 4 +// CHECK9-NEXT: [[TMP136:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED53]], align 8 +// CHECK9-NEXT: [[TMP137:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK9-NEXT: [[TMP138:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to i64* +// CHECK9-NEXT: store i64 [[TMP134]], i64* [[TMP139]], align 8 +// CHECK9-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i64* +// CHECK9-NEXT: store i64 [[TMP134]], i64* [[TMP141]], align 8 +// CHECK9-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP142]], align 8 +// CHECK9-NEXT: [[TMP143:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP143]], align 8 +// CHECK9-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP145]], align 8 +// CHECK9-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP147]], align 8 +// CHECK9-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 1 +// CHECK9-NEXT: store i64 8, i64* [[TMP148]], align 8 +// CHECK9-NEXT: [[TMP149:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP149]], align 8 +// CHECK9-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP151]], align 8 +// CHECK9-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP153]], align 8 +// CHECK9-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 2 +// CHECK9-NEXT: store i64 [[TMP137]], i64* [[TMP154]], align 8 +// CHECK9-NEXT: [[TMP155:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP155]], align 8 +// CHECK9-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* +// CHECK9-NEXT: store i64 [[TMP136]], i64* [[TMP157]], align 8 +// CHECK9-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* +// CHECK9-NEXT: store i64 [[TMP136]], i64* [[TMP159]], align 8 +// CHECK9-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 3 +// CHECK9-NEXT: store i64 4, i64* [[TMP160]], align 8 +// CHECK9-NEXT: [[TMP161:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP161]], align 8 +// CHECK9-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP163:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP165:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP165]], i32* [[DOTCAPTURE_EXPR_60]], align 4 +// CHECK9-NEXT: [[TMP166:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_60]], align 4 +// CHECK9-NEXT: [[SUB62:%.*]] = sub nsw i32 [[TMP166]], 0 +// CHECK9-NEXT: [[DIV63:%.*]] = sdiv i32 [[SUB62]], 1 +// CHECK9-NEXT: [[SUB64:%.*]] = sub nsw i32 [[DIV63]], 1 +// CHECK9-NEXT: store i32 [[SUB64]], i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK9-NEXT: [[TMP167:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK9-NEXT: [[ADD65:%.*]] = add nsw i32 [[TMP167]], 1 +// CHECK9-NEXT: [[TMP168:%.*]] = zext i32 [[ADD65]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP168]]) +// CHECK9-NEXT: [[TMP169:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155.region_id, i32 4, i8** [[TMP162]], i8** [[TMP163]], i64* [[TMP164]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP170:%.*]] = icmp ne i32 [[TMP169]], 0 +// CHECK9-NEXT: br i1 [[TMP170]], label [[OMP_OFFLOAD_FAILED66:%.*]], label [[OMP_OFFLOAD_CONT67:%.*]] +// CHECK9: omp_offload.failed66: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP134]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP136]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT67]] +// CHECK9: omp_offload.cont67: +// CHECK9-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) +// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK9-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) +// CHECK9-NEXT: [[TMP173:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK9-NEXT: ret i32 [[TMP173]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK9-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] +// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] +// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP30]], [[TMP31]] +// CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] +// CHECK9: cond.true14: +// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: br label [[COND_END16:%.*]] +// CHECK9: cond.false15: +// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END16]] +// CHECK9: cond.end16: +// CHECK9-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE14]] ], [ [[TMP33]], [[COND_FALSE15]] ] +// CHECK9-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK9-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 35, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[I7]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK9-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK9: omp_offload.failed5: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK9: omp_offload.cont6: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK9-NEXT: store i64 [[TMP20]], i64* [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK9-NEXT: store i64 [[TMP20]], i64* [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK9-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK9: omp_offload.failed11: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120([10 x i32]* [[A]], i64 [[TMP20]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK9: omp_offload.cont12: +// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP36]], align 8 +// CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP38]], align 8 +// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124.region_id, i32 1, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK9-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK9: omp_offload.failed17: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK9: omp_offload.cont18: +// CHECK9-NEXT: [[TMP44:%.*]] = load i32, i32* [[M]], align 4 +// CHECK9-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_19]], align 4 +// CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 +// CHECK9-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED20]] to i32* +// CHECK9-NEXT: store i32 [[TMP45]], i32* [[CONV21]], align 4 +// CHECK9-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED20]], align 8 +// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP48]], align 8 +// CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP50]], align 8 +// CHECK9-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP51]], align 8 +// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* +// CHECK9-NEXT: store i64 [[TMP46]], i64* [[TMP53]], align 8 +// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i64* +// CHECK9-NEXT: store i64 [[TMP46]], i64* [[TMP55]], align 8 +// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP56]], align 8 +// CHECK9-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128.region_id, i32 2, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 +// CHECK9-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED26:%.*]], label [[OMP_OFFLOAD_CONT27:%.*]] +// CHECK9: omp_offload.failed26: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128([10 x i32]* [[A]], i64 [[TMP46]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT27]] +// CHECK9: omp_offload.cont27: +// CHECK9-NEXT: ret i32 0 +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I22:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I32:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3:%.*]] -// CHECK9: for.cond3: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK9-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK9: for.body5: -// CHECK9-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK9-NEXT: br label [[FOR_INC9:%.*]] -// CHECK9: for.inc9: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK9-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK9: for.end11: -// CHECK9-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK9-NEXT: br label [[FOR_COND13:%.*]] -// CHECK9: for.cond13: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK9-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK9: for.body15: -// CHECK9-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK9-NEXT: br label [[FOR_INC19:%.*]] -// CHECK9: for.inc19: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK9-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end21: -// CHECK9-NEXT: store i32 0, i32* [[I22]], align 4 -// CHECK9-NEXT: br label [[FOR_COND23:%.*]] -// CHECK9: for.cond23: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[CMP24:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK9-NEXT: br i1 [[CMP24]], label [[FOR_BODY25:%.*]], label [[FOR_END31:%.*]] -// CHECK9: for.body25: -// CHECK9-NEXT: [[A26:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[IDXPROM27:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A26]], i64 0, i64 [[IDXPROM27]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX28]], align 4 -// CHECK9-NEXT: br label [[FOR_INC29:%.*]] -// CHECK9: for.inc29: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK9-NEXT: store i32 [[INC30]], i32* [[I22]], align 4 -// CHECK9-NEXT: br label [[FOR_COND23]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK9: for.end31: -// CHECK9-NEXT: store i32 0, i32* [[I32]], align 4 -// CHECK9-NEXT: br label [[FOR_COND33:%.*]] -// CHECK9: for.cond33: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[CMP34:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK9-NEXT: br i1 [[CMP34]], label [[FOR_BODY35:%.*]], label [[FOR_END41:%.*]] -// CHECK9: for.body35: -// CHECK9-NEXT: [[A36:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A36]], i64 0, i64 [[IDXPROM37]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK9-NEXT: br label [[FOR_INC39:%.*]] -// CHECK9: for.inc39: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[INC40:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[INC40]], i32* [[I32]], align 4 -// CHECK9-NEXT: br label [[FOR_COND33]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK9: for.end41: -// CHECK9-NEXT: [[A42:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A42]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX43]], align 4 -// CHECK9-NEXT: ret i32 [[TMP15]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK10-NEXT: ret i32 [[CALL]] +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..21 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[CONV3]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CONV4:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ] +// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[COND]] to i32 +// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..25 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@main +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK10-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 +// CHECK10-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED35:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS37:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS38:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS39:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES40:%.*]] = alloca [3 x i64], align 8 +// CHECK10-NEXT: [[_TMP41:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_42:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_43:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_50:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED51:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED53:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS55:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS56:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS57:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES58:%.*]] = alloca [4 x i64], align 8 +// CHECK10-NEXT: [[_TMP59:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_60:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK10-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK10-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK10-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK10-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK10-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK10-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK10-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) +// CHECK10-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK10-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK10: omp_offload.failed16: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK10: omp_offload.cont17: +// CHECK10-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 +// CHECK10-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK10-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* +// CHECK10-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 +// CHECK10-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 +// CHECK10-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK10-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 +// CHECK10-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK10-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* +// CHECK10-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 +// CHECK10-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* +// CHECK10-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 +// CHECK10-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP73]], align 8 +// CHECK10-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP74]], align 8 +// CHECK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 +// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 +// CHECK10-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 +// CHECK10-NEXT: store i64 8, i64* [[TMP79]], align 8 +// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP80]], align 8 +// CHECK10-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 +// CHECK10-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 +// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 +// CHECK10-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 +// CHECK10-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP86]], align 8 +// CHECK10-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* +// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 +// CHECK10-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* +// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 +// CHECK10-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 +// CHECK10-NEXT: store i64 4, i64* [[TMP91]], align 8 +// CHECK10-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP92]], align 8 +// CHECK10-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK10-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 +// CHECK10-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK10-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 +// CHECK10-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK10-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 +// CHECK10-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 +// CHECK10-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP99]]) +// CHECK10-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 +// CHECK10-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK10: omp_offload.failed33: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK10: omp_offload.cont34: +// CHECK10-NEXT: [[TMP102:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[CONV36:%.*]] = bitcast i64* [[N_CASTED35]] to i32* +// CHECK10-NEXT: store i32 [[TMP102]], i32* [[CONV36]], align 4 +// CHECK10-NEXT: [[TMP103:%.*]] = load i64, i64* [[N_CASTED35]], align 8 +// CHECK10-NEXT: [[TMP104:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK10-NEXT: [[TMP105:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to i64* +// CHECK10-NEXT: store i64 [[TMP103]], i64* [[TMP106]], align 8 +// CHECK10-NEXT: [[TMP107:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* +// CHECK10-NEXT: store i64 [[TMP103]], i64* [[TMP108]], align 8 +// CHECK10-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP109]], align 8 +// CHECK10-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP110]], align 8 +// CHECK10-NEXT: [[TMP111:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP112]], align 8 +// CHECK10-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP114]], align 8 +// CHECK10-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 1 +// CHECK10-NEXT: store i64 8, i64* [[TMP115]], align 8 +// CHECK10-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP116]], align 8 +// CHECK10-NEXT: [[TMP117:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP118]], align 8 +// CHECK10-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP120]], align 8 +// CHECK10-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 2 +// CHECK10-NEXT: store i64 [[TMP104]], i64* [[TMP121]], align 8 +// CHECK10-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP122]], align 8 +// CHECK10-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP126:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP126]], i32* [[DOTCAPTURE_EXPR_42]], align 4 +// CHECK10-NEXT: [[TMP127:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_42]], align 4 +// CHECK10-NEXT: [[SUB44:%.*]] = sub nsw i32 [[TMP127]], 0 +// CHECK10-NEXT: [[DIV45:%.*]] = sdiv i32 [[SUB44]], 1 +// CHECK10-NEXT: [[SUB46:%.*]] = sub nsw i32 [[DIV45]], 1 +// CHECK10-NEXT: store i32 [[SUB46]], i32* [[DOTCAPTURE_EXPR_43]], align 4 +// CHECK10-NEXT: [[TMP128:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_43]], align 4 +// CHECK10-NEXT: [[ADD47:%.*]] = add nsw i32 [[TMP128]], 1 +// CHECK10-NEXT: [[TMP129:%.*]] = zext i32 [[ADD47]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP129]]) +// CHECK10-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151.region_id, i32 3, i8** [[TMP123]], i8** [[TMP124]], i64* [[TMP125]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0 +// CHECK10-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED48:%.*]], label [[OMP_OFFLOAD_CONT49:%.*]] +// CHECK10: omp_offload.failed48: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151(i64 [[TMP103]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT49]] +// CHECK10: omp_offload.cont49: +// CHECK10-NEXT: [[TMP132:%.*]] = load i32, i32* [[M]], align 4 +// CHECK10-NEXT: store i32 [[TMP132]], i32* [[DOTCAPTURE_EXPR_50]], align 4 +// CHECK10-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[CONV52:%.*]] = bitcast i64* [[N_CASTED51]] to i32* +// CHECK10-NEXT: store i32 [[TMP133]], i32* [[CONV52]], align 4 +// CHECK10-NEXT: [[TMP134:%.*]] = load i64, i64* [[N_CASTED51]], align 8 +// CHECK10-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_50]], align 4 +// CHECK10-NEXT: [[CONV54:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED53]] to i32* +// CHECK10-NEXT: store i32 [[TMP135]], i32* [[CONV54]], align 4 +// CHECK10-NEXT: [[TMP136:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED53]], align 8 +// CHECK10-NEXT: [[TMP137:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK10-NEXT: [[TMP138:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to i64* +// CHECK10-NEXT: store i64 [[TMP134]], i64* [[TMP139]], align 8 +// CHECK10-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i64* +// CHECK10-NEXT: store i64 [[TMP134]], i64* [[TMP141]], align 8 +// CHECK10-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP142]], align 8 +// CHECK10-NEXT: [[TMP143:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP143]], align 8 +// CHECK10-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP145]], align 8 +// CHECK10-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP147]], align 8 +// CHECK10-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 1 +// CHECK10-NEXT: store i64 8, i64* [[TMP148]], align 8 +// CHECK10-NEXT: [[TMP149:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP149]], align 8 +// CHECK10-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP151]], align 8 +// CHECK10-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP153]], align 8 +// CHECK10-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 2 +// CHECK10-NEXT: store i64 [[TMP137]], i64* [[TMP154]], align 8 +// CHECK10-NEXT: [[TMP155:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP155]], align 8 +// CHECK10-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* +// CHECK10-NEXT: store i64 [[TMP136]], i64* [[TMP157]], align 8 +// CHECK10-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* +// CHECK10-NEXT: store i64 [[TMP136]], i64* [[TMP159]], align 8 +// CHECK10-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 3 +// CHECK10-NEXT: store i64 4, i64* [[TMP160]], align 8 +// CHECK10-NEXT: [[TMP161:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP161]], align 8 +// CHECK10-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP163:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP165:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP165]], i32* [[DOTCAPTURE_EXPR_60]], align 4 +// CHECK10-NEXT: [[TMP166:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_60]], align 4 +// CHECK10-NEXT: [[SUB62:%.*]] = sub nsw i32 [[TMP166]], 0 +// CHECK10-NEXT: [[DIV63:%.*]] = sdiv i32 [[SUB62]], 1 +// CHECK10-NEXT: [[SUB64:%.*]] = sub nsw i32 [[DIV63]], 1 +// CHECK10-NEXT: store i32 [[SUB64]], i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK10-NEXT: [[TMP167:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 +// CHECK10-NEXT: [[ADD65:%.*]] = add nsw i32 [[TMP167]], 1 +// CHECK10-NEXT: [[TMP168:%.*]] = zext i32 [[ADD65]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP168]]) +// CHECK10-NEXT: [[TMP169:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155.region_id, i32 4, i8** [[TMP162]], i8** [[TMP163]], i64* [[TMP164]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP170:%.*]] = icmp ne i32 [[TMP169]], 0 +// CHECK10-NEXT: br i1 [[TMP170]], label [[OMP_OFFLOAD_FAILED66:%.*]], label [[OMP_OFFLOAD_CONT67:%.*]] +// CHECK10: omp_offload.failed66: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP134]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP136]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT67]] +// CHECK10: omp_offload.cont67: +// CHECK10-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) +// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK10-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) +// CHECK10-NEXT: [[TMP173:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK10-NEXT: ret i32 [[TMP173]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I22:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I32:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK10-NEXT: br label [[FOR_COND3:%.*]] -// CHECK10: for.cond3: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK10-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK10: for.body5: -// CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: br label [[FOR_INC9:%.*]] -// CHECK10: for.inc9: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK10-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK10-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK10: for.end11: -// CHECK10-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK10-NEXT: br label [[FOR_COND13:%.*]] -// CHECK10: for.cond13: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK10-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK10: for.body15: -// CHECK10-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK10-NEXT: br label [[FOR_INC19:%.*]] -// CHECK10: for.inc19: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK10-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end21: -// CHECK10-NEXT: store i32 0, i32* [[I22]], align 4 -// CHECK10-NEXT: br label [[FOR_COND23:%.*]] -// CHECK10: for.cond23: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[CMP24:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK10-NEXT: br i1 [[CMP24]], label [[FOR_BODY25:%.*]], label [[FOR_END31:%.*]] -// CHECK10: for.body25: -// CHECK10-NEXT: [[A26:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[IDXPROM27:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A26]], i64 0, i64 [[IDXPROM27]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX28]], align 4 -// CHECK10-NEXT: br label [[FOR_INC29:%.*]] -// CHECK10: for.inc29: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: store i32 [[INC30]], i32* [[I22]], align 4 -// CHECK10-NEXT: br label [[FOR_COND23]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK10: for.end31: -// CHECK10-NEXT: store i32 0, i32* [[I32]], align 4 -// CHECK10-NEXT: br label [[FOR_COND33:%.*]] -// CHECK10: for.cond33: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[CMP34:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK10-NEXT: br i1 [[CMP34]], label [[FOR_BODY35:%.*]], label [[FOR_END41:%.*]] -// CHECK10: for.body35: -// CHECK10-NEXT: [[A36:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A36]], i64 0, i64 [[IDXPROM37]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK10-NEXT: br label [[FOR_INC39:%.*]] -// CHECK10: for.inc39: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[INC40:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[INC40]], i32* [[I32]], align 4 -// CHECK10-NEXT: br label [[FOR_COND33]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK10: for.end41: -// CHECK10-NEXT: [[A42:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A42]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX43]], align 4 -// CHECK10-NEXT: ret i32 [[TMP15]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK11-NEXT: ret i32 [[CALL]] +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] +// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP30]], [[TMP31]] +// CHECK10-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] +// CHECK10: cond.true14: +// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: br label [[COND_END16:%.*]] +// CHECK10: cond.false15: +// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END16]] +// CHECK10: cond.end16: +// CHECK10-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE14]] ], [ [[TMP33]], [[COND_FALSE15]] ] +// CHECK10-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK10-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 35, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[I7]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK10-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK10-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK10: omp_offload.failed5: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK10: omp_offload.cont6: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK10-NEXT: store i64 [[TMP20]], i64* [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK10-NEXT: store i64 [[TMP20]], i64* [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK10-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK10: omp_offload.failed11: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120([10 x i32]* [[A]], i64 [[TMP20]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK10: omp_offload.cont12: +// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP36]], align 8 +// CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP38]], align 8 +// CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124.region_id, i32 1, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK10-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK10: omp_offload.failed17: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK10: omp_offload.cont18: +// CHECK10-NEXT: [[TMP44:%.*]] = load i32, i32* [[M]], align 4 +// CHECK10-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_19]], align 4 +// CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 +// CHECK10-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED20]] to i32* +// CHECK10-NEXT: store i32 [[TMP45]], i32* [[CONV21]], align 4 +// CHECK10-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED20]], align 8 +// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP48]], align 8 +// CHECK10-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP50]], align 8 +// CHECK10-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP51]], align 8 +// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* +// CHECK10-NEXT: store i64 [[TMP46]], i64* [[TMP53]], align 8 +// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i64* +// CHECK10-NEXT: store i64 [[TMP46]], i64* [[TMP55]], align 8 +// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP56]], align 8 +// CHECK10-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128.region_id, i32 2, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 +// CHECK10-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED26:%.*]], label [[OMP_OFFLOAD_CONT27:%.*]] +// CHECK10: omp_offload.failed26: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128([10 x i32]* [[A]], i64 [[TMP46]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT27]] +// CHECK10: omp_offload.cont27: +// CHECK10-NEXT: ret i32 0 +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..21 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[CONV3]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CONV4:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ] +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[COND]] to i32 +// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..25 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-LABEL: define {{[^@]+}}@main +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK11-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 +// CHECK11-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED32:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES36:%.*]] = alloca [3 x i64], align 4 +// CHECK11-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_46:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED47:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED48:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS49:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS50:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS51:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES52:%.*]] = alloca [4 x i64], align 4 +// CHECK11-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK11-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK11-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK11-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK11-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK11-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK11-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK11-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK11-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK11-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK11-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) +// CHECK11-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK11-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK11: omp_offload.failed15: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK11: omp_offload.cont16: +// CHECK11-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 +// CHECK11-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK11-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 +// CHECK11-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 +// CHECK11-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK11-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK11-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 +// CHECK11-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* +// CHECK11-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 +// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK11-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 +// CHECK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP75]], align 4 +// CHECK11-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP76]], align 4 +// CHECK11-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 +// CHECK11-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 +// CHECK11-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP81]], align 4 +// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK11-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 +// CHECK11-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 +// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 +// CHECK11-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 +// CHECK11-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP88]], align 4 +// CHECK11-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* +// CHECK11-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 +// CHECK11-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* +// CHECK11-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 +// CHECK11-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 +// CHECK11-NEXT: store i64 4, i64* [[TMP93]], align 4 +// CHECK11-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP94]], align 4 +// CHECK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK11-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK11-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 +// CHECK11-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// CHECK11-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 +// CHECK11-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK11-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK11-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 +// CHECK11-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP101]]) +// CHECK11-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 +// CHECK11-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK11: omp_offload.failed30: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK11: omp_offload.cont31: +// CHECK11-NEXT: [[TMP104:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP104]], i32* [[N_CASTED32]], align 4 +// CHECK11-NEXT: [[TMP105:%.*]] = load i32, i32* [[N_CASTED32]], align 4 +// CHECK11-NEXT: [[TMP106:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK11-NEXT: [[TMP107:%.*]] = sext i32 [[TMP106]] to i64 +// CHECK11-NEXT: [[TMP108:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* +// CHECK11-NEXT: store i32 [[TMP105]], i32* [[TMP109]], align 4 +// CHECK11-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32* +// CHECK11-NEXT: store i32 [[TMP105]], i32* [[TMP111]], align 4 +// CHECK11-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP112]], align 4 +// CHECK11-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP113]], align 4 +// CHECK11-NEXT: [[TMP114:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP115]], align 4 +// CHECK11-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP117]], align 4 +// CHECK11-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP118]], align 4 +// CHECK11-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP119]], align 4 +// CHECK11-NEXT: [[TMP120:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP121]], align 4 +// CHECK11-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP123]], align 4 +// CHECK11-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 2 +// CHECK11-NEXT: store i64 [[TMP107]], i64* [[TMP124]], align 4 +// CHECK11-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP125]], align 4 +// CHECK11-NEXT: [[TMP126:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP127:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP128:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP129:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP129]], i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK11-NEXT: [[TMP130:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK11-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP130]], 0 +// CHECK11-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 +// CHECK11-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 +// CHECK11-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK11-NEXT: [[TMP131:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK11-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP131]], 1 +// CHECK11-NEXT: [[TMP132:%.*]] = zext i32 [[ADD43]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP132]]) +// CHECK11-NEXT: [[TMP133:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151.region_id, i32 3, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP134:%.*]] = icmp ne i32 [[TMP133]], 0 +// CHECK11-NEXT: br i1 [[TMP134]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] +// CHECK11: omp_offload.failed44: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151(i32 [[TMP105]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT45]] +// CHECK11: omp_offload.cont45: +// CHECK11-NEXT: [[TMP135:%.*]] = load i32, i32* [[M]], align 4 +// CHECK11-NEXT: store i32 [[TMP135]], i32* [[DOTCAPTURE_EXPR_46]], align 4 +// CHECK11-NEXT: [[TMP136:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP136]], i32* [[N_CASTED47]], align 4 +// CHECK11-NEXT: [[TMP137:%.*]] = load i32, i32* [[N_CASTED47]], align 4 +// CHECK11-NEXT: [[TMP138:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_46]], align 4 +// CHECK11-NEXT: store i32 [[TMP138]], i32* [[DOTCAPTURE_EXPR__CASTED48]], align 4 +// CHECK11-NEXT: [[TMP139:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED48]], align 4 +// CHECK11-NEXT: [[TMP140:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK11-NEXT: [[TMP141:%.*]] = sext i32 [[TMP140]] to i64 +// CHECK11-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32* +// CHECK11-NEXT: store i32 [[TMP137]], i32* [[TMP143]], align 4 +// CHECK11-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i32* +// CHECK11-NEXT: store i32 [[TMP137]], i32* [[TMP145]], align 4 +// CHECK11-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP146]], align 4 +// CHECK11-NEXT: [[TMP147:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP147]], align 4 +// CHECK11-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP149]], align 4 +// CHECK11-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP151]], align 4 +// CHECK11-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP152]], align 4 +// CHECK11-NEXT: [[TMP153:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP153]], align 4 +// CHECK11-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP155]], align 4 +// CHECK11-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP157]], align 4 +// CHECK11-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 2 +// CHECK11-NEXT: store i64 [[TMP141]], i64* [[TMP158]], align 4 +// CHECK11-NEXT: [[TMP159:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP159]], align 4 +// CHECK11-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP161:%.*]] = bitcast i8** [[TMP160]] to i32* +// CHECK11-NEXT: store i32 [[TMP139]], i32* [[TMP161]], align 4 +// CHECK11-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP163:%.*]] = bitcast i8** [[TMP162]] to i32* +// CHECK11-NEXT: store i32 [[TMP139]], i32* [[TMP163]], align 4 +// CHECK11-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 3 +// CHECK11-NEXT: store i64 4, i64* [[TMP164]], align 4 +// CHECK11-NEXT: [[TMP165:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP165]], align 4 +// CHECK11-NEXT: [[TMP166:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP167:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP168:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP169:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP169]], i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK11-NEXT: [[TMP170:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK11-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP170]], 0 +// CHECK11-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 +// CHECK11-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 +// CHECK11-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK11-NEXT: [[TMP171:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK11-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP171]], 1 +// CHECK11-NEXT: [[TMP172:%.*]] = zext i32 [[ADD59]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP172]]) +// CHECK11-NEXT: [[TMP173:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155.region_id, i32 4, i8** [[TMP166]], i8** [[TMP167]], i64* [[TMP168]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0 +// CHECK11-NEXT: br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] +// CHECK11: omp_offload.failed60: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP137]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP139]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT61]] +// CHECK11: omp_offload.cont61: +// CHECK11-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) +// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK11-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) +// CHECK11-NEXT: [[TMP177:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK11-NEXT: ret i32 [[TMP177]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I20:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3:%.*]] -// CHECK11: for.cond3: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK11-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK11: for.body5: -// CHECK11-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK11-NEXT: br label [[FOR_INC8:%.*]] -// CHECK11: for.inc8: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK11-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK11: for.end10: -// CHECK11-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK11-NEXT: br label [[FOR_COND12:%.*]] -// CHECK11: for.cond12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK11-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK11: for.body14: -// CHECK11-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK11-NEXT: br label [[FOR_INC17:%.*]] -// CHECK11: for.inc17: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK11-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK11-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end19: -// CHECK11-NEXT: store i32 0, i32* [[I20]], align 4 -// CHECK11-NEXT: br label [[FOR_COND21:%.*]] -// CHECK11: for.cond21: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[CMP22:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK11-NEXT: br i1 [[CMP22]], label [[FOR_BODY23:%.*]], label [[FOR_END28:%.*]] -// CHECK11: for.body23: -// CHECK11-NEXT: [[A24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A24]], i32 0, i32 [[TMP10]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX25]], align 4 -// CHECK11-NEXT: br label [[FOR_INC26:%.*]] -// CHECK11: for.inc26: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[INC27:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: store i32 [[INC27]], i32* [[I20]], align 4 -// CHECK11-NEXT: br label [[FOR_COND21]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK11: for.end28: -// CHECK11-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK11-NEXT: br label [[FOR_COND30:%.*]] -// CHECK11: for.cond30: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK11-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK11: for.body32: -// CHECK11-NEXT: [[A33:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A33]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK11-NEXT: br label [[FOR_INC35:%.*]] -// CHECK11: for.inc35: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK11-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end37: -// CHECK11-NEXT: [[A38:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A38]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX39]], align 4 -// CHECK11-NEXT: ret i32 [[TMP15]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK12-NEXT: ret i32 [[CALL]] +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK11-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] +// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP28]], [[TMP29]] +// CHECK11-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK11: cond.true11: +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: br label [[COND_END13:%.*]] +// CHECK11: cond.false12: +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END13]] +// CHECK11: cond.end13: +// CHECK11-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE11]] ], [ [[TMP31]], [[COND_FALSE12]] ] +// CHECK11-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 35, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP19]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP20]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP20]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK11-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK11-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK11: omp_offload.failed5: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK11: omp_offload.cont6: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK11-NEXT: store i32 [[TMP20]], i32* [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK11-NEXT: store i32 [[TMP20]], i32* [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK11-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK11: omp_offload.failed11: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120([10 x i32]* [[A]], i32 [[TMP20]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK11: omp_offload.cont12: +// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP36]], align 4 +// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP38]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124.region_id, i32 1, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK11-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK11: omp_offload.failed17: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK11: omp_offload.cont18: +// CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[M]], align 4 +// CHECK11-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_19]], align 4 +// CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 +// CHECK11-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP48]], align 4 +// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP50]], align 4 +// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP51]], align 4 +// CHECK11-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* +// CHECK11-NEXT: store i32 [[TMP46]], i32* [[TMP53]], align 4 +// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i32* +// CHECK11-NEXT: store i32 [[TMP46]], i32* [[TMP55]], align 4 +// CHECK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP56]], align 4 +// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128.region_id, i32 2, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 +// CHECK11-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] +// CHECK11: omp_offload.failed25: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128([10 x i32]* [[A]], i32 [[TMP46]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT26]] +// CHECK11: omp_offload.cont26: +// CHECK11-NEXT: ret i32 0 +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..21 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..25 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK11-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK11-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-LABEL: define {{[^@]+}}@main +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 +// CHECK12-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED32:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES36:%.*]] = alloca [3 x i64], align 4 +// CHECK12-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_46:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED47:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED48:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS49:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS50:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS51:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES52:%.*]] = alloca [4 x i64], align 4 +// CHECK12-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK12-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK12-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK12-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK12-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK12-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK12-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK12-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK12-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK12-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK12-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK12-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK12-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) +// CHECK12-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK12-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK12: omp_offload.failed15: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK12: omp_offload.cont16: +// CHECK12-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 +// CHECK12-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK12-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 +// CHECK12-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 +// CHECK12-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK12-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK12-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 +// CHECK12-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* +// CHECK12-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 +// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK12-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 +// CHECK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP75]], align 4 +// CHECK12-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP76]], align 4 +// CHECK12-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 +// CHECK12-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 +// CHECK12-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP81]], align 4 +// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK12-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 +// CHECK12-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 +// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 +// CHECK12-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 +// CHECK12-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP88]], align 4 +// CHECK12-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* +// CHECK12-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 +// CHECK12-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* +// CHECK12-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 +// CHECK12-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 +// CHECK12-NEXT: store i64 4, i64* [[TMP93]], align 4 +// CHECK12-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP94]], align 4 +// CHECK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK12-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK12-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 +// CHECK12-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// CHECK12-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 +// CHECK12-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK12-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK12-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 +// CHECK12-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP101]]) +// CHECK12-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 +// CHECK12-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK12: omp_offload.failed30: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK12: omp_offload.cont31: +// CHECK12-NEXT: [[TMP104:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP104]], i32* [[N_CASTED32]], align 4 +// CHECK12-NEXT: [[TMP105:%.*]] = load i32, i32* [[N_CASTED32]], align 4 +// CHECK12-NEXT: [[TMP106:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK12-NEXT: [[TMP107:%.*]] = sext i32 [[TMP106]] to i64 +// CHECK12-NEXT: [[TMP108:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* +// CHECK12-NEXT: store i32 [[TMP105]], i32* [[TMP109]], align 4 +// CHECK12-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32* +// CHECK12-NEXT: store i32 [[TMP105]], i32* [[TMP111]], align 4 +// CHECK12-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP112]], align 4 +// CHECK12-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP113]], align 4 +// CHECK12-NEXT: [[TMP114:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP115]], align 4 +// CHECK12-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP117]], align 4 +// CHECK12-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP118]], align 4 +// CHECK12-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP119]], align 4 +// CHECK12-NEXT: [[TMP120:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP121]], align 4 +// CHECK12-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP123]], align 4 +// CHECK12-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 2 +// CHECK12-NEXT: store i64 [[TMP107]], i64* [[TMP124]], align 4 +// CHECK12-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP125]], align 4 +// CHECK12-NEXT: [[TMP126:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP127:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP128:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP129:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP129]], i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK12-NEXT: [[TMP130:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK12-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP130]], 0 +// CHECK12-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 +// CHECK12-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 +// CHECK12-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK12-NEXT: [[TMP131:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 +// CHECK12-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP131]], 1 +// CHECK12-NEXT: [[TMP132:%.*]] = zext i32 [[ADD43]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP132]]) +// CHECK12-NEXT: [[TMP133:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151.region_id, i32 3, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP134:%.*]] = icmp ne i32 [[TMP133]], 0 +// CHECK12-NEXT: br i1 [[TMP134]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] +// CHECK12: omp_offload.failed44: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151(i32 [[TMP105]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT45]] +// CHECK12: omp_offload.cont45: +// CHECK12-NEXT: [[TMP135:%.*]] = load i32, i32* [[M]], align 4 +// CHECK12-NEXT: store i32 [[TMP135]], i32* [[DOTCAPTURE_EXPR_46]], align 4 +// CHECK12-NEXT: [[TMP136:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP136]], i32* [[N_CASTED47]], align 4 +// CHECK12-NEXT: [[TMP137:%.*]] = load i32, i32* [[N_CASTED47]], align 4 +// CHECK12-NEXT: [[TMP138:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_46]], align 4 +// CHECK12-NEXT: store i32 [[TMP138]], i32* [[DOTCAPTURE_EXPR__CASTED48]], align 4 +// CHECK12-NEXT: [[TMP139:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED48]], align 4 +// CHECK12-NEXT: [[TMP140:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK12-NEXT: [[TMP141:%.*]] = sext i32 [[TMP140]] to i64 +// CHECK12-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32* +// CHECK12-NEXT: store i32 [[TMP137]], i32* [[TMP143]], align 4 +// CHECK12-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i32* +// CHECK12-NEXT: store i32 [[TMP137]], i32* [[TMP145]], align 4 +// CHECK12-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP146]], align 4 +// CHECK12-NEXT: [[TMP147:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP147]], align 4 +// CHECK12-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP149]], align 4 +// CHECK12-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP151]], align 4 +// CHECK12-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP152]], align 4 +// CHECK12-NEXT: [[TMP153:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP153]], align 4 +// CHECK12-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP155]], align 4 +// CHECK12-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP157]], align 4 +// CHECK12-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 2 +// CHECK12-NEXT: store i64 [[TMP141]], i64* [[TMP158]], align 4 +// CHECK12-NEXT: [[TMP159:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP159]], align 4 +// CHECK12-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP161:%.*]] = bitcast i8** [[TMP160]] to i32* +// CHECK12-NEXT: store i32 [[TMP139]], i32* [[TMP161]], align 4 +// CHECK12-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP163:%.*]] = bitcast i8** [[TMP162]] to i32* +// CHECK12-NEXT: store i32 [[TMP139]], i32* [[TMP163]], align 4 +// CHECK12-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 3 +// CHECK12-NEXT: store i64 4, i64* [[TMP164]], align 4 +// CHECK12-NEXT: [[TMP165:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP165]], align 4 +// CHECK12-NEXT: [[TMP166:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP167:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP168:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP169:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP169]], i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK12-NEXT: [[TMP170:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 +// CHECK12-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP170]], 0 +// CHECK12-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 +// CHECK12-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 +// CHECK12-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK12-NEXT: [[TMP171:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 +// CHECK12-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP171]], 1 +// CHECK12-NEXT: [[TMP172:%.*]] = zext i32 [[ADD59]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP172]]) +// CHECK12-NEXT: [[TMP173:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155.region_id, i32 4, i8** [[TMP166]], i8** [[TMP167]], i64* [[TMP168]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0 +// CHECK12-NEXT: br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] +// CHECK12: omp_offload.failed60: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP137]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP139]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT61]] +// CHECK12: omp_offload.cont61: +// CHECK12-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) +// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK12-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) +// CHECK12-NEXT: [[TMP177:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK12-NEXT: ret i32 [[TMP177]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] +// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP28]], [[TMP29]] +// CHECK12-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK12: cond.true11: +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: br label [[COND_END13:%.*]] +// CHECK12: cond.false12: +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END13]] +// CHECK12: cond.end13: +// CHECK12-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE11]] ], [ [[TMP31]], [[COND_FALSE12]] ] +// CHECK12-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 35, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP19]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I20:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP20]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP20]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK12-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK12-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK12: omp_offload.failed5: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK12: omp_offload.cont6: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK12-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK12-NEXT: store i32 [[TMP20]], i32* [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK12-NEXT: store i32 [[TMP20]], i32* [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK12-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK12: omp_offload.failed11: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120([10 x i32]* [[A]], i32 [[TMP20]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK12: omp_offload.cont12: +// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP36]], align 4 +// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP38]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124.region_id, i32 1, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK12-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK12: omp_offload.failed17: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK12: omp_offload.cont18: +// CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[M]], align 4 +// CHECK12-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_19]], align 4 +// CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 +// CHECK12-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP48]], align 4 +// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP50]], align 4 +// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP51]], align 4 +// CHECK12-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* +// CHECK12-NEXT: store i32 [[TMP46]], i32* [[TMP53]], align 4 +// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i32* +// CHECK12-NEXT: store i32 [[TMP46]], i32* [[TMP55]], align 4 +// CHECK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP56]], align 4 +// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128.region_id, i32 2, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 +// CHECK12-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] +// CHECK12: omp_offload.failed25: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128([10 x i32]* [[A]], i32 [[TMP46]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT26]] +// CHECK12: omp_offload.cont26: +// CHECK12-NEXT: ret i32 0 +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..21 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP16]] // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3:%.*]] -// CHECK12: for.cond3: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK12-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK12: for.body5: -// CHECK12-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK12-NEXT: br label [[FOR_INC8:%.*]] -// CHECK12: for.inc8: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK12-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK12: for.end10: -// CHECK12-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK12-NEXT: br label [[FOR_COND12:%.*]] -// CHECK12: for.cond12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK12-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK12: for.body14: -// CHECK12-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK12-NEXT: br label [[FOR_INC17:%.*]] -// CHECK12: for.inc17: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK12-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK12-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end19: -// CHECK12-NEXT: store i32 0, i32* [[I20]], align 4 -// CHECK12-NEXT: br label [[FOR_COND21:%.*]] -// CHECK12: for.cond21: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[CMP22:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK12-NEXT: br i1 [[CMP22]], label [[FOR_BODY23:%.*]], label [[FOR_END28:%.*]] -// CHECK12: for.body23: -// CHECK12-NEXT: [[A24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A24]], i32 0, i32 [[TMP10]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX25]], align 4 -// CHECK12-NEXT: br label [[FOR_INC26:%.*]] -// CHECK12: for.inc26: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[INC27:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: store i32 [[INC27]], i32* [[I20]], align 4 -// CHECK12-NEXT: br label [[FOR_COND21]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK12: for.end28: -// CHECK12-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK12-NEXT: br label [[FOR_COND30:%.*]] -// CHECK12: for.cond30: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK12-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK12: for.body32: -// CHECK12-NEXT: [[A33:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A33]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK12-NEXT: br label [[FOR_INC35:%.*]] -// CHECK12: for.inc35: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK12-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end37: -// CHECK12-NEXT: [[A38:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A38]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX39]], align 4 -// CHECK12-NEXT: ret i32 [[TMP15]] +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..25 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK12-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK12-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK12-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@main @@ -9142,7 +18546,7 @@ // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 35, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) +// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 1073741859, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13: omp.dispatch.cond: // CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -9380,7 +18784,7 @@ // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) +// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13: omp.dispatch.cond: // CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -10177,7 +19581,7 @@ // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13: omp.dispatch.cond: // CHECK13-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -10345,7 +19749,7 @@ // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13: omp.dispatch.cond: // CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -11662,7 +21066,7 @@ // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 35, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) +// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 1073741859, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14: omp.dispatch.cond: // CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -11900,7 +21304,7 @@ // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) +// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14: omp.dispatch.cond: // CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -12697,7 +22101,7 @@ // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14: omp.dispatch.cond: // CHECK14-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -12865,7 +22269,7 @@ // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14: omp.dispatch.cond: // CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -14135,7 +23539,7 @@ // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 35, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) +// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 1073741859, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15: omp.dispatch.cond: // CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 @@ -14358,7 +23762,7 @@ // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) +// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15: omp.dispatch.cond: // CHECK15-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 @@ -15125,7 +24529,7 @@ // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15: omp.dispatch.cond: // CHECK15-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -15283,7 +24687,7 @@ // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15: omp.dispatch.cond: // CHECK15-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -16552,7 +25956,7 @@ // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 35, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) +// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 1073741859, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16: omp.dispatch.cond: // CHECK16-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 @@ -16775,7 +26179,7 @@ // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) +// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16: omp.dispatch.cond: // CHECK16-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 @@ -17542,7 +26946,7 @@ // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16: omp.dispatch.cond: // CHECK16-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -17700,7 +27104,7 @@ // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16: omp.dispatch.cond: // CHECK16-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -17745,10847 +27149,3 @@ // CHECK16-NEXT: call void @__tgt_register_requires(i64 1) // CHECK16-NEXT: ret void // -// -// CHECK17-LABEL: define {{[^@]+}}@main -// CHECK17-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK17-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK17-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 -// CHECK17-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED35:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS37:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS38:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS39:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES40:%.*]] = alloca [3 x i64], align 8 -// CHECK17-NEXT: [[_TMP41:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_42:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_43:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_50:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED51:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED53:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS55:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS56:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS57:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES58:%.*]] = alloca [4 x i64], align 8 -// CHECK17-NEXT: [[_TMP59:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_60:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK17-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK17-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK17-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK17-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK17-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK17-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK17-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK17-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK17-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK17-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK17-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK17-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK17-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK17-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK17-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK17-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK17-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK17-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK17-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK17-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) -// CHECK17-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK17-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK17: omp_offload.failed16: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK17: omp_offload.cont17: -// CHECK17-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 -// CHECK17-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK17-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* -// CHECK17-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 -// CHECK17-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 -// CHECK17-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK17-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 -// CHECK17-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* -// CHECK17-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 -// CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* -// CHECK17-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 -// CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP73]], align 8 -// CHECK17-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP74]], align 8 -// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 -// CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 -// CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 -// CHECK17-NEXT: store i64 8, i64* [[TMP79]], align 8 -// CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP80]], align 8 -// CHECK17-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 -// CHECK17-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 -// CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 -// CHECK17-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 -// CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP86]], align 8 -// CHECK17-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* -// CHECK17-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 -// CHECK17-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* -// CHECK17-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 -// CHECK17-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 -// CHECK17-NEXT: store i64 4, i64* [[TMP91]], align 8 -// CHECK17-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK17-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK17-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK17-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 -// CHECK17-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK17-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 -// CHECK17-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK17-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK17-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 -// CHECK17-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP99]]) -// CHECK17-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 -// CHECK17-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] -// CHECK17: omp_offload.failed33: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT34]] -// CHECK17: omp_offload.cont34: -// CHECK17-NEXT: [[TMP102:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CONV36:%.*]] = bitcast i64* [[N_CASTED35]] to i32* -// CHECK17-NEXT: store i32 [[TMP102]], i32* [[CONV36]], align 4 -// CHECK17-NEXT: [[TMP103:%.*]] = load i64, i64* [[N_CASTED35]], align 8 -// CHECK17-NEXT: [[TMP104:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to i64* -// CHECK17-NEXT: store i64 [[TMP103]], i64* [[TMP106]], align 8 -// CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* -// CHECK17-NEXT: store i64 [[TMP103]], i64* [[TMP108]], align 8 -// CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP109]], align 8 -// CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP110]], align 8 -// CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP112]], align 8 -// CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP114]], align 8 -// CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 1 -// CHECK17-NEXT: store i64 8, i64* [[TMP115]], align 8 -// CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP116]], align 8 -// CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP118]], align 8 -// CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP120]], align 8 -// CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 2 -// CHECK17-NEXT: store i64 [[TMP104]], i64* [[TMP121]], align 8 -// CHECK17-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP122]], align 8 -// CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP126:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: store i32 [[TMP126]], i32* [[DOTCAPTURE_EXPR_42]], align 4 -// CHECK17-NEXT: [[TMP127:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_42]], align 4 -// CHECK17-NEXT: [[SUB44:%.*]] = sub nsw i32 [[TMP127]], 0 -// CHECK17-NEXT: [[DIV45:%.*]] = sdiv i32 [[SUB44]], 1 -// CHECK17-NEXT: [[SUB46:%.*]] = sub nsw i32 [[DIV45]], 1 -// CHECK17-NEXT: store i32 [[SUB46]], i32* [[DOTCAPTURE_EXPR_43]], align 4 -// CHECK17-NEXT: [[TMP128:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_43]], align 4 -// CHECK17-NEXT: [[ADD47:%.*]] = add nsw i32 [[TMP128]], 1 -// CHECK17-NEXT: [[TMP129:%.*]] = zext i32 [[ADD47]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP129]]) -// CHECK17-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151.region_id, i32 3, i8** [[TMP123]], i8** [[TMP124]], i64* [[TMP125]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0 -// CHECK17-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED48:%.*]], label [[OMP_OFFLOAD_CONT49:%.*]] -// CHECK17: omp_offload.failed48: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151(i64 [[TMP103]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT49]] -// CHECK17: omp_offload.cont49: -// CHECK17-NEXT: [[TMP132:%.*]] = load i32, i32* [[M]], align 4 -// CHECK17-NEXT: store i32 [[TMP132]], i32* [[DOTCAPTURE_EXPR_50]], align 4 -// CHECK17-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CONV52:%.*]] = bitcast i64* [[N_CASTED51]] to i32* -// CHECK17-NEXT: store i32 [[TMP133]], i32* [[CONV52]], align 4 -// CHECK17-NEXT: [[TMP134:%.*]] = load i64, i64* [[N_CASTED51]], align 8 -// CHECK17-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_50]], align 4 -// CHECK17-NEXT: [[CONV54:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED53]] to i32* -// CHECK17-NEXT: store i32 [[TMP135]], i32* [[CONV54]], align 4 -// CHECK17-NEXT: [[TMP136:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED53]], align 8 -// CHECK17-NEXT: [[TMP137:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK17-NEXT: [[TMP138:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to i64* -// CHECK17-NEXT: store i64 [[TMP134]], i64* [[TMP139]], align 8 -// CHECK17-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i64* -// CHECK17-NEXT: store i64 [[TMP134]], i64* [[TMP141]], align 8 -// CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP142]], align 8 -// CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP143]], align 8 -// CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP145]], align 8 -// CHECK17-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP147]], align 8 -// CHECK17-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 1 -// CHECK17-NEXT: store i64 8, i64* [[TMP148]], align 8 -// CHECK17-NEXT: [[TMP149:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP149]], align 8 -// CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP151]], align 8 -// CHECK17-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP153]], align 8 -// CHECK17-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 2 -// CHECK17-NEXT: store i64 [[TMP137]], i64* [[TMP154]], align 8 -// CHECK17-NEXT: [[TMP155:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP155]], align 8 -// CHECK17-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* -// CHECK17-NEXT: store i64 [[TMP136]], i64* [[TMP157]], align 8 -// CHECK17-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* -// CHECK17-NEXT: store i64 [[TMP136]], i64* [[TMP159]], align 8 -// CHECK17-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 3 -// CHECK17-NEXT: store i64 4, i64* [[TMP160]], align 8 -// CHECK17-NEXT: [[TMP161:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP161]], align 8 -// CHECK17-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP163:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP165:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: store i32 [[TMP165]], i32* [[DOTCAPTURE_EXPR_60]], align 4 -// CHECK17-NEXT: [[TMP166:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_60]], align 4 -// CHECK17-NEXT: [[SUB62:%.*]] = sub nsw i32 [[TMP166]], 0 -// CHECK17-NEXT: [[DIV63:%.*]] = sdiv i32 [[SUB62]], 1 -// CHECK17-NEXT: [[SUB64:%.*]] = sub nsw i32 [[DIV63]], 1 -// CHECK17-NEXT: store i32 [[SUB64]], i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK17-NEXT: [[TMP167:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK17-NEXT: [[ADD65:%.*]] = add nsw i32 [[TMP167]], 1 -// CHECK17-NEXT: [[TMP168:%.*]] = zext i32 [[ADD65]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP168]]) -// CHECK17-NEXT: [[TMP169:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155.region_id, i32 4, i8** [[TMP162]], i8** [[TMP163]], i64* [[TMP164]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP170:%.*]] = icmp ne i32 [[TMP169]], 0 -// CHECK17-NEXT: br i1 [[TMP170]], label [[OMP_OFFLOAD_FAILED66:%.*]], label [[OMP_OFFLOAD_CONT67:%.*]] -// CHECK17: omp_offload.failed66: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP134]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP136]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT67]] -// CHECK17: omp_offload.cont67: -// CHECK17-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) -// CHECK17-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK17-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) -// CHECK17-NEXT: [[TMP173:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK17-NEXT: ret i32 [[TMP173]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 -// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK17-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 -// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK17-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 -// CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 -// CHECK17-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP30]], [[TMP31]] -// CHECK17-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] -// CHECK17: cond.true14: -// CHECK17-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: br label [[COND_END16:%.*]] -// CHECK17: cond.false15: -// CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END16]] -// CHECK17: cond.end16: -// CHECK17-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE14]] ], [ [[TMP33]], [[COND_FALSE15]] ] -// CHECK17-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I7:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK17-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK17-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 -// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK17-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 1073741859, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4 -// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4 -// CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I7:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[I7]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK17-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK17-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK17-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK17-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK17-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK17-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK17: omp_offload.failed5: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK17: omp_offload.cont6: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK17-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 8 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK17-NEXT: store i64 [[TMP20]], i64* [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK17-NEXT: store i64 [[TMP20]], i64* [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK17: omp_offload.failed11: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120([10 x i32]* [[A]], i64 [[TMP20]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK17: omp_offload.cont12: -// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP36]], align 8 -// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP38]], align 8 -// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124.region_id, i32 1, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 -// CHECK17-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK17: omp_offload.failed17: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK17: omp_offload.cont18: -// CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[M]], align 4 -// CHECK17-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_19]], align 4 -// CHECK17-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 -// CHECK17-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED20]] to i32* -// CHECK17-NEXT: store i32 [[TMP45]], i32* [[CONV21]], align 4 -// CHECK17-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED20]], align 8 -// CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP48]], align 8 -// CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP50]], align 8 -// CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP51]], align 8 -// CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* -// CHECK17-NEXT: store i64 [[TMP46]], i64* [[TMP53]], align 8 -// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i64* -// CHECK17-NEXT: store i64 [[TMP46]], i64* [[TMP55]], align 8 -// CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP56]], align 8 -// CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128.region_id, i32 2, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 -// CHECK17-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED26:%.*]], label [[OMP_OFFLOAD_CONT27:%.*]] -// CHECK17: omp_offload.failed26: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128([10 x i32]* [[A]], i64 [[TMP46]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT27]] -// CHECK17: omp_offload.cont27: -// CHECK17-NEXT: ret i32 0 -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[CONV3]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CONV4:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ] -// CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[COND]] to i32 -// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK17-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK18-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK18-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES25:%.*]] = alloca [4 x i64], align 8 -// CHECK18-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED35:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS37:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS38:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS39:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES40:%.*]] = alloca [3 x i64], align 8 -// CHECK18-NEXT: [[_TMP41:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_42:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_43:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_50:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED51:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED53:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS55:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS56:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS57:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES58:%.*]] = alloca [4 x i64], align 8 -// CHECK18-NEXT: [[_TMP59:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_60:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_61:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK18-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK18-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK18-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK18-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK18-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK18-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK18-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK18-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK18-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK18-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK18-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK18-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK18-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK18-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK18-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK18-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK18-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK18-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK18-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK18-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK18-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) -// CHECK18-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK18-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK18: omp_offload.failed16: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK18: omp_offload.cont17: -// CHECK18-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 -// CHECK18-NEXT: store i32 [[TMP63]], i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK18-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* -// CHECK18-NEXT: store i32 [[TMP64]], i32* [[CONV20]], align 4 -// CHECK18-NEXT: [[TMP65:%.*]] = load i64, i64* [[N_CASTED19]], align 8 -// CHECK18-NEXT: [[TMP66:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 -// CHECK18-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP66]], i32* [[CONV21]], align 4 -// CHECK18-NEXT: [[TMP67:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP68:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK18-NEXT: [[TMP69:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* -// CHECK18-NEXT: store i64 [[TMP65]], i64* [[TMP70]], align 8 -// CHECK18-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* -// CHECK18-NEXT: store i64 [[TMP65]], i64* [[TMP72]], align 8 -// CHECK18-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP73]], align 8 -// CHECK18-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP74]], align 8 -// CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP76]], align 8 -// CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP78]], align 8 -// CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 1 -// CHECK18-NEXT: store i64 8, i64* [[TMP79]], align 8 -// CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP80]], align 8 -// CHECK18-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP82]], align 8 -// CHECK18-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 8 -// CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 2 -// CHECK18-NEXT: store i64 [[TMP68]], i64* [[TMP85]], align 8 -// CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP86]], align 8 -// CHECK18-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* -// CHECK18-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 -// CHECK18-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* -// CHECK18-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 -// CHECK18-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 3 -// CHECK18-NEXT: store i64 4, i64* [[TMP91]], align 8 -// CHECK18-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK18-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES25]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP96:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: store i32 [[TMP96]], i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK18-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK18-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP97]], 0 -// CHECK18-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK18-NEXT: [[SUB31:%.*]] = sub nsw i32 [[DIV30]], 1 -// CHECK18-NEXT: store i32 [[SUB31]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK18-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK18-NEXT: [[ADD32:%.*]] = add nsw i32 [[TMP98]], 1 -// CHECK18-NEXT: [[TMP99:%.*]] = zext i32 [[ADD32]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP99]]) -// CHECK18-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147.region_id, i32 4, i8** [[TMP93]], i8** [[TMP94]], i64* [[TMP95]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 -// CHECK18-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] -// CHECK18: omp_offload.failed33: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147(i64 [[TMP65]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP67]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT34]] -// CHECK18: omp_offload.cont34: -// CHECK18-NEXT: [[TMP102:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[CONV36:%.*]] = bitcast i64* [[N_CASTED35]] to i32* -// CHECK18-NEXT: store i32 [[TMP102]], i32* [[CONV36]], align 4 -// CHECK18-NEXT: [[TMP103:%.*]] = load i64, i64* [[N_CASTED35]], align 8 -// CHECK18-NEXT: [[TMP104:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to i64* -// CHECK18-NEXT: store i64 [[TMP103]], i64* [[TMP106]], align 8 -// CHECK18-NEXT: [[TMP107:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* -// CHECK18-NEXT: store i64 [[TMP103]], i64* [[TMP108]], align 8 -// CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP109]], align 8 -// CHECK18-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP110]], align 8 -// CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP112]], align 8 -// CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP114]], align 8 -// CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 1 -// CHECK18-NEXT: store i64 8, i64* [[TMP115]], align 8 -// CHECK18-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP116]], align 8 -// CHECK18-NEXT: [[TMP117:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP118]], align 8 -// CHECK18-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP120]], align 8 -// CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 2 -// CHECK18-NEXT: store i64 [[TMP104]], i64* [[TMP121]], align 8 -// CHECK18-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS39]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP122]], align 8 -// CHECK18-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS37]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS38]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES40]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP126:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: store i32 [[TMP126]], i32* [[DOTCAPTURE_EXPR_42]], align 4 -// CHECK18-NEXT: [[TMP127:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_42]], align 4 -// CHECK18-NEXT: [[SUB44:%.*]] = sub nsw i32 [[TMP127]], 0 -// CHECK18-NEXT: [[DIV45:%.*]] = sdiv i32 [[SUB44]], 1 -// CHECK18-NEXT: [[SUB46:%.*]] = sub nsw i32 [[DIV45]], 1 -// CHECK18-NEXT: store i32 [[SUB46]], i32* [[DOTCAPTURE_EXPR_43]], align 4 -// CHECK18-NEXT: [[TMP128:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_43]], align 4 -// CHECK18-NEXT: [[ADD47:%.*]] = add nsw i32 [[TMP128]], 1 -// CHECK18-NEXT: [[TMP129:%.*]] = zext i32 [[ADD47]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP129]]) -// CHECK18-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151.region_id, i32 3, i8** [[TMP123]], i8** [[TMP124]], i64* [[TMP125]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0 -// CHECK18-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED48:%.*]], label [[OMP_OFFLOAD_CONT49:%.*]] -// CHECK18: omp_offload.failed48: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151(i64 [[TMP103]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT49]] -// CHECK18: omp_offload.cont49: -// CHECK18-NEXT: [[TMP132:%.*]] = load i32, i32* [[M]], align 4 -// CHECK18-NEXT: store i32 [[TMP132]], i32* [[DOTCAPTURE_EXPR_50]], align 4 -// CHECK18-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[CONV52:%.*]] = bitcast i64* [[N_CASTED51]] to i32* -// CHECK18-NEXT: store i32 [[TMP133]], i32* [[CONV52]], align 4 -// CHECK18-NEXT: [[TMP134:%.*]] = load i64, i64* [[N_CASTED51]], align 8 -// CHECK18-NEXT: [[TMP135:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_50]], align 4 -// CHECK18-NEXT: [[CONV54:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED53]] to i32* -// CHECK18-NEXT: store i32 [[TMP135]], i32* [[CONV54]], align 4 -// CHECK18-NEXT: [[TMP136:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED53]], align 8 -// CHECK18-NEXT: [[TMP137:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK18-NEXT: [[TMP138:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to i64* -// CHECK18-NEXT: store i64 [[TMP134]], i64* [[TMP139]], align 8 -// CHECK18-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i64* -// CHECK18-NEXT: store i64 [[TMP134]], i64* [[TMP141]], align 8 -// CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP142]], align 8 -// CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP143]], align 8 -// CHECK18-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP145]], align 8 -// CHECK18-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP147]], align 8 -// CHECK18-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 1 -// CHECK18-NEXT: store i64 8, i64* [[TMP148]], align 8 -// CHECK18-NEXT: [[TMP149:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP149]], align 8 -// CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP151]], align 8 -// CHECK18-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP153]], align 8 -// CHECK18-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 2 -// CHECK18-NEXT: store i64 [[TMP137]], i64* [[TMP154]], align 8 -// CHECK18-NEXT: [[TMP155:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP155]], align 8 -// CHECK18-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* -// CHECK18-NEXT: store i64 [[TMP136]], i64* [[TMP157]], align 8 -// CHECK18-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* -// CHECK18-NEXT: store i64 [[TMP136]], i64* [[TMP159]], align 8 -// CHECK18-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 3 -// CHECK18-NEXT: store i64 4, i64* [[TMP160]], align 8 -// CHECK18-NEXT: [[TMP161:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS57]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP161]], align 8 -// CHECK18-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS55]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP163:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS56]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES58]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP165:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: store i32 [[TMP165]], i32* [[DOTCAPTURE_EXPR_60]], align 4 -// CHECK18-NEXT: [[TMP166:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_60]], align 4 -// CHECK18-NEXT: [[SUB62:%.*]] = sub nsw i32 [[TMP166]], 0 -// CHECK18-NEXT: [[DIV63:%.*]] = sdiv i32 [[SUB62]], 1 -// CHECK18-NEXT: [[SUB64:%.*]] = sub nsw i32 [[DIV63]], 1 -// CHECK18-NEXT: store i32 [[SUB64]], i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK18-NEXT: [[TMP167:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_61]], align 4 -// CHECK18-NEXT: [[ADD65:%.*]] = add nsw i32 [[TMP167]], 1 -// CHECK18-NEXT: [[TMP168:%.*]] = zext i32 [[ADD65]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP168]]) -// CHECK18-NEXT: [[TMP169:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155.region_id, i32 4, i8** [[TMP162]], i8** [[TMP163]], i64* [[TMP164]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP170:%.*]] = icmp ne i32 [[TMP169]], 0 -// CHECK18-NEXT: br i1 [[TMP170]], label [[OMP_OFFLOAD_FAILED66:%.*]], label [[OMP_OFFLOAD_CONT67:%.*]] -// CHECK18: omp_offload.failed66: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP134]], i64 [[TMP1]], i32* [[VLA]], i64 [[TMP136]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT67]] -// CHECK18: omp_offload.cont67: -// CHECK18-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) -// CHECK18-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK18-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) -// CHECK18-NEXT: [[TMP173:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: ret i32 [[TMP173]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK18-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 -// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK18-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK18-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 -// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK18-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 -// CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 -// CHECK18-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP30]], [[TMP31]] -// CHECK18-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] -// CHECK18: cond.true14: -// CHECK18-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: br label [[COND_END16:%.*]] -// CHECK18: cond.false15: -// CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END16]] -// CHECK18: cond.end16: -// CHECK18-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE14]] ], [ [[TMP33]], [[COND_FALSE15]] ] -// CHECK18-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I7:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK18-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK18-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK18-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 -// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK18-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 1073741859, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4 -// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4 -// CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I7:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK18-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[I7]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK18-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK18-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK18-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK18-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK18-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK18-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK18: omp_offload.failed5: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK18: omp_offload.cont6: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK18-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 8 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK18-NEXT: store i64 [[TMP20]], i64* [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK18-NEXT: store i64 [[TMP20]], i64* [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK18: omp_offload.failed11: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120([10 x i32]* [[A]], i64 [[TMP20]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK18: omp_offload.cont12: -// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP36]], align 8 -// CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP38]], align 8 -// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124.region_id, i32 1, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 -// CHECK18-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK18: omp_offload.failed17: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK18: omp_offload.cont18: -// CHECK18-NEXT: [[TMP44:%.*]] = load i32, i32* [[M]], align 4 -// CHECK18-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_19]], align 4 -// CHECK18-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 -// CHECK18-NEXT: [[CONV21:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED20]] to i32* -// CHECK18-NEXT: store i32 [[TMP45]], i32* [[CONV21]], align 4 -// CHECK18-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED20]], align 8 -// CHECK18-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP48]], align 8 -// CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP50]], align 8 -// CHECK18-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP51]], align 8 -// CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* -// CHECK18-NEXT: store i64 [[TMP46]], i64* [[TMP53]], align 8 -// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i64* -// CHECK18-NEXT: store i64 [[TMP46]], i64* [[TMP55]], align 8 -// CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP56]], align 8 -// CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128.region_id, i32 2, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 -// CHECK18-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED26:%.*]], label [[OMP_OFFLOAD_CONT27:%.*]] -// CHECK18: omp_offload.failed26: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128([10 x i32]* [[A]], i64 [[TMP46]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT27]] -// CHECK18: omp_offload.cont27: -// CHECK18-NEXT: ret i32 0 -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[CONV3]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CONV4:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ] -// CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[COND]] to i32 -// CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK18-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK19-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK19-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 -// CHECK19-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED32:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES36:%.*]] = alloca [3 x i64], align 4 -// CHECK19-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_46:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED47:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED48:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS49:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS50:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS51:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES52:%.*]] = alloca [4 x i64], align 4 -// CHECK19-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK19-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK19-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK19-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK19-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK19-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK19-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK19-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK19-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK19-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK19-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK19-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK19-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK19-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK19-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK19-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK19-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK19-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK19-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK19-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) -// CHECK19-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK19-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK19: omp_offload.failed15: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK19: omp_offload.cont16: -// CHECK19-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 -// CHECK19-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK19-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 -// CHECK19-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 -// CHECK19-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK19-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK19-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 -// CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* -// CHECK19-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 -// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK19-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 -// CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP75]], align 4 -// CHECK19-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP76]], align 4 -// CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 -// CHECK19-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 -// CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP81]], align 4 -// CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 -// CHECK19-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 -// CHECK19-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 -// CHECK19-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 -// CHECK19-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP88]], align 4 -// CHECK19-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* -// CHECK19-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 -// CHECK19-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* -// CHECK19-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 -// CHECK19-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 -// CHECK19-NEXT: store i64 4, i64* [[TMP93]], align 4 -// CHECK19-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP94]], align 4 -// CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK19-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK19-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 -// CHECK19-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// CHECK19-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 -// CHECK19-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK19-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK19-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 -// CHECK19-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP101]]) -// CHECK19-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 -// CHECK19-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK19: omp_offload.failed30: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK19: omp_offload.cont31: -// CHECK19-NEXT: [[TMP104:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP104]], i32* [[N_CASTED32]], align 4 -// CHECK19-NEXT: [[TMP105:%.*]] = load i32, i32* [[N_CASTED32]], align 4 -// CHECK19-NEXT: [[TMP106:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK19-NEXT: [[TMP107:%.*]] = sext i32 [[TMP106]] to i64 -// CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* -// CHECK19-NEXT: store i32 [[TMP105]], i32* [[TMP109]], align 4 -// CHECK19-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32* -// CHECK19-NEXT: store i32 [[TMP105]], i32* [[TMP111]], align 4 -// CHECK19-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP112]], align 4 -// CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP113]], align 4 -// CHECK19-NEXT: [[TMP114:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP115]], align 4 -// CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP117]], align 4 -// CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP118]], align 4 -// CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP119]], align 4 -// CHECK19-NEXT: [[TMP120:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP121]], align 4 -// CHECK19-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP123]], align 4 -// CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 2 -// CHECK19-NEXT: store i64 [[TMP107]], i64* [[TMP124]], align 4 -// CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP125]], align 4 -// CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP128:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP129:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP129]], i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK19-NEXT: [[TMP130:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK19-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP130]], 0 -// CHECK19-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 -// CHECK19-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 -// CHECK19-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK19-NEXT: [[TMP131:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK19-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP131]], 1 -// CHECK19-NEXT: [[TMP132:%.*]] = zext i32 [[ADD43]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP132]]) -// CHECK19-NEXT: [[TMP133:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151.region_id, i32 3, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP134:%.*]] = icmp ne i32 [[TMP133]], 0 -// CHECK19-NEXT: br i1 [[TMP134]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] -// CHECK19: omp_offload.failed44: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151(i32 [[TMP105]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT45]] -// CHECK19: omp_offload.cont45: -// CHECK19-NEXT: [[TMP135:%.*]] = load i32, i32* [[M]], align 4 -// CHECK19-NEXT: store i32 [[TMP135]], i32* [[DOTCAPTURE_EXPR_46]], align 4 -// CHECK19-NEXT: [[TMP136:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP136]], i32* [[N_CASTED47]], align 4 -// CHECK19-NEXT: [[TMP137:%.*]] = load i32, i32* [[N_CASTED47]], align 4 -// CHECK19-NEXT: [[TMP138:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_46]], align 4 -// CHECK19-NEXT: store i32 [[TMP138]], i32* [[DOTCAPTURE_EXPR__CASTED48]], align 4 -// CHECK19-NEXT: [[TMP139:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED48]], align 4 -// CHECK19-NEXT: [[TMP140:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK19-NEXT: [[TMP141:%.*]] = sext i32 [[TMP140]] to i64 -// CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32* -// CHECK19-NEXT: store i32 [[TMP137]], i32* [[TMP143]], align 4 -// CHECK19-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i32* -// CHECK19-NEXT: store i32 [[TMP137]], i32* [[TMP145]], align 4 -// CHECK19-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP146]], align 4 -// CHECK19-NEXT: [[TMP147:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP147]], align 4 -// CHECK19-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP149]], align 4 -// CHECK19-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP151]], align 4 -// CHECK19-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP152]], align 4 -// CHECK19-NEXT: [[TMP153:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP153]], align 4 -// CHECK19-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP155]], align 4 -// CHECK19-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP157]], align 4 -// CHECK19-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 2 -// CHECK19-NEXT: store i64 [[TMP141]], i64* [[TMP158]], align 4 -// CHECK19-NEXT: [[TMP159:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP159]], align 4 -// CHECK19-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP161:%.*]] = bitcast i8** [[TMP160]] to i32* -// CHECK19-NEXT: store i32 [[TMP139]], i32* [[TMP161]], align 4 -// CHECK19-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP163:%.*]] = bitcast i8** [[TMP162]] to i32* -// CHECK19-NEXT: store i32 [[TMP139]], i32* [[TMP163]], align 4 -// CHECK19-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 3 -// CHECK19-NEXT: store i64 4, i64* [[TMP164]], align 4 -// CHECK19-NEXT: [[TMP165:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP165]], align 4 -// CHECK19-NEXT: [[TMP166:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP167:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP168:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP169:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP169]], i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK19-NEXT: [[TMP170:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK19-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP170]], 0 -// CHECK19-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 -// CHECK19-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 -// CHECK19-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK19-NEXT: [[TMP171:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK19-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP171]], 1 -// CHECK19-NEXT: [[TMP172:%.*]] = zext i32 [[ADD59]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP172]]) -// CHECK19-NEXT: [[TMP173:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155.region_id, i32 4, i8** [[TMP166]], i8** [[TMP167]], i64* [[TMP168]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0 -// CHECK19-NEXT: br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] -// CHECK19: omp_offload.failed60: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP137]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP139]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT61]] -// CHECK19: omp_offload.cont61: -// CHECK19-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) -// CHECK19-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK19-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) -// CHECK19-NEXT: [[TMP177:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: ret i32 [[TMP177]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK19-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] -// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP28]], [[TMP29]] -// CHECK19-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK19: cond.true11: -// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: br label [[COND_END13:%.*]] -// CHECK19: cond.false12: -// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END13]] -// CHECK19: cond.end13: -// CHECK19-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE11]] ], [ [[TMP31]], [[COND_FALSE12]] ] -// CHECK19-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 1073741859, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP19]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP20]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP20]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK19-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK19-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK19-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK19-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK19-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK19: omp_offload.failed5: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK19: omp_offload.cont6: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK19-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* -// CHECK19-NEXT: store i32 [[TMP20]], i32* [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK19-NEXT: store i32 [[TMP20]], i32* [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK19: omp_offload.failed11: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120([10 x i32]* [[A]], i32 [[TMP20]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK19: omp_offload.cont12: -// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP36]], align 4 -// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP38]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124.region_id, i32 1, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 -// CHECK19-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK19: omp_offload.failed17: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK19: omp_offload.cont18: -// CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[M]], align 4 -// CHECK19-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_19]], align 4 -// CHECK19-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 -// CHECK19-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 -// CHECK19-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 -// CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP48]], align 4 -// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP50]], align 4 -// CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP51]], align 4 -// CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* -// CHECK19-NEXT: store i32 [[TMP46]], i32* [[TMP53]], align 4 -// CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i32* -// CHECK19-NEXT: store i32 [[TMP46]], i32* [[TMP55]], align 4 -// CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP56]], align 4 -// CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128.region_id, i32 2, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 -// CHECK19-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] -// CHECK19: omp_offload.failed25: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128([10 x i32]* [[A]], i32 [[TMP46]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT26]] -// CHECK19: omp_offload.cont26: -// CHECK19-NEXT: ret i32 0 -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP16]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP12]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK20-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK20-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED18:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS19:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS20:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS21:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES22:%.*]] = alloca [4 x i64], align 4 -// CHECK20-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED32:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES36:%.*]] = alloca [3 x i64], align 4 -// CHECK20-NEXT: [[_TMP37:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_39:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_46:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED47:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED48:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS49:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS50:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS51:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES52:%.*]] = alloca [4 x i64], align 4 -// CHECK20-NEXT: [[_TMP53:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_54:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK20-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK20-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK20-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK20-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK20-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK20-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK20-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK20-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK20-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK20-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK20-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK20-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK20-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK20-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK20-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK20-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK20-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK20-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK20-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK20-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK20-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK20-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK20-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) -// CHECK20-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK20-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK20: omp_offload.failed15: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK20: omp_offload.cont16: -// CHECK20-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 -// CHECK20-NEXT: store i32 [[TMP64]], i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK20-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP65]], i32* [[N_CASTED18]], align 4 -// CHECK20-NEXT: [[TMP66:%.*]] = load i32, i32* [[N_CASTED18]], align 4 -// CHECK20-NEXT: [[TMP67:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK20-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP68:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP69:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK20-NEXT: [[TMP70:%.*]] = sext i32 [[TMP69]] to i64 -// CHECK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32* -// CHECK20-NEXT: store i32 [[TMP66]], i32* [[TMP72]], align 4 -// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* -// CHECK20-NEXT: store i32 [[TMP66]], i32* [[TMP74]], align 4 -// CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP75]], align 4 -// CHECK20-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP76]], align 4 -// CHECK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP78]], align 4 -// CHECK20-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP80]], align 4 -// CHECK20-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP81]], align 4 -// CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP82]], align 4 -// CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP84]], align 4 -// CHECK20-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP86]], align 4 -// CHECK20-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 2 -// CHECK20-NEXT: store i64 [[TMP70]], i64* [[TMP87]], align 4 -// CHECK20-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP88]], align 4 -// CHECK20-NEXT: [[TMP89:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* -// CHECK20-NEXT: store i32 [[TMP68]], i32* [[TMP90]], align 4 -// CHECK20-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i32* -// CHECK20-NEXT: store i32 [[TMP68]], i32* [[TMP92]], align 4 -// CHECK20-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 3 -// CHECK20-NEXT: store i64 4, i64* [[TMP93]], align 4 -// CHECK20-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS21]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP94]], align 4 -// CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS19]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS20]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES22]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP98:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK20-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK20-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP99]], 0 -// CHECK20-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// CHECK20-NEXT: [[SUB28:%.*]] = sub nsw i32 [[DIV27]], 1 -// CHECK20-NEXT: store i32 [[SUB28]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK20-NEXT: [[TMP100:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK20-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP100]], 1 -// CHECK20-NEXT: [[TMP101:%.*]] = zext i32 [[ADD29]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP101]]) -// CHECK20-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147.region_id, i32 4, i8** [[TMP95]], i8** [[TMP96]], i64* [[TMP97]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 -// CHECK20-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] -// CHECK20: omp_offload.failed30: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147(i32 [[TMP66]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP68]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT31]] -// CHECK20: omp_offload.cont31: -// CHECK20-NEXT: [[TMP104:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP104]], i32* [[N_CASTED32]], align 4 -// CHECK20-NEXT: [[TMP105:%.*]] = load i32, i32* [[N_CASTED32]], align 4 -// CHECK20-NEXT: [[TMP106:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK20-NEXT: [[TMP107:%.*]] = sext i32 [[TMP106]] to i64 -// CHECK20-NEXT: [[TMP108:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* -// CHECK20-NEXT: store i32 [[TMP105]], i32* [[TMP109]], align 4 -// CHECK20-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32* -// CHECK20-NEXT: store i32 [[TMP105]], i32* [[TMP111]], align 4 -// CHECK20-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP112]], align 4 -// CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP113]], align 4 -// CHECK20-NEXT: [[TMP114:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP115]], align 4 -// CHECK20-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP117]], align 4 -// CHECK20-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP118]], align 4 -// CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP119]], align 4 -// CHECK20-NEXT: [[TMP120:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP121]], align 4 -// CHECK20-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP123]], align 4 -// CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 2 -// CHECK20-NEXT: store i64 [[TMP107]], i64* [[TMP124]], align 4 -// CHECK20-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP125]], align 4 -// CHECK20-NEXT: [[TMP126:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP128:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES36]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP129:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP129]], i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK20-NEXT: [[TMP130:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK20-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP130]], 0 -// CHECK20-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 -// CHECK20-NEXT: [[SUB42:%.*]] = sub nsw i32 [[DIV41]], 1 -// CHECK20-NEXT: store i32 [[SUB42]], i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK20-NEXT: [[TMP131:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_39]], align 4 -// CHECK20-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP131]], 1 -// CHECK20-NEXT: [[TMP132:%.*]] = zext i32 [[ADD43]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP132]]) -// CHECK20-NEXT: [[TMP133:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151.region_id, i32 3, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP134:%.*]] = icmp ne i32 [[TMP133]], 0 -// CHECK20-NEXT: br i1 [[TMP134]], label [[OMP_OFFLOAD_FAILED44:%.*]], label [[OMP_OFFLOAD_CONT45:%.*]] -// CHECK20: omp_offload.failed44: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151(i32 [[TMP105]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT45]] -// CHECK20: omp_offload.cont45: -// CHECK20-NEXT: [[TMP135:%.*]] = load i32, i32* [[M]], align 4 -// CHECK20-NEXT: store i32 [[TMP135]], i32* [[DOTCAPTURE_EXPR_46]], align 4 -// CHECK20-NEXT: [[TMP136:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP136]], i32* [[N_CASTED47]], align 4 -// CHECK20-NEXT: [[TMP137:%.*]] = load i32, i32* [[N_CASTED47]], align 4 -// CHECK20-NEXT: [[TMP138:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_46]], align 4 -// CHECK20-NEXT: store i32 [[TMP138]], i32* [[DOTCAPTURE_EXPR__CASTED48]], align 4 -// CHECK20-NEXT: [[TMP139:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED48]], align 4 -// CHECK20-NEXT: [[TMP140:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK20-NEXT: [[TMP141:%.*]] = sext i32 [[TMP140]] to i64 -// CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32* -// CHECK20-NEXT: store i32 [[TMP137]], i32* [[TMP143]], align 4 -// CHECK20-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i32* -// CHECK20-NEXT: store i32 [[TMP137]], i32* [[TMP145]], align 4 -// CHECK20-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP146]], align 4 -// CHECK20-NEXT: [[TMP147:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP147]], align 4 -// CHECK20-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP149]], align 4 -// CHECK20-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP151]], align 4 -// CHECK20-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP152]], align 4 -// CHECK20-NEXT: [[TMP153:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP153]], align 4 -// CHECK20-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP155]], align 4 -// CHECK20-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP157]], align 4 -// CHECK20-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 2 -// CHECK20-NEXT: store i64 [[TMP141]], i64* [[TMP158]], align 4 -// CHECK20-NEXT: [[TMP159:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP159]], align 4 -// CHECK20-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP161:%.*]] = bitcast i8** [[TMP160]] to i32* -// CHECK20-NEXT: store i32 [[TMP139]], i32* [[TMP161]], align 4 -// CHECK20-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP163:%.*]] = bitcast i8** [[TMP162]] to i32* -// CHECK20-NEXT: store i32 [[TMP139]], i32* [[TMP163]], align 4 -// CHECK20-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 3 -// CHECK20-NEXT: store i64 4, i64* [[TMP164]], align 4 -// CHECK20-NEXT: [[TMP165:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS51]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP165]], align 4 -// CHECK20-NEXT: [[TMP166:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP167:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS50]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP168:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES52]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP169:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP169]], i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK20-NEXT: [[TMP170:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_54]], align 4 -// CHECK20-NEXT: [[SUB56:%.*]] = sub nsw i32 [[TMP170]], 0 -// CHECK20-NEXT: [[DIV57:%.*]] = sdiv i32 [[SUB56]], 1 -// CHECK20-NEXT: [[SUB58:%.*]] = sub nsw i32 [[DIV57]], 1 -// CHECK20-NEXT: store i32 [[SUB58]], i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK20-NEXT: [[TMP171:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_55]], align 4 -// CHECK20-NEXT: [[ADD59:%.*]] = add nsw i32 [[TMP171]], 1 -// CHECK20-NEXT: [[TMP172:%.*]] = zext i32 [[ADD59]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP172]]) -// CHECK20-NEXT: [[TMP173:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155.region_id, i32 4, i8** [[TMP166]], i8** [[TMP167]], i64* [[TMP168]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0 -// CHECK20-NEXT: br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED60:%.*]], label [[OMP_OFFLOAD_CONT61:%.*]] -// CHECK20: omp_offload.failed60: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP137]], i32 [[TMP0]], i32* [[VLA]], i32 [[TMP139]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT61]] -// CHECK20: omp_offload.cont61: -// CHECK20-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) -// CHECK20-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK20-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) -// CHECK20-NEXT: [[TMP177:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: ret i32 [[TMP177]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK20-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] -// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP28]], [[TMP29]] -// CHECK20-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK20: cond.true11: -// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: br label [[COND_END13:%.*]] -// CHECK20: cond.false12: -// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END13]] -// CHECK20: cond.end13: -// CHECK20-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE11]] ], [ [[TMP31]], [[COND_FALSE12]] ] -// CHECK20-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 1073741859, i32 [[TMP8]], i32 [[TMP9]], i32 1, i32 1) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP19]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP5]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP20]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP20]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK20-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK20-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK20-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK20-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK20-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK20: omp_offload.failed5: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK20: omp_offload.cont6: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK20-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP24]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* -// CHECK20-NEXT: store i32 [[TMP20]], i32* [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK20-NEXT: store i32 [[TMP20]], i32* [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120.region_id, i32 2, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK20: omp_offload.failed11: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120([10 x i32]* [[A]], i32 [[TMP20]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK20: omp_offload.cont12: -// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP36]], align 4 -// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP38]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 -// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124.region_id, i32 1, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 -// CHECK20-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK20: omp_offload.failed17: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK20: omp_offload.cont18: -// CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[M]], align 4 -// CHECK20-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_19]], align 4 -// CHECK20-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 -// CHECK20-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 -// CHECK20-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 -// CHECK20-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP48]], align 4 -// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP50]], align 4 -// CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP51]], align 4 -// CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* -// CHECK20-NEXT: store i32 [[TMP46]], i32* [[TMP53]], align 4 -// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i32* -// CHECK20-NEXT: store i32 [[TMP46]], i32* [[TMP55]], align 4 -// CHECK20-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP56]], align 4 -// CHECK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128.region_id, i32 2, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 -// CHECK20-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] -// CHECK20: omp_offload.failed25: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128([10 x i32]* [[A]], i32 [[TMP46]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT26]] -// CHECK20: omp_offload.cont26: -// CHECK20-NEXT: ret i32 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP16]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP12]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@main -// CHECK21-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK21-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK21-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2:%.*]] -// CHECK21: for.cond2: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK21-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK21: for.body4: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK21-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK21: for.end9: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11:%.*]] -// CHECK21: for.cond11: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK21-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK21: for.body13: -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK21-NEXT: br label [[FOR_INC16:%.*]] -// CHECK21: for.inc16: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK21-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end18: -// CHECK21-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20:%.*]] -// CHECK21: for.cond20: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], [[TMP17]] -// CHECK21-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK21: for.body22: -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM23]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK21-NEXT: br label [[FOR_INC25:%.*]] -// CHECK21: for.inc25: -// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK21-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK21: for.end27: -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30:%.*]] -// CHECK21: for.cond30: -// CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] -// CHECK21-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK21: for.body32: -// CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK21-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM33]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK21-NEXT: br label [[FOR_INC35:%.*]] -// CHECK21: for.inc35: -// CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK21-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK21: for.end37: -// CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP25]]) -// CHECK21-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK21-NEXT: [[TMP26:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP26]]) -// CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: ret i32 [[TMP27]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK21-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2:%.*]] -// CHECK21: for.cond2: -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK21-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK21: for.body4: -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK21-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK21: for.end9: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11:%.*]] -// CHECK21: for.cond11: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK21-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK21: for.body13: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK21-NEXT: br label [[FOR_INC16:%.*]] -// CHECK21: for.inc16: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK21: for.end18: -// CHECK21-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20:%.*]] -// CHECK21: for.cond20: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK21-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK21: for.body22: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM23]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK21-NEXT: br label [[FOR_INC25:%.*]] -// CHECK21: for.inc25: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK21: for.end27: -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30:%.*]] -// CHECK21: for.cond30: -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK21-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK21: for.body32: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK21-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM33]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK21-NEXT: br label [[FOR_INC35:%.*]] -// CHECK21: for.inc35: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK21-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK21: for.end37: -// CHECK21-NEXT: ret i32 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@main -// CHECK22-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK22-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK22-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2:%.*]] -// CHECK22: for.cond2: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK22-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK22: for.body4: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK22-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK22: for.end9: -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11:%.*]] -// CHECK22: for.cond11: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK22-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK22: for.body13: -// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK22-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK22-NEXT: br label [[FOR_INC16:%.*]] -// CHECK22: for.inc16: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK22-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK22: for.end18: -// CHECK22-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20:%.*]] -// CHECK22: for.cond20: -// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], [[TMP17]] -// CHECK22-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK22: for.body22: -// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK22-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM23]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK22-NEXT: br label [[FOR_INC25:%.*]] -// CHECK22: for.inc25: -// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK22-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK22: for.end27: -// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30:%.*]] -// CHECK22: for.cond30: -// CHECK22-NEXT: [[TMP21:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] -// CHECK22-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK22: for.body32: -// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK22-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM33]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK22-NEXT: br label [[FOR_INC35:%.*]] -// CHECK22: for.inc35: -// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK22-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK22: for.end37: -// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP25]]) -// CHECK22-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK22-NEXT: [[TMP26:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP26]]) -// CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: ret i32 [[TMP27]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK22-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2:%.*]] -// CHECK22: for.cond2: -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK22-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK22: for.body4: -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK22-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK22: for.end9: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11:%.*]] -// CHECK22: for.cond11: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK22-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK22: for.body13: -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK22-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK22-NEXT: br label [[FOR_INC16:%.*]] -// CHECK22: for.inc16: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK22-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK22: for.end18: -// CHECK22-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20:%.*]] -// CHECK22: for.cond20: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK22-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK22: for.body22: -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK22-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM23]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK22-NEXT: br label [[FOR_INC25:%.*]] -// CHECK22: for.inc25: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK22-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK22: for.end27: -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30:%.*]] -// CHECK22: for.cond30: -// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK22-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK22: for.body32: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK22-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM33]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK22-NEXT: br label [[FOR_INC35:%.*]] -// CHECK22: for.inc35: -// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK22-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK22: for.end37: -// CHECK22-NEXT: ret i32 0 -// -// -// CHECK23-LABEL: define {{[^@]+}}@main -// CHECK23-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK23-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK23-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK23-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2:%.*]] -// CHECK23: for.cond2: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK23-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK23: for.body4: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK23-NEXT: br label [[FOR_INC6:%.*]] -// CHECK23: for.inc6: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK23: for.end8: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10:%.*]] -// CHECK23: for.cond10: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK23-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK23: for.body12: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: br label [[FOR_INC14:%.*]] -// CHECK23: for.inc14: -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK23-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK23: for.end16: -// CHECK23-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18:%.*]] -// CHECK23: for.cond18: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP15]], [[TMP16]] -// CHECK23-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK23: for.body20: -// CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP17]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK23-NEXT: br label [[FOR_INC22:%.*]] -// CHECK23: for.inc22: -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK23-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK23: for.end24: -// CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27:%.*]] -// CHECK23: for.cond27: -// CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[TMP21:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]] -// CHECK23-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK23: for.body29: -// CHECK23-NEXT: [[TMP22:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP22]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK23-NEXT: br label [[FOR_INC31:%.*]] -// CHECK23: for.inc31: -// CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK23-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK23: for.end33: -// CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP24]]) -// CHECK23-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK23-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) -// CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK23-NEXT: ret i32 [[TMP26]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK23-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2:%.*]] -// CHECK23: for.cond2: -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK23-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK23: for.body4: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK23-NEXT: br label [[FOR_INC6:%.*]] -// CHECK23: for.inc6: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK23-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK23: for.end8: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10:%.*]] -// CHECK23: for.cond10: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK23-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK23: for.body12: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: br label [[FOR_INC14:%.*]] -// CHECK23: for.inc14: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK23: for.end16: -// CHECK23-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18:%.*]] -// CHECK23: for.cond18: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK23-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK23: for.body20: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK23-NEXT: br label [[FOR_INC22:%.*]] -// CHECK23: for.inc22: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK23-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK23: for.end24: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27:%.*]] -// CHECK23: for.cond27: -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK23-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK23: for.body29: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP15]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK23-NEXT: br label [[FOR_INC31:%.*]] -// CHECK23: for.inc31: -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK23-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK23: for.end33: -// CHECK23-NEXT: ret i32 0 -// -// -// CHECK24-LABEL: define {{[^@]+}}@main -// CHECK24-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK24-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK24-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK24-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2:%.*]] -// CHECK24: for.cond2: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK24-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK24: for.body4: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK24-NEXT: br label [[FOR_INC6:%.*]] -// CHECK24: for.inc6: -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK24-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK24: for.end8: -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10:%.*]] -// CHECK24: for.cond10: -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK24-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK24: for.body12: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: br label [[FOR_INC14:%.*]] -// CHECK24: for.inc14: -// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK24-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK24: for.end16: -// CHECK24-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18:%.*]] -// CHECK24: for.cond18: -// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP15]], [[TMP16]] -// CHECK24-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK24: for.body20: -// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP17]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK24-NEXT: br label [[FOR_INC22:%.*]] -// CHECK24: for.inc22: -// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK24-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK24: for.end24: -// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27:%.*]] -// CHECK24: for.cond27: -// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[TMP21:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]] -// CHECK24-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK24: for.body29: -// CHECK24-NEXT: [[TMP22:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP22]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK24-NEXT: br label [[FOR_INC31:%.*]] -// CHECK24: for.inc31: -// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK24-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK24: for.end33: -// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP24]]) -// CHECK24-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK24-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) -// CHECK24-NEXT: [[TMP26:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK24-NEXT: ret i32 [[TMP26]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK24-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2:%.*]] -// CHECK24: for.cond2: -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK24-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK24: for.body4: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK24-NEXT: br label [[FOR_INC6:%.*]] -// CHECK24: for.inc6: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK24-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK24: for.end8: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10:%.*]] -// CHECK24: for.cond10: -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK24-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK24: for.body12: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: br label [[FOR_INC14:%.*]] -// CHECK24: for.inc14: -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK24-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK24: for.end16: -// CHECK24-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18:%.*]] -// CHECK24: for.cond18: -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK24-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK24: for.body20: -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK24-NEXT: br label [[FOR_INC22:%.*]] -// CHECK24: for.inc22: -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK24-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK24: for.end24: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27:%.*]] -// CHECK24: for.cond27: -// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK24-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK24: for.body29: -// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP15]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK24-NEXT: br label [[FOR_INC31:%.*]] -// CHECK24: for.inc31: -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK24-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK24: for.end33: -// CHECK24-NEXT: ret i32 0 -// diff --git a/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2091,6 +2091,28 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: @@ -2129,191 +2151,6 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done8: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK5: arraydestroy.body10: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK5: arraydestroy.done14: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP11]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: @@ -2331,73 +2168,108 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* undef, i32** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK5-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[SIVAR]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK5-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK5-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK5-NEXT: ret void // // @@ -2410,6 +2282,13 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: @@ -2438,6 +2317,28 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: @@ -2476,191 +2377,6 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done8: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK6: arraydestroy.body10: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK6: arraydestroy.done14: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP11]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: @@ -2678,73 +2394,108 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK6-NEXT: ret i32 0 // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* undef, i32** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK6-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[SIVAR]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK6-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK6-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK6-NEXT: ret void // // @@ -2757,1404 +2508,9 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK7-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK7-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done7: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK7: arraydestroy.body9: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK7: arraydestroy.done13: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP11]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK8-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done7: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK8: arraydestroy.body9: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK8: arraydestroy.done13: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP11]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 -// CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init() -// CHECK9-NEXT: call void @__cxx_global_var_init.1() -// CHECK9-NEXT: call void @__cxx_global_var_init.2() -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 -// CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__cxx_global_var_init() -// CHECK10-NEXT: call void @__cxx_global_var_init.1() -// CHECK10-NEXT: call void @__cxx_global_var_init.2() -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1374,544 +1374,292 @@ // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP14:%.*]] = bitcast i32* [[SIVAR1]] to i8* +// CHECK5-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK5-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP15]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: switch i32 [[TMP16]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK5-NEXT: ] +// CHECK5: .omp.reduction.case1: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK5: .omp.reduction.case2: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP19]] monotonic, align 4 +// CHECK5-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK5: .omp.reduction.default: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK5-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK5-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP14:%.*]] = bitcast i32* [[SIVAR1]] to i8* -// CHECK9-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP15]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: switch i32 [[TMP16]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK9-NEXT: ] -// CHECK9: .omp.reduction.case1: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.case2: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP19]] monotonic, align 4 -// CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.default: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK9-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK10-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK10-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP14:%.*]] = bitcast i32* [[SIVAR1]] to i8* -// CHECK10-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP15]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: switch i32 [[TMP16]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK10-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK10-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK10-NEXT: ] -// CHECK10: .omp.reduction.case1: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK10: .omp.reduction.case2: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP19]] monotonic, align 4 -// CHECK10-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK10: .omp.reduction.default: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK10-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP14:%.*]] = bitcast i32* [[SIVAR1]] to i8* +// CHECK6-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK6-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP15]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: switch i32 [[TMP16]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.reduction.case1: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.case2: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP19]] monotonic, align 4 +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.default: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp --- a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp @@ -7,65 +7,65 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1974,426 +1974,1004 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK5-NEXT: ret i32 [[CONV4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK5-SAME: () #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: ret i32 [[ADD2]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK6-NEXT: ret i32 [[CONV4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: ret i32 [[ADD2]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK7-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK7-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK7-NEXT: ret i32 [[CONV4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: ret i32 [[ADD2]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK8-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK8-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK8-NEXT: ret i32 [[CONV4]] +// CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: ret i32 [[ADD2]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK8-SAME: () #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z3bari +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP6]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK9-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK9-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK9-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK9-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK9-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) +// CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK9-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK9: omp_offload.failed7: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK9: omp_offload.cont8: +// CHECK9-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK9-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK9-NEXT: ret i32 [[CONV10]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) +// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK9-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK9-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK9-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK9: omp_offload.failed7: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK9: omp_offload.cont8: +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK9-NEXT: ret i32 [[ADD9]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) +// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK9-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK9-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK9-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK9-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) +// CHECK9-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK9-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK9: omp_offload.failed3: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK9: omp_offload.cont4: +// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP30]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2412,12 +2990,12 @@ // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2438,19 +3016,19 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2464,17 +3042,63 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK9-SAME: () #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK9-SAME: () #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2484,7 +3108,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2509,12 +3133,12 @@ // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2534,54 +3158,277 @@ // CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@_Z3bari +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP6]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK10-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK10-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK10-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK10-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK10-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) +// CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK10-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK10: omp_offload.failed7: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK10: omp_offload.cont8: +// CHECK10-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK10-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK10-NEXT: ret i32 [[CONV10]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: ret void +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) +// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK10-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK10-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK10-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK10: omp_offload.failed7: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK10: omp_offload.cont8: +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK10-NEXT: ret i32 [[ADD9]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) +// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK10-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK10-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK10-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK10-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) +// CHECK10-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK10-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK10: omp_offload.failed3: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK10: omp_offload.cont4: +// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP30]] // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2600,12 +3447,12 @@ // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2626,19 +3473,19 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2652,17 +3499,63 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK10-SAME: () #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2672,7 +3565,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2697,12 +3590,12 @@ // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2722,52 +3615,272 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: ret void +// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@_Z3bari +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP6]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK11-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: ret void +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK11-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK11-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK11-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK11-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) +// CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK11-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK11: omp_offload.failed6: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK11: omp_offload.cont7: +// CHECK11-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK11-NEXT: ret i32 [[CONV]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) +// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK11-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK11-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK11: omp_offload.failed6: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK11: omp_offload.cont7: +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK11-NEXT: ret i32 [[ADD8]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) +// CHECK11-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK11-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK11-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK11-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) +// CHECK11-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK11-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK11: omp_offload.failed2: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK11: omp_offload.cont3: +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP30]] // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2783,12 +3896,12 @@ // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2808,19 +3921,19 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2834,17 +3947,61 @@ // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK11-SAME: () #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK11-SAME: () #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2854,7 +4011,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2877,12 +4034,12 @@ // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2901,52 +4058,272 @@ // CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void +// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@_Z3bari +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP6]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK12-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK12-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK12-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK12-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK12-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) +// CHECK12-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK12-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK12: omp_offload.failed6: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK12: omp_offload.cont7: +// CHECK12-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK12-NEXT: ret i32 [[CONV]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: ret void +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) +// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK12-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK12-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK12: omp_offload.failed6: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK12: omp_offload.cont7: +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK12-NEXT: ret i32 [[ADD8]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) +// CHECK12-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK12-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK12-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK12-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) +// CHECK12-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK12-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK12: omp_offload.failed2: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK12: omp_offload.cont3: +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP30]] // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2962,12 +4339,12 @@ // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2987,19 +4364,19 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3013,17 +4390,61 @@ // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK12-SAME: () #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK12-SAME: () #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3033,7 +4454,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3056,12 +4477,12 @@ // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3080,3652 +4501,743 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK12-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK13-NEXT: ret i32 [[CONV4]] +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK13-SAME: () #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: ret i32 [[ADD2]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK14-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK14-NEXT: ret i32 [[CONV4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK14-SAME: () #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void // // -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: ret i32 [[ADD2]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK15-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK15-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK15-NEXT: ret i32 [[CONV4]] +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK15-SAME: () #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void // // -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: ret i32 [[ADD2]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK16-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK16-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK16-NEXT: ret i32 [[CONV4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK16-SAME: () #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void // // -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: ret i32 [[ADD2]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP6]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK17-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK17-NEXT: store double* [[A]], double** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) -// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK17-NEXT: store double* [[A3]], double** [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) -// CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK17: omp_offload.failed7: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK17: omp_offload.cont8: -// CHECK17-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 -// CHECK17-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK17-NEXT: ret i32 [[CONV10]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) -// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* -// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) -// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK17: omp_offload.failed7: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK17: omp_offload.cont8: -// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 -// CHECK17-NEXT: ret i32 [[ADD9]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) -// CHECK17-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK17-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* -// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK17-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 -// CHECK17-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) -// CHECK17-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK17-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK17: omp_offload.failed3: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK17: omp_offload.cont4: -// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP30]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK17-SAME: () #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP6]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK18-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK18-NEXT: store double* [[A]], double** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) -// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK18-NEXT: store double* [[A3]], double** [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) -// CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK18: omp_offload.failed7: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK18: omp_offload.cont8: -// CHECK18-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 -// CHECK18-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK18-NEXT: ret i32 [[CONV10]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) -// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* -// CHECK18-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) -// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK18: omp_offload.failed7: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK18: omp_offload.cont8: -// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 -// CHECK18-NEXT: ret i32 [[ADD9]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) -// CHECK18-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK18-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* -// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK18-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 -// CHECK18-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) -// CHECK18-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK18-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK18: omp_offload.failed3: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK18: omp_offload.cont4: -// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP30]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK18-SAME: () #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP6]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK19-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK19-NEXT: store double* [[A]], double** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) -// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK19-NEXT: store double* [[A2]], double** [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) -// CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK19: omp_offload.failed6: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK19: omp_offload.cont7: -// CHECK19-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK19-NEXT: ret i32 [[CONV]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) -// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) -// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK19: omp_offload.failed6: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK19: omp_offload.cont7: -// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 -// CHECK19-NEXT: ret i32 [[ADD8]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) -// CHECK19-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK19-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK19-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 -// CHECK19-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) -// CHECK19-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK19-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK19: omp_offload.failed2: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK19: omp_offload.cont3: -// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP30]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK19-SAME: () #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP6]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK20-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK20-NEXT: store double* [[A]], double** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) -// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK20-NEXT: store double* [[A2]], double** [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) -// CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK20: omp_offload.failed6: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK20: omp_offload.cont7: -// CHECK20-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK20-NEXT: ret i32 [[CONV]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) -// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 -// CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) -// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK20: omp_offload.failed6: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK20: omp_offload.cont7: -// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 -// CHECK20-NEXT: ret i32 [[ADD8]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) -// CHECK20-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK20-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK20-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 -// CHECK20-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) -// CHECK20-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK20-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK20: omp_offload.failed2: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK20: omp_offload.cont3: -// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP30]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK20-SAME: () #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP6]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK21-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK21-NEXT: ret i32 [[CONV4]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: ret i32 [[ADD2]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP6]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK22-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK22-NEXT: ret i32 [[CONV4]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: ret i32 [[ADD2]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP6]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK23-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK23-NEXT: ret i32 [[CONV4]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: ret i32 [[ADD2]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP6]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK24-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK24-NEXT: ret i32 [[CONV4]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: ret i32 [[ADD2]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK25-SAME: () #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK26-SAME: () #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK27-SAME: () #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK28-SAME: () #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP6]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK29-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK29-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK29-NEXT: ret i32 [[CONV4]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: ret i32 [[ADD2]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP6]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK30-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK30-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK30-NEXT: ret i32 [[CONV4]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: ret i32 [[ADD2]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP6]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK31-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK31-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK31-NEXT: ret i32 [[CONV4]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: ret i32 [[ADD2]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP6]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK32-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK32-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK32-NEXT: ret i32 [[CONV4]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: ret i32 [[ADD2]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp --- a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp +++ b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp @@ -7,65 +7,65 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2058,446 +2058,1036 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK5-NEXT: ret i32 [[CONV4]] +// CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK5-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: ret i32 [[ADD3]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK5-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK6-NEXT: ret i32 [[CONV4]] +// CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK6-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: ret i32 [[ADD3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK6-SAME: () #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK6-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK7-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK7-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK7-NEXT: ret i32 [[CONV4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK7-SAME: () #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK7-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: ret i32 [[ADD3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK7-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK7-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK8-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK8-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK8-NEXT: ret i32 [[CONV4]] +// CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK8-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: ret i32 [[ADD3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK8-SAME: () #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK8-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK8-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z3bari +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP6]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK9-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK9-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK9-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) +// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK9-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK9-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK9-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) +// CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK9-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK9: omp_offload.failed7: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK9: omp_offload.cont8: +// CHECK9-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK9-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK9-NEXT: ret i32 [[CONV10]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 +// CHECK9-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) +// CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK9-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5]] to i32* +// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV6]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK9-NEXT: store i64 [[TMP24]], i64* [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK9-NEXT: store i64 [[TMP24]], i64* [[TMP28]], align 8 +// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) +// CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK9-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] +// CHECK9: omp_offload.failed10: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP24]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT11]] +// CHECK9: omp_offload.cont11: +// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK9-NEXT: ret i32 [[ADD12]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) +// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK9-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK9-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK9-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK9-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK9-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) +// CHECK9-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK9-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK9: omp_offload.failed3: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK9: omp_offload.cont4: +// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: ret i32 [[TMP30]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2516,12 +3106,12 @@ // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2542,19 +3132,19 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2568,17 +3158,67 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK9-SAME: () #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK9-SAME: () #[[ATTR1]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2588,7 +3228,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2613,12 +3253,12 @@ // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2638,58 +3278,295 @@ // CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@_Z3bari +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP6]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK10-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK10-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK10-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) +// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK10-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK10-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK10-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) +// CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK10-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK10: omp_offload.failed7: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK10: omp_offload.cont8: +// CHECK10-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK10-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK10-NEXT: ret i32 [[CONV10]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: ret void +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 +// CHECK10-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP12]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP14]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) +// CHECK10-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK10-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5]] to i32* +// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK10-NEXT: store i64 [[TMP24]], i64* [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK10-NEXT: store i64 [[TMP24]], i64* [[TMP28]], align 8 +// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK10-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) +// CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK10-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] +// CHECK10: omp_offload.failed10: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP24]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT11]] +// CHECK10: omp_offload.cont11: +// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK10-NEXT: ret i32 [[ADD12]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) +// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK10-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK10-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK10-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK10-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) +// CHECK10-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK10-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK10: omp_offload.failed3: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK10: omp_offload.cont4: +// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: ret i32 [[TMP30]] // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2708,12 +3585,12 @@ // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2734,19 +3611,19 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2760,17 +3637,67 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK10-SAME: () #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2780,7 +3707,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2805,12 +3732,12 @@ // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2830,55 +3757,289 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void +// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@_Z3bari +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP6]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK11-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK11-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK11-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) +// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK11-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK11-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK11-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) +// CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK11-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK11: omp_offload.failed6: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK11: omp_offload.cont7: +// CHECK11-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK11-NEXT: ret i32 [[CONV]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 +// CHECK11-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) +// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK11-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK11-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK11-NEXT: store i32 [[TMP24]], i32* [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK11-NEXT: store i32 [[TMP24]], i32* [[TMP28]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK11-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) +// CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK11-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] +// CHECK11: omp_offload.failed8: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP24]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT9]] +// CHECK11: omp_offload.cont9: +// CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK11-NEXT: ret i32 [[ADD10]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: ret void +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) +// CHECK11-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK11-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK11-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK11-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK11-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) +// CHECK11-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK11-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK11: omp_offload.failed2: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK11: omp_offload.cont3: +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: ret i32 [[TMP30]] // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2894,12 +4055,12 @@ // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2919,19 +4080,19 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2945,17 +4106,64 @@ // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK11-SAME: () #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK11-SAME: () #[[ATTR1]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2965,7 +4173,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2988,12 +4196,12 @@ // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3012,55 +4220,289 @@ // CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void +// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@_Z3bari +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP6]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK12-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK12-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK12-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) +// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK12-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK12-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK12-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) +// CHECK12-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK12-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK12: omp_offload.failed6: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK12: omp_offload.cont7: +// CHECK12-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK12-NEXT: ret i32 [[CONV]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: ret void +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 +// CHECK12-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) +// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK12-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK12-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK12-NEXT: store i32 [[TMP24]], i32* [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK12-NEXT: store i32 [[TMP24]], i32* [[TMP28]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK12-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) +// CHECK12-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK12-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] +// CHECK12: omp_offload.failed8: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP24]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT9]] +// CHECK12: omp_offload.cont9: +// CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK12-NEXT: ret i32 [[ADD10]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) +// CHECK12-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK12-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK12-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK12-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) +// CHECK12-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK12-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK12: omp_offload.failed2: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK12: omp_offload.cont3: +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: ret i32 [[TMP30]] // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3076,12 +4518,12 @@ // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3101,19 +4543,19 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3127,17 +4569,64 @@ // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK12-SAME: () #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK12-SAME: () #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3147,7 +4636,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3170,12 +4659,12 @@ // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3194,3798 +4683,757 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK12-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK13-NEXT: ret i32 [[CONV4]] +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK13-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK13-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK13-SAME: () #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK13-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: ret i32 [[ADD3]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK13-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK13-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK13-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK14-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK14-NEXT: ret i32 [[CONV4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK14-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK14-SAME: () #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: ret void // // -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK14-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK14-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: ret i32 [[ADD3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK14-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK15-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK15-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK15-NEXT: ret i32 [[CONV4]] +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK15-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK15-SAME: () #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: ret void // // -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK15-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK15-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: ret i32 [[ADD3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK15-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK15-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK15-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK16-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK16-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double // CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK16-NEXT: ret i32 [[CONV4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK16-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK16-SAME: () #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: ret void // // -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK16-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK16-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: ret i32 [[ADD3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK16-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP6]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK17-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK17-NEXT: store double* [[A]], double** [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) -// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK17-NEXT: store double* [[A3]], double** [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) -// CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK17: omp_offload.failed7: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK17: omp_offload.cont8: -// CHECK17-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 -// CHECK17-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK17-NEXT: ret i32 [[CONV10]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK17-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* -// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP14]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) -// CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK17-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5]] to i32* -// CHECK17-NEXT: store i32 [[TMP23]], i32* [[CONV6]], align 4 -// CHECK17-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5]], align 8 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK17-NEXT: store i64 [[TMP24]], i64* [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK17-NEXT: store i64 [[TMP24]], i64* [[TMP28]], align 8 -// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) -// CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] -// CHECK17: omp_offload.failed10: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP24]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT11]] -// CHECK17: omp_offload.cont11: -// CHECK17-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK17-NEXT: ret i32 [[ADD12]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) -// CHECK17-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK17-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK17-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* -// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK17-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 -// CHECK17-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) -// CHECK17-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK17-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK17: omp_offload.failed3: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK17: omp_offload.cont4: -// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: ret i32 [[TMP30]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK17-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK17-SAME: () #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP6]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK18-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK18-NEXT: store double* [[A]], double** [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) -// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK18-NEXT: store double* [[A3]], double** [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) -// CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK18: omp_offload.failed7: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK18: omp_offload.cont8: -// CHECK18-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 -// CHECK18-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK18-NEXT: ret i32 [[CONV10]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK18-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* -// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP12]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP14]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) -// CHECK18-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK18-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5]] to i32* -// CHECK18-NEXT: store i32 [[TMP23]], i32* [[CONV6]], align 4 -// CHECK18-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5]], align 8 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK18-NEXT: store i64 [[TMP24]], i64* [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK18-NEXT: store i64 [[TMP24]], i64* [[TMP28]], align 8 -// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) -// CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] -// CHECK18: omp_offload.failed10: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP24]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT11]] -// CHECK18: omp_offload.cont11: -// CHECK18-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK18-NEXT: ret i32 [[ADD12]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) -// CHECK18-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK18-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK18-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* -// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* -// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* -// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK18-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 -// CHECK18-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) -// CHECK18-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK18-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK18: omp_offload.failed3: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK18: omp_offload.cont4: -// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: ret i32 [[TMP30]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK18-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK18-SAME: () #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP6]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK19-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK19-NEXT: store double* [[A]], double** [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) -// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK19-NEXT: store double* [[A2]], double** [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) -// CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK19: omp_offload.failed6: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK19: omp_offload.cont7: -// CHECK19-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK19-NEXT: ret i32 [[CONV]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK19-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) -// CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK19-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK19-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK19-NEXT: store i32 [[TMP24]], i32* [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK19-NEXT: store i32 [[TMP24]], i32* [[TMP28]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) -// CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] -// CHECK19: omp_offload.failed8: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP24]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT9]] -// CHECK19: omp_offload.cont9: -// CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK19-NEXT: ret i32 [[ADD10]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) -// CHECK19-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK19-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK19-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK19-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 -// CHECK19-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) -// CHECK19-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK19-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK19: omp_offload.failed2: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK19: omp_offload.cont3: -// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: ret i32 [[TMP30]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK19-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK19-SAME: () #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP6]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK20-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** -// CHECK20-NEXT: store double* [[A]], double** [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) -// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** -// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** -// CHECK20-NEXT: store double* [[A2]], double** [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) -// CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK20: omp_offload.failed6: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK20: omp_offload.cont7: -// CHECK20-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 -// CHECK20-NEXT: ret i32 [[CONV]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK20-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) -// CHECK20-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK20-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK20-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK20-NEXT: store i32 [[TMP24]], i32* [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK20-NEXT: store i32 [[TMP24]], i32* [[TMP28]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) -// CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 -// CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] -// CHECK20: omp_offload.failed8: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP24]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT9]] -// CHECK20: omp_offload.cont9: -// CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK20-NEXT: ret i32 [[ADD10]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) -// CHECK20-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK20-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 -// CHECK20-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK20-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 -// CHECK20-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) -// CHECK20-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK20-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK20: omp_offload.failed2: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK20: omp_offload.cont3: -// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: ret i32 [[TMP30]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK20-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK20-SAME: () #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP6]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK21-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK21-NEXT: ret i32 [[CONV4]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK21-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: ret i32 [[ADD3]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP6]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK22-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK22-NEXT: ret i32 [[CONV4]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK22-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: ret i32 [[ADD3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP6]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK23-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK23-NEXT: ret i32 [[CONV4]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK23-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: ret i32 [[ADD3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP6]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK24-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK24-NEXT: ret i32 [[CONV4]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK24-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: ret i32 [[ADD3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK25-SAME: () #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK26-SAME: () #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* -// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 -// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* -// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 -// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK27-SAME: () #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK28-SAME: () #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* -// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* -// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* -// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 -// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP6]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK29-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK29-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK29-NEXT: ret i32 [[CONV4]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK29-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: ret i32 [[ADD3]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP6]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK30-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK30-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK30-NEXT: ret i32 [[CONV4]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK30-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: ret i32 [[ADD3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP6]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK31-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK31-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK31-NEXT: ret i32 [[CONV4]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK31-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: ret i32 [[ADD3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP6]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK32-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK32-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK32-NEXT: ret i32 [[CONV4]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK32-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: ret i32 [[ADD3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 +// CHECK16-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK16-NEXT: ret void // diff --git a/clang/test/OpenMP/task_codegen.cpp b/clang/test/OpenMP/task_codegen.cpp --- a/clang/test/OpenMP/task_codegen.cpp +++ b/clang/test/OpenMP/task_codegen.cpp @@ -6,9 +6,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -4692,341 +4692,3 @@ // CHECK4-NEXT: call void @__cxx_global_var_init() // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[FLAG:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[C:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[S1:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[S2:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: store i32 15, i32* @a, align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* @a, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP4]] to i8 -// CHECK5-NEXT: store i8 [[CONV]], i8* [[B]], align 1 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i64 0, i64 0 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYIDX]], i32 0, i32 0 -// CHECK5-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 15, i32* @a, align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i64 0, i64 1 -// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYIDX1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 10, i32* [[A2]], align 4 -// CHECK5-NEXT: store i32 1, i32* @a, align 4 -// CHECK5-NEXT: store i32 1, i32* @a, align 4 -// CHECK5-NEXT: store i32 1, i32* @a, align 4 -// CHECK5-NEXT: store i32 2, i32* @a, align 4 -// CHECK5-NEXT: store i32 2, i32* @a, align 4 -// CHECK5-NEXT: store i8 0, i8* [[FLAG]], align 1 -// CHECK5-NEXT: store i32 3, i32* @a, align 4 -// CHECK5-NEXT: store i32 4, i32* @a, align 4 -// CHECK5-NEXT: store i32 5, i32* [[C]], align 128 -// CHECK5-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[S1]]) -// CHECK5-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[S2]]) -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A3]], align 4 -// CHECK5-NEXT: store i32 4, i32* [[C]], align 128 -// CHECK5-NEXT: store i32 4, i32* @a, align 4 -// CHECK5-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[S1]] to i8* -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR6:[0-9]+]] -// CHECK5-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2]], i32 0, i32 0 -// CHECK5-NEXT: store i32 10, i32* [[A4]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[S2]]) #[[ATTR6]] -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[S1]]) #[[ATTR6]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* @a, align 4 -// CHECK5-NEXT: store i32 [[TMP7]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done6: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP10]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR4:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN2S1C1Ev(%struct.S1* nonnull dereferenceable(4) @s1) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S1C1Ev -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2S1C2Ev(%struct.S1* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S1C2Ev -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S18taskinitEv -// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(4) [[THIS:%.*]]) #[[ATTR5:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_task_codegen.cpp -// CHECK5-SAME: () #[[ATTR4]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[FLAG:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[C:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[S1:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[S2:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16 -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: store i32 15, i32* @a, align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* @a, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP4]] to i8 -// CHECK6-NEXT: store i8 [[CONV]], i8* [[B]], align 1 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i64 0, i64 0 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYIDX]], i32 0, i32 0 -// CHECK6-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 15, i32* @a, align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i64 0, i64 1 -// CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYIDX1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 10, i32* [[A2]], align 4 -// CHECK6-NEXT: store i32 1, i32* @a, align 4 -// CHECK6-NEXT: store i32 1, i32* @a, align 4 -// CHECK6-NEXT: store i32 1, i32* @a, align 4 -// CHECK6-NEXT: store i32 2, i32* @a, align 4 -// CHECK6-NEXT: store i32 2, i32* @a, align 4 -// CHECK6-NEXT: store i8 0, i8* [[FLAG]], align 1 -// CHECK6-NEXT: store i32 3, i32* @a, align 4 -// CHECK6-NEXT: store i32 4, i32* @a, align 4 -// CHECK6-NEXT: store i32 5, i32* [[C]], align 128 -// CHECK6-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[S1]]) -// CHECK6-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[S2]]) -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A3]], align 4 -// CHECK6-NEXT: store i32 4, i32* [[C]], align 128 -// CHECK6-NEXT: store i32 4, i32* @a, align 4 -// CHECK6-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[S1]] to i8* -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[REF_TMP]]) #[[ATTR6:[0-9]+]] -// CHECK6-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2]], i32 0, i32 0 -// CHECK6-NEXT: store i32 10, i32* [[A4]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[S2]]) #[[ATTR6]] -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[S1]]) #[[ATTR6]] -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* @a, align 4 -// CHECK6-NEXT: store i32 [[TMP7]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK6-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done6: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP10]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR4:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN2S1C1Ev(%struct.S1* nonnull dereferenceable(4) @s1) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S1C1Ev -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2S1C2Ev(%struct.S1* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S1C2Ev -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S18taskinitEv -// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(4) [[THIS:%.*]]) #[[ATTR5:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_task_codegen.cpp -// CHECK6-SAME: () #[[ATTR4]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: ret void -// diff --git a/clang/test/OpenMP/task_if_codegen.cpp b/clang/test/OpenMP/task_if_codegen.cpp --- a/clang/test/OpenMP/task_if_codegen.cpp +++ b/clang/test/OpenMP/task_if_codegen.cpp @@ -3,17 +3,17 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1324,1373 +1324,1233 @@ // CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_Z9gtid_testv() +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK3-NEXT: ret void // // +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to %struct.kmp_task_t_with_privates* +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP2]]) +// CHECK3-NEXT: [[TMP5:%.*]] = call i32 @.omp_task_entry.(i32 [[TMP1]], %struct.kmp_task_t_with_privates* [[TMP3]]) #[[ATTR3:[0-9]+]] +// CHECK3-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP2]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11 +// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11 +// CHECK3-NEXT: call void @_Z9gtid_testv() #[[ATTR3]] +// CHECK3-NEXT: ret i32 0 +// +// // CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: () #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1 +// CHECK3-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 +// CHECK3-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 +// CHECK3-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 +// CHECK3-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK3-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_Z3fn7v() -// CHECK3-NEXT: call void @_Z3fn8v() -// CHECK3-NEXT: call void @_Z3fn9v() -// CHECK3-NEXT: call void @_Z4fn10v() -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) +// CHECK3-NEXT: [[TMP1:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..3 to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.kmp_task_t_with_privates.1* +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP2]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP1]]) +// CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..5 to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.3* +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP6]], i32 0, i32 0 +// CHECK3-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK3-NEXT: [[TMP8:%.*]] = call i32 @.omp_task_entry..5(i32 [[TMP0]], %struct.kmp_task_t_with_privates.3* [[TMP6]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK3-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.5*)* @.omp_task_entry..7 to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.5* +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], %struct.kmp_task_t_with_privates.5* [[TMP10]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK3-NEXT: [[TMP14:%.*]] = call i32 @.omp_task_entry..7(i32 [[TMP0]], %struct.kmp_task_t_with_privates.5* [[TMP10]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: [[TMP15:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.7*)* @.omp_task_entry..9 to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %struct.kmp_task_t_with_privates.7* +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], %struct.kmp_task_t_with_privates.7* [[TMP16]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], %struct.kmp_depend_info* [[TMP18]], i64 0 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 0 +// CHECK3-NEXT: store i64 ptrtoint (i32* @Arg to i64), i64* [[TMP20]], align 8 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 1 +// CHECK3-NEXT: store i64 4, i64* [[TMP21]], align 8 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 2 +// CHECK3-NEXT: store i8 3, i8* [[TMP22]], align 8 +// CHECK3-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR]], align 8 +// CHECK3-NEXT: [[TMP23:%.*]] = bitcast %struct.kmp_depend_info* [[TMP18]] to i8* +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE6:%.*]] +// CHECK3: omp_if.then5: +// CHECK3-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]], i32 1, i8* [[TMP23]], i32 0, i8* null) +// CHECK3-NEXT: br label [[OMP_IF_END7:%.*]] +// CHECK3: omp_if.else6: +// CHECK3-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP23]], i32 0, i8* null) +// CHECK3-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) +// CHECK3-NEXT: [[TMP26:%.*]] = call i32 @.omp_task_entry..9(i32 [[TMP0]], %struct.kmp_task_t_with_privates.7* [[TMP16]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) +// CHECK3-NEXT: br label [[OMP_IF_END7]] +// CHECK3: omp_if.end7: +// CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP27]]) // CHECK3-NEXT: ret i32 [[CALL]] // // +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..3 +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.0*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.1*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates.1* [[TMP1]], %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.1*, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.0* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.1* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 +// CHECK3-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK3-NEXT: call void @_Z3fn7v() #[[ATTR3]] +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..5 +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.2*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates.3* [[TMP1]], %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.3*, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.2* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.3* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !33 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !33 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !33 +// CHECK3-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.2*, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33 +// CHECK3-NEXT: call void @_Z3fn8v() #[[ATTR3]] +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..7 +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.4*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.5*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates.5* [[TMP1]], %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.5*, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.4* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.5* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !43 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !43 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !43 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !43 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !43 +// CHECK3-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.4*, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43 +// CHECK3-NEXT: call void @_Z3fn9v() #[[ATTR3]] +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..9 +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.6*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.7*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates.7* [[TMP1]], %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.7*, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.6* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.7* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !53 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !53 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !53 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !53 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !53 +// CHECK3-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.6*, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53 +// CHECK3-NEXT: call void @_Z4fn10v() #[[ATTR3]] +// CHECK3-NEXT: ret i32 0 +// +// // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 +// CHECK3-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 +// CHECK3-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_12:%.*]], align 1 +// CHECK3-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_14:%.*]], align 1 +// CHECK3-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK3-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[AGG_CAPTURED8:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 1 +// CHECK3-NEXT: [[DOTDEP_ARR_ADDR9:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK3-NEXT: [[DEP_COUNTER_ADDR10:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[AGG_CAPTURED15:%.*]] = alloca [[STRUCT_ANON_18:%.*]], align 1 +// CHECK3-NEXT: [[DOTDEP_ARR_ADDR16:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK3-NEXT: [[DEP_COUNTER_ADDR17:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: call void @_Z3fn1v() -// CHECK3-NEXT: call void @_Z3fn2v() -// CHECK3-NEXT: call void @_Z3fn3v() -// CHECK3-NEXT: call void @_Z3fn4v() -// CHECK3-NEXT: call void @_Z3fn5v() -// CHECK3-NEXT: call void @_Z3fn6v() +// CHECK3-NEXT: [[TMP1:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.9*)* @.omp_task_entry..11 to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.kmp_task_t_with_privates.9* +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], %struct.kmp_task_t_with_privates.9* [[TMP2]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP1]]) +// CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.11*)* @.omp_task_entry..13 to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.11* +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], %struct.kmp_task_t_with_privates.11* [[TMP6]], i32 0, i32 0 +// CHECK3-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK3-NEXT: [[TMP8:%.*]] = call i32 @.omp_task_entry..13(i32 [[TMP0]], %struct.kmp_task_t_with_privates.11* [[TMP6]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK3-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.13*)* @.omp_task_entry..15 to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.13* +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.*]], %struct.kmp_task_t_with_privates.13* [[TMP10]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK3-NEXT: [[TMP14:%.*]] = call i32 @.omp_task_entry..15(i32 [[TMP0]], %struct.kmp_task_t_with_privates.13* [[TMP10]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: [[TMP15:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.15*)* @.omp_task_entry..17 to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %struct.kmp_task_t_with_privates.15* +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.*]], %struct.kmp_task_t_with_privates.15* [[TMP16]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], %struct.kmp_depend_info* [[TMP18]], i64 0 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP21:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 +// CHECK3-NEXT: store i64 [[TMP21]], i64* [[TMP20]], align 8 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 1 +// CHECK3-NEXT: store i64 4, i64* [[TMP22]], align 8 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 2 +// CHECK3-NEXT: store i8 1, i8* [[TMP23]], align 8 +// CHECK3-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR]], align 8 +// CHECK3-NEXT: [[TMP24:%.*]] = bitcast %struct.kmp_depend_info* [[TMP18]] to i8* +// CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK3-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE6:%.*]] +// CHECK3: omp_if.then5: +// CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]], i32 1, i8* [[TMP24]], i32 0, i8* null) +// CHECK3-NEXT: br label [[OMP_IF_END7:%.*]] +// CHECK3: omp_if.else6: +// CHECK3-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP24]], i32 0, i8* null) +// CHECK3-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) +// CHECK3-NEXT: [[TMP27:%.*]] = call i32 @.omp_task_entry..17(i32 [[TMP0]], %struct.kmp_task_t_with_privates.15* [[TMP16]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) +// CHECK3-NEXT: br label [[OMP_IF_END7]] +// CHECK3: omp_if.end7: +// CHECK3-NEXT: [[TMP28:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.17*)* @.omp_task_entry..19 to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to %struct.kmp_task_t_with_privates.17* +// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.*]], %struct.kmp_task_t_with_privates.17* [[TMP29]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR9]], i64 0, i64 0 +// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP31]], i64 0 +// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP34:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 +// CHECK3-NEXT: store i64 [[TMP34]], i64* [[TMP33]], align 8 +// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 1 +// CHECK3-NEXT: store i64 4, i64* [[TMP35]], align 8 +// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 2 +// CHECK3-NEXT: store i8 3, i8* [[TMP36]], align 8 +// CHECK3-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR10]], align 8 +// CHECK3-NEXT: [[TMP37:%.*]] = bitcast %struct.kmp_depend_info* [[TMP31]] to i8* +// CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK3-NEXT: [[TOBOOL11:%.*]] = icmp ne i32 [[TMP38]], 0 +// CHECK3-NEXT: br i1 [[TOBOOL11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE13:%.*]] +// CHECK3: omp_if.then12: +// CHECK3-NEXT: [[TMP39:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]], i32 1, i8* [[TMP37]], i32 0, i8* null) +// CHECK3-NEXT: br label [[OMP_IF_END14:%.*]] +// CHECK3: omp_if.else13: +// CHECK3-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP37]], i32 0, i8* null) +// CHECK3-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]]) +// CHECK3-NEXT: [[TMP40:%.*]] = call i32 @.omp_task_entry..19(i32 [[TMP0]], %struct.kmp_task_t_with_privates.17* [[TMP29]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]]) +// CHECK3-NEXT: br label [[OMP_IF_END14]] +// CHECK3: omp_if.end14: +// CHECK3-NEXT: [[TMP41:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.19*)* @.omp_task_entry..21 to i32 (i32, i8*)*)) +// CHECK3-NEXT: [[TMP42:%.*]] = bitcast i8* [[TMP41]] to %struct.kmp_task_t_with_privates.19* +// CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], %struct.kmp_task_t_with_privates.19* [[TMP42]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR16]], i64 0, i64 0 +// CHECK3-NEXT: [[TMP45:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP44]], i64 0 +// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP47:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 +// CHECK3-NEXT: store i64 [[TMP47]], i64* [[TMP46]], align 8 +// CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 1 +// CHECK3-NEXT: store i64 4, i64* [[TMP48]], align 8 +// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 2 +// CHECK3-NEXT: store i8 3, i8* [[TMP49]], align 8 +// CHECK3-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR17]], align 8 +// CHECK3-NEXT: [[TMP50:%.*]] = bitcast %struct.kmp_depend_info* [[TMP44]] to i8* +// CHECK3-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK3-NEXT: [[TOBOOL18:%.*]] = icmp ne i32 [[TMP51]], 0 +// CHECK3-NEXT: br i1 [[TOBOOL18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE20:%.*]] +// CHECK3: omp_if.then19: +// CHECK3-NEXT: [[TMP52:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]], i32 1, i8* [[TMP50]], i32 0, i8* null) +// CHECK3-NEXT: br label [[OMP_IF_END21:%.*]] +// CHECK3: omp_if.else20: +// CHECK3-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP50]], i32 0, i8* null) +// CHECK3-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]]) +// CHECK3-NEXT: [[TMP53:%.*]] = call i32 @.omp_task_entry..21(i32 [[TMP0]], %struct.kmp_task_t_with_privates.19* [[TMP42]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]]) +// CHECK3-NEXT: br label [[OMP_IF_END21]] +// CHECK3: omp_if.end21: +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..11 +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.8*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.9*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates.9* [[TMP1]], %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.9*, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.8* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.9* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63 +// CHECK3-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.8*, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63 +// CHECK3-NEXT: call void @_Z3fn1v() #[[ATTR3]] +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..13 +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.10*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.11*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates.11* [[TMP1]], %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.11*, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.10* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.11* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META64:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META71:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !73 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !73 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !73 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !73 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !73 +// CHECK3-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.10*, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73 +// CHECK3-NEXT: call void @_Z3fn2v() #[[ATTR3]] +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..15 +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.12*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.13*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates.13* [[TMP1]], %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.13*, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.*]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.12* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.13* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META74:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META81:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !83 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !83 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !83 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !83 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !83 +// CHECK3-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.12*, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83 +// CHECK3-NEXT: call void @_Z3fn3v() #[[ATTR3]] +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..17 +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.14*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.15*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates.15* [[TMP1]], %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.15*, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.*]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.14* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.15* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META84:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META91:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !93 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !93 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !93 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !93 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !93 +// CHECK3-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.14*, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93 +// CHECK3-NEXT: call void @_Z3fn4v() #[[ATTR3]] +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..19 +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.16*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.17*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates.17* [[TMP1]], %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.17*, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.*]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.16* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.17* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META94:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META101:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !103 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !103 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !103 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !103 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !103 +// CHECK3-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.16*, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103 +// CHECK3-NEXT: call void @_Z3fn5v() #[[ATTR3]] +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..21 +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.18*, align 8 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.19*, align 8 +// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: store %struct.kmp_task_t_with_privates.19* [[TMP1]], %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.19*, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.18* +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.19* [[TMP3]] to i8* +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META104:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META111:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !113 +// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !113 +// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !113 +// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !113 +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !113 +// CHECK3-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.18*, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113 +// CHECK3-NEXT: call void @_Z3fn6v() #[[ATTR3]] // CHECK3-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_Z9gtid_testv() +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to %struct.kmp_task_t_with_privates* +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP2]]) +// CHECK4-NEXT: [[TMP5:%.*]] = call i32 @.omp_task_entry.(i32 [[TMP1]], %struct.kmp_task_t_with_privates* [[TMP3]]) #[[ATTR3:[0-9]+]] +// CHECK4-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP2]]) // CHECK4-NEXT: ret void // // +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11 +// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11 +// CHECK4-NEXT: call void @_Z9gtid_testv() #[[ATTR3]] +// CHECK4-NEXT: ret i32 0 +// +// // CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: () #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1 +// CHECK4-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 +// CHECK4-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 +// CHECK4-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 +// CHECK4-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK4-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_Z3fn7v() -// CHECK4-NEXT: call void @_Z3fn8v() -// CHECK4-NEXT: call void @_Z3fn9v() -// CHECK4-NEXT: call void @_Z4fn10v() -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) +// CHECK4-NEXT: [[TMP1:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..3 to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.kmp_task_t_with_privates.1* +// CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP2]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP1]]) +// CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..5 to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.3* +// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP6]], i32 0, i32 0 +// CHECK4-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK4-NEXT: [[TMP8:%.*]] = call i32 @.omp_task_entry..5(i32 [[TMP0]], %struct.kmp_task_t_with_privates.3* [[TMP6]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK4-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.5*)* @.omp_task_entry..7 to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.5* +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], %struct.kmp_task_t_with_privates.5* [[TMP10]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK4-NEXT: [[TMP14:%.*]] = call i32 @.omp_task_entry..7(i32 [[TMP0]], %struct.kmp_task_t_with_privates.5* [[TMP10]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: [[TMP15:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.7*)* @.omp_task_entry..9 to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %struct.kmp_task_t_with_privates.7* +// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], %struct.kmp_task_t_with_privates.7* [[TMP16]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], %struct.kmp_depend_info* [[TMP18]], i64 0 +// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 0 +// CHECK4-NEXT: store i64 ptrtoint (i32* @Arg to i64), i64* [[TMP20]], align 8 +// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 1 +// CHECK4-NEXT: store i64 4, i64* [[TMP21]], align 8 +// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 2 +// CHECK4-NEXT: store i8 3, i8* [[TMP22]], align 8 +// CHECK4-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR]], align 8 +// CHECK4-NEXT: [[TMP23:%.*]] = bitcast %struct.kmp_depend_info* [[TMP18]] to i8* +// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE6:%.*]] +// CHECK4: omp_if.then5: +// CHECK4-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]], i32 1, i8* [[TMP23]], i32 0, i8* null) +// CHECK4-NEXT: br label [[OMP_IF_END7:%.*]] +// CHECK4: omp_if.else6: +// CHECK4-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP23]], i32 0, i8* null) +// CHECK4-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) +// CHECK4-NEXT: [[TMP26:%.*]] = call i32 @.omp_task_entry..9(i32 [[TMP0]], %struct.kmp_task_t_with_privates.7* [[TMP16]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) +// CHECK4-NEXT: br label [[OMP_IF_END7]] +// CHECK4: omp_if.end7: +// CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP27]]) // CHECK4-NEXT: ret i32 [[CALL]] // // +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..3 +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.0*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.1*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates.1* [[TMP1]], %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.1*, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.0* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.1* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 +// CHECK4-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 +// CHECK4-NEXT: call void @_Z3fn7v() #[[ATTR3]] +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..5 +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.2*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates.3* [[TMP1]], %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.3*, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.2* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.3* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !33 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !33 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !33 +// CHECK4-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.2*, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33 +// CHECK4-NEXT: call void @_Z3fn8v() #[[ATTR3]] +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..7 +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.4*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.5*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates.5* [[TMP1]], %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.5*, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.4* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.5* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !43 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !43 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !43 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !43 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !43 +// CHECK4-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.4*, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43 +// CHECK4-NEXT: call void @_Z3fn9v() #[[ATTR3]] +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..9 +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.6*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.7*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates.7* [[TMP1]], %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.7*, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.6* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.7* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !53 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !53 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !53 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !53 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !53 +// CHECK4-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.6*, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53 +// CHECK4-NEXT: call void @_Z4fn10v() #[[ATTR3]] +// CHECK4-NEXT: ret i32 0 +// +// // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 +// CHECK4-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 +// CHECK4-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_12:%.*]], align 1 +// CHECK4-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_14:%.*]], align 1 +// CHECK4-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK4-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[AGG_CAPTURED8:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 1 +// CHECK4-NEXT: [[DOTDEP_ARR_ADDR9:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK4-NEXT: [[DEP_COUNTER_ADDR10:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[AGG_CAPTURED15:%.*]] = alloca [[STRUCT_ANON_18:%.*]], align 1 +// CHECK4-NEXT: [[DOTDEP_ARR_ADDR16:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK4-NEXT: [[DEP_COUNTER_ADDR17:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: call void @_Z3fn1v() -// CHECK4-NEXT: call void @_Z3fn2v() -// CHECK4-NEXT: call void @_Z3fn3v() -// CHECK4-NEXT: call void @_Z3fn4v() -// CHECK4-NEXT: call void @_Z3fn5v() -// CHECK4-NEXT: call void @_Z3fn6v() +// CHECK4-NEXT: [[TMP1:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.9*)* @.omp_task_entry..11 to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.kmp_task_t_with_privates.9* +// CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], %struct.kmp_task_t_with_privates.9* [[TMP2]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP1]]) +// CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.11*)* @.omp_task_entry..13 to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.11* +// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], %struct.kmp_task_t_with_privates.11* [[TMP6]], i32 0, i32 0 +// CHECK4-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK4-NEXT: [[TMP8:%.*]] = call i32 @.omp_task_entry..13(i32 [[TMP0]], %struct.kmp_task_t_with_privates.11* [[TMP6]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK4-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.13*)* @.omp_task_entry..15 to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.13* +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.*]], %struct.kmp_task_t_with_privates.13* [[TMP10]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 +// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK4-NEXT: [[TMP14:%.*]] = call i32 @.omp_task_entry..15(i32 [[TMP0]], %struct.kmp_task_t_with_privates.13* [[TMP10]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: [[TMP15:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.15*)* @.omp_task_entry..17 to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %struct.kmp_task_t_with_privates.15* +// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.*]], %struct.kmp_task_t_with_privates.15* [[TMP16]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], %struct.kmp_depend_info* [[TMP18]], i64 0 +// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP21:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 +// CHECK4-NEXT: store i64 [[TMP21]], i64* [[TMP20]], align 8 +// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 1 +// CHECK4-NEXT: store i64 4, i64* [[TMP22]], align 8 +// CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 2 +// CHECK4-NEXT: store i8 1, i8* [[TMP23]], align 8 +// CHECK4-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR]], align 8 +// CHECK4-NEXT: [[TMP24:%.*]] = bitcast %struct.kmp_depend_info* [[TMP18]] to i8* +// CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK4-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE6:%.*]] +// CHECK4: omp_if.then5: +// CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]], i32 1, i8* [[TMP24]], i32 0, i8* null) +// CHECK4-NEXT: br label [[OMP_IF_END7:%.*]] +// CHECK4: omp_if.else6: +// CHECK4-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP24]], i32 0, i8* null) +// CHECK4-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) +// CHECK4-NEXT: [[TMP27:%.*]] = call i32 @.omp_task_entry..17(i32 [[TMP0]], %struct.kmp_task_t_with_privates.15* [[TMP16]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) +// CHECK4-NEXT: br label [[OMP_IF_END7]] +// CHECK4: omp_if.end7: +// CHECK4-NEXT: [[TMP28:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.17*)* @.omp_task_entry..19 to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to %struct.kmp_task_t_with_privates.17* +// CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.*]], %struct.kmp_task_t_with_privates.17* [[TMP29]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR9]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP32:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP31]], i64 0 +// CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP34:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 +// CHECK4-NEXT: store i64 [[TMP34]], i64* [[TMP33]], align 8 +// CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 1 +// CHECK4-NEXT: store i64 4, i64* [[TMP35]], align 8 +// CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 2 +// CHECK4-NEXT: store i8 3, i8* [[TMP36]], align 8 +// CHECK4-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR10]], align 8 +// CHECK4-NEXT: [[TMP37:%.*]] = bitcast %struct.kmp_depend_info* [[TMP31]] to i8* +// CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK4-NEXT: [[TOBOOL11:%.*]] = icmp ne i32 [[TMP38]], 0 +// CHECK4-NEXT: br i1 [[TOBOOL11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE13:%.*]] +// CHECK4: omp_if.then12: +// CHECK4-NEXT: [[TMP39:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]], i32 1, i8* [[TMP37]], i32 0, i8* null) +// CHECK4-NEXT: br label [[OMP_IF_END14:%.*]] +// CHECK4: omp_if.else13: +// CHECK4-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP37]], i32 0, i8* null) +// CHECK4-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]]) +// CHECK4-NEXT: [[TMP40:%.*]] = call i32 @.omp_task_entry..19(i32 [[TMP0]], %struct.kmp_task_t_with_privates.17* [[TMP29]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]]) +// CHECK4-NEXT: br label [[OMP_IF_END14]] +// CHECK4: omp_if.end14: +// CHECK4-NEXT: [[TMP41:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.19*)* @.omp_task_entry..21 to i32 (i32, i8*)*)) +// CHECK4-NEXT: [[TMP42:%.*]] = bitcast i8* [[TMP41]] to %struct.kmp_task_t_with_privates.19* +// CHECK4-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], %struct.kmp_task_t_with_privates.19* [[TMP42]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR16]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP45:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP44]], i64 0 +// CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP47:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 +// CHECK4-NEXT: store i64 [[TMP47]], i64* [[TMP46]], align 8 +// CHECK4-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 1 +// CHECK4-NEXT: store i64 4, i64* [[TMP48]], align 8 +// CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 2 +// CHECK4-NEXT: store i8 3, i8* [[TMP49]], align 8 +// CHECK4-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR17]], align 8 +// CHECK4-NEXT: [[TMP50:%.*]] = bitcast %struct.kmp_depend_info* [[TMP44]] to i8* +// CHECK4-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK4-NEXT: [[TOBOOL18:%.*]] = icmp ne i32 [[TMP51]], 0 +// CHECK4-NEXT: br i1 [[TOBOOL18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE20:%.*]] +// CHECK4: omp_if.then19: +// CHECK4-NEXT: [[TMP52:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]], i32 1, i8* [[TMP50]], i32 0, i8* null) +// CHECK4-NEXT: br label [[OMP_IF_END21:%.*]] +// CHECK4: omp_if.else20: +// CHECK4-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP50]], i32 0, i8* null) +// CHECK4-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]]) +// CHECK4-NEXT: [[TMP53:%.*]] = call i32 @.omp_task_entry..21(i32 [[TMP0]], %struct.kmp_task_t_with_privates.19* [[TMP42]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]]) +// CHECK4-NEXT: br label [[OMP_IF_END21]] +// CHECK4: omp_if.end21: +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..11 +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.8*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.9*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates.9* [[TMP1]], %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.9*, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.8* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.9* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63 +// CHECK4-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.8*, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63 +// CHECK4-NEXT: call void @_Z3fn1v() #[[ATTR3]] +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..13 +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.10*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.11*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates.11* [[TMP1]], %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.11*, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.10* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.11* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META64:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META71:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !73 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !73 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !73 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !73 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !73 +// CHECK4-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.10*, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73 +// CHECK4-NEXT: call void @_Z3fn2v() #[[ATTR3]] // CHECK4-NEXT: ret i32 0 // // -// CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to %struct.kmp_task_t_with_privates* -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP2]]) -// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @.omp_task_entry.(i32 [[TMP1]], %struct.kmp_task_t_with_privates* [[TMP3]]) #[[ATTR3:[0-9]+]] -// CHECK5-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP2]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11 -// CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11 -// CHECK5-NEXT: call void @_Z9gtid_testv() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1 -// CHECK5-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 -// CHECK5-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 -// CHECK5-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 -// CHECK5-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 -// CHECK5-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..3 to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.kmp_task_t_with_privates.1* -// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP2]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP1]]) -// CHECK5-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..5 to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.3* -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP6]], i32 0, i32 0 -// CHECK5-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK5-NEXT: [[TMP8:%.*]] = call i32 @.omp_task_entry..5(i32 [[TMP0]], %struct.kmp_task_t_with_privates.3* [[TMP6]]) #[[ATTR3]] -// CHECK5-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK5-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.5*)* @.omp_task_entry..7 to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.5* -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], %struct.kmp_task_t_with_privates.5* [[TMP10]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK5: omp_if.then: -// CHECK5-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK5: omp_if.else: -// CHECK5-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK5-NEXT: [[TMP14:%.*]] = call i32 @.omp_task_entry..7(i32 [[TMP0]], %struct.kmp_task_t_with_privates.5* [[TMP10]]) #[[ATTR3]] -// CHECK5-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK5-NEXT: br label [[OMP_IF_END]] -// CHECK5: omp_if.end: -// CHECK5-NEXT: [[TMP15:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.7*)* @.omp_task_entry..9 to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %struct.kmp_task_t_with_privates.7* -// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], %struct.kmp_task_t_with_privates.7* [[TMP16]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], %struct.kmp_depend_info* [[TMP18]], i64 0 -// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 0 -// CHECK5-NEXT: store i64 ptrtoint (i32* @Arg to i64), i64* [[TMP20]], align 8 -// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 1 -// CHECK5-NEXT: store i64 4, i64* [[TMP21]], align 8 -// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 2 -// CHECK5-NEXT: store i8 3, i8* [[TMP22]], align 8 -// CHECK5-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR]], align 8 -// CHECK5-NEXT: [[TMP23:%.*]] = bitcast %struct.kmp_depend_info* [[TMP18]] to i8* -// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK5-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE6:%.*]] -// CHECK5: omp_if.then5: -// CHECK5-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]], i32 1, i8* [[TMP23]], i32 0, i8* null) -// CHECK5-NEXT: br label [[OMP_IF_END7:%.*]] -// CHECK5: omp_if.else6: -// CHECK5-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP23]], i32 0, i8* null) -// CHECK5-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) -// CHECK5-NEXT: [[TMP26:%.*]] = call i32 @.omp_task_entry..9(i32 [[TMP0]], %struct.kmp_task_t_with_privates.7* [[TMP16]]) #[[ATTR3]] -// CHECK5-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) -// CHECK5-NEXT: br label [[OMP_IF_END7]] -// CHECK5: omp_if.end7: -// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP27]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..3 -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.0*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.1*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates.1* [[TMP1]], %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.1*, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.0* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.1* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 -// CHECK5-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK5-NEXT: call void @_Z3fn7v() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..5 -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.2*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates.3* [[TMP1]], %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.3*, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.2* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.3* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !33 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.2*, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: call void @_Z3fn8v() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.4*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.5*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates.5* [[TMP1]], %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.5*, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.4* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.5* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !43 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !43 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !43 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !43 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !43 -// CHECK5-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.4*, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43 -// CHECK5-NEXT: call void @_Z3fn9v() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..9 -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.6*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.7*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates.7* [[TMP1]], %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.7*, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.6* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.7* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !53 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !53 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !53 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !53 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !53 -// CHECK5-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.6*, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53 -// CHECK5-NEXT: call void @_Z4fn10v() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 -// CHECK5-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 -// CHECK5-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_12:%.*]], align 1 -// CHECK5-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_14:%.*]], align 1 -// CHECK5-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 -// CHECK5-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[AGG_CAPTURED8:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 1 -// CHECK5-NEXT: [[DOTDEP_ARR_ADDR9:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 -// CHECK5-NEXT: [[DEP_COUNTER_ADDR10:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[AGG_CAPTURED15:%.*]] = alloca [[STRUCT_ANON_18:%.*]], align 1 -// CHECK5-NEXT: [[DOTDEP_ARR_ADDR16:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 -// CHECK5-NEXT: [[DEP_COUNTER_ADDR17:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK5-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.9*)* @.omp_task_entry..11 to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.kmp_task_t_with_privates.9* -// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], %struct.kmp_task_t_with_privates.9* [[TMP2]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP1]]) -// CHECK5-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.11*)* @.omp_task_entry..13 to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.11* -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], %struct.kmp_task_t_with_privates.11* [[TMP6]], i32 0, i32 0 -// CHECK5-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK5-NEXT: [[TMP8:%.*]] = call i32 @.omp_task_entry..13(i32 [[TMP0]], %struct.kmp_task_t_with_privates.11* [[TMP6]]) #[[ATTR3]] -// CHECK5-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK5-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.13*)* @.omp_task_entry..15 to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.13* -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.*]], %struct.kmp_task_t_with_privates.13* [[TMP10]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK5: omp_if.then: -// CHECK5-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK5: omp_if.else: -// CHECK5-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK5-NEXT: [[TMP14:%.*]] = call i32 @.omp_task_entry..15(i32 [[TMP0]], %struct.kmp_task_t_with_privates.13* [[TMP10]]) #[[ATTR3]] -// CHECK5-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK5-NEXT: br label [[OMP_IF_END]] -// CHECK5: omp_if.end: -// CHECK5-NEXT: [[TMP15:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.15*)* @.omp_task_entry..17 to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %struct.kmp_task_t_with_privates.15* -// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.*]], %struct.kmp_task_t_with_privates.15* [[TMP16]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], %struct.kmp_depend_info* [[TMP18]], i64 0 -// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP21:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 -// CHECK5-NEXT: store i64 [[TMP21]], i64* [[TMP20]], align 8 -// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 1 -// CHECK5-NEXT: store i64 4, i64* [[TMP22]], align 8 -// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 2 -// CHECK5-NEXT: store i8 1, i8* [[TMP23]], align 8 -// CHECK5-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR]], align 8 -// CHECK5-NEXT: [[TMP24:%.*]] = bitcast %struct.kmp_depend_info* [[TMP18]] to i8* -// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK5-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK5-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE6:%.*]] -// CHECK5: omp_if.then5: -// CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]], i32 1, i8* [[TMP24]], i32 0, i8* null) -// CHECK5-NEXT: br label [[OMP_IF_END7:%.*]] -// CHECK5: omp_if.else6: -// CHECK5-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP24]], i32 0, i8* null) -// CHECK5-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) -// CHECK5-NEXT: [[TMP27:%.*]] = call i32 @.omp_task_entry..17(i32 [[TMP0]], %struct.kmp_task_t_with_privates.15* [[TMP16]]) #[[ATTR3]] -// CHECK5-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) -// CHECK5-NEXT: br label [[OMP_IF_END7]] -// CHECK5: omp_if.end7: -// CHECK5-NEXT: [[TMP28:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.17*)* @.omp_task_entry..19 to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to %struct.kmp_task_t_with_privates.17* -// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.*]], %struct.kmp_task_t_with_privates.17* [[TMP29]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR9]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP31]], i64 0 -// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP34:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 -// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP33]], align 8 -// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 1 -// CHECK5-NEXT: store i64 4, i64* [[TMP35]], align 8 -// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 2 -// CHECK5-NEXT: store i8 3, i8* [[TMP36]], align 8 -// CHECK5-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR10]], align 8 -// CHECK5-NEXT: [[TMP37:%.*]] = bitcast %struct.kmp_depend_info* [[TMP31]] to i8* -// CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK5-NEXT: [[TOBOOL11:%.*]] = icmp ne i32 [[TMP38]], 0 -// CHECK5-NEXT: br i1 [[TOBOOL11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE13:%.*]] -// CHECK5: omp_if.then12: -// CHECK5-NEXT: [[TMP39:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]], i32 1, i8* [[TMP37]], i32 0, i8* null) -// CHECK5-NEXT: br label [[OMP_IF_END14:%.*]] -// CHECK5: omp_if.else13: -// CHECK5-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP37]], i32 0, i8* null) -// CHECK5-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]]) -// CHECK5-NEXT: [[TMP40:%.*]] = call i32 @.omp_task_entry..19(i32 [[TMP0]], %struct.kmp_task_t_with_privates.17* [[TMP29]]) #[[ATTR3]] -// CHECK5-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]]) -// CHECK5-NEXT: br label [[OMP_IF_END14]] -// CHECK5: omp_if.end14: -// CHECK5-NEXT: [[TMP41:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.19*)* @.omp_task_entry..21 to i32 (i32, i8*)*)) -// CHECK5-NEXT: [[TMP42:%.*]] = bitcast i8* [[TMP41]] to %struct.kmp_task_t_with_privates.19* -// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], %struct.kmp_task_t_with_privates.19* [[TMP42]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR16]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP45:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP44]], i64 0 -// CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP47:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 -// CHECK5-NEXT: store i64 [[TMP47]], i64* [[TMP46]], align 8 -// CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 1 -// CHECK5-NEXT: store i64 4, i64* [[TMP48]], align 8 -// CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 2 -// CHECK5-NEXT: store i8 3, i8* [[TMP49]], align 8 -// CHECK5-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR17]], align 8 -// CHECK5-NEXT: [[TMP50:%.*]] = bitcast %struct.kmp_depend_info* [[TMP44]] to i8* -// CHECK5-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK5-NEXT: [[TOBOOL18:%.*]] = icmp ne i32 [[TMP51]], 0 -// CHECK5-NEXT: br i1 [[TOBOOL18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE20:%.*]] -// CHECK5: omp_if.then19: -// CHECK5-NEXT: [[TMP52:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]], i32 1, i8* [[TMP50]], i32 0, i8* null) -// CHECK5-NEXT: br label [[OMP_IF_END21:%.*]] -// CHECK5: omp_if.else20: -// CHECK5-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP50]], i32 0, i8* null) -// CHECK5-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]]) -// CHECK5-NEXT: [[TMP53:%.*]] = call i32 @.omp_task_entry..21(i32 [[TMP0]], %struct.kmp_task_t_with_privates.19* [[TMP42]]) #[[ATTR3]] -// CHECK5-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]]) -// CHECK5-NEXT: br label [[OMP_IF_END21]] -// CHECK5: omp_if.end21: -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..11 -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.8*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.9*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates.9* [[TMP1]], %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.9*, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.8* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.9* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63 -// CHECK5-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.8*, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63 -// CHECK5-NEXT: call void @_Z3fn1v() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..13 -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.10*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.11*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates.11* [[TMP1]], %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.11*, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.10* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.11* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META64:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META71:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !73 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !73 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !73 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !73 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !73 -// CHECK5-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.10*, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73 -// CHECK5-NEXT: call void @_Z3fn2v() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..15 -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.12*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.13*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates.13* [[TMP1]], %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.13*, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.*]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.12* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.13* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META74:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META81:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !83 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !83 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !83 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !83 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !83 -// CHECK5-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.12*, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83 -// CHECK5-NEXT: call void @_Z3fn3v() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..17 -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.14*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.15*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates.15* [[TMP1]], %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.15*, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.*]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.14* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.15* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META84:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META91:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !93 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !93 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !93 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !93 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !93 -// CHECK5-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.14*, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93 -// CHECK5-NEXT: call void @_Z3fn4v() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..19 -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.16*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.17*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates.17* [[TMP1]], %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.17*, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.*]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.16* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.17* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META94:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META101:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !103 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !103 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !103 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !103 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !103 -// CHECK5-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.16*, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103 -// CHECK5-NEXT: call void @_Z3fn5v() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..21 -// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.18*, align 8 -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.19*, align 8 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: store %struct.kmp_task_t_with_privates.19* [[TMP1]], %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.19*, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.18* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.19* [[TMP3]] to i8* -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META104:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META111:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !113 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !113 -// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !113 -// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !113 -// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !113 -// CHECK5-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113 -// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.18*, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113 -// CHECK5-NEXT: call void @_Z3fn6v() #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to %struct.kmp_task_t_with_privates* -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP2]]) -// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @.omp_task_entry.(i32 [[TMP1]], %struct.kmp_task_t_with_privates* [[TMP3]]) #[[ATTR3:[0-9]+]] -// CHECK6-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP2]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11 -// CHECK6-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11 -// CHECK6-NEXT: call void @_Z9gtid_testv() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 -// CHECK6-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 -// CHECK6-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..3 to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.kmp_task_t_with_privates.1* -// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP2]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP1]]) -// CHECK6-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..5 to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.3* -// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP6]], i32 0, i32 0 -// CHECK6-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK6-NEXT: [[TMP8:%.*]] = call i32 @.omp_task_entry..5(i32 [[TMP0]], %struct.kmp_task_t_with_privates.3* [[TMP6]]) #[[ATTR3]] -// CHECK6-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK6-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.5*)* @.omp_task_entry..7 to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.5* -// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], %struct.kmp_task_t_with_privates.5* [[TMP10]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK6: omp_if.then: -// CHECK6-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK6: omp_if.else: -// CHECK6-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK6-NEXT: [[TMP14:%.*]] = call i32 @.omp_task_entry..7(i32 [[TMP0]], %struct.kmp_task_t_with_privates.5* [[TMP10]]) #[[ATTR3]] -// CHECK6-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK6-NEXT: br label [[OMP_IF_END]] -// CHECK6: omp_if.end: -// CHECK6-NEXT: [[TMP15:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.7*)* @.omp_task_entry..9 to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %struct.kmp_task_t_with_privates.7* -// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], %struct.kmp_task_t_with_privates.7* [[TMP16]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], %struct.kmp_depend_info* [[TMP18]], i64 0 -// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 0 -// CHECK6-NEXT: store i64 ptrtoint (i32* @Arg to i64), i64* [[TMP20]], align 8 -// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 1 -// CHECK6-NEXT: store i64 4, i64* [[TMP21]], align 8 -// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 2 -// CHECK6-NEXT: store i8 3, i8* [[TMP22]], align 8 -// CHECK6-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR]], align 8 -// CHECK6-NEXT: [[TMP23:%.*]] = bitcast %struct.kmp_depend_info* [[TMP18]] to i8* -// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE6:%.*]] -// CHECK6: omp_if.then5: -// CHECK6-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]], i32 1, i8* [[TMP23]], i32 0, i8* null) -// CHECK6-NEXT: br label [[OMP_IF_END7:%.*]] -// CHECK6: omp_if.else6: -// CHECK6-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP23]], i32 0, i8* null) -// CHECK6-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) -// CHECK6-NEXT: [[TMP26:%.*]] = call i32 @.omp_task_entry..9(i32 [[TMP0]], %struct.kmp_task_t_with_privates.7* [[TMP16]]) #[[ATTR3]] -// CHECK6-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) -// CHECK6-NEXT: br label [[OMP_IF_END7]] -// CHECK6: omp_if.end7: -// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP27]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..3 -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.0*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.1*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates.1* [[TMP1]], %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.1*, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.0* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.1* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 -// CHECK6-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 -// CHECK6-NEXT: call void @_Z3fn7v() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..5 -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.2*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates.3* [[TMP1]], %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.3*, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.2* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.3* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !33 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !33 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !33 -// CHECK6-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.2*, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33 -// CHECK6-NEXT: call void @_Z3fn8v() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.4*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.5*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates.5* [[TMP1]], %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.5*, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.4* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.5* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !43 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !43 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !43 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !43 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !43 -// CHECK6-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.4*, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43 -// CHECK6-NEXT: call void @_Z3fn9v() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..9 -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.6*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.7*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates.7* [[TMP1]], %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.7*, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.6* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.7* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !53 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !53 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !53 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !53 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !53 -// CHECK6-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.6*, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53 -// CHECK6-NEXT: call void @_Z4fn10v() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_12:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_14:%.*]], align 1 -// CHECK6-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 -// CHECK6-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[AGG_CAPTURED8:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 1 -// CHECK6-NEXT: [[DOTDEP_ARR_ADDR9:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 -// CHECK6-NEXT: [[DEP_COUNTER_ADDR10:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[AGG_CAPTURED15:%.*]] = alloca [[STRUCT_ANON_18:%.*]], align 1 -// CHECK6-NEXT: [[DOTDEP_ARR_ADDR16:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 -// CHECK6-NEXT: [[DEP_COUNTER_ADDR17:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK6-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.9*)* @.omp_task_entry..11 to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.kmp_task_t_with_privates.9* -// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], %struct.kmp_task_t_with_privates.9* [[TMP2]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP1]]) -// CHECK6-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.11*)* @.omp_task_entry..13 to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.11* -// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], %struct.kmp_task_t_with_privates.11* [[TMP6]], i32 0, i32 0 -// CHECK6-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK6-NEXT: [[TMP8:%.*]] = call i32 @.omp_task_entry..13(i32 [[TMP0]], %struct.kmp_task_t_with_privates.11* [[TMP6]]) #[[ATTR3]] -// CHECK6-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK6-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.13*)* @.omp_task_entry..15 to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.13* -// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.*]], %struct.kmp_task_t_with_privates.13* [[TMP10]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK6: omp_if.then: -// CHECK6-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK6: omp_if.else: -// CHECK6-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK6-NEXT: [[TMP14:%.*]] = call i32 @.omp_task_entry..15(i32 [[TMP0]], %struct.kmp_task_t_with_privates.13* [[TMP10]]) #[[ATTR3]] -// CHECK6-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP9]]) -// CHECK6-NEXT: br label [[OMP_IF_END]] -// CHECK6: omp_if.end: -// CHECK6-NEXT: [[TMP15:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.15*)* @.omp_task_entry..17 to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %struct.kmp_task_t_with_privates.15* -// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.*]], %struct.kmp_task_t_with_privates.15* [[TMP16]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], %struct.kmp_depend_info* [[TMP18]], i64 0 -// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP21:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 -// CHECK6-NEXT: store i64 [[TMP21]], i64* [[TMP20]], align 8 -// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 1 -// CHECK6-NEXT: store i64 4, i64* [[TMP22]], align 8 -// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP19]], i32 0, i32 2 -// CHECK6-NEXT: store i8 1, i8* [[TMP23]], align 8 -// CHECK6-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR]], align 8 -// CHECK6-NEXT: [[TMP24:%.*]] = bitcast %struct.kmp_depend_info* [[TMP18]] to i8* -// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK6-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE6:%.*]] -// CHECK6: omp_if.then5: -// CHECK6-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]], i32 1, i8* [[TMP24]], i32 0, i8* null) -// CHECK6-NEXT: br label [[OMP_IF_END7:%.*]] -// CHECK6: omp_if.else6: -// CHECK6-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP24]], i32 0, i8* null) -// CHECK6-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) -// CHECK6-NEXT: [[TMP27:%.*]] = call i32 @.omp_task_entry..17(i32 [[TMP0]], %struct.kmp_task_t_with_privates.15* [[TMP16]]) #[[ATTR3]] -// CHECK6-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP15]]) -// CHECK6-NEXT: br label [[OMP_IF_END7]] -// CHECK6: omp_if.end7: -// CHECK6-NEXT: [[TMP28:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.17*)* @.omp_task_entry..19 to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to %struct.kmp_task_t_with_privates.17* -// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.*]], %struct.kmp_task_t_with_privates.17* [[TMP29]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR9]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP31]], i64 0 -// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP34:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 -// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP33]], align 8 -// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 1 -// CHECK6-NEXT: store i64 4, i64* [[TMP35]], align 8 -// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP32]], i32 0, i32 2 -// CHECK6-NEXT: store i8 3, i8* [[TMP36]], align 8 -// CHECK6-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR10]], align 8 -// CHECK6-NEXT: [[TMP37:%.*]] = bitcast %struct.kmp_depend_info* [[TMP31]] to i8* -// CHECK6-NEXT: [[TMP38:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK6-NEXT: [[TOBOOL11:%.*]] = icmp ne i32 [[TMP38]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE13:%.*]] -// CHECK6: omp_if.then12: -// CHECK6-NEXT: [[TMP39:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]], i32 1, i8* [[TMP37]], i32 0, i8* null) -// CHECK6-NEXT: br label [[OMP_IF_END14:%.*]] -// CHECK6: omp_if.else13: -// CHECK6-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP37]], i32 0, i8* null) -// CHECK6-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]]) -// CHECK6-NEXT: [[TMP40:%.*]] = call i32 @.omp_task_entry..19(i32 [[TMP0]], %struct.kmp_task_t_with_privates.17* [[TMP29]]) #[[ATTR3]] -// CHECK6-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP28]]) -// CHECK6-NEXT: br label [[OMP_IF_END14]] -// CHECK6: omp_if.end14: -// CHECK6-NEXT: [[TMP41:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.19*)* @.omp_task_entry..21 to i32 (i32, i8*)*)) -// CHECK6-NEXT: [[TMP42:%.*]] = bitcast i8* [[TMP41]] to %struct.kmp_task_t_with_privates.19* -// CHECK6-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], %struct.kmp_task_t_with_privates.19* [[TMP42]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP44:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* [[DOTDEP_ARR_ADDR16]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP45:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP44]], i64 0 -// CHECK6-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP47:%.*]] = ptrtoint i32* [[ARG_ADDR]] to i64 -// CHECK6-NEXT: store i64 [[TMP47]], i64* [[TMP46]], align 8 -// CHECK6-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 1 -// CHECK6-NEXT: store i64 4, i64* [[TMP48]], align 8 -// CHECK6-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], %struct.kmp_depend_info* [[TMP45]], i32 0, i32 2 -// CHECK6-NEXT: store i8 3, i8* [[TMP49]], align 8 -// CHECK6-NEXT: store i64 1, i64* [[DEP_COUNTER_ADDR17]], align 8 -// CHECK6-NEXT: [[TMP50:%.*]] = bitcast %struct.kmp_depend_info* [[TMP44]] to i8* -// CHECK6-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK6-NEXT: [[TOBOOL18:%.*]] = icmp ne i32 [[TMP51]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE20:%.*]] -// CHECK6: omp_if.then19: -// CHECK6-NEXT: [[TMP52:%.*]] = call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]], i32 1, i8* [[TMP50]], i32 0, i8* null) -// CHECK6-NEXT: br label [[OMP_IF_END21:%.*]] -// CHECK6: omp_if.else20: -// CHECK6-NEXT: call void @__kmpc_omp_wait_deps(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i8* [[TMP50]], i32 0, i8* null) -// CHECK6-NEXT: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]]) -// CHECK6-NEXT: [[TMP53:%.*]] = call i32 @.omp_task_entry..21(i32 [[TMP0]], %struct.kmp_task_t_with_privates.19* [[TMP42]]) #[[ATTR3]] -// CHECK6-NEXT: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP41]]) -// CHECK6-NEXT: br label [[OMP_IF_END21]] -// CHECK6: omp_if.end21: -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..11 -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.8*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.9*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates.9* [[TMP1]], %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.9*, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.8* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.9* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63 -// CHECK6-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.8*, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63 -// CHECK6-NEXT: call void @_Z3fn1v() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..13 -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.10*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.11*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates.11* [[TMP1]], %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.11*, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.10* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.11* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META64:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META71:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !73 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !73 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !73 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !73 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !73 -// CHECK6-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.10*, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73 -// CHECK6-NEXT: call void @_Z3fn2v() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..15 -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.12*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.13*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates.13* [[TMP1]], %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.13*, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.*]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.12* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.13* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META74:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META81:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !83 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !83 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !83 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !83 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !83 -// CHECK6-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.12*, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83 -// CHECK6-NEXT: call void @_Z3fn3v() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..17 -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.14*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.15*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates.15* [[TMP1]], %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.15*, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.*]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.14* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.15* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META84:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META91:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !93 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !93 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !93 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !93 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !93 -// CHECK6-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.14*, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93 -// CHECK6-NEXT: call void @_Z3fn4v() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..19 -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.16*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.17*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates.17* [[TMP1]], %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.17*, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.*]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.16* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.17* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META94:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META101:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !103 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !103 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !103 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !103 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !103 -// CHECK6-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.16*, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103 -// CHECK6-NEXT: call void @_Z3fn5v() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..21 -// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR2]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.18*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.19*, align 8 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: store %struct.kmp_task_t_with_privates.19* [[TMP1]], %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.19*, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.18* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.19* [[TMP3]] to i8* -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META104:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META111:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !113 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !113 -// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !113 -// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !113 -// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !113 -// CHECK6-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113 -// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.18*, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113 -// CHECK6-NEXT: call void @_Z3fn6v() #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_Z9gtid_testv() -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_Z3fn7v() -// CHECK7-NEXT: call void @_Z3fn8v() -// CHECK7-NEXT: call void @_Z3fn9v() -// CHECK7-NEXT: call void @_Z4fn10v() -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: call void @_Z3fn1v() -// CHECK7-NEXT: call void @_Z3fn2v() -// CHECK7-NEXT: call void @_Z3fn3v() -// CHECK7-NEXT: call void @_Z3fn4v() -// CHECK7-NEXT: call void @_Z3fn5v() -// CHECK7-NEXT: call void @_Z3fn6v() -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_Z9gtid_testv() -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_Z3fn7v() -// CHECK8-NEXT: call void @_Z3fn8v() -// CHECK8-NEXT: call void @_Z3fn9v() -// CHECK8-NEXT: call void @_Z4fn10v() -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: call void @_Z3fn1v() -// CHECK8-NEXT: call void @_Z3fn2v() -// CHECK8-NEXT: call void @_Z3fn3v() -// CHECK8-NEXT: call void @_Z3fn4v() -// CHECK8-NEXT: call void @_Z3fn5v() -// CHECK8-NEXT: call void @_Z3fn6v() -// CHECK8-NEXT: ret i32 0 +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..15 +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.12*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.13*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates.13* [[TMP1]], %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.13*, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.*]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.12* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.13* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META74:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META81:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !83 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !83 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !83 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !83 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !83 +// CHECK4-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.12*, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83 +// CHECK4-NEXT: call void @_Z3fn3v() #[[ATTR3]] +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..17 +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.14*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.15*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates.15* [[TMP1]], %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.15*, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.*]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.14* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.15* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META84:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META91:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !93 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !93 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !93 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !93 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !93 +// CHECK4-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.14*, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93 +// CHECK4-NEXT: call void @_Z3fn4v() #[[ATTR3]] +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..19 +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.16*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.17*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates.17* [[TMP1]], %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.17*, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.*]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.16* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.17* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META94:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META101:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !103 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !103 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !103 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !103 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !103 +// CHECK4-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.16*, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103 +// CHECK4-NEXT: call void @_Z3fn5v() #[[ATTR3]] +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..21 +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.18*, align 8 +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.19*, align 8 +// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: store %struct.kmp_task_t_with_privates.19* [[TMP1]], %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.19*, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.18* +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates.19* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META104:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META111:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !113 +// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !113 +// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !113 +// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !113 +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !113 +// CHECK4-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.18*, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113 +// CHECK4-NEXT: call void @_Z3fn6v() #[[ATTR3]] +// CHECK4-NEXT: ret i32 0 // diff --git a/clang/test/OpenMP/task_in_reduction_codegen.cpp b/clang/test/OpenMP/task_in_reduction_codegen.cpp --- a/clang/test/OpenMP/task_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/task_in_reduction_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1394,203 +1394,3 @@ // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK3-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK3: arrayctor.loop: -// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK3: arrayctor.cont: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK3-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[CONV]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK3: arraydestroy.done3: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP9]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK4-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK4: arrayctor.loop: -// CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK4: arrayctor.cont: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK4-NEXT: [[TMP4:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[CONV]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK4: arraydestroy.body: -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK4: arraydestroy.done3: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP9]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: ret void -// diff --git a/clang/test/OpenMP/taskgroup_codegen.cpp b/clang/test/OpenMP/taskgroup_codegen.cpp --- a/clang/test/OpenMP/taskgroup_codegen.cpp +++ b/clang/test/OpenMP/taskgroup_codegen.cpp @@ -2,9 +2,9 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=DEBUG1 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" @@ -205,90 +205,90 @@ // CHECK2-NEXT: unreachable // // -// DEBUG1-LABEL: define {{[^@]+}}@_Z3foov -// DEBUG1-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG9:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG10:![0-9]+]] +// CHECK3-LABEL: define {{[^@]+}}@_Z3foov +// CHECK3-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG9:![0-9]+]] +// CHECK3-NEXT: ret void, !dbg [[DBG10:![0-9]+]] // // -// DEBUG1-LABEL: define {{[^@]+}}@main -// DEBUG1-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG11:![0-9]+]] { -// DEBUG1-NEXT: entry: -// DEBUG1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// DEBUG1-NEXT: [[A:%.*]] = alloca i8, align 1 -// DEBUG1-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// DEBUG1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG12:![0-9]+]] -// DEBUG1-NEXT: store i8 2, i8* [[A]], align 1, !dbg [[DBG13:![0-9]+]] -// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG14:![0-9]+]] -// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG15:![0-9]+]] -// DEBUG1-NEXT: invoke void @_Z3foov() -// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG16:![0-9]+]] -// DEBUG1: invoke.cont: -// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG16]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load i8, i8* [[A]], align 1, !dbg [[DBG17:![0-9]+]] -// DEBUG1-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32, !dbg [[DBG17]] -// DEBUG1-NEXT: ret i32 [[CONV]], !dbg [[DBG18:![0-9]+]] -// DEBUG1: lpad: -// DEBUG1-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// DEBUG1-NEXT: catch i8* null, !dbg [[DBG19:![0-9]+]] -// DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0, !dbg [[DBG19]] -// DEBUG1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG19]] -// DEBUG1-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1, !dbg [[DBG19]] -// DEBUG1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG19]] -// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG16]] -// DEBUG1-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG16]] -// DEBUG1: terminate.handler: -// DEBUG1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG16]] -// DEBUG1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8:[0-9]+]], !dbg [[DBG16]] -// DEBUG1-NEXT: unreachable, !dbg [[DBG16]] +// CHECK3-LABEL: define {{[^@]+}}@main +// CHECK3-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG11:![0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG12:![0-9]+]] +// CHECK3-NEXT: store i8 2, i8* [[A]], align 1, !dbg [[DBG13:![0-9]+]] +// CHECK3-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG14:![0-9]+]] +// CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG15:![0-9]+]] +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG16:![0-9]+]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG16]] +// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[A]], align 1, !dbg [[DBG17:![0-9]+]] +// CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32, !dbg [[DBG17]] +// CHECK3-NEXT: ret i32 [[CONV]], !dbg [[DBG18:![0-9]+]] +// CHECK3: lpad: +// CHECK3-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null, !dbg [[DBG19:![0-9]+]] +// CHECK3-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0, !dbg [[DBG19]] +// CHECK3-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG19]] +// CHECK3-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1, !dbg [[DBG19]] +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG19]] +// CHECK3-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG16]] +// CHECK3-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG16]] +// CHECK3: terminate.handler: +// CHECK3-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG16]] +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8:[0-9]+]], !dbg [[DBG16]] +// CHECK3-NEXT: unreachable, !dbg [[DBG16]] // // -// DEBUG1-LABEL: define {{[^@]+}}@__clang_call_terminate -// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] { -// DEBUG1-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3:[0-9]+]] -// DEBUG1-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// DEBUG1-NEXT: unreachable +// CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3:[0-9]+]] +// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] +// CHECK3-NEXT: unreachable // // -// DEBUG1-LABEL: define {{[^@]+}}@_Z18parallel_taskgroupv -// DEBUG1-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG20:![0-9]+]] { -// DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)), !dbg [[DBG21:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG22:![0-9]+]] +// CHECK3-LABEL: define {{[^@]+}}@_Z18parallel_taskgroupv +// CHECK3-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG20:![0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)), !dbg [[DBG21:![0-9]+]] +// CHECK3-NEXT: ret void, !dbg [[DBG22:![0-9]+]] // // -// DEBUG1-LABEL: define {{[^@]+}}@.omp_outlined. -// DEBUG1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR7:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG23:![0-9]+]] { -// DEBUG1-NEXT: entry: -// DEBUG1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// DEBUG1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// DEBUG1-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// DEBUG1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// DEBUG1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG24:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4, !dbg [[DBG24]] -// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG24]] -// DEBUG1-NEXT: invoke void @_Z3foov() -// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG25:![0-9]+]] -// DEBUG1: invoke.cont: -// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG25]] -// DEBUG1-NEXT: ret void, !dbg [[DBG26:![0-9]+]] -// DEBUG1: lpad: -// DEBUG1-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// DEBUG1-NEXT: catch i8* null, !dbg [[DBG27:![0-9]+]] -// DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0, !dbg [[DBG27]] -// DEBUG1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG27]] -// DEBUG1-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1, !dbg [[DBG27]] -// DEBUG1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG27]] -// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG25]] -// DEBUG1-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG25]] -// DEBUG1: terminate.handler: -// DEBUG1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG25]] -// DEBUG1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8]], !dbg [[DBG25]] -// DEBUG1-NEXT: unreachable, !dbg [[DBG25]] +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR7:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG23:![0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG24:![0-9]+]] +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4, !dbg [[DBG24]] +// CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG24]] +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG25:![0-9]+]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG25]] +// CHECK3-NEXT: ret void, !dbg [[DBG26:![0-9]+]] +// CHECK3: lpad: +// CHECK3-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null, !dbg [[DBG27:![0-9]+]] +// CHECK3-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0, !dbg [[DBG27]] +// CHECK3-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG27]] +// CHECK3-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1, !dbg [[DBG27]] +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG27]] +// CHECK3-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG25]] +// CHECK3-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG25]] +// CHECK3: terminate.handler: +// CHECK3-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG25]] +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8]], !dbg [[DBG25]] +// CHECK3-NEXT: unreachable, !dbg [[DBG25]] // diff --git a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp --- a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1379,227 +1379,3 @@ // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK3-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK3: arrayctor.loop: -// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK3: arrayctor.cont: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK3-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 5 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CONV]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK3: arraydestroy.done3: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP10]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK4-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK4: arrayctor.loop: -// CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK4: arrayctor.cont: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 5 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CONV]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK4: arraydestroy.body: -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK4: arraydestroy.done3: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP10]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: ret void -// diff --git a/clang/test/OpenMP/teams_codegen.cpp b/clang/test/OpenMP/teams_codegen.cpp --- a/clang/test/OpenMP/teams_codegen.cpp +++ b/clang/test/OpenMP/teams_codegen.cpp @@ -10,12 +10,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 int Gbla; @@ -80,19 +80,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -132,19 +132,19 @@ #endif // CK2 // Test host codegen. -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK3 @@ -184,22 +184,22 @@ // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 // RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 // RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 @@ -226,22 +226,22 @@ // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK33 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK34 +// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 // RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK35 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK36 +// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 // RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK37 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK38 +// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK39 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK40 +// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifdef CK5 @@ -275,19 +275,19 @@ #endif // CK5 // Test host codegen. -// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-version=50 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK41 +// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-version=50 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK6 -fopenmp-version=50 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK42 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK43 +// RUN: %clang_cc1 -DCK6 -fopenmp-version=50 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 +// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK44 +// RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp-version=50 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK45 +// RUN: %clang_cc1 -DCK6 -verify -fopenmp-version=50 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK46 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 +// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK48 +// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK6 void foo() { @@ -2222,294 +2222,873 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK5-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@_Z18teams_template_argv +// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[LA:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[LC:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK5-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 +// CHECK5-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[COMP_CASTED2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 8 // CHECK5-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK5-NEXT: store i32 23, i32* [[LA]], align 4 -// CHECK5-NEXT: store float 2.500000e+01, float* [[LC]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 8 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: ret i32 [[TMP10]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK6-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** +// CHECK5-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** +// CHECK5-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** +// CHECK5-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** +// CHECK5-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 +// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = fptosi float [[TMP20]] to i64 +// CHECK5-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV1]] to i32 +// CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) +// CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK5-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_CASTED2]] to i32* +// CHECK5-NEXT: store i32 [[TMP24]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED2]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** +// CHECK5-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** +// CHECK5-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** +// CHECK5-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** +// CHECK5-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP35]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK5-NEXT: store i64 [[TMP25]], i64* [[TMP37]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK5-NEXT: store i64 [[TMP25]], i64* [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP40]], align 8 +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP43:%.*]] = load float, float* [[B7]], align 8 +// CHECK5-NEXT: [[CONV8:%.*]] = fptosi float [[TMP43]] to i64 +// CHECK5-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV8]] to i32 +// CHECK5-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 8 +// CHECK5-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 +// CHECK5-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) +// CHECK5-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 +// CHECK5-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] +// CHECK5: omp_offload.failed9: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i64 [[TMP25]]) #[[ATTR2]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT10]] +// CHECK5: omp_offload.cont10: +// CHECK5-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK5-NEXT: ret i32 [[TMP49]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 8 +// CHECK5-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = fptosi float [[TMP4]] to i64 +// CHECK5-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV1]] to i32 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 +// CHECK5-SAME: (%struct.SS.0* nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 +// CHECK5-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 +// CHECK5-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK5-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 8 +// CHECK5-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* +// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = fptosi float [[TMP3]] to i64 +// CHECK5-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV1]] to i32 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z18teams_template_argv +// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[LA:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[LC:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK6-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 +// CHECK6-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[COMP_CASTED2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 8 // CHECK6-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK6-NEXT: store i32 23, i32* [[LA]], align 4 -// CHECK6-NEXT: store float 2.500000e+01, float* [[LC]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 8 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: ret i32 [[TMP10]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK7-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** +// CHECK6-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** +// CHECK6-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** +// CHECK6-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** +// CHECK6-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 +// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = fptosi float [[TMP20]] to i64 +// CHECK6-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV1]] to i32 +// CHECK6-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) +// CHECK6-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK6-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_CASTED2]] to i32* +// CHECK6-NEXT: store i32 [[TMP24]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED2]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** +// CHECK6-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** +// CHECK6-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** +// CHECK6-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** +// CHECK6-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP35]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK6-NEXT: store i64 [[TMP25]], i64* [[TMP37]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK6-NEXT: store i64 [[TMP25]], i64* [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP40]], align 8 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP43:%.*]] = load float, float* [[B7]], align 8 +// CHECK6-NEXT: [[CONV8:%.*]] = fptosi float [[TMP43]] to i64 +// CHECK6-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV8]] to i32 +// CHECK6-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 8 +// CHECK6-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 +// CHECK6-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) +// CHECK6-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 +// CHECK6-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] +// CHECK6: omp_offload.failed9: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i64 [[TMP25]]) #[[ATTR2]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT10]] +// CHECK6: omp_offload.cont10: +// CHECK6-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK6-NEXT: ret i32 [[TMP49]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 8 +// CHECK6-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = fptosi float [[TMP4]] to i64 +// CHECK6-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV1]] to i32 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 +// CHECK6-SAME: (%struct.SS.0* nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 +// CHECK6-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 +// CHECK6-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK6-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 8 +// CHECK6-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* +// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = fptosi float [[TMP3]] to i64 +// CHECK6-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV1]] to i32 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z18teams_template_argv +// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[LA:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[LC:%.*]] = alloca float, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK7-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 +// CHECK7-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [3 x i8*], align 4 // CHECK7-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK7-NEXT: store i32 23, i32* [[LA]], align 4 -// CHECK7-NEXT: store float 2.500000e+01, float* [[LC]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 4 -// CHECK7-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK7-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: ret i32 [[TMP10]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK8-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** +// CHECK7-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** +// CHECK7-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP6]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** +// CHECK7-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** +// CHECK7-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 +// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = fptosi float [[TMP20]] to i64 +// CHECK7-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV]] to i32 +// CHECK7-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) +// CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK7-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK7-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED1]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** +// CHECK7-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** +// CHECK7-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** +// CHECK7-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** +// CHECK7-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP35]], align 4 +// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* +// CHECK7-NEXT: store i32 [[TMP25]], i32* [[TMP37]], align 4 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* +// CHECK7-NEXT: store i32 [[TMP25]], i32* [[TMP39]], align 4 +// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK7-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP43:%.*]] = load float, float* [[B5]], align 4 +// CHECK7-NEXT: [[CONV6:%.*]] = fptosi float [[TMP43]] to i64 +// CHECK7-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV6]] to i32 +// CHECK7-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 4 +// CHECK7-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 +// CHECK7-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) +// CHECK7-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 +// CHECK7-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK7: omp_offload.failed7: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i32 [[TMP25]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK7: omp_offload.cont8: +// CHECK7-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK7-NEXT: ret i32 [[TMP49]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 4 +// CHECK7-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i64 +// CHECK7-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV]] to i32 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 +// CHECK7-SAME: (%struct.SS.0* nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 +// CHECK7-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 +// CHECK7-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK7-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 4 +// CHECK7-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 4 +// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = fptosi float [[TMP3]] to i64 +// CHECK7-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV]] to i32 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z18teams_template_argv +// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[LA:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[LC:%.*]] = alloca float, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK8-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 +// CHECK8-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [3 x i8*], align 4 // CHECK8-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK8-NEXT: store i32 23, i32* [[LA]], align 4 -// CHECK8-NEXT: store float 2.500000e+01, float* [[LC]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 4 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK8-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: ret i32 [[TMP10]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z18teams_template_argv +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** +// CHECK8-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** +// CHECK8-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP6]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** +// CHECK8-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** +// CHECK8-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 +// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = fptosi float [[TMP20]] to i64 +// CHECK8-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV]] to i32 +// CHECK8-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) +// CHECK8-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK8-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK8-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED1]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** +// CHECK8-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** +// CHECK8-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** +// CHECK8-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** +// CHECK8-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP35]], align 4 +// CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* +// CHECK8-NEXT: store i32 [[TMP25]], i32* [[TMP37]], align 4 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* +// CHECK8-NEXT: store i32 [[TMP25]], i32* [[TMP39]], align 4 +// CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK8-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP43:%.*]] = load float, float* [[B5]], align 4 +// CHECK8-NEXT: [[CONV6:%.*]] = fptosi float [[TMP43]] to i64 +// CHECK8-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV6]] to i32 +// CHECK8-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 4 +// CHECK8-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 +// CHECK8-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) +// CHECK8-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 +// CHECK8-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK8: omp_offload.failed7: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i32 [[TMP25]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK8: omp_offload.cont8: +// CHECK8-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK8-NEXT: ret i32 [[TMP49]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 4 +// CHECK8-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i64 +// CHECK8-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV]] to i32 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 +// CHECK8-SAME: (%struct.SS.0* nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 +// CHECK8-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 +// CHECK8-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK8-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 4 +// CHECK8-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 4 +// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = fptosi float [[TMP3]] to i64 +// CHECK8-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV]] to i32 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: +// CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) +// CHECK9-NEXT: ret i32 [[CALL]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK9-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 // CHECK9-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[COMP_CASTED2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[COMP_CASTED3:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store i32 1, i32* [[COMP]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** -// CHECK9-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** -// CHECK9-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** +// CHECK9-NEXT: store i32* [[A]], i32** [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 // CHECK9-NEXT: store i8* null, i8** [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** -// CHECK9-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** -// CHECK9-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 // CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = fptosi float [[TMP20]] to i64 -// CHECK9-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV1]] to i32 -// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) -// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK9-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) +// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK9-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_CASTED2]] to i32* -// CHECK9-NEXT: store i32 [[TMP24]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED2]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** -// CHECK9-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** -// CHECK9-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** -// CHECK9-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** -// CHECK9-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK9-NEXT: store i64 [[TMP25]], i64* [[TMP37]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK9-NEXT: store i64 [[TMP25]], i64* [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP40]], align 8 -// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP43:%.*]] = load float, float* [[B7]], align 8 -// CHECK9-NEXT: [[CONV8:%.*]] = fptosi float [[TMP43]] to i64 -// CHECK9-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV8]] to i32 -// CHECK9-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 8 -// CHECK9-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 -// CHECK9-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) -// CHECK9-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 -// CHECK9-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] -// CHECK9: omp_offload.failed9: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i64 [[TMP25]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT10]] -// CHECK9: omp_offload.cont10: -// CHECK9-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK9-NEXT: ret i32 [[TMP49]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 -// CHECK9-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[COMP_CASTED3]] to i32* +// CHECK9-NEXT: store i32 [[TMP17]], i32* [[CONV4]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[COMP_CASTED3]], align 8 +// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** +// CHECK9-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** +// CHECK9-NEXT: store float* [[B]], float** [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK9-NEXT: store i64 [[TMP18]], i64* [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK9-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK9-NEXT: [[B8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP31:%.*]] = load float, float* [[B8]], align 4 +// CHECK9-NEXT: [[CONV9:%.*]] = fptosi float [[TMP31]] to i32 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 123 +// CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) +// CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] +// CHECK9: omp_offload.failed10: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i64 [[TMP18]]) #[[ATTR2]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT11]] +// CHECK9: omp_offload.cont11: +// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK9-NEXT: ret i32 [[TMP34]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 +// CHECK9-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 8 -// CHECK9-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 8 +// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = fptosi float [[TMP4]] to i64 -// CHECK9-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV1]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) // CHECK9-NEXT: ret void // @@ -2530,27 +3109,21 @@ // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 -// CHECK9-SAME: (%struct.SS.0* nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 +// CHECK9-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 -// CHECK9-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK9-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 8 -// CHECK9-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 8 +// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = fptosi float [[TMP3]] to i64 -// CHECK9-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV1]] to i32 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) +// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 +// CHECK9-NEXT: [[CONV1:%.*]] = fptosi float [[TMP2]] to i32 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 123 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) // CHECK9-NEXT: ret void // @@ -2578,130 +3151,113 @@ // CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z18teams_template_argv +// CHECK10-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: +// CHECK10-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) +// CHECK10-NEXT: ret i32 [[CALL]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK10-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 // CHECK10-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[COMP_CASTED2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[COMP_CASTED3:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store i32 1, i32* [[COMP]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** -// CHECK10-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** -// CHECK10-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** +// CHECK10-NEXT: store i32* [[A]], i32** [[TMP5]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 // CHECK10-NEXT: store i8* null, i8** [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** -// CHECK10-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** -// CHECK10-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 // CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 -// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = fptosi float [[TMP20]] to i64 -// CHECK10-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV1]] to i32 -// CHECK10-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) -// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK10-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) +// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK10-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_CASTED2]] to i32* -// CHECK10-NEXT: store i32 [[TMP24]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED2]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** -// CHECK10-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** -// CHECK10-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP30]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** -// CHECK10-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 8 -// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** -// CHECK10-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK10-NEXT: store i64 [[TMP25]], i64* [[TMP37]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK10-NEXT: store i64 [[TMP25]], i64* [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP40]], align 8 -// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP43:%.*]] = load float, float* [[B7]], align 8 -// CHECK10-NEXT: [[CONV8:%.*]] = fptosi float [[TMP43]] to i64 -// CHECK10-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV8]] to i32 -// CHECK10-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 8 -// CHECK10-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 -// CHECK10-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) -// CHECK10-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 -// CHECK10-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] -// CHECK10: omp_offload.failed9: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i64 [[TMP25]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT10]] -// CHECK10: omp_offload.cont10: -// CHECK10-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK10-NEXT: ret i32 [[TMP49]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 -// CHECK10-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[COMP_CASTED3]] to i32* +// CHECK10-NEXT: store i32 [[TMP17]], i32* [[CONV4]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[COMP_CASTED3]], align 8 +// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** +// CHECK10-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** +// CHECK10-NEXT: store float* [[B]], float** [[TMP22]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK10-NEXT: store i64 [[TMP18]], i64* [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK10-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK10-NEXT: [[B8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP31:%.*]] = load float, float* [[B8]], align 4 +// CHECK10-NEXT: [[CONV9:%.*]] = fptosi float [[TMP31]] to i32 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 123 +// CHECK10-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) +// CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK10-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] +// CHECK10: omp_offload.failed10: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i64 [[TMP18]]) #[[ATTR2]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT11]] +// CHECK10: omp_offload.cont11: +// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK10-NEXT: ret i32 [[TMP34]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 +// CHECK10-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 8 -// CHECK10-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 8 +// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = fptosi float [[TMP4]] to i64 -// CHECK10-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV1]] to i32 -// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) // CHECK10-NEXT: ret void // @@ -2722,27 +3278,21 @@ // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 -// CHECK10-SAME: (%struct.SS.0* nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 +// CHECK10-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 -// CHECK10-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK10-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 8 -// CHECK10-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 8 +// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* -// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = fptosi float [[TMP3]] to i64 -// CHECK10-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV1]] to i32 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) +// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = fptosi float [[TMP2]] to i32 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 123 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) // CHECK10-NEXT: ret void // @@ -2770,127 +3320,110 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z18teams_template_argv +// CHECK11-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: +// CHECK11-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) +// CHECK11-NEXT: ret i32 [[CALL]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK11-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 // CHECK11-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[COMP_CASTED3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK11-NEXT: store i32 1, i32* [[COMP]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** -// CHECK11-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** -// CHECK11-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** +// CHECK11-NEXT: store i32* [[A]], i32** [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 // CHECK11-NEXT: store i8* null, i8** [[TMP6]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** -// CHECK11-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** -// CHECK11-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 // CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 -// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP20]] to i64 -// CHECK11-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV]] to i32 -// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) -// CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK11-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) +// CHECK11-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK11-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK11-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED1]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** -// CHECK11-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** -// CHECK11-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** -// CHECK11-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** -// CHECK11-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP35]], align 4 -// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* -// CHECK11-NEXT: store i32 [[TMP25]], i32* [[TMP37]], align 4 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* -// CHECK11-NEXT: store i32 [[TMP25]], i32* [[TMP39]], align 4 -// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK11-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP43:%.*]] = load float, float* [[B5]], align 4 -// CHECK11-NEXT: [[CONV6:%.*]] = fptosi float [[TMP43]] to i64 -// CHECK11-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV6]] to i32 -// CHECK11-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 4 -// CHECK11-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 -// CHECK11-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) -// CHECK11-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 -// CHECK11-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK11: omp_offload.failed7: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i32 [[TMP25]]) #[[ATTR2]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK11: omp_offload.cont8: -// CHECK11-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK11-NEXT: ret i32 [[TMP49]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 -// CHECK11-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK11-NEXT: store i32 [[TMP17]], i32* [[COMP_CASTED3]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[COMP_CASTED3]], align 4 +// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** +// CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** +// CHECK11-NEXT: store float* [[B]], float** [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK11-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP31:%.*]] = load float, float* [[B7]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP31]] to i32 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 +// CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) +// CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] +// CHECK11: omp_offload.failed8: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i32 [[TMP18]]) #[[ATTR2]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT9]] +// CHECK11: omp_offload.cont9: +// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK11-NEXT: ret i32 [[TMP34]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 +// CHECK11-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK11-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK11-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 4 -// CHECK11-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 4 +// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 // CHECK11-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i64 -// CHECK11-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV]] to i32 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) // CHECK11-NEXT: ret void // @@ -2911,26 +3444,20 @@ // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 -// CHECK11-SAME: (%struct.SS.0* nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 +// CHECK11-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 -// CHECK11-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK11-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 4 -// CHECK11-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 4 +// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 // CHECK11-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 4 -// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP3]] to i64 -// CHECK11-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV]] to i32 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) +// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP2]] to i32 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) // CHECK11-NEXT: ret void // @@ -2958,127 +3485,110 @@ // CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_Z18teams_template_argv +// CHECK12-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: +// CHECK12-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) +// CHECK12-NEXT: ret i32 [[CALL]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK12-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 // CHECK12-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[COMP_CASTED3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK12-NEXT: store i32 1, i32* [[COMP]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** -// CHECK12-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** -// CHECK12-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** +// CHECK12-NEXT: store i32* [[A]], i32** [[TMP5]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 // CHECK12-NEXT: store i8* null, i8** [[TMP6]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** -// CHECK12-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** -// CHECK12-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 // CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 -// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP20]] to i64 -// CHECK12-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV]] to i32 -// CHECK12-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) -// CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK12-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) +// CHECK12-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK12-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK12-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED1]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** -// CHECK12-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** -// CHECK12-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** -// CHECK12-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** -// CHECK12-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP35]], align 4 -// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* -// CHECK12-NEXT: store i32 [[TMP25]], i32* [[TMP37]], align 4 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* -// CHECK12-NEXT: store i32 [[TMP25]], i32* [[TMP39]], align 4 -// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK12-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP43:%.*]] = load float, float* [[B5]], align 4 -// CHECK12-NEXT: [[CONV6:%.*]] = fptosi float [[TMP43]] to i64 -// CHECK12-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV6]] to i32 -// CHECK12-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 4 -// CHECK12-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 -// CHECK12-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) -// CHECK12-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 -// CHECK12-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK12: omp_offload.failed7: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i32 [[TMP25]]) #[[ATTR2]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK12: omp_offload.cont8: -// CHECK12-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK12-NEXT: ret i32 [[TMP49]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 -// CHECK12-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK12-NEXT: store i32 [[TMP17]], i32* [[COMP_CASTED3]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[COMP_CASTED3]], align 4 +// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** +// CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** +// CHECK12-NEXT: store float* [[B]], float** [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK12-NEXT: store i32 [[TMP18]], i32* [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK12-NEXT: store i32 [[TMP18]], i32* [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK12-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP31:%.*]] = load float, float* [[B7]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP31]] to i32 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 +// CHECK12-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) +// CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK12-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] +// CHECK12: omp_offload.failed8: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i32 [[TMP18]]) #[[ATTR2]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT9]] +// CHECK12: omp_offload.cont9: +// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 +// CHECK12-NEXT: ret i32 [[TMP34]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 +// CHECK12-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK12-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK12-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 4 -// CHECK12-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 4 +// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 // CHECK12-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i64 -// CHECK12-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV]] to i32 -// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) // CHECK12-NEXT: ret void // @@ -3099,26 +3609,20 @@ // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 -// CHECK12-SAME: (%struct.SS.0* nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 +// CHECK12-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 -// CHECK12-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK12-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 4 -// CHECK12-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 4 +// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 // CHECK12-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 4 -// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP3]] to i64 -// CHECK12-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV]] to i32 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP2]] to i32 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) // CHECK12-NEXT: ret void // @@ -3146,1602 +3650,514 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z18teams_template_argv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 +// CHECK13-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK13-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 -// CHECK13-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK13-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK13-NEXT: ret i32 [[TMP2]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z18teams_template_argv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK13-NEXT: store i32 0, i32* [[TMP0]], align 4 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 +// CHECK13-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 +// CHECK13-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 +// CHECK13-NEXT: store i8** null, i8*** [[TMP0]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 +// CHECK14-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[TMP0]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 +// CHECK14-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 +// CHECK14-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK14-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 -// CHECK14-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK14-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK14-NEXT: ret i32 [[TMP2]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z18teams_template_argv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 +// CHECK14-NEXT: store i8** null, i8*** [[TMP0]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK15-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK15-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK15-NEXT: ret i32 [[TMP2]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z18teams_template_argv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[TMP0]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 +// CHECK15-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 +// CHECK15-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: store i8** null, i8*** [[TMP0]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK16-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK16-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK16-NEXT: ret i32 [[TMP2]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) -// CHECK17-NEXT: ret i32 [[CALL]] +// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) +// CHECK16-NEXT: ret void // // -// CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK17-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK17-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[COMP_CASTED3:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** -// CHECK17-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** -// CHECK17-NEXT: store i32* [[A]], i32** [[TMP5]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) -// CHECK17-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK17-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[COMP_CASTED3]] to i32* -// CHECK17-NEXT: store i32 [[TMP17]], i32* [[CONV4]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = load i64, i64* [[COMP_CASTED3]], align 8 -// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** -// CHECK17-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** -// CHECK17-NEXT: store float* [[B]], float** [[TMP22]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK17-NEXT: [[B8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP31:%.*]] = load float, float* [[B8]], align 4 -// CHECK17-NEXT: [[CONV9:%.*]] = fptosi float [[TMP31]] to i32 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 123 -// CHECK17-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) -// CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK17-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] -// CHECK17: omp_offload.failed10: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i64 [[TMP18]]) #[[ATTR2]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT11]] -// CHECK17: omp_offload.cont11: -// CHECK17-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK17-NEXT: ret i32 [[TMP34]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 -// CHECK17-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[TMP0]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 +// CHECK16-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 +// CHECK16-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: store i8** null, i8*** [[TMP0]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]]) // CHECK17-NEXT: ret void // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK17-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK17-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK17-NEXT: store i32 0, i32* [[TMP0]], align 4 // CHECK17-NEXT: ret void // // -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 -// CHECK17-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* -// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 -// CHECK17-NEXT: [[CONV1:%.*]] = fptosi float [[TMP2]] to i32 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 123 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) // CHECK17-NEXT: ret void // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK17-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK17-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 +// CHECK17-NEXT: store i8** null, i8*** [[TMP0]], align 8 // CHECK17-NEXT: ret void // // -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: -// CHECK18-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) -// CHECK18-NEXT: ret i32 [[CALL]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK18-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK18-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[COMP_CASTED3:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** -// CHECK18-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** -// CHECK18-NEXT: store i32* [[A]], i32** [[TMP5]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) -// CHECK18-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK18-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[COMP_CASTED3]] to i32* -// CHECK18-NEXT: store i32 [[TMP17]], i32* [[CONV4]], align 4 -// CHECK18-NEXT: [[TMP18:%.*]] = load i64, i64* [[COMP_CASTED3]], align 8 -// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** -// CHECK18-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** -// CHECK18-NEXT: store float* [[B]], float** [[TMP22]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK18-NEXT: [[B8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP31:%.*]] = load float, float* [[B8]], align 4 -// CHECK18-NEXT: [[CONV9:%.*]] = fptosi float [[TMP31]] to i32 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 123 -// CHECK18-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) -// CHECK18-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK18-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] -// CHECK18: omp_offload.failed10: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i64 [[TMP18]]) #[[ATTR2]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT11]] -// CHECK18: omp_offload.cont11: -// CHECK18-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK18-NEXT: ret i32 [[TMP34]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 -// CHECK18-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK18-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[TMP0]], align 4 // CHECK18-NEXT: ret void // // -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 -// CHECK18-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* -// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 -// CHECK18-NEXT: [[CONV1:%.*]] = fptosi float [[TMP2]] to i32 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 123 -// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK18-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 +// CHECK18-NEXT: store i8** null, i8*** [[TMP0]], align 8 // CHECK18-NEXT: ret void // // -// CHECK19-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) -// CHECK19-NEXT: ret i32 [[CALL]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK19-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK19-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[COMP_CASTED3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** -// CHECK19-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** -// CHECK19-NEXT: store i32* [[A]], i32** [[TMP5]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP6]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) -// CHECK19-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK19-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK19-NEXT: store i32 [[TMP17]], i32* [[COMP_CASTED3]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[COMP_CASTED3]], align 4 -// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** -// CHECK19-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** -// CHECK19-NEXT: store float* [[B]], float** [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK19-NEXT: store i32 [[TMP18]], i32* [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* -// CHECK19-NEXT: store i32 [[TMP18]], i32* [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK19-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP31:%.*]] = load float, float* [[B7]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = fptosi float [[TMP31]] to i32 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 -// CHECK19-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) -// CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK19-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] -// CHECK19: omp_offload.failed8: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i32 [[TMP18]]) #[[ATTR2]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT9]] -// CHECK19: omp_offload.cont9: -// CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK19-NEXT: ret i32 [[TMP34]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 -// CHECK19-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK19-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[TMP0]], align 4 // CHECK19-NEXT: ret void // // -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 -// CHECK19-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = fptosi float [[TMP2]] to i32 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK19-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 +// CHECK19-NEXT: store i8** null, i8*** [[TMP0]], align 4 // CHECK19-NEXT: ret void // // -// CHECK20-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) -// CHECK20-NEXT: ret i32 [[CALL]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK20-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK20-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[COMP_CASTED3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** -// CHECK20-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** -// CHECK20-NEXT: store i32* [[A]], i32** [[TMP5]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP6]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) -// CHECK20-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK20-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK20-NEXT: store i32 [[TMP17]], i32* [[COMP_CASTED3]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[COMP_CASTED3]], align 4 -// CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** -// CHECK20-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** -// CHECK20-NEXT: store float* [[B]], float** [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* -// CHECK20-NEXT: store i32 [[TMP18]], i32* [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* -// CHECK20-NEXT: store i32 [[TMP18]], i32* [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK20-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP31:%.*]] = load float, float* [[B7]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = fptosi float [[TMP31]] to i32 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 -// CHECK20-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) -// CHECK20-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK20-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] -// CHECK20: omp_offload.failed8: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i32 [[TMP18]]) #[[ATTR2]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT9]] -// CHECK20: omp_offload.cont9: -// CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK20-NEXT: ret i32 [[TMP34]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 -// CHECK20-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK20-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[TMP0]], align 4 // CHECK20-NEXT: ret void // // -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 -// CHECK20-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = fptosi float [[TMP2]] to i32 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 -// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK20-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 +// CHECK20-NEXT: store i8** null, i8*** [[TMP0]], align 4 // CHECK20-NEXT: ret void // // -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z21teams_template_structv +// CHECK21-LABEL: define {{[^@]+}}@_Z3foov // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: -// CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) -// CHECK21-NEXT: ret i32 [[CALL]] +// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK21-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK21-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK21-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK21-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK21-NEXT: ret i32 [[TMP2]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z21teams_template_structv +// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK21-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@_Z3foov // CHECK22-SAME: () #[[ATTR0:[0-9]+]] { // CHECK22-NEXT: entry: -// CHECK22-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) -// CHECK22-NEXT: ret i32 [[CALL]] +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK22-NEXT: ret void // // -// CHECK22-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK22-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK22-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK22-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK22-NEXT: ret i32 [[TMP2]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z21teams_template_structv +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: ret void +// +// +// CHECK23-LABEL: define {{[^@]+}}@_Z3foov // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: -// CHECK23-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) -// CHECK23-NEXT: ret i32 [[CALL]] +// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK23-NEXT: ret void // // -// CHECK23-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK23-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK23-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK23-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK23-NEXT: ret i32 [[TMP2]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) -// CHECK24-NEXT: ret i32 [[CALL]] +// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK23-NEXT: ret void // // -// CHECK24-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK24-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK24-LABEL: define {{[^@]+}}@_Z3foov +// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { // CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK24-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK24-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK24-NEXT: ret i32 [[TMP2]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK25-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 -// CHECK25-NEXT: store i32 0, i32* [[TMP0]], align 4 -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK25-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK25-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 -// CHECK25-NEXT: store i8** null, i8*** [[TMP0]], align 8 -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK26-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 -// CHECK26-NEXT: store i32 0, i32* [[TMP0]], align 4 -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK26-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK26-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 -// CHECK26-NEXT: store i8** null, i8*** [[TMP0]], align 8 -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK27-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[TMP0]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK27-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK27-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: store i8** null, i8*** [[TMP0]], align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK28-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[TMP0]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK28-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK28-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: store i8** null, i8*** [[TMP0]], align 4 -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@main -// CHECK29-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK29-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK29-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK29-NEXT: ret i32 [[CALL]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK29-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK29-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK29-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 -// CHECK29-NEXT: ret i32 0 -// -// -// CHECK30-LABEL: define {{[^@]+}}@main -// CHECK30-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK30-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK30-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK30-NEXT: ret i32 [[CALL]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK30-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK30-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK30-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 -// CHECK30-NEXT: ret i32 0 -// -// -// CHECK31-LABEL: define {{[^@]+}}@main -// CHECK31-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK31-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK31-NEXT: ret i32 [[CALL]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK31-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK31-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: ret i32 0 -// -// -// CHECK32-LABEL: define {{[^@]+}}@main -// CHECK32-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK32-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK32-NEXT: ret i32 [[CALL]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK32-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK32-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: ret i32 0 -// -// -// CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK33-NEXT: entry: -// CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 -// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK33-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK33-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK33-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 -// CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK33-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* -// CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]]) -// CHECK33-NEXT: ret void -// -// -// CHECK33-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK33-NEXT: entry: -// CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK33-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK33-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 -// CHECK33-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 -// CHECK33-NEXT: store i32 0, i32* [[TMP0]], align 4 -// CHECK33-NEXT: ret void -// -// -// CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK33-NEXT: entry: -// CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK33-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK33-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK33-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) -// CHECK33-NEXT: ret void -// -// -// CHECK33-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK33-NEXT: entry: -// CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 -// CHECK33-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK33-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK33-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 -// CHECK33-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 -// CHECK33-NEXT: store i8** null, i8*** [[TMP0]], align 8 -// CHECK33-NEXT: ret void -// -// -// CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK34-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK34-NEXT: entry: -// CHECK34-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 -// CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK34-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 -// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK34-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* -// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]]) -// CHECK34-NEXT: ret void -// -// -// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK34-NEXT: entry: -// CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK34-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK34-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 -// CHECK34-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 -// CHECK34-NEXT: store i32 0, i32* [[TMP0]], align 4 -// CHECK34-NEXT: ret void -// -// -// CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK34-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK34-NEXT: entry: -// CHECK34-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK34-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) -// CHECK34-NEXT: ret void -// -// -// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK34-NEXT: entry: -// CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 -// CHECK34-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK34-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK34-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 -// CHECK34-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 -// CHECK34-NEXT: store i8** null, i8*** [[TMP0]], align 8 -// CHECK34-NEXT: ret void -// -// -// CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK35-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK35-NEXT: entry: -// CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK35-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK35-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK35-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK35-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK35-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK35-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK35-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) -// CHECK35-NEXT: ret void -// -// -// CHECK35-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK35-NEXT: entry: -// CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 -// CHECK35-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK35-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK35-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 -// CHECK35-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 -// CHECK35-NEXT: store i32 0, i32* [[TMP0]], align 4 -// CHECK35-NEXT: ret void -// -// -// CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK35-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK35-NEXT: entry: -// CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK35-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK35-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK35-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK35-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK35-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK35-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK35-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) -// CHECK35-NEXT: ret void -// -// -// CHECK35-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK35-NEXT: entry: -// CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 -// CHECK35-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK35-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK35-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 -// CHECK35-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 -// CHECK35-NEXT: store i8** null, i8*** [[TMP0]], align 4 -// CHECK35-NEXT: ret void -// -// -// CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK36-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK36-NEXT: entry: -// CHECK36-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK36-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK36-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK36-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK36-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK36-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK36-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK36-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK36-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK36-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) -// CHECK36-NEXT: ret void -// -// -// CHECK36-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK36-NEXT: entry: -// CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 -// CHECK36-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK36-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK36-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 -// CHECK36-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 -// CHECK36-NEXT: store i32 0, i32* [[TMP0]], align 4 -// CHECK36-NEXT: ret void -// -// -// CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK36-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK36-NEXT: entry: -// CHECK36-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK36-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK36-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK36-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK36-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK36-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK36-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK36-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK36-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK36-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) -// CHECK36-NEXT: ret void -// -// -// CHECK36-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { -// CHECK36-NEXT: entry: -// CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 -// CHECK36-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK36-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK36-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 -// CHECK36-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 -// CHECK36-NEXT: store i8** null, i8*** [[TMP0]], align 4 -// CHECK36-NEXT: ret void -// -// -// CHECK37-LABEL: define {{[^@]+}}@main -// CHECK37-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK37-NEXT: entry: -// CHECK37-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK37-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK37-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK37-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK37-NEXT: store i32 20, i32* [[A]], align 4 -// CHECK37-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK37-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK37-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK37-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK37-NEXT: ret i32 [[CALL]] -// -// -// CHECK37-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK37-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK37-NEXT: entry: -// CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK37-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK37-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK37-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK37-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 -// CHECK37-NEXT: ret i32 0 -// -// -// CHECK38-LABEL: define {{[^@]+}}@main -// CHECK38-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK38-NEXT: entry: -// CHECK38-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK38-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK38-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK38-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK38-NEXT: store i32 20, i32* [[A]], align 4 -// CHECK38-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK38-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK38-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK38-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK38-NEXT: ret i32 [[CALL]] -// -// -// CHECK38-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK38-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK38-NEXT: entry: -// CHECK38-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK38-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK38-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK38-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK38-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 -// CHECK38-NEXT: ret i32 0 -// -// -// CHECK39-LABEL: define {{[^@]+}}@main -// CHECK39-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK39-NEXT: entry: -// CHECK39-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK39-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK39-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK39-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK39-NEXT: store i32 20, i32* [[A]], align 4 -// CHECK39-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK39-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK39-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 -// CHECK39-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK39-NEXT: ret i32 [[CALL]] -// -// -// CHECK39-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK39-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK39-NEXT: entry: -// CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK39-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK39-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK39-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK39-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 -// CHECK39-NEXT: ret i32 0 -// -// -// CHECK40-LABEL: define {{[^@]+}}@main -// CHECK40-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK40-NEXT: entry: -// CHECK40-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK40-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK40-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK40-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK40-NEXT: store i32 20, i32* [[A]], align 4 -// CHECK40-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK40-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK40-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 -// CHECK40-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK40-NEXT: ret i32 [[CALL]] -// -// -// CHECK40-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK40-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK40-NEXT: entry: -// CHECK40-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK40-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK40-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK40-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK40-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 -// CHECK40-NEXT: ret i32 0 -// -// -// CHECK41-LABEL: define {{[^@]+}}@_Z3foov -// CHECK41-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK41-NEXT: ret void -// -// -// CHECK41-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK41-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK41-NEXT: ret void -// -// -// CHECK42-LABEL: define {{[^@]+}}@_Z3foov -// CHECK42-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK42-NEXT: ret void -// -// -// CHECK42-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK42-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK42-NEXT: ret void -// -// -// CHECK43-LABEL: define {{[^@]+}}@_Z3foov -// CHECK43-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK43-NEXT: entry: -// CHECK43-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK43-NEXT: ret void -// -// -// CHECK43-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK43-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK43-NEXT: entry: -// CHECK43-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK43-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK43-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK43-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK43-NEXT: ret void -// -// -// CHECK44-LABEL: define {{[^@]+}}@_Z3foov -// CHECK44-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK44-NEXT: entry: -// CHECK44-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK44-NEXT: ret void -// -// -// CHECK44-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK44-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK44-NEXT: entry: -// CHECK44-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK44-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK44-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK44-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK44-NEXT: ret void -// -// -// CHECK45-LABEL: define {{[^@]+}}@_Z3foov -// CHECK45-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK45-NEXT: entry: -// CHECK45-NEXT: ret void -// -// -// CHECK46-LABEL: define {{[^@]+}}@_Z3foov -// CHECK46-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK46-NEXT: entry: -// CHECK46-NEXT: ret void -// -// -// CHECK47-LABEL: define {{[^@]+}}@_Z3foov -// CHECK47-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK47-NEXT: entry: -// CHECK47-NEXT: ret void +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK24-NEXT: ret void // // -// CHECK48-LABEL: define {{[^@]+}}@_Z3foov -// CHECK48-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK48-NEXT: entry: -// CHECK48-NEXT: ret void +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_codegen.cpp b/clang/test/OpenMP/teams_distribute_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_codegen.cpp @@ -10,12 +10,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 int a[100]; @@ -51,19 +51,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 int teams_local_arg(void) { @@ -84,19 +84,19 @@ #endif // CK2 // Test host codegen. -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK3 @@ -127,19 +127,19 @@ #endif // CK3 // Test host codegen. -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 @@ -1611,1031 +1611,1338 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK5-NEXT: ret i32 [[TMP33]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK5-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i64 0, i64 0), align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK6-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK6-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK6-NEXT: ret i32 [[TMP33]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK6-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] // CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i64 0, i64 0), align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK7-NEXT: ret i32 [[TMP33]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK7-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP3]] +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i32 0, i32 0), align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK8-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK8-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK8-NEXT: ret i32 [[TMP33]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK8-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP3]] +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] // CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i32 0, i32 0), align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) +// CHECK9-NEXT: ret i32 [[CALL]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** +// CHECK9-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** +// CHECK9-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123) +// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK9-NEXT: ret i32 [[TMP33]] +// CHECK9-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: ret i32 [[TMP9]] // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 +// CHECK9-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: +// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9: cond.true: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9: cond.false: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: br label [[COND_END]] // CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) // CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK10-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK10-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) +// CHECK10-NEXT: ret i32 [[CALL]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** +// CHECK10-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** +// CHECK10-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123) +// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK10-NEXT: ret i32 [[TMP33]] +// CHECK10-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: ret i32 [[TMP9]] // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 +// CHECK10-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: +// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10: cond.true: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: br label [[COND_END:%.*]] // CHECK10: cond.false: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: br label [[COND_END]] // CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK11-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK11-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) +// CHECK11-NEXT: ret i32 [[CALL]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** +// CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** +// CHECK11-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123) +// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK11-NEXT: ret i32 [[TMP33]] +// CHECK11-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: ret i32 [[TMP9]] // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 +// CHECK11-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: +// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK11: cond.true: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK11-NEXT: br label [[COND_END:%.*]] // CHECK11: cond.false: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: br label [[COND_END]] // CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) // CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK12-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK12-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) +// CHECK12-NEXT: ret i32 [[CALL]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** +// CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** +// CHECK12-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123) +// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK12-NEXT: ret i32 [[TMP33]] +// CHECK12-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: ret i32 [[TMP9]] // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 +// CHECK12-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: +// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK12: cond.true: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK12-NEXT: br label [[COND_END:%.*]] // CHECK12: cond.false: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: br label [[COND_END]] // CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP9]] // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK13-LABEL: define {{[^@]+}}@main +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: +// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store i32 100, i32* [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 @@ -2643,39 +2950,359 @@ // CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK13-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK13-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK13-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK13-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK13-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK13-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK13-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK13-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK13-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK13-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK13-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK13-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK13-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK13-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK13-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK13-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK13-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK13-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK13-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK13-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK13-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK13-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK13-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK13: omp_offload.failed: +// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK13: omp_offload.cont: +// CHECK13-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) +// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK13-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK13-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK13-NEXT: ret i32 [[TMP35]] +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK13: omp.precond.then: +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK13-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK13-NEXT: br label [[OMP_PRECOND_END]] +// CHECK13: omp.precond.end: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK13-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TE_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TH_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[TE]], align 4 +// CHECK13-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[TE_CASTED]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[TH_CASTED]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK13-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK13-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK13-NEXT: store i8* null, i8** [[TMP8]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK13-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK13-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK13-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK13-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK13-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** +// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 8 +// CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK13-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** +// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 8 +// CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK13-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK13-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 [[TMP22]]) +// CHECK13-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK13-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK13: omp_offload.failed: +// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK13: omp_offload.cont: +// CHECK13-NEXT: ret i32 0 +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 +// CHECK13-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK13-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK13-NEXT: ret i32 [[TMP7]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK13-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK13-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK13-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@main +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: +// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 // CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 // CHECK14-NEXT: store i32 100, i32* [[N]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 // CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 @@ -2683,2510 +3310,1039 @@ // CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK14-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK14-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK14-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK14-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK14-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK14-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK14-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK14-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK14-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK14-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK14-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK14-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK14-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK14-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK14-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK14-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK14-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK14-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK14-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK14-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK14-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK14-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK14-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK14-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK14-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK14-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK14-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK14: omp_offload.failed: +// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK14: omp_offload.cont: +// CHECK14-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) +// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK14-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK14-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK14-NEXT: ret i32 [[TMP35]] +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK14: omp.precond.then: +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK14-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK14-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK14-NEXT: br label [[OMP_PRECOND_END]] +// CHECK14: omp.precond.end: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK14-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TE_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TH_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[TE]], align 4 +// CHECK14-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[TE_CASTED]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[TH_CASTED]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK14-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK14-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK14-NEXT: store i8* null, i8** [[TMP8]], align 8 +// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK14-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK14-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK14-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK14-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK14-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** +// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 8 +// CHECK14-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK14-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** +// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 8 +// CHECK14-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK14-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK14-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK14-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 [[TMP22]]) +// CHECK14-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK14-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK14: omp_offload.failed: +// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK14: omp_offload.cont: +// CHECK14-NEXT: ret i32 0 +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 +// CHECK14-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK14-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK14-NEXT: ret i32 [[TMP7]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK14-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK14-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK14-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@main +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store i32 100, i32* [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() // CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK15-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK15-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK15-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK15-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK15-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK15-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK15-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK15-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK15-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK15-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK15-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK15-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK15-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK15-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK15-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK15-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK15-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK15-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK15-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK15-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK15-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK15: omp_offload.failed: +// CHECK15-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK15: omp_offload.cont: +// CHECK15-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) +// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK15-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK15-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK15-NEXT: ret i32 [[TMP35]] +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK15-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK15-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK15: omp.precond.then: +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK15-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK15-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] +// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK15-NEXT: br label [[OMP_PRECOND_END]] +// CHECK15: omp.precond.end: +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK15-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TE_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TH_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[TE]], align 4 +// CHECK15-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[TE_CASTED]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK15-NEXT: store i32 [[TMP2]], i32* [[TH_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK15-NEXT: store i8* null, i8** [[TMP8]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK15-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** +// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 4 +// CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** +// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 4 +// CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK15-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK15-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 [[TMP22]]) +// CHECK15-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK15-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK15: omp_offload.failed: +// CHECK15-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK15: omp_offload.cont: +// CHECK15-NEXT: ret i32 0 +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 +// CHECK15-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK15-NEXT: store i32 [[TE]], i32* [[TE_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TH]], i32* [[TH_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TE_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK15-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK15-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK15-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@main +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: +// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 // CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 // CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 // CHECK16-NEXT: store i32 100, i32* [[N]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() // CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK16-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK16-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK16-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK16-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK16-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK16-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK16-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK16-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK16-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK16-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK16-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK16-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK16-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK16-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK16-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK16-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK16-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK16-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK16-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK16-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK16-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK16-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK16-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK16: omp_offload.failed: +// CHECK16-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK16-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK16: omp_offload.cont: +// CHECK16-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) +// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK16-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK16-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK16-NEXT: ret i32 [[TMP35]] +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK16-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK16-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK16: omp.precond.then: +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK16-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK16-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] // CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK17-NEXT: ret i32 [[CALL]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK17-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** -// CHECK17-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** -// CHECK17-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123) -// CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK17-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: ret i32 [[TMP9]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK17-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK18-NEXT: ret i32 [[CALL]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK18-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** -// CHECK18-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** -// CHECK18-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123) -// CHECK18-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK18-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: ret i32 [[TMP9]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK18-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK19-NEXT: ret i32 [[CALL]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK19-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** -// CHECK19-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** -// CHECK19-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123) -// CHECK19-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK19-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: ret i32 [[TMP9]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK19-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP9]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK20-NEXT: ret i32 [[CALL]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK20-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** -// CHECK20-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** -// CHECK20-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123) -// CHECK20-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK20-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: ret i32 [[TMP9]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK20-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP9]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK21-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK22-NEXT: ret i32 [[CALL]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK22-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK23-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK23-NEXT: ret i32 [[CALL]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK23-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK24-NEXT: ret i32 [[CALL]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK24-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@main -// CHECK25-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK25-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK25-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK25-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK25-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK25-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK25-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK25-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK25-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK25-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK25-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK25-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK25-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK25-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK25-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK25-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK25-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK25-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK25-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK25-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK25-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK25-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK25-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK25-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK25-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK25-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK25-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK25-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK25-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK25-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK25-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK25-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK25-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK25-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK25-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK25-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK25-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK25-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK25-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK25-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK25-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK25-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK25-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK25-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK25: omp_offload.failed: -// CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK25: omp_offload.cont: -// CHECK25-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) -// CHECK25-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK25-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK25-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK25-NEXT: ret i32 [[TMP35]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK25-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK25-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK25-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK25-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK25: omp.precond.then: -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK25-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK25-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK25-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK25-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK25-NEXT: br label [[OMP_PRECOND_END]] -// CHECK25: omp.precond.end: -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK25-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK25-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TE_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TH_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK25-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[TE_CASTED]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[TH_CASTED]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK25-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK25-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK25-NEXT: store i8* null, i8** [[TMP8]], align 8 -// CHECK25-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK25-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK25-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK25-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK25-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK25-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK25-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK25-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 8 -// CHECK25-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK25-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 8 -// CHECK25-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK25-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK25-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK25-NEXT: [[TMP22:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK25-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK25-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 [[TMP22]]) -// CHECK25-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK25-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK25: omp_offload.failed: -// CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK25: omp_offload.cont: -// CHECK25-NEXT: ret i32 0 -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK25-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) -// CHECK25-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK25-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK25-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK25-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@main -// CHECK26-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK26-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK26-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK26-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK26-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK26-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK26-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK26-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK26-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK26-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK26-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK26-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK26-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK26-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK26-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK26-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK26-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK26-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK26-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK26-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK26-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK26-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK26-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK26-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK26-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK26-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK26-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK26-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK26-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK26-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK26-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK26-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK26-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK26-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK26-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK26-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK26-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK26-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK26-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK26-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK26-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK26-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK26-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK26-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK26: omp_offload.failed: -// CHECK26-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK26-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK26: omp_offload.cont: -// CHECK26-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) -// CHECK26-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK26-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK26-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK26-NEXT: ret i32 [[TMP35]] -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK26-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK26-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK26-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK26-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK26: omp.precond.then: -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK26-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK26-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK26-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK26-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK26-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK26-NEXT: br label [[OMP_PRECOND_END]] -// CHECK26: omp.precond.end: -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK26-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK26-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TE_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TH_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK26-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[TE_CASTED]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[TH_CASTED]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK26-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK26-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK26-NEXT: store i8* null, i8** [[TMP8]], align 8 -// CHECK26-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK26-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK26-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK26-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK26-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK26-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK26-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK26-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 8 -// CHECK26-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK26-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 8 -// CHECK26-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK26-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK26-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK26-NEXT: [[TMP22:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK26-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK26-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 [[TMP22]]) -// CHECK26-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK26-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK26: omp_offload.failed: -// CHECK26-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK26-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK26: omp_offload.cont: -// CHECK26-NEXT: ret i32 0 -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK26-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) -// CHECK26-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK26-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK26-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK26-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK26-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@main -// CHECK27-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK27-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK27-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK27-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK27-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK27-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK27-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK27-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK27-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK27-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK27-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK27-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK27-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK27-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK27-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK27-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK27-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK27-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK27-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK27-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK27-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK27-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK27-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK27-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK27-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK27-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK27-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK27-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK27-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK27-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK27-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK27-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK27-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK27-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK27-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK27-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK27-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK27: omp_offload.failed: -// CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK27: omp_offload.cont: -// CHECK27-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) -// CHECK27-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK27-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK27-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK27-NEXT: ret i32 [[TMP35]] -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK27-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK27-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK27-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK27-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK27: omp.precond.then: -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK27-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] -// CHECK27-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK27-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK27-NEXT: br label [[OMP_PRECOND_END]] -// CHECK27: omp.precond.end: -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK27-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK27-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TE_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TH_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK27-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[TE_CASTED]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK27-NEXT: store i32 [[TMP2]], i32* [[TH_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK27-NEXT: store i8* null, i8** [[TMP8]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK27-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK27-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK27-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK27-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK27-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 4 -// CHECK27-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK27-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 4 -// CHECK27-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK27-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK27-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK27-NEXT: [[TMP22:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK27-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 [[TMP22]]) -// CHECK27-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK27-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK27: omp_offload.failed: -// CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK27: omp_offload.cont: -// CHECK27-NEXT: ret i32 0 -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK27-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) -// CHECK27-NEXT: store i32 [[TE]], i32* [[TE_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TH]], i32* [[TH_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TE_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK27-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK27-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK27-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@main -// CHECK28-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK28-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK28-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK28-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK28-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK28-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK28-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK28-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK28-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK28-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK28-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK28-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK28-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK28-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK28-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK28-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK28-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK28-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK28-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK28-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK28-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK28-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK28-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK28-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK28-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK28-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK28-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK28-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK28-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK28-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK28-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK28-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK28-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK28-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK28-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK28-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK28-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK28: omp_offload.failed: -// CHECK28-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK28-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK28: omp_offload.cont: -// CHECK28-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) -// CHECK28-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK28-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK28-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK28-NEXT: ret i32 [[TMP35]] -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK28-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK28-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK28-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK28-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK28: omp.precond.then: -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK28-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] -// CHECK28-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK28-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK28-NEXT: br label [[OMP_PRECOND_END]] -// CHECK28: omp.precond.end: -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK28-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK28-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TE_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TH_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK28-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[TE_CASTED]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK28-NEXT: store i32 [[TMP2]], i32* [[TH_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK28-NEXT: store i8* null, i8** [[TMP8]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK28-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK28-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK28-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK28-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK28-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 4 -// CHECK28-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK28-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 4 -// CHECK28-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK28-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK28-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK28-NEXT: [[TMP22:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK28-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 [[TMP22]]) -// CHECK28-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK28-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK28: omp_offload.failed: -// CHECK28-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK28-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK28: omp_offload.cont: -// CHECK28-NEXT: ret i32 0 -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK28-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) -// CHECK28-NEXT: store i32 [[TE]], i32* [[TE_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TH]], i32* [[TH_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TE_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK28-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK28-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK28-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@main -// CHECK29-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK29-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK29-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK29-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP7]]) -// CHECK29-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK29-NEXT: ret i32 [[TMP9]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK29-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK29-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK29-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: ret i32 0 -// -// -// CHECK30-LABEL: define {{[^@]+}}@main -// CHECK30-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK30-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK30-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK30-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP7]]) -// CHECK30-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK30-NEXT: ret i32 [[TMP9]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK30-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK30-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK30-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: ret i32 0 -// -// -// CHECK31-LABEL: define {{[^@]+}}@main -// CHECK31-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK31-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK31-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK31-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP6]]) -// CHECK31-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK31-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK31-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK31-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK31-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: ret i32 0 -// -// -// CHECK32-LABEL: define {{[^@]+}}@main -// CHECK32-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK32-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK32-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK32-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP6]]) -// CHECK32-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK32-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK32-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK32-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK32-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: ret i32 0 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK16-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK16-NEXT: br label [[OMP_PRECOND_END]] +// CHECK16: omp.precond.end: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK16-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TE_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TH_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[TE]], align 4 +// CHECK16-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[TE_CASTED]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK16-NEXT: store i32 [[TMP2]], i32* [[TH_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK16-NEXT: store i8* null, i8** [[TMP8]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK16-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** +// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** +// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK16-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK16-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 [[TMP22]]) +// CHECK16-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK16-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK16: omp_offload.failed: +// CHECK16-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK16-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK16: omp_offload.cont: +// CHECK16-NEXT: ret i32 0 +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 +// CHECK16-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK16-NEXT: store i32 [[TE]], i32* [[TE_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TH]], i32* [[TH_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TE_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK16-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK16-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK16-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -47,19 +47,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -669,2428 +669,1720 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK5-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK5-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() +// CHECK5-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK5-NEXT: store i64 4, i64* [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK5-NEXT: store i64 8, i64* [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK5-NEXT: store i64 8, i64* [[TMP34]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP35]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK5-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 +// CHECK5-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 +// CHECK5-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK5-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] +// CHECK5-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK5-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK5-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK5-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 +// CHECK5-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) +// CHECK5-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP54]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK5-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK5-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK5-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK5-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body: // CHECK5-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: land.lhs.true: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK5-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK5-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 +// CHECK5-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK5-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// CHECK5-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// CHECK5-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] +// CHECK5-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// CHECK5-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK5-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK5-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// CHECK5-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// CHECK5-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// CHECK5-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 +// CHECK5-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK5-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// CHECK5-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// CHECK5-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// CHECK5-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] +// CHECK5-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// CHECK5-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// CHECK5-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// CHECK5-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK5-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]] +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 +// CHECK5-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK5-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 +// CHECK5-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK5-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) +// CHECK5-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK5-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 +// CHECK5-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] +// CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 +// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK6-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK6-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() +// CHECK6-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK6-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK6-NEXT: store i64 4, i64* [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK6-NEXT: store i64 8, i64* [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK6-NEXT: store i64 8, i64* [[TMP34]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP35]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK6-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 +// CHECK6-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 +// CHECK6-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK6-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] +// CHECK6-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK6-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK6-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK6-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 +// CHECK6-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) +// CHECK6-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP54]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK6-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK6-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK6-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK6-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body: // CHECK6-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: land.lhs.true: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK6-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK6-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK6-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 +// CHECK6-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK6-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// CHECK6-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// CHECK6-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] +// CHECK6-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// CHECK6-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK6-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK6-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// CHECK6-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// CHECK6-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// CHECK6-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 +// CHECK6-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK6-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// CHECK6-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// CHECK6-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// CHECK6-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] +// CHECK6-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// CHECK6-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// CHECK6-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// CHECK6-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK6-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]] +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 +// CHECK6-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK6-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 +// CHECK6-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK6-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) +// CHECK6-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK6-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 +// CHECK6-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] +// CHECK6-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 +// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@main +// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK7-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK7-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 +// CHECK7-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK7-NEXT: store i64 4, i64* [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK7-NEXT: store i64 4, i64* [[TMP33]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 +// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 +// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK7-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 +// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK7-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 +// CHECK7-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] +// CHECK7-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK7-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 +// CHECK7-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) +// CHECK7-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP53]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK7-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK7-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body: // CHECK7-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: land.lhs.true: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 +// CHECK7-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK7-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// CHECK7-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// CHECK7-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] +// CHECK7-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// CHECK7-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK7-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK7-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// CHECK7-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// CHECK7-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// CHECK7-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 +// CHECK7-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK7-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// CHECK7-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// CHECK7-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// CHECK7-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] +// CHECK7-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// CHECK7-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// CHECK7-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// CHECK7-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]] +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 +// CHECK7-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 +// CHECK7-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK7-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 +// CHECK7-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] +// CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@main +// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK8-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK8-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 +// CHECK8-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK8-NEXT: store i64 4, i64* [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK8-NEXT: store i64 4, i64* [[TMP33]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 +// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 +// CHECK8-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK8-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 +// CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK8-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK8-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 +// CHECK8-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] +// CHECK8-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK8-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 +// CHECK8-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) +// CHECK8-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP53]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK8-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK8-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK8-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body: // CHECK8-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK9-NEXT: store i64 4, i64* [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK9-NEXT: store i64 8, i64* [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK9-NEXT: store i64 8, i64* [[TMP34]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 -// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 -// CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] -// CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK9-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK9-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 -// CHECK9-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) -// CHECK9-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP54]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: land.lhs.true: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 -// CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 -// CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] -// CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 -// CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] -// CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] -// CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 -// CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 -// CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] -// CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 -// CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 -// CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 -// CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] -// CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 -// CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] -// CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] -// CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 -// CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] -// CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]] -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 -// CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK9-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] -// CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK10-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK10-NEXT: store i64 4, i64* [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK10-NEXT: store i64 8, i64* [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 -// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK10-NEXT: store i64 8, i64* [[TMP34]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK10-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 -// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 -// CHECK10-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 -// CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] -// CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK10-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK10-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 -// CHECK10-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) -// CHECK10-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP54]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: land.lhs.true: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 -// CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 -// CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] -// CHECK10-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 -// CHECK10-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] -// CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] -// CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 -// CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 -// CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] -// CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 -// CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 -// CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 -// CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] -// CHECK10-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 -// CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] -// CHECK10-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] -// CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 -// CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] -// CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK10-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]] -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 -// CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK10-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] -// CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 -// CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK11-NEXT: store i64 4, i64* [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK11-NEXT: store i64 4, i64* [[TMP33]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP34]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 -// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 -// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 -// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 -// CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] -// CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK11-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 -// CHECK11-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) -// CHECK11-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP53]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: land.lhs.true: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 -// CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 -// CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] -// CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 -// CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] -// CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] -// CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 -// CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 -// CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] -// CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 -// CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 -// CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 -// CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] -// CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 -// CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] -// CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] -// CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 -// CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] -// CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]] -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 -// CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) -// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] -// CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 -// CHECK12-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK12-NEXT: store i64 4, i64* [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK12-NEXT: store i64 4, i64* [[TMP33]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP34]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 -// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 -// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK12-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 -// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK12-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 -// CHECK12-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] -// CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK12-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 -// CHECK12-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) -// CHECK12-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP53]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: land.lhs.true: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 -// CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 -// CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] -// CHECK12-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 -// CHECK12-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] -// CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] -// CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 -// CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 -// CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] -// CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 -// CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 -// CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 -// CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] -// CHECK12-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 -// CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] -// CHECK12-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] -// CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 -// CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] -// CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]] -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 -// CHECK12-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) -// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] -// CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP17]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP17]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP15]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP15]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: land.lhs.true: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 +// CHECK8-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK8-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// CHECK8-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// CHECK8-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] +// CHECK8-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// CHECK8-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK8-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK8-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// CHECK8-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// CHECK8-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// CHECK8-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 +// CHECK8-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK8-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// CHECK8-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// CHECK8-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// CHECK8-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] +// CHECK8-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// CHECK8-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// CHECK8-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// CHECK8-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]] +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 +// CHECK8-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 +// CHECK8-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK8-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 +// CHECK8-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK8-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] +// CHECK8-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 +// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -58,19 +58,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -1513,4554 +1513,3626 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES23:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK5-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK5-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK5-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK5-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK5-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK5-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK5-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP60]]) +// CHECK5-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK5-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK5: omp_offload.failed16: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK5: omp_offload.cont17: +// CHECK5-NEXT: [[TMP63:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* +// CHECK5-NEXT: store i32 [[TMP63]], i32* [[CONV19]], align 4 +// CHECK5-NEXT: [[TMP64:%.*]] = load i64, i64* [[N_CASTED18]], align 8 +// CHECK5-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* +// CHECK5-NEXT: store i64 [[TMP64]], i64* [[TMP67]], align 8 +// CHECK5-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* +// CHECK5-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 +// CHECK5-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP70]], align 8 +// CHECK5-NEXT: [[TMP71:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP71]], align 8 +// CHECK5-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP73]], align 8 +// CHECK5-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP75]], align 8 +// CHECK5-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP76]], align 8 +// CHECK5-NEXT: [[TMP77:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP77]], align 8 +// CHECK5-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP79]], align 8 +// CHECK5-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 8 +// CHECK5-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP65]], i64* [[TMP82]], align 8 +// CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP83]], align 8 +// CHECK5-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP87:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK5-NEXT: [[TMP88:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK5-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP88]], 0 +// CHECK5-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK5-NEXT: [[SUB29:%.*]] = sub nsw i32 [[DIV28]], 1 +// CHECK5-NEXT: store i32 [[SUB29]], i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK5-NEXT: [[TMP89:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK5-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP89]], 1 +// CHECK5-NEXT: [[TMP90:%.*]] = zext i32 [[ADD30]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP90]]) +// CHECK5-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP84]], i8** [[TMP85]], i64* [[TMP86]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0 +// CHECK5-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]] +// CHECK5: omp_offload.failed31: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP64]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT32]] +// CHECK5: omp_offload.cont32: +// CHECK5-NEXT: [[TMP93:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP93]]) +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[TMP94:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP94]]) +// CHECK5-NEXT: [[TMP95:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP95]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK5-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK5-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK5-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK5: omp_offload.failed5: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK5: omp_offload.cont6: +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK5-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK5: omp_offload.failed11: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK5: omp_offload.cont12: +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3:%.*]] -// CHECK5: for.cond3: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK5: for.body5: -// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK5-NEXT: br label [[FOR_INC9:%.*]] -// CHECK5: for.inc9: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end11: -// CHECK5-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13:%.*]] -// CHECK5: for.cond13: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK5-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK5: for.body15: -// CHECK5-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK5-NEXT: br label [[FOR_INC19:%.*]] -// CHECK5: for.inc19: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end21: -// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void +// // +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void // -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES23:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK6-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK6-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK6-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK6-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK6-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK6-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK6-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK6-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK6-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK6-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK6-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK6-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK6-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK6-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK6-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK6-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK6-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP60]]) +// CHECK6-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK6-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK6: omp_offload.failed16: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK6: omp_offload.cont17: +// CHECK6-NEXT: [[TMP63:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* +// CHECK6-NEXT: store i32 [[TMP63]], i32* [[CONV19]], align 4 +// CHECK6-NEXT: [[TMP64:%.*]] = load i64, i64* [[N_CASTED18]], align 8 +// CHECK6-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* +// CHECK6-NEXT: store i64 [[TMP64]], i64* [[TMP67]], align 8 +// CHECK6-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* +// CHECK6-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 +// CHECK6-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP70]], align 8 +// CHECK6-NEXT: [[TMP71:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP71]], align 8 +// CHECK6-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP73]], align 8 +// CHECK6-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP75]], align 8 +// CHECK6-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP76]], align 8 +// CHECK6-NEXT: [[TMP77:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP77]], align 8 +// CHECK6-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP79]], align 8 +// CHECK6-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 8 +// CHECK6-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP65]], i64* [[TMP82]], align 8 +// CHECK6-NEXT: [[TMP83:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP83]], align 8 +// CHECK6-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP87:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK6-NEXT: [[TMP88:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 +// CHECK6-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP88]], 0 +// CHECK6-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK6-NEXT: [[SUB29:%.*]] = sub nsw i32 [[DIV28]], 1 +// CHECK6-NEXT: store i32 [[SUB29]], i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK6-NEXT: [[TMP89:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK6-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP89]], 1 +// CHECK6-NEXT: [[TMP90:%.*]] = zext i32 [[ADD30]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP90]]) +// CHECK6-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP84]], i8** [[TMP85]], i64* [[TMP86]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0 +// CHECK6-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]] +// CHECK6: omp_offload.failed31: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP64]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT32]] +// CHECK6: omp_offload.cont32: +// CHECK6-NEXT: [[TMP93:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP93]]) +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[TMP94:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP94]]) +// CHECK6-NEXT: [[TMP95:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP95]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] // CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC9:%.*]] -// CHECK6: for.inc9: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end11: -// CHECK6-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13:%.*]] -// CHECK6: for.cond13: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK6-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK6: for.body15: -// CHECK6-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK6-NEXT: br label [[FOR_INC19:%.*]] -// CHECK6: for.inc19: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end21: -// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK6-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK6-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK6-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK6: omp_offload.failed5: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK6: omp_offload.cont6: +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK6-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK6: omp_offload.failed11: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK6: omp_offload.cont12: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@main +// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK7-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK7-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK7-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK7-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK7-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK7-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP61]]) +// CHECK7-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK7-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK7: omp_offload.failed15: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK7: omp_offload.cont16: +// CHECK7-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP64]], i32* [[N_CASTED17]], align 4 +// CHECK7-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_CASTED17]], align 4 +// CHECK7-NEXT: [[TMP66:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP67:%.*]] = sext i32 [[TMP66]] to i64 +// CHECK7-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32* +// CHECK7-NEXT: store i32 [[TMP65]], i32* [[TMP69]], align 4 +// CHECK7-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* +// CHECK7-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 +// CHECK7-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP72]], align 4 +// CHECK7-NEXT: [[TMP73:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP73]], align 4 +// CHECK7-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP75]], align 4 +// CHECK7-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP77]], align 4 +// CHECK7-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP78]], align 4 +// CHECK7-NEXT: [[TMP79:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP79]], align 4 +// CHECK7-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 4 +// CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP83]], align 4 +// CHECK7-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP67]], i64* [[TMP84]], align 4 +// CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP85]], align 4 +// CHECK7-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP89:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK7-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK7-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP90]], 0 +// CHECK7-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 +// CHECK7-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 +// CHECK7-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK7-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK7-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP91]], 1 +// CHECK7-NEXT: [[TMP92:%.*]] = zext i32 [[ADD28]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP92]]) +// CHECK7-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP86]], i8** [[TMP87]], i64* [[TMP88]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0 +// CHECK7-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] +// CHECK7: omp_offload.failed29: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP65]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT30]] +// CHECK7: omp_offload.cont30: +// CHECK7-NEXT: [[TMP95:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP95]]) +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[TMP96:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP96]]) +// CHECK7-NEXT: [[TMP97:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP97]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC8:%.*]] -// CHECK7: for.inc8: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end10: -// CHECK7-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12:%.*]] -// CHECK7: for.cond12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK7-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK7: for.body14: -// CHECK7-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK7-NEXT: br label [[FOR_INC17:%.*]] -// CHECK7: for.inc17: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end19: -// CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP20]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK7-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK7-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK7: omp_offload.failed5: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK7: omp_offload.cont6: +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK7-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK7: omp_offload.failed11: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK7: omp_offload.cont12: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK7: omp.dispatch.cond: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK7: omp.dispatch.body: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK7: omp.dispatch.inc: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK7: omp.dispatch.end: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@main +// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK8-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK8-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK8-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK8-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK8-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK8-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK8-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK8-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK8-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK8-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK8-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK8-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK8-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK8-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK8-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK8-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK8-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP61]]) +// CHECK8-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK8-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK8: omp_offload.failed15: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK8: omp_offload.cont16: +// CHECK8-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP64]], i32* [[N_CASTED17]], align 4 +// CHECK8-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_CASTED17]], align 4 +// CHECK8-NEXT: [[TMP66:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP67:%.*]] = sext i32 [[TMP66]] to i64 +// CHECK8-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32* +// CHECK8-NEXT: store i32 [[TMP65]], i32* [[TMP69]], align 4 +// CHECK8-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* +// CHECK8-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 +// CHECK8-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP72]], align 4 +// CHECK8-NEXT: [[TMP73:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP73]], align 4 +// CHECK8-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP75]], align 4 +// CHECK8-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP77]], align 4 +// CHECK8-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP78]], align 4 +// CHECK8-NEXT: [[TMP79:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP79]], align 4 +// CHECK8-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 4 +// CHECK8-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP83]], align 4 +// CHECK8-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP67]], i64* [[TMP84]], align 4 +// CHECK8-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP85]], align 4 +// CHECK8-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP87:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP88:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP89:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK8-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK8-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP90]], 0 +// CHECK8-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 +// CHECK8-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 +// CHECK8-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK8-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK8-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP91]], 1 +// CHECK8-NEXT: [[TMP92:%.*]] = zext i32 [[ADD28]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP92]]) +// CHECK8-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP86]], i8** [[TMP87]], i64* [[TMP88]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0 +// CHECK8-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] +// CHECK8: omp_offload.failed29: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP65]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT30]] +// CHECK8: omp_offload.cont30: +// CHECK8-NEXT: [[TMP95:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP95]]) +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[TMP96:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP96]]) +// CHECK8-NEXT: [[TMP97:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP97]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP20]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK8-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK8-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK8: omp_offload.failed5: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK8: omp_offload.cont6: +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK8-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK8: omp_offload.failed11: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK8: omp_offload.cont12: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] // CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC8:%.*]] -// CHECK8: for.inc8: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end10: -// CHECK8-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12:%.*]] -// CHECK8: for.cond12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK8-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK8: for.body14: -// CHECK8-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK8-NEXT: br label [[FOR_INC17:%.*]] -// CHECK8: for.inc17: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end19: -// CHECK8-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK9-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES23:%.*]] = alloca [3 x i64], align 8 -// CHECK9-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK9-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK9-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK9-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK9-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP60]]) -// CHECK9-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK9-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK9: omp_offload.failed16: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK9: omp_offload.cont17: -// CHECK9-NEXT: [[TMP63:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* -// CHECK9-NEXT: store i32 [[TMP63]], i32* [[CONV19]], align 4 -// CHECK9-NEXT: [[TMP64:%.*]] = load i64, i64* [[N_CASTED18]], align 8 -// CHECK9-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* -// CHECK9-NEXT: store i64 [[TMP64]], i64* [[TMP67]], align 8 -// CHECK9-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* -// CHECK9-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 -// CHECK9-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP70]], align 8 -// CHECK9-NEXT: [[TMP71:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP71]], align 8 -// CHECK9-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP73]], align 8 -// CHECK9-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP75]], align 8 -// CHECK9-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP76]], align 8 -// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP77]], align 8 -// CHECK9-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP79]], align 8 -// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 8 -// CHECK9-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP65]], i64* [[TMP82]], align 8 -// CHECK9-NEXT: [[TMP83:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP83]], align 8 -// CHECK9-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP87:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK9-NEXT: [[TMP88:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP88]], 0 -// CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 -// CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[DIV28]], 1 -// CHECK9-NEXT: store i32 [[SUB29]], i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK9-NEXT: [[TMP89:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK9-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP89]], 1 -// CHECK9-NEXT: [[TMP90:%.*]] = zext i32 [[ADD30]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP90]]) -// CHECK9-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP84]], i8** [[TMP85]], i64* [[TMP86]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0 -// CHECK9-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]] -// CHECK9: omp_offload.failed31: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP64]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]] -// CHECK9: omp_offload.cont32: -// CHECK9-NEXT: [[TMP93:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP93]]) -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[TMP94:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP94]]) -// CHECK9-NEXT: [[TMP95:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP95]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK9: omp.dispatch.cond: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK9: omp.dispatch.body: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK9: omp.dispatch.inc: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK9: omp.dispatch.end: -// CHECK9-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK9: omp_offload.failed5: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK9: omp_offload.cont6: -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK9-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK9: omp_offload.failed11: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK9: omp_offload.cont12: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK9: omp.dispatch.cond: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK9: omp.dispatch.body: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK9: omp.dispatch.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK9: omp.dispatch.end: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK10-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES23:%.*]] = alloca [3 x i64], align 8 -// CHECK10-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK10-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK10-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK10-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK10-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP60]]) -// CHECK10-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK10-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK10: omp_offload.failed16: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK10: omp_offload.cont17: -// CHECK10-NEXT: [[TMP63:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32* -// CHECK10-NEXT: store i32 [[TMP63]], i32* [[CONV19]], align 4 -// CHECK10-NEXT: [[TMP64:%.*]] = load i64, i64* [[N_CASTED18]], align 8 -// CHECK10-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* -// CHECK10-NEXT: store i64 [[TMP64]], i64* [[TMP67]], align 8 -// CHECK10-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* -// CHECK10-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 -// CHECK10-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP70]], align 8 -// CHECK10-NEXT: [[TMP71:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP71]], align 8 -// CHECK10-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP73]], align 8 -// CHECK10-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP75]], align 8 -// CHECK10-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP76]], align 8 -// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP77]], align 8 -// CHECK10-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP79]], align 8 -// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 8 -// CHECK10-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP65]], i64* [[TMP82]], align 8 -// CHECK10-NEXT: [[TMP83:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP83]], align 8 -// CHECK10-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP87:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK10-NEXT: [[TMP88:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP88]], 0 -// CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 -// CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[DIV28]], 1 -// CHECK10-NEXT: store i32 [[SUB29]], i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK10-NEXT: [[TMP89:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK10-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP89]], 1 -// CHECK10-NEXT: [[TMP90:%.*]] = zext i32 [[ADD30]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP90]]) -// CHECK10-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP84]], i8** [[TMP85]], i64* [[TMP86]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0 -// CHECK10-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]] -// CHECK10: omp_offload.failed31: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP64]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT32]] -// CHECK10: omp_offload.cont32: -// CHECK10-NEXT: [[TMP93:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP93]]) -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP94:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP94]]) -// CHECK10-NEXT: [[TMP95:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP95]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK10: omp.dispatch.cond: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK10: omp.dispatch.body: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK10: omp.dispatch.inc: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK10: omp.dispatch.end: -// CHECK10-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK10-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK10: omp_offload.failed5: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK10: omp_offload.cont6: -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK10-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK10: omp_offload.failed11: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK10: omp_offload.cont12: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK10: omp.dispatch.cond: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK10: omp.dispatch.body: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK10: omp.dispatch.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK10: omp.dispatch.end: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK11-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [3 x i64], align 4 -// CHECK11-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK11-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK11-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK11-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK11-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK11-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP61]]) -// CHECK11-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK11-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK11: omp_offload.failed15: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK11: omp_offload.cont16: -// CHECK11-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP64]], i32* [[N_CASTED17]], align 4 -// CHECK11-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_CASTED17]], align 4 -// CHECK11-NEXT: [[TMP66:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP67:%.*]] = sext i32 [[TMP66]] to i64 -// CHECK11-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32* -// CHECK11-NEXT: store i32 [[TMP65]], i32* [[TMP69]], align 4 -// CHECK11-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* -// CHECK11-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 -// CHECK11-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP72]], align 4 -// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP73]], align 4 -// CHECK11-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP75]], align 4 -// CHECK11-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP77]], align 4 -// CHECK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP78]], align 4 -// CHECK11-NEXT: [[TMP79:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP79]], align 4 -// CHECK11-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 4 -// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP83]], align 4 -// CHECK11-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP67]], i64* [[TMP84]], align 4 -// CHECK11-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP85]], align 4 -// CHECK11-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP88:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP89:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK11-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK11-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP90]], 0 -// CHECK11-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 -// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 -// CHECK11-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK11-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK11-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP91]], 1 -// CHECK11-NEXT: [[TMP92:%.*]] = zext i32 [[ADD28]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP92]]) -// CHECK11-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP86]], i8** [[TMP87]], i64* [[TMP88]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0 -// CHECK11-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] -// CHECK11: omp_offload.failed29: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP65]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT30]] -// CHECK11: omp_offload.cont30: -// CHECK11-NEXT: [[TMP95:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP95]]) -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP96:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP96]]) -// CHECK11-NEXT: [[TMP97:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP97]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK11: omp.dispatch.cond: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK11: omp.dispatch.body: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP20]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK11: omp.dispatch.inc: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK11: omp.dispatch.end: -// CHECK11-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK11-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK11: omp_offload.failed5: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK11: omp_offload.cont6: -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK11-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK11: omp_offload.failed11: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK11: omp_offload.cont12: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK11: omp.dispatch.cond: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK11: omp.dispatch.body: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK11: omp.dispatch.inc: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK11: omp.dispatch.end: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [3 x i64], align 4 -// CHECK12-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK12-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK12-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK12-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK12-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK12-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK12-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP61]]) -// CHECK12-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK12-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK12: omp_offload.failed15: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK12: omp_offload.cont16: -// CHECK12-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP64]], i32* [[N_CASTED17]], align 4 -// CHECK12-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_CASTED17]], align 4 -// CHECK12-NEXT: [[TMP66:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP67:%.*]] = sext i32 [[TMP66]] to i64 -// CHECK12-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32* -// CHECK12-NEXT: store i32 [[TMP65]], i32* [[TMP69]], align 4 -// CHECK12-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* -// CHECK12-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 -// CHECK12-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP72]], align 4 -// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP73]], align 4 -// CHECK12-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP75]], align 4 -// CHECK12-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP77]], align 4 -// CHECK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP78]], align 4 -// CHECK12-NEXT: [[TMP79:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP79]], align 4 -// CHECK12-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 4 -// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP83]], align 4 -// CHECK12-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP67]], i64* [[TMP84]], align 4 -// CHECK12-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP85]], align 4 -// CHECK12-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP88:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP89:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK12-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK12-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP90]], 0 -// CHECK12-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 -// CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 -// CHECK12-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK12-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK12-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP91]], 1 -// CHECK12-NEXT: [[TMP92:%.*]] = zext i32 [[ADD28]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP92]]) -// CHECK12-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP86]], i8** [[TMP87]], i64* [[TMP88]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0 -// CHECK12-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] -// CHECK12: omp_offload.failed29: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP65]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT30]] -// CHECK12: omp_offload.cont30: -// CHECK12-NEXT: [[TMP95:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP95]]) -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[TMP96:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP96]]) -// CHECK12-NEXT: [[TMP97:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP97]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK12: omp.dispatch.cond: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK12: omp.dispatch.body: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP20]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK12-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK12: omp_offload.failed5: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK12: omp_offload.cont6: -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK12-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK12: omp_offload.failed11: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK12: omp_offload.cont12: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK12: omp.dispatch.cond: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK12: omp.dispatch.body: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK12: omp.dispatch.inc: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK12: omp.dispatch.end: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP17]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP17]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: ret i32 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10) +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK8: omp.dispatch.cond: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK8: omp.dispatch.body: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK8: omp.dispatch.inc: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK8: omp.dispatch.end: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -3306,6 +3306,28 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: @@ -3344,142 +3366,6 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP13]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: @@ -3497,73 +3383,139 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 +// CHECK5-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK5-NEXT: ret void // // @@ -3576,6 +3528,13 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: @@ -3604,6 +3563,28 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: @@ -3642,142 +3623,6 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP13]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: @@ -3795,73 +3640,139 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK6-NEXT: ret i32 0 // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 +// CHECK6-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK6-NEXT: ret void // // @@ -3874,1368 +3785,9 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP13]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP13]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 -// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init() -// CHECK9-NEXT: call void @__cxx_global_var_init.1() -// CHECK9-NEXT: call void @__cxx_global_var_init.2() -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 -// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__cxx_global_var_init() -// CHECK10-NEXT: call void @__cxx_global_var_init.1() -// CHECK10-NEXT: call void @__cxx_global_var_init.2() -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp @@ -6,26 +6,26 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -795,16 +795,693 @@ // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK5-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done3: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP39]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK5-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK5-NEXT: store i32 [[TMP25]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP29]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done13: +// CHECK5-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8* +// CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) +// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK5-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done15: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP32]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK5-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK5-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP28]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done12: +// CHECK5-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done14: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -813,16 +1490,693 @@ // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK6-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done3: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP39]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK6-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK6-NEXT: store i32 [[TMP25]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP29]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done13: +// CHECK6-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8* +// CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK6-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done15: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK6-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP32]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK6-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK6-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP28]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done12: +// CHECK6-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done14: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main @@ -831,16 +2185,683 @@ // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK7-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP39]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK7-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP25]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP29]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done12: +// CHECK7-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8* +// CHECK7-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) +// CHECK7-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK7-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done14: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP32]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP14]] +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP16]] +// CHECK7-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK7-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP28]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done11: +// CHECK7-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* +// CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done13: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main @@ -849,3870 +2870,681 @@ // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP39]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK9-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i64 0, i64 [[IDXPROM9]] -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK9-NEXT: store i32 [[TMP25]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP29]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done13: -// CHECK9-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8* -// CHECK9-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) -// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK9-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done15: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP32]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM8]] -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK9-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK9-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP28]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done12: -// CHECK9-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done14: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK10-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP39]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK10-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i64 0, i64 [[IDXPROM9]] -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK10-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK10-NEXT: store i32 [[TMP25]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP29]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done13: -// CHECK10-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8* -// CHECK10-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) -// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK10-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done15: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP32]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM8]] -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK10-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK10-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP28]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done12: -// CHECK10-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done14: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP39]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]] -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]] -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK11-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: store i32 [[TMP25]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP29]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done12: -// CHECK11-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8* -// CHECK11-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) -// CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done14: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP32]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP14]] -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP16]] -// CHECK11-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK11-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP28]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done11: -// CHECK11-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK11-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done13: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK12-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP39]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]] -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]] -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK12-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: store i32 [[TMP25]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP29]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done12: -// CHECK12-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8* -// CHECK12-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) -// CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done14: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK12-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP32]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP14]] -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP16]] -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK12-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP28]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done11: -// CHECK12-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK12-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done13: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP13]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done4: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP13]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done3: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done3: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK8-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP39]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]] +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK8-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP25]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP29]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done12: +// CHECK8-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8* +// CHECK8-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) +// CHECK8-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK8-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done14: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK8-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP32]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP14]] +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP16]] +// CHECK8-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK8-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP28]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done11: +// CHECK8-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* +// CHECK8-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done13: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp @@ -10,12 +10,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 int a[100]; @@ -51,19 +51,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 int teams_local_arg(void) { @@ -84,19 +84,19 @@ #endif // CK2 // Test host codegen. -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK3 @@ -127,19 +127,19 @@ #endif // CK3 // Test host codegen. -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 @@ -2435,1427 +2435,2018 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK5-NEXT: ret i32 [[TMP33]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK5-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i64 0, i64 0), align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK6-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK6-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK6-NEXT: ret i32 [[TMP33]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK6-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] // CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i64 0, i64 0), align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK7-NEXT: ret i32 [[TMP33]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK7-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP3]] +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i32 0, i32 0), align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK8-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK8-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK8-NEXT: ret i32 [[TMP33]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK8-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP3]] +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] // CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i32 0, i32 0), align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) +// CHECK9-NEXT: ret i32 [[CALL]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** +// CHECK9-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** +// CHECK9-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 123) +// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK9-NEXT: ret i32 [[TMP33]] +// CHECK9-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: ret i32 [[TMP9]] // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 +// CHECK9-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: +// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 122, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9: cond.true: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9: cond.false: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: br label [[COND_END]] // CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: +// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK9-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 122 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9: cond.true: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9: cond.false: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: br label [[COND_END]] // CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) // CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK10-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK10-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) +// CHECK10-NEXT: ret i32 [[CALL]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** +// CHECK10-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** +// CHECK10-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 123) +// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK10-NEXT: ret i32 [[TMP33]] +// CHECK10-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: ret i32 [[TMP9]] // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 +// CHECK10-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: +// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 122, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10: cond.true: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: br label [[COND_END:%.*]] // CHECK10: cond.false: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: br label [[COND_END]] // CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: +// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK10-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 122 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10: cond.true: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: br label [[COND_END:%.*]] // CHECK10: cond.false: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: br label [[COND_END]] // CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK11-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK11-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) +// CHECK11-NEXT: ret i32 [[CALL]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** +// CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** +// CHECK11-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 123) +// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK11-NEXT: ret i32 [[TMP33]] +// CHECK11-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: ret i32 [[TMP9]] // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 +// CHECK11-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: +// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 122, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK11: cond.true: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK11-NEXT: br label [[COND_END:%.*]] // CHECK11: cond.false: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: br label [[COND_END]] // CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: +// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 122 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK11: cond.true: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK11-NEXT: br label [[COND_END:%.*]] // CHECK11: cond.false: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: br label [[COND_END]] // CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) // CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_Z15teams_local_argv +// CHECK12-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK12-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) +// CHECK12-NEXT: ret i32 [[CALL]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv +// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** +// CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** +// CHECK12-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 123) +// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK12-NEXT: ret i32 [[TMP33]] +// CHECK12-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: ret i32 [[TMP9]] // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 +// CHECK12-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: +// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 122, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK12: cond.true: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK12-NEXT: br label [[COND_END:%.*]] // CHECK12: cond.false: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: br label [[COND_END]] // CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] // CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: +// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 122 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK12: cond.true: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK12-NEXT: br label [[COND_END:%.*]] // CHECK12: cond.false: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: br label [[COND_END]] // CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK13-LABEL: define {{[^@]+}}@main +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: +// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store i32 100, i32* [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 @@ -3863,39 +4454,532 @@ // CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK13-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK13-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK13-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK13-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK13-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK13-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK13-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK13-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK13-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK13-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK13-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK13-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK13-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK13-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK13-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK13-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK13-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK13-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK13-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK13-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK13-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK13-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK13-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK13: omp_offload.failed: +// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK13: omp_offload.cont: +// CHECK13-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) +// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK13-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK13-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK13-NEXT: ret i32 [[TMP35]] +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK13: omp.precond.then: +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK13-NEXT: br label [[OMP_PRECOND_END]] +// CHECK13: omp.precond.end: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK13: omp.precond.then: +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK13-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK13-NEXT: ret i32 [[TMP7]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK13-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK13-NEXT: br label [[OMP_PRECOND_END]] +// CHECK13: omp.precond.end: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK13-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TE_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TH_CASTED:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[TE]], align 4 +// CHECK13-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[TE_CASTED]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_CASTED]] to i32* +// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[TH_CASTED]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK13-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK13-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 +// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK13-NEXT: store i8* null, i8** [[TMP8]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK13-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK13-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK13-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK13-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK13-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** +// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 8 +// CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK13-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** +// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 8 +// CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK13-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK13-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 0) +// CHECK13-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK13-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK13: omp_offload.failed: +// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK13: omp_offload.cont: +// CHECK13-NEXT: ret i32 0 +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 +// CHECK13-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) +// CHECK13-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 +// CHECK13-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* +// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* +// CHECK13-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK13-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK13-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@main +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: +// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 // CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 // CHECK14-NEXT: store i32 100, i32* [[N]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 // CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 @@ -3903,3470 +4987,1542 @@ // CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK14-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK14-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK14-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK14-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK14-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK14-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK14-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK14-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK14-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK14-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK14-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK14-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK14-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK14-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK14-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK14-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK14-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK14-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK14-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK14-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK14-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK14-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK14-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK14-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK14-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK14-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK14-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK14: omp_offload.failed: +// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK14: omp_offload.cont: +// CHECK14-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) +// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK14-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK14-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK14-NEXT: ret i32 [[TMP35]] +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK14: omp.precond.then: +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK14-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK14-NEXT: br label [[OMP_PRECOND_END]] +// CHECK14: omp.precond.end: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK14: omp.precond.then: +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK14-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK14-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] // CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK14-NEXT: ret i32 [[TMP7]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK14-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK14-NEXT: br label [[OMP_PRECOND_END]] +// CHECK14: omp.precond.end: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK14-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TE_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TH_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[TE]], align 4 +// CHECK14-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[TE_CASTED]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[TH_CASTED]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK14-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK14-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK14-NEXT: store i8* null, i8** [[TMP8]], align 8 +// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK14-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK14-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK14-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK14-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK14-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK14-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** +// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 8 +// CHECK14-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK14-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** +// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 8 +// CHECK14-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK14-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK14-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK14-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 0) +// CHECK14-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK14-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK14: omp_offload.failed: +// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK14: omp_offload.cont: +// CHECK14-NEXT: ret i32 0 +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 +// CHECK14-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) +// CHECK14-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK14-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK14-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK14-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@main +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: +// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store i32 100, i32* [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() // CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK15-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK15-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK15-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK15-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK15-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK15-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK15-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK15-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK15-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK15-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK15-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK15-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK15-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK15-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK15-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK15-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK15-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK15-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK15-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK15-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK15-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK15: omp_offload.failed: +// CHECK15-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK15: omp_offload.cont: +// CHECK15-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) +// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK15-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK15-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK15-NEXT: ret i32 [[TMP35]] +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK15-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK15-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK15: omp.precond.then: +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK15-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK15-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK15-NEXT: br label [[OMP_PRECOND_END]] +// CHECK15: omp.precond.end: +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK15-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK15-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK15: omp.precond.then: +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK15-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK15-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK15-NEXT: br label [[OMP_PRECOND_END]] +// CHECK15: omp.precond.end: +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK15-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TE_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TH_CASTED:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[TE]], align 4 +// CHECK15-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], i32* [[TE_CASTED]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE_CASTED]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK15-NEXT: store i32 [[TMP2]], i32* [[TH_CASTED]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_CASTED]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK15-NEXT: store i8* null, i8** [[TMP8]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK15-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** +// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 4 +// CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** +// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 4 +// CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK15-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK15-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 0) +// CHECK15-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK15-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK15: omp_offload.failed: +// CHECK15-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK15: omp_offload.cont: +// CHECK15-NEXT: ret i32 0 +// +// +// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 +// CHECK15-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) +// CHECK15-NEXT: store i32 [[TE]], i32* [[TE_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TH]], i32* [[TH_ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TE_ADDR]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_ADDR]], align 4 +// CHECK15-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK15-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK15: cond.true: +// CHECK15-NEXT: br label [[COND_END:%.*]] +// CHECK15: cond.false: +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: br label [[COND_END]] +// CHECK15: cond.end: +// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK15-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK15: omp.loop.exit: +// CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK15-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK15-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@main +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: +// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 // CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 // CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 // CHECK16-NEXT: store i32 100, i32* [[N]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() // CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK16-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK16-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK16-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK16-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK16-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK16-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK16-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK16-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK16-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK16-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK16-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK16-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK16-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK16-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK16-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK16-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK16-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK16-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK16-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK16-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK16-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK16-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK16-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK16: omp_offload.failed: +// CHECK16-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK16-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK16: omp_offload.cont: +// CHECK16-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) +// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK16-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) +// CHECK16-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK16-NEXT: ret i32 [[TMP35]] +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK16-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK16-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK16: omp.precond.then: +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK16-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK16-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK16-NEXT: br label [[OMP_PRECOND_END]] +// CHECK16: omp.precond.end: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK16-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK16-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK16: omp.precond.then: +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK16-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK16-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] // CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK17-NEXT: ret i32 [[CALL]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK17-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** -// CHECK17-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** -// CHECK17-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 123) -// CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK17-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: ret i32 [[TMP9]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK17-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 122, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 122 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK18-NEXT: ret i32 [[CALL]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK18-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** -// CHECK18-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** -// CHECK18-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 123) -// CHECK18-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK18-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: ret i32 [[TMP9]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK18-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 122, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 122 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK19-NEXT: ret i32 [[CALL]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK19-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** -// CHECK19-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** -// CHECK19-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 123) -// CHECK19-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK19-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: ret i32 [[TMP9]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK19-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 122, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 122 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK20-NEXT: ret i32 [[CALL]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK20-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** -// CHECK20-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]** -// CHECK20-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 123) -// CHECK20-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK20-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: ret i32 [[TMP9]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK20-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 122, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 122 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK21-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK22-NEXT: ret i32 [[CALL]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK22-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK23-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK23-NEXT: ret i32 [[CALL]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK23-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK24-NEXT: ret i32 [[CALL]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK24-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@main -// CHECK25-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK25-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK25-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK25-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK25-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK25-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK25-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK25-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK25-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK25-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK25-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK25-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK25-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK25-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK25-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK25-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK25-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK25-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK25-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK25-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK25-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK25-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK25-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK25-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK25-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK25-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK25-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK25-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK25-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK25-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK25-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK25-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK25-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK25-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK25-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK25-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK25-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK25-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK25-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK25-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK25-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK25-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK25-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK25-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK25: omp_offload.failed: -// CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK25: omp_offload.cont: -// CHECK25-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) -// CHECK25-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK25-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK25-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK25-NEXT: ret i32 [[TMP35]] -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK25-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK25-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK25-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK25-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK25: omp.precond.then: -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK25-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK25-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK25-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK25-NEXT: br label [[OMP_PRECOND_END]] -// CHECK25: omp.precond.end: -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK25-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK25-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK25-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK25-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK25: omp.precond.then: -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK25-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK25-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK25-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK25-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK25-NEXT: br label [[OMP_PRECOND_END]] -// CHECK25: omp.precond.end: -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK25-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK25-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TE_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TH_CASTED:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK25-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[TE_CASTED]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_CASTED]] to i32* -// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[TH_CASTED]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK25-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK25-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK25-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 -// CHECK25-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK25-NEXT: store i8* null, i8** [[TMP8]], align 8 -// CHECK25-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK25-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK25-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK25-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK25-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK25-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK25-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK25-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK25-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 8 -// CHECK25-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK25-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 8 -// CHECK25-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK25-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK25-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK25-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK25-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 0) -// CHECK25-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK25-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK25: omp_offload.failed: -// CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK25: omp_offload.cont: -// CHECK25-NEXT: ret i32 0 -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK25-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) -// CHECK25-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* -// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* -// CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK25-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK25-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK25-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK25: omp.body.continue: -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK25-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK25-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK25-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@main -// CHECK26-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK26-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK26-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK26-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK26-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK26-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK26-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK26-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK26-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK26-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK26-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK26-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK26-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK26-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK26-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK26-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK26-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK26-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK26-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK26-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK26-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK26-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK26-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK26-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK26-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK26-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK26-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK26-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK26-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK26-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK26-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK26-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK26-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK26-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK26-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK26-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK26-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK26-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK26-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK26-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK26-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK26-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK26-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK26-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK26-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK26: omp_offload.failed: -// CHECK26-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK26-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK26: omp_offload.cont: -// CHECK26-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) -// CHECK26-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK26-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK26-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK26-NEXT: ret i32 [[TMP35]] -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK26-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK26-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK26-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK26-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK26: omp.precond.then: -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK26-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK26-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK26-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK26-NEXT: br label [[OMP_PRECOND_END]] -// CHECK26: omp.precond.end: -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK26-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK26-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK26-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK26-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK26: omp.precond.then: -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK26-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK26-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK26-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK26-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK26-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK26-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK26-NEXT: br label [[OMP_PRECOND_END]] -// CHECK26: omp.precond.end: -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK26-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK26-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TE_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TH_CASTED:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK26-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[TE_CASTED]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_CASTED]] to i32* -// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[TH_CASTED]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK26-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK26-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK26-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 -// CHECK26-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK26-NEXT: store i8* null, i8** [[TMP8]], align 8 -// CHECK26-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK26-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK26-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK26-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK26-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK26-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK26-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK26-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK26-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 8 -// CHECK26-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK26-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 8 -// CHECK26-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK26-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK26-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK26-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK26-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 0) -// CHECK26-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK26-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK26: omp_offload.failed: -// CHECK26-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK26-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK26: omp_offload.cont: -// CHECK26-NEXT: ret i32 0 -// -// -// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK26-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) -// CHECK26-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 -// CHECK26-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* -// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* -// CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK26-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK26-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK26-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK26-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK26-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK26-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK26-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK26-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK26: cond.true: -// CHECK26-NEXT: br label [[COND_END:%.*]] -// CHECK26: cond.false: -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: br label [[COND_END]] -// CHECK26: cond.end: -// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK26-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK26-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK26-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK26: omp.body.continue: -// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK26-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK26: omp.inner.for.end: -// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK26: omp.loop.exit: -// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK26-NEXT: ret void -// -// -// CHECK26-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK26-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK26-NEXT: entry: -// CHECK26-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK26-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@main -// CHECK27-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK27-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK27-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK27-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK27-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK27-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK27-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK27-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK27-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK27-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK27-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK27-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK27-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK27-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK27-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK27-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK27-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK27-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK27-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK27-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK27-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK27-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK27-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK27-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK27-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK27-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK27-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK27-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK27-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK27-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK27-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK27-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK27-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK27-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK27-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK27-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK27-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK27: omp_offload.failed: -// CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK27: omp_offload.cont: -// CHECK27-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) -// CHECK27-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK27-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK27-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK27-NEXT: ret i32 [[TMP35]] -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK27-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK27-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK27-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK27-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK27: omp.precond.then: -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK27-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK27-NEXT: br label [[OMP_PRECOND_END]] -// CHECK27: omp.precond.end: -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK27-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK27-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK27-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK27: omp.precond.then: -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK27-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK27-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK27-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK27-NEXT: br label [[OMP_PRECOND_END]] -// CHECK27: omp.precond.end: -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK27-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK27-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TE_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TH_CASTED:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK27-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK27-NEXT: store i32 [[TMP0]], i32* [[TE_CASTED]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE_CASTED]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK27-NEXT: store i32 [[TMP2]], i32* [[TH_CASTED]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_CASTED]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK27-NEXT: store i8* null, i8** [[TMP8]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK27-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK27-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK27-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK27-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK27-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK27-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK27-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 4 -// CHECK27-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK27-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK27-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 4 -// CHECK27-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK27-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK27-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK27-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 0) -// CHECK27-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK27-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK27: omp_offload.failed: -// CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK27: omp_offload.cont: -// CHECK27-NEXT: ret i32 0 -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK27-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) -// CHECK27-NEXT: store i32 [[TE]], i32* [[TE_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TH]], i32* [[TH_ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TE_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK27-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK27-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK27-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK27: omp.body.continue: -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK27-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK27-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@main -// CHECK28-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK28-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK28-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK28-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK28-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK28-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK28-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK28-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK28-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK28-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK28-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK28-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK28-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK28-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK28-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK28-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK28-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK28-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK28-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK28-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK28-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK28-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK28-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK28-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK28-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK28-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK28-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK28-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK28-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK28-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK28-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK28-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK28-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK28-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK28-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK28-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK28-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK28: omp_offload.failed: -// CHECK28-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK28-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK28: omp_offload.cont: -// CHECK28-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) -// CHECK28-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK28-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) -// CHECK28-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK28-NEXT: ret i32 [[TMP35]] -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK28-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK28-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK28-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK28-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK28: omp.precond.then: -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK28-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK28-NEXT: br label [[OMP_PRECOND_END]] -// CHECK28: omp.precond.end: -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK28-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK28-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK28-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK28: omp.precond.then: -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK28-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK28-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK28-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK28-NEXT: br label [[OMP_PRECOND_END]] -// CHECK28: omp.precond.end: -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK28-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK28-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TE_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TH_CASTED:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK28-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK28-NEXT: store i32 [[TMP0]], i32* [[TE_CASTED]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE_CASTED]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK28-NEXT: store i32 [[TMP2]], i32* [[TH_CASTED]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_CASTED]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -// CHECK28-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 -// CHECK28-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK28-NEXT: store i8* null, i8** [[TMP8]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK28-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK28-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK28-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK28-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK28-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK28-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK28-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 4 -// CHECK28-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK28-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK28-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 4 -// CHECK28-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK28-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK28-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK28-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 0) -// CHECK28-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK28-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK28: omp_offload.failed: -// CHECK28-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK28-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK28: omp_offload.cont: -// CHECK28-NEXT: ret i32 0 -// -// -// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK28-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) -// CHECK28-NEXT: store i32 [[TE]], i32* [[TE_ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TH]], i32* [[TH_ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TE_ADDR]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_ADDR]], align 4 -// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK28-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK28-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK28-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK28-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK28: cond.true: -// CHECK28-NEXT: br label [[COND_END:%.*]] -// CHECK28: cond.false: -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: br label [[COND_END]] -// CHECK28: cond.end: -// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK28-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK28-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK28: omp.body.continue: -// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK28-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK28: omp.inner.for.end: -// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK28: omp.loop.exit: -// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK28-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK28-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK28-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@main -// CHECK29-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK29-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK29-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK29-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP7]]) -// CHECK29-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK29-NEXT: ret i32 [[TMP9]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK29-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK29-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK29-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: ret i32 0 -// -// -// CHECK30-LABEL: define {{[^@]+}}@main -// CHECK30-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK30-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK30-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK30-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP7]]) -// CHECK30-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK30-NEXT: ret i32 [[TMP9]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK30-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK30-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK30-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: ret i32 0 -// -// -// CHECK31-LABEL: define {{[^@]+}}@main -// CHECK31-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK31-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK31-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK31-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP6]]) -// CHECK31-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK31-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK31-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK31-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK31-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: ret i32 0 -// -// -// CHECK32-LABEL: define {{[^@]+}}@main -// CHECK32-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK32-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK32-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK32-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP6]]) -// CHECK32-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK32-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK32-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK32-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK32-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: ret i32 0 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK16-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK16-NEXT: br label [[OMP_PRECOND_END]] +// CHECK16: omp.precond.end: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK16-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TE_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TH_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[TE]], align 4 +// CHECK16-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[TE_CASTED]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE_CASTED]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK16-NEXT: store i32 [[TMP2]], i32* [[TH_CASTED]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK16-NEXT: store i8* null, i8** [[TMP8]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK16-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK16-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** +// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP15]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK16-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** +// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP17]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK16-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK16-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151.region_id, i32 3, i8** [[TMP19]], i8** [[TMP20]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 [[TMP21]], i32 0) +// CHECK16-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK16-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK16: omp_offload.failed: +// CHECK16-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK16-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK16: omp_offload.cont: +// CHECK16-NEXT: ret i32 0 +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 +// CHECK16-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) +// CHECK16-NEXT: store i32 [[TE]], i32* [[TE_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TH]], i32* [[TH_ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TE_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TH_ADDR]], align 4 +// CHECK16-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK16-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK16-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK16-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -48,19 +48,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -966,3208 +966,2500 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK5-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK5-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() +// CHECK5-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK5-NEXT: store i64 4, i64* [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK5-NEXT: store i64 8, i64* [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK5-NEXT: store i64 8, i64* [[TMP34]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP35]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK5-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 +// CHECK5-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK5-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 +// CHECK5-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK5-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] +// CHECK5-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK5-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK5-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK5-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 +// CHECK5-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) +// CHECK5-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP54]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK5-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK5-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK5-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK5-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[J]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: land.lhs.true: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK5-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK5-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP22]], i32* [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]] +// CHECK5-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK5-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK5-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK5-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK5-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body: // CHECK5-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: land.lhs.true: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK5-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK5-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] +// CHECK5-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK5-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK5-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK5-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK5-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// CHECK5-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// CHECK5-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP23]], [[CONV18]] +// CHECK5-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// CHECK5-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK5-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0 +// CHECK5-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// CHECK5-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// CHECK5-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// CHECK5-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]] +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK5-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK5-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK5-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// CHECK5-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// CHECK5-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// CHECK5-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP25]], [[MUL31]] +// CHECK5-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// CHECK5-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// CHECK5-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// CHECK5-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[I11]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK5-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP30]] +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[J12]], align 4 +// CHECK5-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 +// CHECK5-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1 +// CHECK5-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK5-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) +// CHECK5-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK5-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 +// CHECK5-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 +// CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] +// CHECK5-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 +// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK6-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK6-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() +// CHECK6-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] +// CHECK6-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK6-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK6-NEXT: store i64 4, i64* [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK6-NEXT: store i64 8, i64* [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK6-NEXT: store i64 8, i64* [[TMP34]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP35]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK6-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 +// CHECK6-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK6-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 +// CHECK6-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK6-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] +// CHECK6-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK6-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK6-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK6-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 +// CHECK6-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) +// CHECK6-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP54]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK6-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK6-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK6-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK6-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body: // CHECK6-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: land.lhs.true: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK6-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK6-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK6-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP22]], i32* [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]] +// CHECK6-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK6-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK6-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK6-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK6-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[J]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: land.lhs.true: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK6-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK6-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK6-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK6-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK6-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK6-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// CHECK6-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// CHECK6-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP23]], [[CONV18]] +// CHECK6-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// CHECK6-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK6-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0 +// CHECK6-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// CHECK6-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// CHECK6-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// CHECK6-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]] +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK6-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK6-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK6-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// CHECK6-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// CHECK6-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// CHECK6-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP25]], [[MUL31]] +// CHECK6-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// CHECK6-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// CHECK6-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// CHECK6-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[I11]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK6-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP30]] +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[J12]], align 4 +// CHECK6-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 +// CHECK6-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1 +// CHECK6-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK6-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) +// CHECK6-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK6-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 +// CHECK6-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 +// CHECK6-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] +// CHECK6-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 +// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@main +// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK7-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK7-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 +// CHECK7-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK7-NEXT: store i64 4, i64* [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK7-NEXT: store i64 4, i64* [[TMP33]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 +// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 +// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK7-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 +// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK7-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 +// CHECK7-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] +// CHECK7-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK7-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 +// CHECK7-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) +// CHECK7-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP53]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK7-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK7-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body: // CHECK7-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: land.lhs.true: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK7-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 +// CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK7-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP24]], i32* [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] +// CHECK7-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J14:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK7-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK7-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK7-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[J]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: land.lhs.true: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[CONV11:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: [[CONV12:%.*]] = zext i32 [[TMP13]] to i64 +// CHECK7-NEXT: store i64 [[CONV11]], i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[CONV12]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK7-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK7-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] +// CHECK7-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK7-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 +// CHECK7-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] +// CHECK7-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 +// CHECK7-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP23]], [[CONV20]] +// CHECK7-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] +// CHECK7-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK7-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0 +// CHECK7-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 +// CHECK7-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] +// CHECK7-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 +// CHECK7-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]] +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK7-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK7-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK7-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] +// CHECK7-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 +// CHECK7-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] +// CHECK7-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP25]], [[MUL33]] +// CHECK7-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 +// CHECK7-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] +// CHECK7-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK7-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[I13]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP30]] +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[J14]], align 4 +// CHECK7-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP31]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1 +// CHECK7-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK7-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 +// CHECK7-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(224352) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 +// CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] +// CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@main +// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK8-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 2, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] +// CHECK8-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 +// CHECK8-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK8-NEXT: store i64 4, i64* [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK8-NEXT: store i64 4, i64* [[TMP33]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 +// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 +// CHECK8-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK8-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 +// CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK8-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 +// CHECK8-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 +// CHECK8-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] +// CHECK8-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) +// CHECK8-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 +// CHECK8-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) +// CHECK8-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP53]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK8-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK8-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK8-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body: // CHECK8-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK9-NEXT: store i64 4, i64* [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK9-NEXT: store i64 8, i64* [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK9-NEXT: store i64 8, i64* [[TMP34]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 -// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 -// CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] -// CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK9-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK9-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 -// CHECK9-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) -// CHECK9-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP54]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: land.lhs.true: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP22]], i32* [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]] -// CHECK9-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: land.lhs.true: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0 -// CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 -// CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] -// CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 -// CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP23]], [[CONV18]] -// CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] -// CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0 -// CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 -// CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] -// CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 -// CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]] -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 -// CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] -// CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 -// CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] -// CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP25]], [[MUL31]] -// CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 -// CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] -// CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK9-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP30]] -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[J12]], align 4 -// CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK9-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1 -// CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 -// CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] -// CHECK9-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 -// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK10-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK10-NEXT: store i64 4, i64* [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK10-NEXT: store i64 8, i64* [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 -// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK10-NEXT: store i64 8, i64* [[TMP34]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK10-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 -// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 -// CHECK10-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 -// CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] -// CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK10-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK10-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 -// CHECK10-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) -// CHECK10-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP54]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: land.lhs.true: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP22]], i32* [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]] -// CHECK10-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: land.lhs.true: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_LB]], align 8 -// CHECK10-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] -// CHECK10-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK10-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0 -// CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 -// CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] -// CHECK10-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 -// CHECK10-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP23]], [[CONV18]] -// CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] -// CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0 -// CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 -// CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] -// CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 -// CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]] -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 -// CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] -// CHECK10-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 -// CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] -// CHECK10-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP25]], [[MUL31]] -// CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 -// CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] -// CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK10-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP30]] -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[J12]], align 4 -// CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK10-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1 -// CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 -// CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] -// CHECK10-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 -// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 -// CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK11-NEXT: store i64 4, i64* [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK11-NEXT: store i64 4, i64* [[TMP33]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP34]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 -// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 -// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 -// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 -// CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] -// CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK11-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 -// CHECK11-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) -// CHECK11-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP53]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: land.lhs.true: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK11-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP24]], i32* [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] -// CHECK11-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: land.lhs.true: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[CONV11:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: [[CONV12:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK11-NEXT: store i64 [[CONV11]], i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: store i64 [[CONV12]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] -// CHECK11-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0 -// CHECK11-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 -// CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] -// CHECK11-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 -// CHECK11-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP23]], [[CONV20]] -// CHECK11-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] -// CHECK11-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK11-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0 -// CHECK11-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 -// CHECK11-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] -// CHECK11-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 -// CHECK11-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]] -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK11-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] -// CHECK11-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 -// CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] -// CHECK11-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP25]], [[MUL33]] -// CHECK11-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 -// CHECK11-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] -// CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK11-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[I13]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP30]] -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[J14]], align 4 -// CHECK11-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP31]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1 -// CHECK11-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) -// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 -// CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] -// CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 -// CHECK12-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK12-NEXT: store i64 4, i64* [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK12-NEXT: store i64 4, i64* [[TMP33]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP34]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 -// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 -// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK12-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 -// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 -// CHECK12-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 -// CHECK12-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] -// CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]]) -// CHECK12-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 -// CHECK12-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) -// CHECK12-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP53]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: land.lhs.true: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 -// CHECK12-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 -// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 -// CHECK12-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP24]], i32* [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] -// CHECK12-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: land.lhs.true: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[CONV11:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: [[CONV12:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK12-NEXT: store i64 [[CONV11]], i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: store i64 [[CONV12]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK12-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK12-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] -// CHECK12-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0 -// CHECK12-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 -// CHECK12-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] -// CHECK12-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 -// CHECK12-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP23]], [[CONV20]] -// CHECK12-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] -// CHECK12-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK12-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0 -// CHECK12-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 -// CHECK12-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] -// CHECK12-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 -// CHECK12-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]] -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK12-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK12-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] -// CHECK12-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 -// CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] -// CHECK12-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP25]], [[MUL33]] -// CHECK12-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 -// CHECK12-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] -// CHECK12-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK12-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[I13]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]] -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP30]] -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[J14]], align 4 -// CHECK12-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP31]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1 -// CHECK12-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) -// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 -// CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] -// CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP17]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP17]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP15]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP15]] +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: land.lhs.true: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] +// CHECK8-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK8-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 +// CHECK8-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK8-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP24]], i32* [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] +// CHECK8-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J14:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 +// CHECK8-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK8-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// CHECK8-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK8-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[J]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: land.lhs.true: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[CONV11:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: [[CONV12:%.*]] = zext i32 [[TMP13]] to i64 +// CHECK8-NEXT: store i64 [[CONV11]], i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[CONV12]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK8-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK8-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] +// CHECK8-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK8-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 +// CHECK8-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] +// CHECK8-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 +// CHECK8-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP23]], [[CONV20]] +// CHECK8-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] +// CHECK8-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK8-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0 +// CHECK8-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 +// CHECK8-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] +// CHECK8-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 +// CHECK8-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]] +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK8-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK8-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 +// CHECK8-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] +// CHECK8-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 +// CHECK8-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] +// CHECK8-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP25]], [[MUL33]] +// CHECK8-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 +// CHECK8-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] +// CHECK8-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK8-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[I13]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP30]] +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[J14]], align 4 +// CHECK8-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP31]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1 +// CHECK8-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ +// CHECK8-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 +// CHECK8-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) +// CHECK8-NEXT: ret void // // -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret i32 0 +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 +// CHECK8-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] +// CHECK8-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 +// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1745,56 +1745,192 @@ // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[TMP0]], align 8 +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46 +// CHECK5-SAME: (i64 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: store i64 [[X]], i64* [[X_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[X_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[X_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]], [2 x i32]* [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[X_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store [2 x i32]* [[TMP0]], [2 x i32]** [[TMP14]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK5-NEXT: store i32* [[I]], i32** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK5-NEXT: store i32* [[TMP1]], i32** [[TMP16]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZTW1x +// CHECK5-SAME: () #[[ATTR4:[0-9]+]] comdat { +// CHECK5-NEXT: ret i32* @x +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -1802,576 +1938,190 @@ // CHECK6-NEXT: entry: // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[TMP0]], align 8 +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[TMP0]], align 8 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46 -// CHECK9-SAME: (i64 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: store i64 [[X]], i64* [[X_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[X_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[X_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]], [2 x i32]* [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[X_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP3]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store [2 x i32]* [[TMP0]], [2 x i32]** [[TMP14]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: store i32* [[I]], i32** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[TMP1]], i32** [[TMP16]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZTW1x -// CHECK9-SAME: () #[[ATTR4:[0-9]+]] comdat { -// CHECK9-NEXT: ret i32* @x -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[TMP0]], align 8 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46 -// CHECK10-SAME: (i64 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: store i64 [[X]], i64* [[X_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[X_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[X_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]], [2 x i32]* [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[X_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP3]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store [2 x i32]* [[TMP0]], [2 x i32]** [[TMP14]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: store i32* [[I]], i32** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[TMP1]], i32** [[TMP16]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZTW1x -// CHECK10-SAME: () #[[ATTR4:[0-9]+]] comdat { -// CHECK10-NEXT: ret i32* @x -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[TMP0]], align 8 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK12-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[TMP0]], align 8 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46 +// CHECK6-SAME: (i64 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: store i64 [[X]], i64* [[X_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[X_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]], [2 x i32]* [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store [2 x i32]* [[TMP0]], [2 x i32]** [[TMP14]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK6-NEXT: store i32* [[I]], i32** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK6-NEXT: store i32* [[TMP1]], i32** [[TMP16]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZTW1x +// CHECK6-SAME: () #[[ATTR4:[0-9]+]] comdat { +// CHECK6-NEXT: ret i32* @x +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -62,19 +62,19 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -2389,6906 +2389,5950 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK5-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_SIZES24:%.*]] = alloca [4 x i64], align 8 +// CHECK5-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK5-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK5-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK5-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK5-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK5-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK5-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK5-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK5-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK5-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK5-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK5-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK5-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK5-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) +// CHECK5-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK5-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK5: omp_offload.failed16: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK5: omp_offload.cont17: +// CHECK5-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP63]], i32* [[CONV18]], align 4 +// CHECK5-NEXT: [[TMP64:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK5-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* +// CHECK5-NEXT: store i32 [[TMP65]], i32* [[CONV20]], align 4 +// CHECK5-NEXT: [[TMP66:%.*]] = load i64, i64* [[N_CASTED19]], align 8 +// CHECK5-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK5-NEXT: [[TMP68:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* +// CHECK5-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 +// CHECK5-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* +// CHECK5-NEXT: store i64 [[TMP64]], i64* [[TMP71]], align 8 +// CHECK5-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 +// CHECK5-NEXT: store i64 4, i64* [[TMP72]], align 8 +// CHECK5-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP73]], align 8 +// CHECK5-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* +// CHECK5-NEXT: store i64 [[TMP66]], i64* [[TMP75]], align 8 +// CHECK5-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* +// CHECK5-NEXT: store i64 [[TMP66]], i64* [[TMP77]], align 8 +// CHECK5-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 1 +// CHECK5-NEXT: store i64 4, i64* [[TMP78]], align 8 +// CHECK5-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK5-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP81]], align 8 +// CHECK5-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP83]], align 8 +// CHECK5-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 2 +// CHECK5-NEXT: store i64 8, i64* [[TMP84]], align 8 +// CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP85]], align 8 +// CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP87]], align 8 +// CHECK5-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK5-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 8 +// CHECK5-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 3 +// CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 +// CHECK5-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP91]], align 8 +// CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP95:%.*]] = load i32, i32* [[N]], align 4 +// CHECK5-NEXT: store i32 [[TMP95]], i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK5-NEXT: [[TMP96:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK5-NEXT: [[SUB28:%.*]] = sub nsw i32 [[TMP96]], 0 +// CHECK5-NEXT: [[DIV29:%.*]] = sdiv i32 [[SUB28]], 1 +// CHECK5-NEXT: [[SUB30:%.*]] = sub nsw i32 [[DIV29]], 1 +// CHECK5-NEXT: store i32 [[SUB30]], i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK5-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK5-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP97]], 1 +// CHECK5-NEXT: [[TMP98:%.*]] = zext i32 [[ADD31]] to i64 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP98]]) +// CHECK5-NEXT: [[TMP99:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 4, i8** [[TMP92]], i8** [[TMP93]], i64* [[TMP94]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP100:%.*]] = icmp ne i32 [[TMP99]], 0 +// CHECK5-NEXT: br i1 [[TMP100]], label [[OMP_OFFLOAD_FAILED32:%.*]], label [[OMP_OFFLOAD_CONT33:%.*]] +// CHECK5: omp_offload.failed32: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP64]], i64 [[TMP66]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT33]] +// CHECK5: omp_offload.cont33: +// CHECK5-NEXT: [[TMP101:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP101]]) +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[TMP102:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP102]]) +// CHECK5-NEXT: [[TMP103:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP103]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 +// CHECK5-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 +// CHECK5-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] +// CHECK5-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] +// CHECK5: cond.true12: +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: br label [[COND_END14:%.*]] +// CHECK5: cond.false13: +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END14]] +// CHECK5: cond.end14: +// CHECK5-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE12]] ], [ [[TMP32]], [[COND_FALSE13]] ] +// CHECK5-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK5-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK5-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK5-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK5-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK5-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK5: omp_offload.failed5: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK5: omp_offload.cont6: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP18]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK5-NEXT: store i64 [[TMP19]], i64* [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK5-NEXT: store i64 [[TMP19]], i64* [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK5-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK5-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK5: omp_offload.failed11: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94(i64 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK5: omp_offload.cont12: +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3:%.*]] -// CHECK5: for.cond3: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK5: for.body5: -// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK5-NEXT: br label [[FOR_INC9:%.*]] -// CHECK5: for.inc9: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end11: -// CHECK5-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13:%.*]] -// CHECK5: for.cond13: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK5-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK5: for.body15: -// CHECK5-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK5-NEXT: br label [[FOR_INC19:%.*]] -// CHECK5: for.inc19: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end21: -// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 +// CHECK5-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 +// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK5: cond.true6: +// CHECK5-NEXT: br label [[COND_END8:%.*]] +// CHECK5: cond.false7: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END8]] +// CHECK5: cond.end8: +// CHECK5-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] +// CHECK5-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK6-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_SIZES24:%.*]] = alloca [4 x i64], align 8 +// CHECK6-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK6-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK6-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK6-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK6-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK6-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK6-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK6-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK6-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK6-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK6-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK6-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK6-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK6-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK6-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK6-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK6-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK6-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK6-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK6-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK6-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK6-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) +// CHECK6-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK6-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK6: omp_offload.failed16: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK6: omp_offload.cont17: +// CHECK6-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP63]], i32* [[CONV18]], align 4 +// CHECK6-NEXT: [[TMP64:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK6-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* +// CHECK6-NEXT: store i32 [[TMP65]], i32* [[CONV20]], align 4 +// CHECK6-NEXT: [[TMP66:%.*]] = load i64, i64* [[N_CASTED19]], align 8 +// CHECK6-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK6-NEXT: [[TMP68:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* +// CHECK6-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 +// CHECK6-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* +// CHECK6-NEXT: store i64 [[TMP64]], i64* [[TMP71]], align 8 +// CHECK6-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 +// CHECK6-NEXT: store i64 4, i64* [[TMP72]], align 8 +// CHECK6-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP73]], align 8 +// CHECK6-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* +// CHECK6-NEXT: store i64 [[TMP66]], i64* [[TMP75]], align 8 +// CHECK6-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* +// CHECK6-NEXT: store i64 [[TMP66]], i64* [[TMP77]], align 8 +// CHECK6-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 1 +// CHECK6-NEXT: store i64 4, i64* [[TMP78]], align 8 +// CHECK6-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK6-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP81]], align 8 +// CHECK6-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP83]], align 8 +// CHECK6-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 2 +// CHECK6-NEXT: store i64 8, i64* [[TMP84]], align 8 +// CHECK6-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP85]], align 8 +// CHECK6-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP87]], align 8 +// CHECK6-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK6-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 8 +// CHECK6-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 3 +// CHECK6-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 +// CHECK6-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP91]], align 8 +// CHECK6-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP95:%.*]] = load i32, i32* [[N]], align 4 +// CHECK6-NEXT: store i32 [[TMP95]], i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK6-NEXT: [[TMP96:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK6-NEXT: [[SUB28:%.*]] = sub nsw i32 [[TMP96]], 0 +// CHECK6-NEXT: [[DIV29:%.*]] = sdiv i32 [[SUB28]], 1 +// CHECK6-NEXT: [[SUB30:%.*]] = sub nsw i32 [[DIV29]], 1 +// CHECK6-NEXT: store i32 [[SUB30]], i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK6-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK6-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP97]], 1 +// CHECK6-NEXT: [[TMP98:%.*]] = zext i32 [[ADD31]] to i64 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP98]]) +// CHECK6-NEXT: [[TMP99:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 4, i8** [[TMP92]], i8** [[TMP93]], i64* [[TMP94]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP100:%.*]] = icmp ne i32 [[TMP99]], 0 +// CHECK6-NEXT: br i1 [[TMP100]], label [[OMP_OFFLOAD_FAILED32:%.*]], label [[OMP_OFFLOAD_CONT33:%.*]] +// CHECK6: omp_offload.failed32: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP64]], i64 [[TMP66]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT33]] +// CHECK6: omp_offload.cont33: +// CHECK6-NEXT: [[TMP101:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP101]]) +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[TMP102:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP102]]) +// CHECK6-NEXT: [[TMP103:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP103]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] // CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC9:%.*]] -// CHECK6: for.inc9: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end11: -// CHECK6-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13:%.*]] -// CHECK6: for.cond13: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK6-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK6: for.body15: -// CHECK6-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK6-NEXT: br label [[FOR_INC19:%.*]] -// CHECK6: for.inc19: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end21: -// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 +// CHECK6-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 +// CHECK6-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] +// CHECK6-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] +// CHECK6: cond.true12: +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END14:%.*]] +// CHECK6: cond.false13: +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END14]] +// CHECK6: cond.end14: +// CHECK6-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE12]] ], [ [[TMP32]], [[COND_FALSE13]] ] +// CHECK6-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK6-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK6-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK6-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK6-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK6-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK6: omp_offload.failed5: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK6: omp_offload.cont6: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK6-NEXT: store i64 [[TMP19]], i64* [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK6-NEXT: store i64 [[TMP19]], i64* [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK6-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK6-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK6: omp_offload.failed11: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94(i64 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK6: omp_offload.cont12: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 +// CHECK6-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 +// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK6: cond.true6: +// CHECK6-NEXT: br label [[COND_END8:%.*]] +// CHECK6: cond.false7: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END8]] +// CHECK6: cond.end8: +// CHECK6-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] +// CHECK6-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-LABEL: define {{[^@]+}}@main +// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK7-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [4 x i64], align 4 +// CHECK7-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK7-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK7-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK7-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK7-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK7-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK7-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK7-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK7-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK7-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK7-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) +// CHECK7-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK7-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK7: omp_offload.failed15: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK7: omp_offload.cont16: +// CHECK7-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP64]], i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP65:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP66:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP66]], i32* [[N_CASTED17]], align 4 +// CHECK7-NEXT: [[TMP67:%.*]] = load i32, i32* [[N_CASTED17]], align 4 +// CHECK7-NEXT: [[TMP68:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK7-NEXT: [[TMP69:%.*]] = sext i32 [[TMP68]] to i64 +// CHECK7-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* +// CHECK7-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 +// CHECK7-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32* +// CHECK7-NEXT: store i32 [[TMP65]], i32* [[TMP73]], align 4 +// CHECK7-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK7-NEXT: store i64 4, i64* [[TMP74]], align 4 +// CHECK7-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP75]], align 4 +// CHECK7-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* +// CHECK7-NEXT: store i32 [[TMP67]], i32* [[TMP77]], align 4 +// CHECK7-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK7-NEXT: store i32 [[TMP67]], i32* [[TMP79]], align 4 +// CHECK7-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 +// CHECK7-NEXT: store i64 4, i64* [[TMP80]], align 4 +// CHECK7-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP81]], align 4 +// CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP83]], align 4 +// CHECK7-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[TMP85]], align 4 +// CHECK7-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 +// CHECK7-NEXT: store i64 4, i64* [[TMP86]], align 4 +// CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP87]], align 4 +// CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 4 +// CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** +// CHECK7-NEXT: store i32* [[VLA]], i32** [[TMP91]], align 4 +// CHECK7-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 3 +// CHECK7-NEXT: store i64 [[TMP69]], i64* [[TMP92]], align 4 +// CHECK7-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP93]], align 4 +// CHECK7-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP97:%.*]] = load i32, i32* [[N]], align 4 +// CHECK7-NEXT: store i32 [[TMP97]], i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK7-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK7-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP98]], 0 +// CHECK7-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 +// CHECK7-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 +// CHECK7-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK7-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK7-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP99]], 1 +// CHECK7-NEXT: [[TMP100:%.*]] = zext i32 [[ADD28]] to i64 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP100]]) +// CHECK7-NEXT: [[TMP101:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 4, i8** [[TMP94]], i8** [[TMP95]], i64* [[TMP96]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP102:%.*]] = icmp ne i32 [[TMP101]], 0 +// CHECK7-NEXT: br i1 [[TMP102]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] +// CHECK7: omp_offload.failed29: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP65]], i32 [[TMP67]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT30]] +// CHECK7: omp_offload.cont30: +// CHECK7-NEXT: [[TMP103:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP103]]) +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[TMP104:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP104]]) +// CHECK7-NEXT: [[TMP105:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP105]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC8:%.*]] -// CHECK7: for.inc8: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end10: -// CHECK7-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12:%.*]] -// CHECK7: for.cond12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK7-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK7: for.body14: -// CHECK7-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK7-NEXT: br label [[FOR_INC17:%.*]] -// CHECK7: for.inc17: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end19: -// CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 +// CHECK7-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 +// CHECK7-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] +// CHECK7-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK7: cond.true11: +// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END13:%.*]] +// CHECK7: cond.false12: +// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END13]] +// CHECK7: cond.end13: +// CHECK7-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE11]] ], [ [[TMP30]], [[COND_FALSE12]] ] +// CHECK7-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK7: omp.precond.then: +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK7-NEXT: br label [[OMP_PRECOND_END]] +// CHECK7: omp.precond.end: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK7-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK7-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 +// CHECK7-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK7-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK7-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK7: omp_offload.failed5: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK7: omp_offload.cont6: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK7-NEXT: store i32 [[TMP18]], i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK7-NEXT: store i32 [[TMP19]], i32* [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK7-NEXT: store i32 [[TMP19]], i32* [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK7-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK7-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK7: omp_offload.failed11: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94(i32 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK7: omp_offload.cont12: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK7-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 +// CHECK7-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 +// CHECK7-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] +// CHECK7: cond.true5: +// CHECK7-NEXT: br label [[COND_END7:%.*]] +// CHECK7: cond.false6: +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END7]] +// CHECK7: cond.end7: +// CHECK7-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] +// CHECK7-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-LABEL: define {{[^@]+}}@main +// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK8-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [4 x i64], align 4 +// CHECK8-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK8-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK8-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK8-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK8-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK8-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK8-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK8-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK8-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK8-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK8-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK8-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK8-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK8-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK8-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK8-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK8-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK8-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK8-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK8-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK8-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK8-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) +// CHECK8-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK8-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK8: omp_offload.failed15: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK8: omp_offload.cont16: +// CHECK8-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP64]], i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP65:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP66:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP66]], i32* [[N_CASTED17]], align 4 +// CHECK8-NEXT: [[TMP67:%.*]] = load i32, i32* [[N_CASTED17]], align 4 +// CHECK8-NEXT: [[TMP68:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK8-NEXT: [[TMP69:%.*]] = sext i32 [[TMP68]] to i64 +// CHECK8-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* +// CHECK8-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 +// CHECK8-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32* +// CHECK8-NEXT: store i32 [[TMP65]], i32* [[TMP73]], align 4 +// CHECK8-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK8-NEXT: store i64 4, i64* [[TMP74]], align 4 +// CHECK8-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP75]], align 4 +// CHECK8-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* +// CHECK8-NEXT: store i32 [[TMP67]], i32* [[TMP77]], align 4 +// CHECK8-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK8-NEXT: store i32 [[TMP67]], i32* [[TMP79]], align 4 +// CHECK8-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 +// CHECK8-NEXT: store i64 4, i64* [[TMP80]], align 4 +// CHECK8-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP81]], align 4 +// CHECK8-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP83]], align 4 +// CHECK8-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[TMP85]], align 4 +// CHECK8-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 +// CHECK8-NEXT: store i64 4, i64* [[TMP86]], align 4 +// CHECK8-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP87]], align 4 +// CHECK8-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 4 +// CHECK8-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** +// CHECK8-NEXT: store i32* [[VLA]], i32** [[TMP91]], align 4 +// CHECK8-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 3 +// CHECK8-NEXT: store i64 [[TMP69]], i64* [[TMP92]], align 4 +// CHECK8-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP93]], align 4 +// CHECK8-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP97:%.*]] = load i32, i32* [[N]], align 4 +// CHECK8-NEXT: store i32 [[TMP97]], i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK8-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK8-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP98]], 0 +// CHECK8-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 +// CHECK8-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 +// CHECK8-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK8-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK8-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP99]], 1 +// CHECK8-NEXT: [[TMP100:%.*]] = zext i32 [[ADD28]] to i64 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP100]]) +// CHECK8-NEXT: [[TMP101:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 4, i8** [[TMP94]], i8** [[TMP95]], i64* [[TMP96]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP102:%.*]] = icmp ne i32 [[TMP101]], 0 +// CHECK8-NEXT: br i1 [[TMP102]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] +// CHECK8: omp_offload.failed29: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP65]], i32 [[TMP67]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT30]] +// CHECK8: omp_offload.cont30: +// CHECK8-NEXT: [[TMP103:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP103]]) +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[TMP104:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP104]]) +// CHECK8-NEXT: [[TMP105:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP105]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] // CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC8:%.*]] -// CHECK8: for.inc8: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end10: -// CHECK8-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12:%.*]] -// CHECK8: for.cond12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK8-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK8: for.body14: -// CHECK8-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK8-NEXT: br label [[FOR_INC17:%.*]] -// CHECK8: for.inc17: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end19: -// CHECK8-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK9-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_SIZES24:%.*]] = alloca [4 x i64], align 8 -// CHECK9-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK9-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK9-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK9-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK9-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK9-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK9-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) -// CHECK9-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK9-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK9: omp_offload.failed16: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK9: omp_offload.cont17: -// CHECK9-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP63]], i32* [[CONV18]], align 4 -// CHECK9-NEXT: [[TMP64:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK9-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* -// CHECK9-NEXT: store i32 [[TMP65]], i32* [[CONV20]], align 4 -// CHECK9-NEXT: [[TMP66:%.*]] = load i64, i64* [[N_CASTED19]], align 8 -// CHECK9-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK9-NEXT: [[TMP68:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* -// CHECK9-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 -// CHECK9-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* -// CHECK9-NEXT: store i64 [[TMP64]], i64* [[TMP71]], align 8 -// CHECK9-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 -// CHECK9-NEXT: store i64 4, i64* [[TMP72]], align 8 -// CHECK9-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP73]], align 8 -// CHECK9-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* -// CHECK9-NEXT: store i64 [[TMP66]], i64* [[TMP75]], align 8 -// CHECK9-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* -// CHECK9-NEXT: store i64 [[TMP66]], i64* [[TMP77]], align 8 -// CHECK9-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 1 -// CHECK9-NEXT: store i64 4, i64* [[TMP78]], align 8 -// CHECK9-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP79]], align 8 -// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP81]], align 8 -// CHECK9-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP83]], align 8 -// CHECK9-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 2 -// CHECK9-NEXT: store i64 8, i64* [[TMP84]], align 8 -// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP85]], align 8 -// CHECK9-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP87]], align 8 -// CHECK9-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 8 -// CHECK9-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 3 -// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 -// CHECK9-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP91]], align 8 -// CHECK9-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP95:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: store i32 [[TMP95]], i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK9-NEXT: [[TMP96:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK9-NEXT: [[SUB28:%.*]] = sub nsw i32 [[TMP96]], 0 -// CHECK9-NEXT: [[DIV29:%.*]] = sdiv i32 [[SUB28]], 1 -// CHECK9-NEXT: [[SUB30:%.*]] = sub nsw i32 [[DIV29]], 1 -// CHECK9-NEXT: store i32 [[SUB30]], i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK9-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK9-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP97]], 1 -// CHECK9-NEXT: [[TMP98:%.*]] = zext i32 [[ADD31]] to i64 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP98]]) -// CHECK9-NEXT: [[TMP99:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 4, i8** [[TMP92]], i8** [[TMP93]], i64* [[TMP94]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP100:%.*]] = icmp ne i32 [[TMP99]], 0 -// CHECK9-NEXT: br i1 [[TMP100]], label [[OMP_OFFLOAD_FAILED32:%.*]], label [[OMP_OFFLOAD_CONT33:%.*]] -// CHECK9: omp_offload.failed32: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP64]], i64 [[TMP66]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]] -// CHECK9: omp_offload.cont33: -// CHECK9-NEXT: [[TMP101:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP101]]) -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[TMP102:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP102]]) -// CHECK9-NEXT: [[TMP103:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP103]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 -// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK9-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] -// CHECK9-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] -// CHECK9: cond.true12: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: br label [[COND_END14:%.*]] -// CHECK9: cond.false13: -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END14]] -// CHECK9: cond.end14: -// CHECK9-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE12]] ], [ [[TMP32]], [[COND_FALSE13]] ] -// CHECK9-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 -// CHECK9-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK9: omp_offload.failed5: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK9: omp_offload.cont6: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK9-NEXT: store i64 [[TMP19]], i64* [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK9-NEXT: store i64 [[TMP19]], i64* [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK9: omp_offload.failed11: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94(i64 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK9: omp_offload.cont12: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 -// CHECK9-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] -// CHECK9: cond.true6: -// CHECK9-NEXT: br label [[COND_END8:%.*]] -// CHECK9: cond.false7: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END8]] -// CHECK9: cond.end8: -// CHECK9-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] -// CHECK9-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK10-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_SIZES24:%.*]] = alloca [4 x i64], align 8 -// CHECK10-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK10-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK10-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK10-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK10-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK10-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) -// CHECK10-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK10-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK10: omp_offload.failed16: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK10: omp_offload.cont17: -// CHECK10-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP63]], i32* [[CONV18]], align 4 -// CHECK10-NEXT: [[TMP64:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK10-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* -// CHECK10-NEXT: store i32 [[TMP65]], i32* [[CONV20]], align 4 -// CHECK10-NEXT: [[TMP66:%.*]] = load i64, i64* [[N_CASTED19]], align 8 -// CHECK10-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK10-NEXT: [[TMP68:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* -// CHECK10-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 -// CHECK10-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* -// CHECK10-NEXT: store i64 [[TMP64]], i64* [[TMP71]], align 8 -// CHECK10-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 -// CHECK10-NEXT: store i64 4, i64* [[TMP72]], align 8 -// CHECK10-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP73]], align 8 -// CHECK10-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* -// CHECK10-NEXT: store i64 [[TMP66]], i64* [[TMP75]], align 8 -// CHECK10-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* -// CHECK10-NEXT: store i64 [[TMP66]], i64* [[TMP77]], align 8 -// CHECK10-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 1 -// CHECK10-NEXT: store i64 4, i64* [[TMP78]], align 8 -// CHECK10-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP79]], align 8 -// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP81]], align 8 -// CHECK10-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP83]], align 8 -// CHECK10-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 2 -// CHECK10-NEXT: store i64 8, i64* [[TMP84]], align 8 -// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP85]], align 8 -// CHECK10-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP87]], align 8 -// CHECK10-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 8 -// CHECK10-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 3 -// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 -// CHECK10-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP91]], align 8 -// CHECK10-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP95:%.*]] = load i32, i32* [[N]], align 4 -// CHECK10-NEXT: store i32 [[TMP95]], i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK10-NEXT: [[TMP96:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK10-NEXT: [[SUB28:%.*]] = sub nsw i32 [[TMP96]], 0 -// CHECK10-NEXT: [[DIV29:%.*]] = sdiv i32 [[SUB28]], 1 -// CHECK10-NEXT: [[SUB30:%.*]] = sub nsw i32 [[DIV29]], 1 -// CHECK10-NEXT: store i32 [[SUB30]], i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK10-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK10-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP97]], 1 -// CHECK10-NEXT: [[TMP98:%.*]] = zext i32 [[ADD31]] to i64 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP98]]) -// CHECK10-NEXT: [[TMP99:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 4, i8** [[TMP92]], i8** [[TMP93]], i64* [[TMP94]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP100:%.*]] = icmp ne i32 [[TMP99]], 0 -// CHECK10-NEXT: br i1 [[TMP100]], label [[OMP_OFFLOAD_FAILED32:%.*]], label [[OMP_OFFLOAD_CONT33:%.*]] -// CHECK10: omp_offload.failed32: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP64]], i64 [[TMP66]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT33]] -// CHECK10: omp_offload.cont33: -// CHECK10-NEXT: [[TMP101:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP101]]) -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP102:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP102]]) -// CHECK10-NEXT: [[TMP103:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP103]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 -// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK10-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] -// CHECK10-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] -// CHECK10: cond.true12: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: br label [[COND_END14:%.*]] -// CHECK10: cond.false13: -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END14]] -// CHECK10: cond.end14: -// CHECK10-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE12]] ], [ [[TMP32]], [[COND_FALSE13]] ] -// CHECK10-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK10: omp.precond.then: -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK10-NEXT: br label [[OMP_PRECOND_END]] -// CHECK10: omp.precond.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 -// CHECK10-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK10-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK10: omp_offload.failed5: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK10: omp_offload.cont6: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK10-NEXT: store i64 [[TMP19]], i64* [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK10-NEXT: store i64 [[TMP19]], i64* [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK10-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK10-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK10: omp_offload.failed11: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94(i64 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK10: omp_offload.cont12: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 -// CHECK10-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 -// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] -// CHECK10: cond.true6: -// CHECK10-NEXT: br label [[COND_END8:%.*]] -// CHECK10: cond.false7: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END8]] -// CHECK10: cond.end8: -// CHECK10-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] -// CHECK10-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK11-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [4 x i64], align 4 -// CHECK11-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK11-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK11-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK11-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK11-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK11-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK11-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK11-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK11-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) -// CHECK11-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK11-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK11: omp_offload.failed15: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK11: omp_offload.cont16: -// CHECK11-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP64]], i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP65:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP66:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP66]], i32* [[N_CASTED17]], align 4 -// CHECK11-NEXT: [[TMP67:%.*]] = load i32, i32* [[N_CASTED17]], align 4 -// CHECK11-NEXT: [[TMP68:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK11-NEXT: [[TMP69:%.*]] = sext i32 [[TMP68]] to i64 -// CHECK11-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* -// CHECK11-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 -// CHECK11-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32* -// CHECK11-NEXT: store i32 [[TMP65]], i32* [[TMP73]], align 4 -// CHECK11-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK11-NEXT: store i64 4, i64* [[TMP74]], align 4 -// CHECK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP75]], align 4 -// CHECK11-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* -// CHECK11-NEXT: store i32 [[TMP67]], i32* [[TMP77]], align 4 -// CHECK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK11-NEXT: store i32 [[TMP67]], i32* [[TMP79]], align 4 -// CHECK11-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 -// CHECK11-NEXT: store i64 4, i64* [[TMP80]], align 4 -// CHECK11-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP81]], align 4 -// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP83]], align 4 -// CHECK11-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP85]], align 4 -// CHECK11-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 -// CHECK11-NEXT: store i64 4, i64* [[TMP86]], align 4 -// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP87]], align 4 -// CHECK11-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 4 -// CHECK11-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** -// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP91]], align 4 -// CHECK11-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 3 -// CHECK11-NEXT: store i64 [[TMP69]], i64* [[TMP92]], align 4 -// CHECK11-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP93]], align 4 -// CHECK11-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP97:%.*]] = load i32, i32* [[N]], align 4 -// CHECK11-NEXT: store i32 [[TMP97]], i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK11-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK11-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP98]], 0 -// CHECK11-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 -// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 -// CHECK11-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK11-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK11-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP99]], 1 -// CHECK11-NEXT: [[TMP100:%.*]] = zext i32 [[ADD28]] to i64 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP100]]) -// CHECK11-NEXT: [[TMP101:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 4, i8** [[TMP94]], i8** [[TMP95]], i64* [[TMP96]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP102:%.*]] = icmp ne i32 [[TMP101]], 0 -// CHECK11-NEXT: br i1 [[TMP102]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] -// CHECK11: omp_offload.failed29: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP65]], i32 [[TMP67]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT30]] -// CHECK11: omp_offload.cont30: -// CHECK11-NEXT: [[TMP103:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP103]]) -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP104:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP104]]) -// CHECK11-NEXT: [[TMP105:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP105]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 -// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK11-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK11: cond.true11: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END13:%.*]] -// CHECK11: cond.false12: -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END13]] -// CHECK11: cond.end13: -// CHECK11-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE11]] ], [ [[TMP30]], [[COND_FALSE12]] ] -// CHECK11-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 -// CHECK11-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK11-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK11: omp_offload.failed5: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK11: omp_offload.cont6: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK11-NEXT: store i32 [[TMP19]], i32* [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK11-NEXT: store i32 [[TMP19]], i32* [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK11: omp_offload.failed11: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94(i32 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK11: omp_offload.cont12: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 -// CHECK11-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] -// CHECK11: cond.true5: -// CHECK11-NEXT: br label [[COND_END7:%.*]] -// CHECK11: cond.false6: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END7]] -// CHECK11: cond.end7: -// CHECK11-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] -// CHECK11-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [4 x i64], align 4 -// CHECK12-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK12-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK12-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK12-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK12-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK12-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK12-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK12-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK12-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK12-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) -// CHECK12-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK12-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK12: omp_offload.failed15: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK12: omp_offload.cont16: -// CHECK12-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP64]], i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP65:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP66:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP66]], i32* [[N_CASTED17]], align 4 -// CHECK12-NEXT: [[TMP67:%.*]] = load i32, i32* [[N_CASTED17]], align 4 -// CHECK12-NEXT: [[TMP68:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK12-NEXT: [[TMP69:%.*]] = sext i32 [[TMP68]] to i64 -// CHECK12-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* -// CHECK12-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 -// CHECK12-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32* -// CHECK12-NEXT: store i32 [[TMP65]], i32* [[TMP73]], align 4 -// CHECK12-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK12-NEXT: store i64 4, i64* [[TMP74]], align 4 -// CHECK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP75]], align 4 -// CHECK12-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* -// CHECK12-NEXT: store i32 [[TMP67]], i32* [[TMP77]], align 4 -// CHECK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK12-NEXT: store i32 [[TMP67]], i32* [[TMP79]], align 4 -// CHECK12-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 -// CHECK12-NEXT: store i64 4, i64* [[TMP80]], align 4 -// CHECK12-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP81]], align 4 -// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP83]], align 4 -// CHECK12-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP85]], align 4 -// CHECK12-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 -// CHECK12-NEXT: store i64 4, i64* [[TMP86]], align 4 -// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP87]], align 4 -// CHECK12-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 4 -// CHECK12-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** -// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP91]], align 4 -// CHECK12-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 3 -// CHECK12-NEXT: store i64 [[TMP69]], i64* [[TMP92]], align 4 -// CHECK12-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP93]], align 4 -// CHECK12-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP97:%.*]] = load i32, i32* [[N]], align 4 -// CHECK12-NEXT: store i32 [[TMP97]], i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK12-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK12-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP98]], 0 -// CHECK12-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 -// CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 -// CHECK12-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK12-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK12-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP99]], 1 -// CHECK12-NEXT: [[TMP100:%.*]] = zext i32 [[ADD28]] to i64 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP100]]) -// CHECK12-NEXT: [[TMP101:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 4, i8** [[TMP94]], i8** [[TMP95]], i64* [[TMP96]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP102:%.*]] = icmp ne i32 [[TMP101]], 0 -// CHECK12-NEXT: br i1 [[TMP102]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] -// CHECK12: omp_offload.failed29: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP65]], i32 [[TMP67]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT30]] -// CHECK12: omp_offload.cont30: -// CHECK12-NEXT: [[TMP103:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP103]]) -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[TMP104:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP104]]) -// CHECK12-NEXT: [[TMP105:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP105]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 -// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK12-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] -// CHECK12-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK12: cond.true11: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END13:%.*]] -// CHECK12: cond.false12: -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END13]] -// CHECK12: cond.end13: -// CHECK12-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE11]] ], [ [[TMP30]], [[COND_FALSE12]] ] -// CHECK12-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK12: omp.precond.then: -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK12-NEXT: br label [[OMP_PRECOND_END]] -// CHECK12: omp.precond.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 -// CHECK12-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK12-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK12: omp_offload.failed5: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK12: omp_offload.cont6: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK12-NEXT: store i32 [[TMP18]], i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK12-NEXT: store i32 [[TMP19]], i32* [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK12-NEXT: store i32 [[TMP19]], i32* [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK12-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK12-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK12: omp_offload.failed11: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94(i32 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK12: omp_offload.cont12: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 -// CHECK12-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 -// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] -// CHECK12: cond.true5: -// CHECK12-NEXT: br label [[COND_END7:%.*]] -// CHECK12: cond.false6: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END7]] -// CHECK12: cond.end7: -// CHECK12-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] -// CHECK12-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP17]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP17]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: ret i32 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 +// CHECK8-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 +// CHECK8-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] +// CHECK8-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK8: cond.true11: +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END13:%.*]] +// CHECK8: cond.false12: +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END13]] +// CHECK8: cond.end13: +// CHECK8-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE11]] ], [ [[TMP30]], [[COND_FALSE12]] ] +// CHECK8-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK8: omp.precond.then: +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK8-NEXT: br label [[OMP_PRECOND_END]] +// CHECK8: omp.precond.end: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK8-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK8-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 +// CHECK8-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK8-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK8-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK8: omp_offload.failed5: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK8: omp_offload.cont6: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK8-NEXT: store i32 [[TMP18]], i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK8-NEXT: store i32 [[TMP19]], i32* [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK8-NEXT: store i32 [[TMP19]], i32* [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK8-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK8-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK8: omp_offload.failed11: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94(i32 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK8: omp_offload.cont12: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 +// CHECK8-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 +// CHECK8-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 +// CHECK8-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] +// CHECK8: cond.true5: +// CHECK8-NEXT: br label [[COND_END7:%.*]] +// CHECK8: cond.false6: +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END7]] +// CHECK8: cond.end7: +// CHECK8-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] +// CHECK8-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -4400,6 +4400,28 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: @@ -4438,143 +4460,6 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK5-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP14]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: @@ -4592,73 +4477,236 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 +// CHECK5-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 +// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK5-NEXT: ret void // // @@ -4671,6 +4719,13 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: @@ -4699,6 +4754,28 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: @@ -4737,143 +4814,6 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK6-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP14]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: @@ -4891,73 +4831,236 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK6-NEXT: ret i32 0 // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 +// CHECK6-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 +// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 +// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK6-NEXT: ret void // // @@ -4970,1564 +5073,9 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP14]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK8-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP14]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 -// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 -// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init() -// CHECK9-NEXT: call void @__cxx_global_var_init.1() -// CHECK9-NEXT: call void @__cxx_global_var_init.2() -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 -// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 -// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 -// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__cxx_global_var_init() -// CHECK10-NEXT: call void @__cxx_global_var_init.1() -// CHECK10-NEXT: call void @__cxx_global_var_init.2() -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp @@ -3,33 +3,33 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2790,323 +2790,2675 @@ // CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 +// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z9gtid_testv() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: () #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK3-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK3-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK3-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 +// CHECK3-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) +// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK3-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK3: omp_offload.failed6: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97(i64 [[TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK3: omp_offload.cont7: +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) +// CHECK3-NEXT: ret i32 [[CALL]] +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn4v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn5v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 +// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: +// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK3-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK3-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn6v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK3-NEXT: ret i32 [[CALL]] +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67() #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK3-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK3-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK3-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 +// CHECK3-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) +// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK3-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK3: omp_offload.failed6: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72(i64 [[TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK3: omp_offload.cont7: +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn1v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 +// CHECK3-SAME: () #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn2v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 +// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: +// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK3-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK3-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK3: omp_if.then: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK3: omp_if.else: +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: br label [[OMP_IF_END]] +// CHECK3: omp_if.end: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: call void @_Z3fn3v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: ret i32 0 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK3-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK3-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 +// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z9gtid_testv() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: () #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK4-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK4-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK4-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 +// CHECK4-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) +// CHECK4-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK4-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK4: omp_offload.failed6: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97(i64 [[TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK4: omp_offload.cont7: +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) +// CHECK4-NEXT: ret i32 [[CALL]] +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn4v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn5v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 +// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: +// CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK4-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK4-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK4-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn6v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK4-NEXT: ret i32 [[CALL]] +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67() #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK4-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK4-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK4-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 +// CHECK4-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) +// CHECK4-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK4-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK4: omp_offload.failed6: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72(i64 [[TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK4: omp_offload.cont7: +// CHECK4-NEXT: ret i32 0 +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn1v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 +// CHECK4-SAME: () #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn2v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 +// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: +// CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK4-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK4-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK4-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK4: omp_if.then: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK4: omp_if.else: +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: br label [[OMP_IF_END]] +// CHECK4: omp_if.end: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: call void @_Z3fn3v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: ret i32 0 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK4-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK4-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv @@ -5776,6323 +8128,2683 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK6-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv +// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK7: omp_offload.failed2: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK7: omp_offload.cont3: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 +// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z9gtid_testv() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end7: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK7: omp_offload.failed2: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK7: omp_offload.cont3: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* @Arg, align 4 +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 +// CHECK7-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) +// CHECK7-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK7-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK7: omp_offload.failed6: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97(i64 [[TMP5]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK7: omp_offload.cont7: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) +// CHECK7-NEXT: ret i32 [[CALL]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn4v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn5v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 +// CHECK7-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: +// CHECK7-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK7-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK7-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK7-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.else: +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn6v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK7-NEXT: ret i32 [[CALL]] +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK7-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK7-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK7-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK7: omp_offload.failed2: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67() #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK7: omp_offload.cont3: +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK7-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 +// CHECK7-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK7-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) +// CHECK7-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK7-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK7: omp_offload.failed6: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72(i64 [[TMP5]]) #[[ATTR2]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK7: omp_offload.cont7: +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn1v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 +// CHECK7-SAME: () #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn2v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 +// CHECK7-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: +// CHECK7-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK7-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK7-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK7-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK7-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK7-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK7: omp_if.then: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK7: omp_if.else: +// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK7-NEXT: br label [[OMP_IF_END]] +// CHECK7: omp_if.end: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK7-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: call void @_Z3fn3v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK8: omp_offload.failed2: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK8: omp_offload.cont3: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 +// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z9gtid_testv() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end7: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK8: omp_offload.failed2: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK8: omp_offload.cont3: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* @Arg, align 4 +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 +// CHECK8-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) +// CHECK8-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK8-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK8: omp_offload.failed6: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97(i64 [[TMP5]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK8: omp_offload.cont7: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) +// CHECK8-NEXT: ret i32 [[CALL]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn4v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn5v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 +// CHECK8-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: +// CHECK8-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK8-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK8-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK8-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.else: +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn6v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK8-NEXT: ret i32 [[CALL]] +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ // CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK8-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK8-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK8-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK8: omp_offload.failed2: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67() #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK8: omp_offload.cont3: +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK8-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 +// CHECK8-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK8-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) +// CHECK8-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK8-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK8: omp_offload.failed6: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72(i64 [[TMP5]]) #[[ATTR2]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK8: omp_offload.cont7: +// CHECK8-NEXT: ret i32 0 +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn1v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 +// CHECK8-SAME: () #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn2v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 +// CHECK8-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: +// CHECK8-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK8-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK8-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK8-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK8-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK8-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK8: omp_if.then: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK8: omp_if.else: +// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK8-NEXT: br label [[OMP_IF_END]] +// CHECK8: omp_if.end: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK8-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: call void @_Z3fn3v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: ret i32 0 +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK9: omp_offload.failed2: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK9: omp_offload.cont3: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 -// CHECK9-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z9gtid_testv() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK9: omp_offload.failed2: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK9: omp_offload.cont3: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 -// CHECK9-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) -// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK9: omp_offload.failed6: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97(i64 [[TMP5]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK9: omp_offload.cont7: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn4v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn5v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_IF_END]] -// CHECK9: omp_if.end: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn6v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK9-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK9: omp_offload.failed2: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67() #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK9: omp_offload.cont3: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 -// CHECK9-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) -// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK9: omp_offload.failed6: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72(i64 [[TMP5]]) #[[ATTR2]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK9: omp_offload.cont7: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn1v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK9-SAME: () #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn2v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK9-NEXT: br label [[OMP_IF_END]] -// CHECK9: omp_if.end: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: call void @_Z3fn3v() -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK10: omp_offload.failed2: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK10: omp_offload.cont3: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 -// CHECK10-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z9gtid_testv() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK10: omp_offload.failed2: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK10: omp_offload.cont3: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 -// CHECK10-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) -// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK10-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK10: omp_offload.failed6: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97(i64 [[TMP5]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK10: omp_offload.cont7: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn4v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn5v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_IF_END]] -// CHECK10: omp_if.end: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn6v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK10-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK10-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK10: omp_offload.failed2: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67() #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK10: omp_offload.cont3: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 -// CHECK10-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) -// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK10-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK10: omp_offload.failed6: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72(i64 [[TMP5]]) #[[ATTR2]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK10: omp_offload.cont7: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn1v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK10-SAME: () #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn2v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK10-NEXT: br label [[OMP_IF_END]] -// CHECK10: omp_if.end: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: call void @_Z3fn3v() -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z9gtid_testv() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn4v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn5v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn6v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK11-NEXT: ret i32 [[CALL]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK11-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn1v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn2v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn3v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z9gtid_testv() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn4v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn5v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn6v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK12-NEXT: ret i32 [[CALL]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK12-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn1v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn2v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn3v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK13: omp_offload.failed2: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK13: omp_offload.cont3: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 -// CHECK13-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z9gtid_testv() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK13: omp_offload.failed2: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK13: omp_offload.cont3: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK13-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK13-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK13-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 -// CHECK13-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) -// CHECK13-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK13-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK13: omp_offload.failed6: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97(i64 [[TMP5]]) #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK13: omp_offload.cont7: -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) -// CHECK13-NEXT: ret i32 [[CALL]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn4v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn5v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK13-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 -// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP2]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK13: omp_if.then: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK13: omp_if.else: -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_IF_END]] -// CHECK13: omp_if.end: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn6v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK13-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK13-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK13: omp_offload.failed: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK13: omp_offload.cont: -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK13: omp_offload.failed2: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67() #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK13: omp_offload.cont3: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK13-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK13-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK13-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 -// CHECK13-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK13-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK13-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) -// CHECK13-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK13-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK13: omp_offload.failed6: -// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72(i64 [[TMP5]]) #[[ATTR2]] -// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK13: omp_offload.cont7: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn1v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK13-SAME: () #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn2v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK13-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 -// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK13: omp_if.then: -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK13: omp_if.else: -// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK13-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK13-NEXT: br label [[OMP_IF_END]] -// CHECK13: omp_if.end: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: call void @_Z3fn3v() -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK13-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK14: omp_offload.failed2: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK14: omp_offload.cont3: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 -// CHECK14-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z9gtid_testv() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK14: omp_offload.failed2: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK14: omp_offload.cont3: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK14-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK14-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK14-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 -// CHECK14-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) -// CHECK14-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK14-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK14: omp_offload.failed6: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97(i64 [[TMP5]]) #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK14: omp_offload.cont7: -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) -// CHECK14-NEXT: ret i32 [[CALL]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn4v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn5v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK14-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 -// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP2]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK14: omp_if.then: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK14: omp_if.else: -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_IF_END]] -// CHECK14: omp_if.end: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn6v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK14-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK14-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK14: omp_offload.failed: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK14: omp_offload.cont: -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK14: omp_offload.failed2: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67() #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK14: omp_offload.cont3: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK14-NEXT: store i64 [[TMP5]], i64* [[TMP7]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK14-NEXT: store i64 [[TMP5]], i64* [[TMP9]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK14-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP13]], 0 -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 -// CHECK14-NEXT: [[TMP15:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 -// CHECK14-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK14-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.region_id, i32 1, i8** [[TMP11]], i8** [[TMP12]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP15]]) -// CHECK14-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK14-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] -// CHECK14: omp_offload.failed6: -// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72(i64 [[TMP5]]) #[[ATTR2]] -// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT7]] -// CHECK14: omp_offload.cont7: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn1v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK14-SAME: () #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..12 to void (i32*, i32*, ...)*)) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn2v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK14-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 -// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK14: omp_if.then: -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK14: omp_if.else: -// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK14-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) -// CHECK14-NEXT: br label [[OMP_IF_END]] -// CHECK14: omp_if.end: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK14: cond.true: -// CHECK14-NEXT: br label [[COND_END:%.*]] -// CHECK14: cond.false: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: br label [[COND_END]] -// CHECK14: cond.end: -// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: call void @_Z3fn3v() -// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK14: omp.body.continue: -// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK14: omp.inner.for.end: -// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK14: omp.loop.exit: -// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK14-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z9gtid_testv() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn4v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn5v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn6v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK15-NEXT: ret i32 [[CALL]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK15-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn1v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn2v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn3v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z9gtid_testv() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn4v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn5v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn6v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK16-NEXT: ret i32 [[CALL]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK16-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn1v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn2v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn3v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: ret i32 0 +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp @@ -6,26 +6,26 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1253,16 +1253,997 @@ // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK5-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done3: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP39]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK5-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK5-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK5-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP28]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done10: +// CHECK5-NEXT: [[TMP31:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP5]] to i8* +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP31]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK5-NEXT: store i32 [[TMP34]], i32* [[TMP4]], align 4 +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done12: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK5-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP31]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done14: +// CHECK5-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* +// CHECK5-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) +// CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK5-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done16: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done2: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP32]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK5-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK5-NEXT: store i32 [[TMP23]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP27]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done9: +// CHECK5-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done11: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK5-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK5: omp.inner.for.cond.cleanup: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* +// CHECK5-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK5: .omp.lastprivate.then: +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK5-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP30]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done13: +// CHECK5-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* +// CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) +// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK5: .omp.lastprivate.done: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done15: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main @@ -1271,16 +2252,997 @@ // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK6-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done3: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP39]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* +// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK6-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK6-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK6-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP28]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done10: +// CHECK6-NEXT: [[TMP31:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP5]] to i8* +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP31]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK6-NEXT: store i32 [[TMP34]], i32* [[TMP4]], align 4 +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done12: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) +// CHECK6-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP31]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done14: +// CHECK6-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* +// CHECK6-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) +// CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR8]], align 4 +// CHECK6-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done16: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK6-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK6-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done2: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP32]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK6-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK6-NEXT: store i32 [[TMP23]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP27]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done9: +// CHECK6-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done11: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK6-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) +// CHECK6-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK6: omp.inner.for.cond.cleanup: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* +// CHECK6-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK6-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP30]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done13: +// CHECK6-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* +// CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done15: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@main @@ -1289,16 +3251,979 @@ // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK7-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP39]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP22]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP26]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done10: +// CHECK7-NEXT: [[TMP29:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP5]] to i8* +// CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP29]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK7-NEXT: store i32 [[TMP32]], i32* [[TMP4]], align 4 +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done12: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK7-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP31]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done12: +// CHECK7-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* +// CHECK7-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) +// CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK7-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done14: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done2: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP32]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]]) +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 +// CHECK7-NEXT: br i1 [[TMP20]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP21]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP24:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP25]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done9: +// CHECK7-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* +// CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP28]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done11: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK7: cond.true: +// CHECK7-NEXT: br label [[COND_END:%.*]] +// CHECK7: cond.false: +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: br label [[COND_END]] +// CHECK7: cond.end: +// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK7-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK7: omp.inner.for.cond: +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK7: omp.inner.for.cond.cleanup: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK7: omp.inner.for.body: +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] +// CHECK7-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* +// CHECK7-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) +// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK7: omp.body.continue: +// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK7: omp.inner.for.inc: +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK7: omp.inner.for.end: +// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK7: omp.loop.exit: +// CHECK7-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK7: .omp.lastprivate.then: +// CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP30]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done11: +// CHECK7-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* +// CHECK7-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) +// CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK7: .omp.lastprivate.done: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done13: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@main @@ -1307,5078 +4232,977 @@ // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 // CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP39]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK9-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK9-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK9-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP28]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done10: -// CHECK9-NEXT: [[TMP31:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP5]] to i8* -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP31]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK9-NEXT: store i32 [[TMP34]], i32* [[TMP4]], align 4 -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done12: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK9-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP31]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done14: -// CHECK9-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK9-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK9-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done16: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP32]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK9-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP27]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done9: -// CHECK9-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done11: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK9: omp.inner.for.cond.cleanup: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* -// CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK9-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK9: .omp.lastprivate.then: -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK9-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP30]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done13: -// CHECK9-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK9-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) -// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done15: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* -// CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 -// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK10-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP39]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* -// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK10-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 -// CHECK10-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK10-NEXT: store i32 [[TMP24]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP28]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done10: -// CHECK10-NEXT: [[TMP31:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP5]] to i8* -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP31]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK10-NEXT: store i32 [[TMP34]], i32* [[TMP4]], align 4 -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done12: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) -// CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK10-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP31]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done14: -// CHECK10-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK10-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR8]], align 4 -// CHECK10-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done16: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 -// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP32]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[CONV]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK10-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 -// CHECK10-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP27]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done9: -// CHECK10-NEXT: [[TMP30:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP30]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done11: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK10: omp.inner.for.cond.cleanup: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* -// CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK10-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK10: .omp.lastprivate.then: -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 -// CHECK10-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR5]] to %struct.S.0* -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN12]], [[TMP30]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done13: -// CHECK10-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK10-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK10-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) -// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done15: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP39]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK11-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: store i32 [[TMP22]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP26]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done10: -// CHECK11-NEXT: [[TMP29:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP5]] to i8* -// CHECK11-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP29]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK11-NEXT: store i32 [[TMP32]], i32* [[TMP4]], align 4 -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done12: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK11-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP31]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done12: -// CHECK11-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK11-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) -// CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK11-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done14: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP32]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 -// CHECK11-NEXT: br i1 [[TMP20]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: store i32 [[TMP21]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP24:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP25]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done9: -// CHECK11-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK11-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP28]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done11: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK11: omp.inner.for.cond.cleanup: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] -// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* -// CHECK11-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) -// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK11: omp.body.continue: -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK11-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK11: .omp.lastprivate.then: -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK11-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP30]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK11-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done11: -// CHECK11-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK11-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) -// CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done13: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 -// CHECK12-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP39]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK12-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: store i32 [[TMP22]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP26]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done10: -// CHECK12-NEXT: [[TMP29:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP5]] to i8* -// CHECK12-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP29]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK12-NEXT: store i32 [[TMP32]], i32* [[TMP4]], align 4 -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done12: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) -// CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 -// CHECK12-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP31]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done12: -// CHECK12-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK12-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) -// CHECK12-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR7]], align 4 -// CHECK12-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done14: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 -// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) -// CHECK12-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK12-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP32]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]]) -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 -// CHECK12-NEXT: br i1 [[TMP20]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: store i32 [[TMP21]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP24:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP25]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done9: -// CHECK12-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK12-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP28]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done11: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) -// CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 -// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK12: cond.true: -// CHECK12-NEXT: br label [[COND_END:%.*]] -// CHECK12: cond.false: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: br label [[COND_END]] -// CHECK12: cond.end: -// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] -// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK12: omp.inner.for.cond.cleanup: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] -// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* -// CHECK12-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) -// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK12: omp.body.continue: -// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK12: omp.inner.for.end: -// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK12: omp.loop.exit: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 -// CHECK12-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK12: .omp.lastprivate.then: -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4 -// CHECK12-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* -// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP30]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* -// CHECK12-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done11: -// CHECK12-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 -// CHECK12-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK12-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) -// CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done13: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done4: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done3: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done3: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 +// CHECK8-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP39]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK8-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP22]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP26]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done10: +// CHECK8-NEXT: [[TMP29:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP5]] to i8* +// CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP29]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK8-NEXT: store i32 [[TMP32]], i32* [[TMP4]], align 4 +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done12: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) +// CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK8-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP27]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S* +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP31]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done12: +// CHECK8-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* +// CHECK8-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) +// CHECK8-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK8-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done14: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 +// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) +// CHECK8-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK8-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done2: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP32]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32* [[T_VAR_ADDR]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]]) +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 +// CHECK8-NEXT: br i1 [[TMP20]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP21]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP24:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP25]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done9: +// CHECK8-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* +// CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP28]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done11: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) +// CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK8: cond.true: +// CHECK8-NEXT: br label [[COND_END:%.*]] +// CHECK8: cond.false: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: br label [[COND_END]] +// CHECK8: cond.end: +// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK8-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK8: omp.inner.for.cond: +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK8: omp.inner.for.cond.cleanup: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK8: omp.inner.for.body: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] +// CHECK8-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* +// CHECK8-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) +// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK8: omp.body.continue: +// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK8: omp.inner.for.inc: +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK8: omp.inner.for.end: +// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK8: omp.loop.exit: +// CHECK8-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK8-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK8: .omp.lastprivate.then: +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP26]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* +// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP30]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* +// CHECK8-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done11: +// CHECK8-NEXT: [[TMP33:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* +// CHECK8-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP33]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) +// CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK8: .omp.lastprivate.done: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done13: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp @@ -3,17 +3,17 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2385,31 +2385,26 @@ // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[I2:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) // CHECK3-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK3: invoke.cont: // CHECK3-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont1: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 2) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR6:[0-9]+]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: lpad: // CHECK3-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } // CHECK3-NEXT: cleanup @@ -2417,54 +2412,55 @@ // CHECK3-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK3-NEXT: br label [[EH_RESUME:%.*]] -// CHECK3: for.end: +// CHECK3: omp_offload.cont: // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK3-NEXT: store i8 [[TMP5]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3:%.*]] -// CHECK3: for.cond3: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], 100 -// CHECK3-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK3: for.body5: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont6: -// CHECK3-NEXT: br label [[FOR_INC7:%.*]] -// CHECK3: for.inc7: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK3-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end9: -// CHECK3-NEXT: [[TMP8:%.*]] = load i8, i8* [[A]], align 1 -// CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK3-NEXT: [[CALL11:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() -// CHECK3-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK3: invoke.cont10: -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK3-NEXT: [[CALL13:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() -// CHECK3-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK3: invoke.cont12: -// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK3-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* +// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 +// CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK3-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK3-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1 +// CHECK3-NEXT: store i8 [[TMP14]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP16]]) +// CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK3-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP6]]) #[[ATTR6]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 +// CHECK3-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 +// CHECK3-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() +// CHECK3-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] +// CHECK3: invoke.cont5: +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] +// CHECK3-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] +// CHECK3: invoke.cont7: +// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] +// CHECK3-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 // CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP9]] +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK3-NEXT: ret i32 [[TMP20]] // CHECK3: eh.resume: // CHECK3-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 // CHECK3-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 // CHECK3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK3-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK3-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP10:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP11:%.*]] = extractvalue { i8*, i32 } [[TMP10]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7:[0-9]+]] -// CHECK3-NEXT: unreachable +// CHECK3-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 +// CHECK3-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El @@ -2492,119 +2488,389 @@ // CHECK3-NEXT: ret i8 [[CONV]] // // +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50 +// CHECK3-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// CHECK3: terminate.lpad: +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9:[0-9]+]] +// CHECK3-NEXT: unreachable +// +// // CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] +// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] // CHECK3-NEXT: unreachable // // -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK3-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 +// CHECK3-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK3-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK3-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 +// CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: invoke void @_Z3foov() // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK3: invoke.cont: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont5: -// CHECK3-NEXT: br label [[FOR_INC6:%.*]] -// CHECK3: for.inc6: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end8: -// CHECK3-NEXT: ret i32 0 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void // CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } // CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] // CHECK3-NEXT: unreachable // // +// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv +// CHECK3-SAME: () #[[ATTR2]] comdat { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 5) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR6]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 23) +// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR6]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: +// CHECK3-NEXT: ret i32 0 +// +// // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv // CHECK3-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK3-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3: omp_offload.failed: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK3: omp_offload.cont: +// CHECK3-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK3: invoke.cont: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont1: // CHECK3-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) // CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK3-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3:%.*]] -// CHECK3: for.cond3: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK3: for.body5: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont6: -// CHECK3-NEXT: br label [[FOR_INC7:%.*]] -// CHECK3: for.inc7: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end9: +// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 +// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 [[TMP3]]) +// CHECK3-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK3-NEXT: br i1 [[TMP5]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK3: omp_offload.failed2: +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR6]] +// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK3: omp_offload.cont3: // CHECK3-NEXT: ret i32 0 // CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: [[TMP6:%.*]] = landingpad { i8*, i32 } // CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] +// CHECK3-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP6]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP7]]) #[[ATTR9]] // CHECK3-NEXT: unreachable // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2614,7 +2880,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2627,8 +2893,628 @@ // CHECK3-NEXT: ret void // // +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36 +// CHECK3-SAME: () #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// CHECK3: terminate.lpad: +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] +// CHECK3-NEXT: unreachable +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 +// CHECK3-SAME: () #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// CHECK3: terminate.lpad: +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] +// CHECK3-NEXT: unreachable +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 +// CHECK3-SAME: () #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// CHECK3: terminate.lpad: +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] +// CHECK3-NEXT: unreachable +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 +// CHECK3-SAME: () #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 +// CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK3-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK3-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK3-NEXT: ret void +// CHECK3: lpad: +// CHECK3-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 +// CHECK3-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK3-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK3: terminate.handler: +// CHECK3-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR9]] +// CHECK3-NEXT: unreachable +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 +// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: invoke void @_Z3foov() +// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK3: invoke.cont: +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// CHECK3: terminate.lpad: +// CHECK3-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK3-NEXT: catch i8* null +// CHECK3-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] +// CHECK3-NEXT: unreachable +// +// // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2636,6 +3522,13 @@ // CHECK3-NEXT: ret void // // +// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK3-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK3-NEXT: ret void +// +// // CHECK4-LABEL: define {{[^@]+}}@main // CHECK4-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK4-NEXT: entry: @@ -2644,31 +3537,26 @@ // CHECK4-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK4-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[I2:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) // CHECK4-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK4: invoke.cont: // CHECK4-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont1: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 2) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR6:[0-9]+]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: lpad: // CHECK4-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } // CHECK4-NEXT: cleanup @@ -2676,54 +3564,55 @@ // CHECK4-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK4-NEXT: br label [[EH_RESUME:%.*]] -// CHECK4: for.end: +// CHECK4: omp_offload.cont: // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK4-NEXT: store i8 [[TMP5]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3:%.*]] -// CHECK4: for.cond3: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], 100 -// CHECK4-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK4: for.body5: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont6: -// CHECK4-NEXT: br label [[FOR_INC7:%.*]] -// CHECK4: for.inc7: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK4-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end9: -// CHECK4-NEXT: [[TMP8:%.*]] = load i8, i8* [[A]], align 1 -// CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK4-NEXT: [[CALL11:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() -// CHECK4-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK4: invoke.cont10: -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK4-NEXT: [[CALL13:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() -// CHECK4-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK4: invoke.cont12: -// CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK4-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* +// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 +// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK4-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK4-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1 +// CHECK4-NEXT: store i8 [[TMP14]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP16]]) +// CHECK4-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK4-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP6]]) #[[ATTR6]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 +// CHECK4-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 +// CHECK4-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() +// CHECK4-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] +// CHECK4: invoke.cont5: +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] +// CHECK4-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] +// CHECK4: invoke.cont7: +// CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] +// CHECK4-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 // CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP9]] +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK4-NEXT: ret i32 [[TMP20]] // CHECK4: eh.resume: // CHECK4-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 // CHECK4-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 // CHECK4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK4-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK4-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP10:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP11:%.*]] = extractvalue { i8*, i32 } [[TMP10]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7:[0-9]+]] -// CHECK4-NEXT: unreachable +// CHECK4-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 +// CHECK4-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1El @@ -2751,119 +3640,389 @@ // CHECK4-NEXT: ret i8 [[CONV]] // // +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50 +// CHECK4-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: invoke void @_Z3foov() +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// CHECK4: terminate.lpad: +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9:[0-9]+]] +// CHECK4-NEXT: unreachable +// +// // CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] +// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] // CHECK4-NEXT: unreachable // // -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK4-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 +// CHECK4-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK4-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK4-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 +// CHECK4-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: invoke void @_Z3foov() // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK4: invoke.cont: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont5: -// CHECK4-NEXT: br label [[FOR_INC6:%.*]] -// CHECK4: for.inc6: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end8: -// CHECK4-NEXT: ret i32 0 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void // CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } // CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] // CHECK4-NEXT: unreachable // // +// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv +// CHECK4-SAME: () #[[ATTR2]] comdat { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 5) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR6]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 23) +// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 +// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR6]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: +// CHECK4-NEXT: ret i32 0 +// +// // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv // CHECK4-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK4-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: invoke void @_Z3foov() +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) +// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK4: omp_offload.failed: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK4: omp_offload.cont: +// CHECK4-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK4: invoke.cont: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK4-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont1: // CHECK4-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) // CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK4-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3:%.*]] -// CHECK4: for.cond3: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK4: for.body5: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont6: -// CHECK4-NEXT: br label [[FOR_INC7:%.*]] -// CHECK4: for.inc7: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end9: +// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 +// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) +// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 [[TMP3]]) +// CHECK4-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK4-NEXT: br i1 [[TMP5]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK4: omp_offload.failed2: +// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR6]] +// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK4: omp_offload.cont3: // CHECK4-NEXT: ret i32 0 // CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: [[TMP6:%.*]] = landingpad { i8*, i32 } // CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] +// CHECK4-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP6]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP7]]) #[[ATTR9]] // CHECK4-NEXT: unreachable // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2873,7 +4032,7 @@ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2886,8 +4045,628 @@ // CHECK4-NEXT: ret void // // +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36 +// CHECK4-SAME: () #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: invoke void @_Z3foov() +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// CHECK4: terminate.lpad: +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] +// CHECK4-NEXT: unreachable +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 +// CHECK4-SAME: () #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: invoke void @_Z3foov() +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// CHECK4: terminate.lpad: +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] +// CHECK4-NEXT: unreachable +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 +// CHECK4-SAME: () #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: invoke void @_Z3foov() +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// CHECK4: terminate.lpad: +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] +// CHECK4-NEXT: unreachable +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 +// CHECK4-SAME: () #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 +// CHECK4-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 +// CHECK4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK4-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK4-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK4-NEXT: ret void +// CHECK4: lpad: +// CHECK4-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 +// CHECK4-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK4-NEXT: br label [[TERMINATE_HANDLER:%.*]] +// CHECK4: terminate.handler: +// CHECK4-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR9]] +// CHECK4-NEXT: unreachable +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 +// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: invoke void @_Z3foov() +// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] +// CHECK4: invoke.cont: +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// CHECK4: terminate.lpad: +// CHECK4-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } +// CHECK4-NEXT: catch i8* null +// CHECK4-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 +// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] +// CHECK4-NEXT: unreachable +// +// // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2895,2824 +4674,9 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK5-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 2) -// CHECK5-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK5-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR6:[0-9]+]] -// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK5: lpad: -// CHECK5-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: cleanup -// CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK5-NEXT: br label [[EH_RESUME:%.*]] -// CHECK5: omp_offload.cont: -// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* -// CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 -// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1 -// CHECK5-NEXT: store i8 [[TMP14]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK5-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP16]]) -// CHECK5-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 -// CHECK5-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK5: omp_offload.failed2: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP6]]) #[[ATTR6]] -// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK5: omp_offload.cont3: -// CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 -// CHECK5-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK5-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() -// CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] -// CHECK5: invoke.cont5: -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK5-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() -// CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] -// CHECK5: invoke.cont7: -// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] -// CHECK5-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP20]] -// CHECK5: eh.resume: -// CHECK5-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK5-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK5-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK5-NEXT: ret i8 [[CONV]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50 -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK5: omp.body.continue: -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK5-NEXT: ret void -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9:[0-9]+]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* -// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK5: omp.body.continue: -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK5-NEXT: ret void -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK5-SAME: () #[[ATTR2]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 5) -// CHECK5-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK5-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR6]] -// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK5: omp_offload.cont: -// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK5-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 23) -// CHECK5-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK5-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK5: omp_offload.failed2: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR6]] -// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK5: omp_offload.cont3: -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK5-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK5-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK5-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] -// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK5: omp_offload.cont: -// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK5-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 [[TMP3]]) -// CHECK5-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK5-NEXT: br i1 [[TMP5]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK5: omp_offload.failed2: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR6]] -// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK5: omp_offload.cont3: -// CHECK5-NEXT: ret i32 0 -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP6:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP6]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP7]]) #[[ATTR9]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK5-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36 -// CHECK5-SAME: () #[[ATTR3]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK5: omp.body.continue: -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK5-NEXT: ret void -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 -// CHECK5-SAME: () #[[ATTR3]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK5: omp.body.continue: -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK5-NEXT: ret void -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 -// CHECK5-SAME: () #[[ATTR3]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK5: omp.body.continue: -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK5-NEXT: ret void -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 -// CHECK5-SAME: () #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK5-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK5-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 -// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK5-NEXT: ret void -// CHECK5: lpad: -// CHECK5-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK5: terminate.handler: -// CHECK5-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR9]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK5: omp.body.continue: -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK5-NEXT: ret void -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK5-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK6-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK6-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 100) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 2) -// CHECK6-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK6-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK6: omp_offload.failed: -// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR6:[0-9]+]] -// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK6: lpad: -// CHECK6-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: cleanup -// CHECK6-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK6-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK6-NEXT: br label [[EH_RESUME:%.*]] -// CHECK6: omp_offload.cont: -// CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* -// CHECK6-NEXT: store i8 [[TMP5]], i8* [[CONV]], align 1 -// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP8]], align 8 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP10]], align 8 -// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1 -// CHECK6-NEXT: store i8 [[TMP14]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 -// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK6-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, i32 1, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP16]]) -// CHECK6-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 -// CHECK6-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK6: omp_offload.failed2: -// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP6]]) #[[ATTR6]] -// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK6: omp_offload.cont3: -// CHECK6-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 -// CHECK6-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK6-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() -// CHECK6-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] -// CHECK6: invoke.cont5: -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK6-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() -// CHECK6-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] -// CHECK6: invoke.cont7: -// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] -// CHECK6-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP20]] -// CHECK6: eh.resume: -// CHECK6-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK6-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK6-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK6-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK6-NEXT: resume { i8*, i32 } [[LPAD_VAL10]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK6-NEXT: ret i8 [[CONV]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50 -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK6: omp.body.continue: -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK6-NEXT: ret void -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null -// CHECK6-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9:[0-9]+]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK6-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* -// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK6-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK6-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK6: omp.body.continue: -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK6-NEXT: ret void -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null -// CHECK6-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK6-SAME: () #[[ATTR2]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 5) -// CHECK6-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK6-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK6: omp_offload.failed: -// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR6]] -// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK6: omp_offload.cont: -// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 23) -// CHECK6-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK6-NEXT: br i1 [[TMP3]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK6: omp_offload.failed2: -// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR6]] -// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK6: omp_offload.cont3: -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK6-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) -// CHECK6-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK6-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK6: omp_offload.failed: -// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] -// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK6: omp_offload.cont: -// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK6-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 -// CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 100) -// CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 [[TMP3]]) -// CHECK6-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK6-NEXT: br i1 [[TMP5]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] -// CHECK6: omp_offload.failed2: -// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR6]] -// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT3]] -// CHECK6: omp_offload.cont3: -// CHECK6-NEXT: ret i32 0 -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP6:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null -// CHECK6-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP6]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP7]]) #[[ATTR9]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK6-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36 -// CHECK6-SAME: () #[[ATTR3]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK6: omp.body.continue: -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK6-NEXT: ret void -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null -// CHECK6-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 -// CHECK6-SAME: () #[[ATTR3]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK6: omp.body.continue: -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK6-NEXT: ret void -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null -// CHECK6-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 -// CHECK6-SAME: () #[[ATTR3]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK6: omp.body.continue: -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK6-NEXT: ret void -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null -// CHECK6-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 -// CHECK6-SAME: () #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK6-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK6-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* -// CHECK6-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 -// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK6-NEXT: ret void -// CHECK6: lpad: -// CHECK6-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null -// CHECK6-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK6-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK6-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK6: terminate.handler: -// CHECK6-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR9]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK6: cond.true: -// CHECK6-NEXT: br label [[COND_END:%.*]] -// CHECK6: cond.false: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: br label [[COND_END]] -// CHECK6: cond.end: -// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK6: omp.body.continue: -// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK6: omp.inner.for.end: -// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK6: omp.loop.exit: -// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK6-NEXT: ret void -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null -// CHECK6-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK6-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK7-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont1: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: lpad: -// CHECK7-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: cleanup -// CHECK7-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK7-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] -// CHECK7-NEXT: br label [[EH_RESUME:%.*]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK7-NEXT: store i8 [[TMP5]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], 100 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont6: -// CHECK7-NEXT: br label [[FOR_INC7:%.*]] -// CHECK7: for.inc7: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end9: -// CHECK7-NEXT: [[TMP8:%.*]] = load i8, i8* [[A]], align 1 -// CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK7-NEXT: [[CALL11:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() -// CHECK7-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK7: invoke.cont10: -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK7-NEXT: [[CALL13:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() -// CHECK7-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK7: invoke.cont12: -// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK7-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// CHECK7: eh.resume: -// CHECK7-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK7-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK7-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK7-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP10:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP11:%.*]] = extractvalue { i8*, i32 } [[TMP10]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7:[0-9]+]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK7-NEXT: ret i8 [[CONV]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK7-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont5: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: ret i32 0 -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK7-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK7-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont1: -// CHECK7-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK7-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont6: -// CHECK7-NEXT: br label [[FOR_INC7:%.*]] -// CHECK7: for.inc7: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end9: -// CHECK7-NEXT: ret i32 0 -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK8-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[S]], i64 0) -// CHECK8-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[S]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont1: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: lpad: -// CHECK8-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: cleanup -// CHECK8-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK8-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] -// CHECK8-NEXT: br label [[EH_RESUME:%.*]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK8-NEXT: store i8 [[TMP5]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], 100 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont6: -// CHECK8-NEXT: br label [[FOR_INC7:%.*]] -// CHECK8: for.inc7: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end9: -// CHECK8-NEXT: [[TMP8:%.*]] = load i8, i8* [[A]], align 1 -// CHECK8-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK8-NEXT: [[CALL11:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() -// CHECK8-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK8: invoke.cont10: -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK8-NEXT: [[CALL13:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() -// CHECK8-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK8: invoke.cont12: -// CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK8-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// CHECK8: eh.resume: -// CHECK8-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK8-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK8-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK8-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP10:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP11:%.*]] = extractvalue { i8*, i32 } [[TMP10]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7:[0-9]+]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SC2El(%struct.S* nonnull dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK8-NEXT: ret i8 [[CONV]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK8-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont5: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: ret i32 0 -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK8-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK8-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont1: -// CHECK8-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK8-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont6: -// CHECK8-NEXT: br label [[FOR_INC7:%.*]] -// CHECK8: for.inc7: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end9: -// CHECK8-NEXT: ret i32 0 -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void +// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK4-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK4-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2918,6 +2918,28 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: @@ -2956,191 +2978,6 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done8: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK5: arraydestroy.body10: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK5: arraydestroy.done14: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP11]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: @@ -3158,73 +2995,190 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 +// CHECK5-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* undef, i32** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* undef, i32** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[SIVAR]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK5-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK5-NEXT: ret void // // @@ -3237,6 +3191,13 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: @@ -3265,6 +3226,28 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: @@ -3303,191 +3286,6 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done8: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK6: arraydestroy.body10: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK6: arraydestroy.done14: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP11]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: @@ -3505,73 +3303,190 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK6-NEXT: ret i32 0 // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 +// CHECK6-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* undef, i32** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* undef, i32** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[SIVAR]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK6-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK6-NEXT: ret void // // @@ -3584,1568 +3499,9 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK7-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK7-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done7: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK7: arraydestroy.body9: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK7: arraydestroy.done13: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP11]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK8-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done7: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK8: arraydestroy.body9: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK8: arraydestroy.done13: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP11]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 -// CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init() -// CHECK9-NEXT: call void @__cxx_global_var_init.1() -// CHECK9-NEXT: call void @__cxx_global_var_init.2() -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 -// CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__cxx_global_var_init() -// CHECK10-NEXT: call void @__cxx_global_var_init.1() -// CHECK10-NEXT: call void @__cxx_global_var_init.2() -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp @@ -5,9 +5,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -975,123 +975,3 @@ // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret i32 0 -// diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2365,784 +2365,532 @@ // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 +// CHECK5-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* +// CHECK5-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK5-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK5-NEXT: ] +// CHECK5: .omp.reduction.case1: +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK5: .omp.reduction.case2: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK5: .omp.reduction.default: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[SIVAR2]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR2]] to i8* +// CHECK5-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK5-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK5-NEXT: ] +// CHECK5: .omp.reduction.case1: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR2]], align 4 +// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK5-NEXT: store i32 [[ADD6]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK5: .omp.reduction.case2: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR2]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4 +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK5: .omp.reduction.default: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK5-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK5-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK5-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK5-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK9-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* -// CHECK9-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK9-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK9-NEXT: ] -// CHECK9: .omp.reduction.case1: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.case2: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.default: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[SIVAR2]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR2]] to i8* -// CHECK9-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK9-NEXT: ] -// CHECK9: .omp.reduction.case1: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR2]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.case2: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR2]], align 4 -// CHECK9-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4 -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.default: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK9-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK9-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK10-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* -// CHECK10-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK10-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK10-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK10-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK10-NEXT: ] -// CHECK10: .omp.reduction.case1: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK10: .omp.reduction.case2: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 -// CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK10: .omp.reduction.default: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK10-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[SIVAR2]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR2]] to i8* -// CHECK10-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK10-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK10-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK10-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK10-NEXT: ] -// CHECK10: .omp.reduction.case1: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR2]], align 4 -// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK10: .omp.reduction.case2: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR2]], align 4 -// CHECK10-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4 -// CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK10: .omp.reduction.default: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK10-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK10-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 +// CHECK6-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* +// CHECK6-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK6-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.reduction.case1: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.case2: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.default: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK6-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[SIVAR2]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR2]] to i8* +// CHECK6-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK6-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.reduction.case1: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR2]], align 4 +// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK6-NEXT: store i32 [[ADD6]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.case2: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR2]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4 +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.default: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1909,62 +1909,3 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG23:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG23]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG24:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG25:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG27:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG29:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG31:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG31]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG31]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG32:![0-9]+]], !llvm.loop [[LOOP33:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG36]] -// diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp @@ -18,12 +18,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -87,26 +87,26 @@ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -7416,474 +7416,9718 @@ // CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK9-LABEL: define {{[^@]+}}@main +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK9-NEXT: ret i32 [[CALL]] +// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK9-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES24:%.*]] = alloca [4 x i64], align 8 +// CHECK9-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N_CASTED34:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS36:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS37:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS38:%.*]] = alloca [3 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES39:%.*]] = alloca [3 x i64], align 8 +// CHECK9-NEXT: [[_TMP40:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_41:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_42:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[M_CASTED49:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_CASTED51:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS53:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS54:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS55:%.*]] = alloca [4 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES56:%.*]] = alloca [4 x i64], align 8 +// CHECK9-NEXT: [[_TMP57:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_59:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK9-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK9-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK9-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK9-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK9-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK9-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK9-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK9-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) +// CHECK9-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK9-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK9: omp_offload.failed16: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK9: omp_offload.cont17: +// CHECK9-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 +// CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP63]], i32* [[CONV18]], align 4 +// CHECK9-NEXT: [[TMP64:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK9-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* +// CHECK9-NEXT: store i32 [[TMP65]], i32* [[CONV20]], align 4 +// CHECK9-NEXT: [[TMP66:%.*]] = load i64, i64* [[N_CASTED19]], align 8 +// CHECK9-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK9-NEXT: [[TMP68:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* +// CHECK9-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 +// CHECK9-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* +// CHECK9-NEXT: store i64 [[TMP64]], i64* [[TMP71]], align 8 +// CHECK9-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP72]], align 8 +// CHECK9-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP73]], align 8 +// CHECK9-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* +// CHECK9-NEXT: store i64 [[TMP66]], i64* [[TMP75]], align 8 +// CHECK9-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* +// CHECK9-NEXT: store i64 [[TMP66]], i64* [[TMP77]], align 8 +// CHECK9-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 1 +// CHECK9-NEXT: store i64 4, i64* [[TMP78]], align 8 +// CHECK9-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP81]], align 8 +// CHECK9-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP83]], align 8 +// CHECK9-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP84]], align 8 +// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP85]], align 8 +// CHECK9-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP87]], align 8 +// CHECK9-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 8 +// CHECK9-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 3 +// CHECK9-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 +// CHECK9-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP91]], align 8 +// CHECK9-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP95:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP95]], i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK9-NEXT: [[TMP96:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK9-NEXT: [[SUB28:%.*]] = sub nsw i32 [[TMP96]], 0 +// CHECK9-NEXT: [[DIV29:%.*]] = sdiv i32 [[SUB28]], 1 +// CHECK9-NEXT: [[SUB30:%.*]] = sub nsw i32 [[DIV29]], 1 +// CHECK9-NEXT: store i32 [[SUB30]], i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK9-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK9-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP97]], 1 +// CHECK9-NEXT: [[TMP98:%.*]] = zext i32 [[ADD31]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP98]]) +// CHECK9-NEXT: [[TMP99:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158.region_id, i32 4, i8** [[TMP92]], i8** [[TMP93]], i64* [[TMP94]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP100:%.*]] = icmp ne i32 [[TMP99]], 0 +// CHECK9-NEXT: br i1 [[TMP100]], label [[OMP_OFFLOAD_FAILED32:%.*]], label [[OMP_OFFLOAD_CONT33:%.*]] +// CHECK9: omp_offload.failed32: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158(i64 [[TMP64]], i64 [[TMP66]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]] +// CHECK9: omp_offload.cont33: +// CHECK9-NEXT: [[TMP101:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[CONV35:%.*]] = bitcast i64* [[N_CASTED34]] to i32* +// CHECK9-NEXT: store i32 [[TMP101]], i32* [[CONV35]], align 4 +// CHECK9-NEXT: [[TMP102:%.*]] = load i64, i64* [[N_CASTED34]], align 8 +// CHECK9-NEXT: [[TMP103:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK9-NEXT: [[TMP104:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64* +// CHECK9-NEXT: store i64 [[TMP102]], i64* [[TMP105]], align 8 +// CHECK9-NEXT: [[TMP106:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* +// CHECK9-NEXT: store i64 [[TMP102]], i64* [[TMP107]], align 8 +// CHECK9-NEXT: [[TMP108:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP108]], align 8 +// CHECK9-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP109]], align 8 +// CHECK9-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP111]], align 8 +// CHECK9-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP113]], align 8 +// CHECK9-NEXT: [[TMP114:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 1 +// CHECK9-NEXT: store i64 8, i64* [[TMP114]], align 8 +// CHECK9-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP115]], align 8 +// CHECK9-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP117]], align 8 +// CHECK9-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP119]], align 8 +// CHECK9-NEXT: [[TMP120:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 2 +// CHECK9-NEXT: store i64 [[TMP103]], i64* [[TMP120]], align 8 +// CHECK9-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP121]], align 8 +// CHECK9-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP125:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP125]], i32* [[DOTCAPTURE_EXPR_41]], align 4 +// CHECK9-NEXT: [[TMP126:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_41]], align 4 +// CHECK9-NEXT: [[SUB43:%.*]] = sub nsw i32 [[TMP126]], 0 +// CHECK9-NEXT: [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1 +// CHECK9-NEXT: [[SUB45:%.*]] = sub nsw i32 [[DIV44]], 1 +// CHECK9-NEXT: store i32 [[SUB45]], i32* [[DOTCAPTURE_EXPR_42]], align 4 +// CHECK9-NEXT: [[TMP127:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_42]], align 4 +// CHECK9-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP127]], 1 +// CHECK9-NEXT: [[TMP128:%.*]] = zext i32 [[ADD46]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP128]]) +// CHECK9-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163.region_id, i32 3, i8** [[TMP122]], i8** [[TMP123]], i64* [[TMP124]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0 +// CHECK9-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]] +// CHECK9: omp_offload.failed47: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163(i64 [[TMP102]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT48]] +// CHECK9: omp_offload.cont48: +// CHECK9-NEXT: [[TMP131:%.*]] = load i32, i32* [[M]], align 4 +// CHECK9-NEXT: [[CONV50:%.*]] = bitcast i64* [[M_CASTED49]] to i32* +// CHECK9-NEXT: store i32 [[TMP131]], i32* [[CONV50]], align 4 +// CHECK9-NEXT: [[TMP132:%.*]] = load i64, i64* [[M_CASTED49]], align 8 +// CHECK9-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: [[CONV52:%.*]] = bitcast i64* [[N_CASTED51]] to i32* +// CHECK9-NEXT: store i32 [[TMP133]], i32* [[CONV52]], align 4 +// CHECK9-NEXT: [[TMP134:%.*]] = load i64, i64* [[N_CASTED51]], align 8 +// CHECK9-NEXT: [[TMP135:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK9-NEXT: [[TMP136:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64* +// CHECK9-NEXT: store i64 [[TMP132]], i64* [[TMP137]], align 8 +// CHECK9-NEXT: [[TMP138:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to i64* +// CHECK9-NEXT: store i64 [[TMP132]], i64* [[TMP139]], align 8 +// CHECK9-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 0 +// CHECK9-NEXT: store i64 4, i64* [[TMP140]], align 8 +// CHECK9-NEXT: [[TMP141:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP141]], align 8 +// CHECK9-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i64* +// CHECK9-NEXT: store i64 [[TMP134]], i64* [[TMP143]], align 8 +// CHECK9-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i64* +// CHECK9-NEXT: store i64 [[TMP134]], i64* [[TMP145]], align 8 +// CHECK9-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 1 +// CHECK9-NEXT: store i64 4, i64* [[TMP146]], align 8 +// CHECK9-NEXT: [[TMP147:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP147]], align 8 +// CHECK9-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP149]], align 8 +// CHECK9-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP151]], align 8 +// CHECK9-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP152]], align 8 +// CHECK9-NEXT: [[TMP153:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP153]], align 8 +// CHECK9-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP155]], align 8 +// CHECK9-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** +// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP157]], align 8 +// CHECK9-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 3 +// CHECK9-NEXT: store i64 [[TMP135]], i64* [[TMP158]], align 8 +// CHECK9-NEXT: [[TMP159:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP159]], align 8 +// CHECK9-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP161:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP163:%.*]] = load i32, i32* [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP163]], i32* [[DOTCAPTURE_EXPR_58]], align 4 +// CHECK9-NEXT: [[TMP164:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_58]], align 4 +// CHECK9-NEXT: [[SUB60:%.*]] = sub nsw i32 [[TMP164]], 0 +// CHECK9-NEXT: [[DIV61:%.*]] = sdiv i32 [[SUB60]], 1 +// CHECK9-NEXT: [[SUB62:%.*]] = sub nsw i32 [[DIV61]], 1 +// CHECK9-NEXT: store i32 [[SUB62]], i32* [[DOTCAPTURE_EXPR_59]], align 4 +// CHECK9-NEXT: [[TMP165:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_59]], align 4 +// CHECK9-NEXT: [[ADD63:%.*]] = add nsw i32 [[TMP165]], 1 +// CHECK9-NEXT: [[TMP166:%.*]] = zext i32 [[ADD63]] to i64 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP166]]) +// CHECK9-NEXT: [[TMP167:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168.region_id, i32 4, i8** [[TMP160]], i8** [[TMP161]], i64* [[TMP162]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP168:%.*]] = icmp ne i32 [[TMP167]], 0 +// CHECK9-NEXT: br i1 [[TMP168]], label [[OMP_OFFLOAD_FAILED64:%.*]], label [[OMP_OFFLOAD_CONT65:%.*]] +// CHECK9: omp_offload.failed64: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i64 [[TMP132]], i64 [[TMP134]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT65]] +// CHECK9: omp_offload.cont65: +// CHECK9-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) +// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK9-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) +// CHECK9-NEXT: [[TMP171:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK9-NEXT: ret i32 [[TMP171]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 +// CHECK9-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] +// CHECK9-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] +// CHECK9: cond.true12: +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: br label [[COND_END14:%.*]] +// CHECK9: cond.false13: +// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END14]] +// CHECK9: cond.end14: +// CHECK9-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE12]] ], [ [[TMP32]], [[COND_FALSE13]] ] +// CHECK9-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK9-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 +// CHECK9-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK9: omp.precond.then: +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: br label [[OMP_PRECOND_END]] +// CHECK9: omp.precond.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 8 +// CHECK9-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[M_CASTED19:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [2 x i8*], align 8 +// CHECK9-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK9-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK9: omp_offload.failed5: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK9: omp_offload.cont6: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK9-NEXT: store i64 [[TMP19]], i64* [[TMP21]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK9-NEXT: store i64 [[TMP19]], i64* [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 8 +// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK9: omp_offload.failed11: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126(i64 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK9: omp_offload.cont12: +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP35]], align 8 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP37]], align 8 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP38]], align 8 +// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131.region_id, i32 1, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK9-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK9: omp_offload.failed17: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK9: omp_offload.cont18: +// CHECK9-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 +// CHECK9-NEXT: [[CONV20:%.*]] = bitcast i64* [[M_CASTED19]] to i32* +// CHECK9-NEXT: store i32 [[TMP43]], i32* [[CONV20]], align 4 +// CHECK9-NEXT: [[TMP44:%.*]] = load i64, i64* [[M_CASTED19]], align 8 +// CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* +// CHECK9-NEXT: store i64 [[TMP44]], i64* [[TMP46]], align 8 +// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* +// CHECK9-NEXT: store i64 [[TMP44]], i64* [[TMP48]], align 8 +// CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP49]], align 8 +// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP51]], align 8 +// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to [10 x i32]** +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP53]], align 8 +// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP54]], align 8 +// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK9-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 +// CHECK9-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] +// CHECK9: omp_offload.failed25: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136(i64 [[TMP44]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT26]] +// CHECK9: omp_offload.cont26: +// CHECK9-NEXT: ret i32 0 +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I22:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I32:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3:%.*]] -// CHECK9: for.cond3: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK9-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK9: for.body5: -// CHECK9-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK9-NEXT: br label [[FOR_INC9:%.*]] -// CHECK9: for.inc9: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK9-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK9: for.end11: -// CHECK9-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK9-NEXT: br label [[FOR_COND13:%.*]] -// CHECK9: for.cond13: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK9-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK9: for.body15: -// CHECK9-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK9-NEXT: br label [[FOR_INC19:%.*]] -// CHECK9: for.inc19: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK9-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end21: -// CHECK9-NEXT: store i32 0, i32* [[I22]], align 4 -// CHECK9-NEXT: br label [[FOR_COND23:%.*]] -// CHECK9: for.cond23: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[CMP24:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK9-NEXT: br i1 [[CMP24]], label [[FOR_BODY25:%.*]], label [[FOR_END31:%.*]] -// CHECK9: for.body25: -// CHECK9-NEXT: [[A26:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[IDXPROM27:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A26]], i64 0, i64 [[IDXPROM27]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX28]], align 4 -// CHECK9-NEXT: br label [[FOR_INC29:%.*]] -// CHECK9: for.inc29: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK9-NEXT: store i32 [[INC30]], i32* [[I22]], align 4 -// CHECK9-NEXT: br label [[FOR_COND23]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK9: for.end31: -// CHECK9-NEXT: store i32 0, i32* [[I32]], align 4 -// CHECK9-NEXT: br label [[FOR_COND33:%.*]] -// CHECK9: for.cond33: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[CMP34:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK9-NEXT: br i1 [[CMP34]], label [[FOR_BODY35:%.*]], label [[FOR_END41:%.*]] -// CHECK9: for.body35: -// CHECK9-NEXT: [[A36:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A36]], i64 0, i64 [[IDXPROM37]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK9-NEXT: br label [[FOR_INC39:%.*]] -// CHECK9: for.inc39: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[INC40:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[INC40]], i32* [[I32]], align 4 -// CHECK9-NEXT: br label [[FOR_COND33]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK9: for.end41: -// CHECK9-NEXT: [[A42:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A42]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX43]], align 4 -// CHECK9-NEXT: ret i32 [[TMP15]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK10-NEXT: ret i32 [[CALL]] +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 +// CHECK9-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..21 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[CONV3]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CONV4:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ] +// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[COND]] to i32 +// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..25 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 +// CHECK9-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK9: cond.true: +// CHECK9-NEXT: br label [[COND_END:%.*]] +// CHECK9: cond.false: +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: br label [[COND_END]] +// CHECK9: cond.end: +// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK9: omp.loop.exit: +// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK9-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK9: omp.dispatch.cond: +// CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK9: omp.dispatch.body: +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK9: omp.inner.for.cond: +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK9: omp.inner.for.body: +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK9: omp.body.continue: +// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK9: omp.inner.for.inc: +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK9: omp.inner.for.end: +// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK9: omp.dispatch.inc: +// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK9: omp.dispatch.end: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@main +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 +// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 +// CHECK10-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES24:%.*]] = alloca [4 x i64], align 8 +// CHECK10-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED34:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS36:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS37:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS38:%.*]] = alloca [3 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES39:%.*]] = alloca [3 x i64], align 8 +// CHECK10-NEXT: [[_TMP40:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_41:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_42:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[M_CASTED49:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_CASTED51:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS53:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS54:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS55:%.*]] = alloca [4 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES56:%.*]] = alloca [4 x i64], align 8 +// CHECK10-NEXT: [[_TMP57:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_59:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 +// CHECK10-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 8, i64* [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* +// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 +// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 +// CHECK10-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP40]], align 8 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 +// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 +// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 +// CHECK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 +// CHECK10-NEXT: store i64 8, i64* [[TMP46]], align 8 +// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP47]], align 8 +// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 +// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 +// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 +// CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 +// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP53]], align 8 +// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK10-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 +// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK10-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 +// CHECK10-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK10-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 +// CHECK10-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) +// CHECK10-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 +// CHECK10-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK10: omp_offload.failed16: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK10: omp_offload.cont17: +// CHECK10-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 +// CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP63]], i32* [[CONV18]], align 4 +// CHECK10-NEXT: [[TMP64:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK10-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* +// CHECK10-NEXT: store i32 [[TMP65]], i32* [[CONV20]], align 4 +// CHECK10-NEXT: [[TMP66:%.*]] = load i64, i64* [[N_CASTED19]], align 8 +// CHECK10-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK10-NEXT: [[TMP68:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* +// CHECK10-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 +// CHECK10-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* +// CHECK10-NEXT: store i64 [[TMP64]], i64* [[TMP71]], align 8 +// CHECK10-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP72]], align 8 +// CHECK10-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP73]], align 8 +// CHECK10-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* +// CHECK10-NEXT: store i64 [[TMP66]], i64* [[TMP75]], align 8 +// CHECK10-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* +// CHECK10-NEXT: store i64 [[TMP66]], i64* [[TMP77]], align 8 +// CHECK10-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 1 +// CHECK10-NEXT: store i64 4, i64* [[TMP78]], align 8 +// CHECK10-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP81]], align 8 +// CHECK10-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP83]], align 8 +// CHECK10-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP84]], align 8 +// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP85]], align 8 +// CHECK10-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP87]], align 8 +// CHECK10-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 8 +// CHECK10-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 3 +// CHECK10-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 +// CHECK10-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP91]], align 8 +// CHECK10-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP95:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP95]], i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK10-NEXT: [[TMP96:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 +// CHECK10-NEXT: [[SUB28:%.*]] = sub nsw i32 [[TMP96]], 0 +// CHECK10-NEXT: [[DIV29:%.*]] = sdiv i32 [[SUB28]], 1 +// CHECK10-NEXT: [[SUB30:%.*]] = sub nsw i32 [[DIV29]], 1 +// CHECK10-NEXT: store i32 [[SUB30]], i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK10-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 +// CHECK10-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP97]], 1 +// CHECK10-NEXT: [[TMP98:%.*]] = zext i32 [[ADD31]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP98]]) +// CHECK10-NEXT: [[TMP99:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158.region_id, i32 4, i8** [[TMP92]], i8** [[TMP93]], i64* [[TMP94]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP100:%.*]] = icmp ne i32 [[TMP99]], 0 +// CHECK10-NEXT: br i1 [[TMP100]], label [[OMP_OFFLOAD_FAILED32:%.*]], label [[OMP_OFFLOAD_CONT33:%.*]] +// CHECK10: omp_offload.failed32: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158(i64 [[TMP64]], i64 [[TMP66]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT33]] +// CHECK10: omp_offload.cont33: +// CHECK10-NEXT: [[TMP101:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[CONV35:%.*]] = bitcast i64* [[N_CASTED34]] to i32* +// CHECK10-NEXT: store i32 [[TMP101]], i32* [[CONV35]], align 4 +// CHECK10-NEXT: [[TMP102:%.*]] = load i64, i64* [[N_CASTED34]], align 8 +// CHECK10-NEXT: [[TMP103:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK10-NEXT: [[TMP104:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64* +// CHECK10-NEXT: store i64 [[TMP102]], i64* [[TMP105]], align 8 +// CHECK10-NEXT: [[TMP106:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* +// CHECK10-NEXT: store i64 [[TMP102]], i64* [[TMP107]], align 8 +// CHECK10-NEXT: [[TMP108:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP108]], align 8 +// CHECK10-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP109]], align 8 +// CHECK10-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP111]], align 8 +// CHECK10-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP113]], align 8 +// CHECK10-NEXT: [[TMP114:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 1 +// CHECK10-NEXT: store i64 8, i64* [[TMP114]], align 8 +// CHECK10-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP115]], align 8 +// CHECK10-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP117]], align 8 +// CHECK10-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP119]], align 8 +// CHECK10-NEXT: [[TMP120:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 2 +// CHECK10-NEXT: store i64 [[TMP103]], i64* [[TMP120]], align 8 +// CHECK10-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP121]], align 8 +// CHECK10-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP125:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP125]], i32* [[DOTCAPTURE_EXPR_41]], align 4 +// CHECK10-NEXT: [[TMP126:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_41]], align 4 +// CHECK10-NEXT: [[SUB43:%.*]] = sub nsw i32 [[TMP126]], 0 +// CHECK10-NEXT: [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1 +// CHECK10-NEXT: [[SUB45:%.*]] = sub nsw i32 [[DIV44]], 1 +// CHECK10-NEXT: store i32 [[SUB45]], i32* [[DOTCAPTURE_EXPR_42]], align 4 +// CHECK10-NEXT: [[TMP127:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_42]], align 4 +// CHECK10-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP127]], 1 +// CHECK10-NEXT: [[TMP128:%.*]] = zext i32 [[ADD46]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP128]]) +// CHECK10-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163.region_id, i32 3, i8** [[TMP122]], i8** [[TMP123]], i64* [[TMP124]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0 +// CHECK10-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]] +// CHECK10: omp_offload.failed47: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163(i64 [[TMP102]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT48]] +// CHECK10: omp_offload.cont48: +// CHECK10-NEXT: [[TMP131:%.*]] = load i32, i32* [[M]], align 4 +// CHECK10-NEXT: [[CONV50:%.*]] = bitcast i64* [[M_CASTED49]] to i32* +// CHECK10-NEXT: store i32 [[TMP131]], i32* [[CONV50]], align 4 +// CHECK10-NEXT: [[TMP132:%.*]] = load i64, i64* [[M_CASTED49]], align 8 +// CHECK10-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: [[CONV52:%.*]] = bitcast i64* [[N_CASTED51]] to i32* +// CHECK10-NEXT: store i32 [[TMP133]], i32* [[CONV52]], align 4 +// CHECK10-NEXT: [[TMP134:%.*]] = load i64, i64* [[N_CASTED51]], align 8 +// CHECK10-NEXT: [[TMP135:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK10-NEXT: [[TMP136:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64* +// CHECK10-NEXT: store i64 [[TMP132]], i64* [[TMP137]], align 8 +// CHECK10-NEXT: [[TMP138:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to i64* +// CHECK10-NEXT: store i64 [[TMP132]], i64* [[TMP139]], align 8 +// CHECK10-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 0 +// CHECK10-NEXT: store i64 4, i64* [[TMP140]], align 8 +// CHECK10-NEXT: [[TMP141:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP141]], align 8 +// CHECK10-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i64* +// CHECK10-NEXT: store i64 [[TMP134]], i64* [[TMP143]], align 8 +// CHECK10-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i64* +// CHECK10-NEXT: store i64 [[TMP134]], i64* [[TMP145]], align 8 +// CHECK10-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 1 +// CHECK10-NEXT: store i64 4, i64* [[TMP146]], align 8 +// CHECK10-NEXT: [[TMP147:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP147]], align 8 +// CHECK10-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP149]], align 8 +// CHECK10-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP151]], align 8 +// CHECK10-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP152]], align 8 +// CHECK10-NEXT: [[TMP153:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP153]], align 8 +// CHECK10-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP155]], align 8 +// CHECK10-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** +// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP157]], align 8 +// CHECK10-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 3 +// CHECK10-NEXT: store i64 [[TMP135]], i64* [[TMP158]], align 8 +// CHECK10-NEXT: [[TMP159:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP159]], align 8 +// CHECK10-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP161:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP163:%.*]] = load i32, i32* [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP163]], i32* [[DOTCAPTURE_EXPR_58]], align 4 +// CHECK10-NEXT: [[TMP164:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_58]], align 4 +// CHECK10-NEXT: [[SUB60:%.*]] = sub nsw i32 [[TMP164]], 0 +// CHECK10-NEXT: [[DIV61:%.*]] = sdiv i32 [[SUB60]], 1 +// CHECK10-NEXT: [[SUB62:%.*]] = sub nsw i32 [[DIV61]], 1 +// CHECK10-NEXT: store i32 [[SUB62]], i32* [[DOTCAPTURE_EXPR_59]], align 4 +// CHECK10-NEXT: [[TMP165:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_59]], align 4 +// CHECK10-NEXT: [[ADD63:%.*]] = add nsw i32 [[TMP165]], 1 +// CHECK10-NEXT: [[TMP166:%.*]] = zext i32 [[ADD63]] to i64 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP166]]) +// CHECK10-NEXT: [[TMP167:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168.region_id, i32 4, i8** [[TMP160]], i8** [[TMP161]], i64* [[TMP162]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP168:%.*]] = icmp ne i32 [[TMP167]], 0 +// CHECK10-NEXT: br i1 [[TMP168]], label [[OMP_OFFLOAD_FAILED64:%.*]], label [[OMP_OFFLOAD_CONT65:%.*]] +// CHECK10: omp_offload.failed64: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i64 [[TMP132]], i64 [[TMP134]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT65]] +// CHECK10: omp_offload.cont65: +// CHECK10-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) +// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK10-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) +// CHECK10-NEXT: [[TMP171:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK10-NEXT: ret i32 [[TMP171]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I22:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I32:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK10-NEXT: br label [[FOR_COND3:%.*]] -// CHECK10: for.cond3: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK10-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK10: for.body5: -// CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: br label [[FOR_INC9:%.*]] -// CHECK10: for.inc9: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK10-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK10-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK10: for.end11: -// CHECK10-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK10-NEXT: br label [[FOR_COND13:%.*]] -// CHECK10: for.cond13: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK10-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK10: for.body15: -// CHECK10-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK10-NEXT: br label [[FOR_INC19:%.*]] -// CHECK10: for.inc19: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK10-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end21: -// CHECK10-NEXT: store i32 0, i32* [[I22]], align 4 -// CHECK10-NEXT: br label [[FOR_COND23:%.*]] -// CHECK10: for.cond23: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[CMP24:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK10-NEXT: br i1 [[CMP24]], label [[FOR_BODY25:%.*]], label [[FOR_END31:%.*]] -// CHECK10: for.body25: -// CHECK10-NEXT: [[A26:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[IDXPROM27:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A26]], i64 0, i64 [[IDXPROM27]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX28]], align 4 -// CHECK10-NEXT: br label [[FOR_INC29:%.*]] -// CHECK10: for.inc29: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: store i32 [[INC30]], i32* [[I22]], align 4 -// CHECK10-NEXT: br label [[FOR_COND23]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK10: for.end31: -// CHECK10-NEXT: store i32 0, i32* [[I32]], align 4 -// CHECK10-NEXT: br label [[FOR_COND33:%.*]] -// CHECK10: for.cond33: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[CMP34:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK10-NEXT: br i1 [[CMP34]], label [[FOR_BODY35:%.*]], label [[FOR_END41:%.*]] -// CHECK10: for.body35: -// CHECK10-NEXT: [[A36:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A36]], i64 0, i64 [[IDXPROM37]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK10-NEXT: br label [[FOR_INC39:%.*]] -// CHECK10: for.inc39: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[INC40:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[INC40]], i32* [[I32]], align 4 -// CHECK10-NEXT: br label [[FOR_COND33]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK10: for.end41: -// CHECK10-NEXT: [[A42:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A42]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX43]], align 4 -// CHECK10-NEXT: ret i32 [[TMP15]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK11-NEXT: ret i32 [[CALL]] +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 +// CHECK10-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] +// CHECK10-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] +// CHECK10: cond.true12: +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: br label [[COND_END14:%.*]] +// CHECK10: cond.false13: +// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END14]] +// CHECK10: cond.end14: +// CHECK10-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE12]] ], [ [[TMP32]], [[COND_FALSE13]] ] +// CHECK10-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 +// CHECK10-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 8 +// CHECK10-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[M_CASTED19:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [2 x i8*], align 8 +// CHECK10-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK10-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK10-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK10: omp_offload.failed5: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK10: omp_offload.cont6: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK10-NEXT: store i64 [[TMP19]], i64* [[TMP21]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK10-NEXT: store i64 [[TMP19]], i64* [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 8 +// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK10-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK10: omp_offload.failed11: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126(i64 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK10: omp_offload.cont12: +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP35]], align 8 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP37]], align 8 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP38]], align 8 +// CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131.region_id, i32 1, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK10-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK10: omp_offload.failed17: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK10: omp_offload.cont18: +// CHECK10-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 +// CHECK10-NEXT: [[CONV20:%.*]] = bitcast i64* [[M_CASTED19]] to i32* +// CHECK10-NEXT: store i32 [[TMP43]], i32* [[CONV20]], align 4 +// CHECK10-NEXT: [[TMP44:%.*]] = load i64, i64* [[M_CASTED19]], align 8 +// CHECK10-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* +// CHECK10-NEXT: store i64 [[TMP44]], i64* [[TMP46]], align 8 +// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* +// CHECK10-NEXT: store i64 [[TMP44]], i64* [[TMP48]], align 8 +// CHECK10-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP49]], align 8 +// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP51]], align 8 +// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to [10 x i32]** +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP53]], align 8 +// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP54]], align 8 +// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 +// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK10-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 +// CHECK10-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] +// CHECK10: omp_offload.failed25: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136(i64 [[TMP44]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT26]] +// CHECK10: omp_offload.cont26: +// CHECK10-NEXT: ret i32 0 +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 +// CHECK10-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..21 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[CONV3]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CONV4:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ] +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[COND]] to i32 +// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..25 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 +// CHECK10-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK10-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-LABEL: define {{[^@]+}}@main +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK11-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [4 x i64], align 4 +// CHECK11-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED31:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS32:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS33:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS34:%.*]] = alloca [3 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES35:%.*]] = alloca [3 x i64], align 4 +// CHECK11-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_37:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[M_CASTED45:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED46:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS47:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS48:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS49:%.*]] = alloca [4 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES50:%.*]] = alloca [4 x i64], align 4 +// CHECK11-NEXT: [[_TMP51:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_52:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_53:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK11-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK11-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK11-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK11-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK11-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK11-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK11-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK11-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK11-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK11-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK11-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) +// CHECK11-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK11-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK11: omp_offload.failed15: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK11: omp_offload.cont16: +// CHECK11-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 +// CHECK11-NEXT: store i32 [[TMP64]], i32* [[M_CASTED]], align 4 +// CHECK11-NEXT: [[TMP65:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK11-NEXT: [[TMP66:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP66]], i32* [[N_CASTED17]], align 4 +// CHECK11-NEXT: [[TMP67:%.*]] = load i32, i32* [[N_CASTED17]], align 4 +// CHECK11-NEXT: [[TMP68:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK11-NEXT: [[TMP69:%.*]] = sext i32 [[TMP68]] to i64 +// CHECK11-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* +// CHECK11-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 +// CHECK11-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32* +// CHECK11-NEXT: store i32 [[TMP65]], i32* [[TMP73]], align 4 +// CHECK11-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP74]], align 4 +// CHECK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP75]], align 4 +// CHECK11-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* +// CHECK11-NEXT: store i32 [[TMP67]], i32* [[TMP77]], align 4 +// CHECK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK11-NEXT: store i32 [[TMP67]], i32* [[TMP79]], align 4 +// CHECK11-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP80]], align 4 +// CHECK11-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP81]], align 4 +// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP83]], align 4 +// CHECK11-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP85]], align 4 +// CHECK11-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP86]], align 4 +// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP87]], align 4 +// CHECK11-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 4 +// CHECK11-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP91]], align 4 +// CHECK11-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 3 +// CHECK11-NEXT: store i64 [[TMP69]], i64* [[TMP92]], align 4 +// CHECK11-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP93]], align 4 +// CHECK11-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP97:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP97]], i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK11-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK11-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP98]], 0 +// CHECK11-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 +// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 +// CHECK11-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK11-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK11-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP99]], 1 +// CHECK11-NEXT: [[TMP100:%.*]] = zext i32 [[ADD28]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP100]]) +// CHECK11-NEXT: [[TMP101:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158.region_id, i32 4, i8** [[TMP94]], i8** [[TMP95]], i64* [[TMP96]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP102:%.*]] = icmp ne i32 [[TMP101]], 0 +// CHECK11-NEXT: br i1 [[TMP102]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] +// CHECK11: omp_offload.failed29: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158(i32 [[TMP65]], i32 [[TMP67]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT30]] +// CHECK11: omp_offload.cont30: +// CHECK11-NEXT: [[TMP103:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP103]], i32* [[N_CASTED31]], align 4 +// CHECK11-NEXT: [[TMP104:%.*]] = load i32, i32* [[N_CASTED31]], align 4 +// CHECK11-NEXT: [[TMP105:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK11-NEXT: [[TMP106:%.*]] = sext i32 [[TMP105]] to i64 +// CHECK11-NEXT: [[TMP107:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* +// CHECK11-NEXT: store i32 [[TMP104]], i32* [[TMP108]], align 4 +// CHECK11-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* +// CHECK11-NEXT: store i32 [[TMP104]], i32* [[TMP110]], align 4 +// CHECK11-NEXT: [[TMP111:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP111]], align 4 +// CHECK11-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP112]], align 4 +// CHECK11-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP114]], align 4 +// CHECK11-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP116]], align 4 +// CHECK11-NEXT: [[TMP117:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP117]], align 4 +// CHECK11-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP118]], align 4 +// CHECK11-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP120]], align 4 +// CHECK11-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP122]], align 4 +// CHECK11-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 2 +// CHECK11-NEXT: store i64 [[TMP106]], i64* [[TMP123]], align 4 +// CHECK11-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP124]], align 4 +// CHECK11-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP126:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP127:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP128:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP128]], i32* [[DOTCAPTURE_EXPR_37]], align 4 +// CHECK11-NEXT: [[TMP129:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_37]], align 4 +// CHECK11-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP129]], 0 +// CHECK11-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 +// CHECK11-NEXT: [[SUB41:%.*]] = sub nsw i32 [[DIV40]], 1 +// CHECK11-NEXT: store i32 [[SUB41]], i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK11-NEXT: [[TMP130:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK11-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP130]], 1 +// CHECK11-NEXT: [[TMP131:%.*]] = zext i32 [[ADD42]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP131]]) +// CHECK11-NEXT: [[TMP132:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163.region_id, i32 3, i8** [[TMP125]], i8** [[TMP126]], i64* [[TMP127]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP133:%.*]] = icmp ne i32 [[TMP132]], 0 +// CHECK11-NEXT: br i1 [[TMP133]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] +// CHECK11: omp_offload.failed43: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163(i32 [[TMP104]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT44]] +// CHECK11: omp_offload.cont44: +// CHECK11-NEXT: [[TMP134:%.*]] = load i32, i32* [[M]], align 4 +// CHECK11-NEXT: store i32 [[TMP134]], i32* [[M_CASTED45]], align 4 +// CHECK11-NEXT: [[TMP135:%.*]] = load i32, i32* [[M_CASTED45]], align 4 +// CHECK11-NEXT: [[TMP136:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP136]], i32* [[N_CASTED46]], align 4 +// CHECK11-NEXT: [[TMP137:%.*]] = load i32, i32* [[N_CASTED46]], align 4 +// CHECK11-NEXT: [[TMP138:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK11-NEXT: [[TMP139:%.*]] = sext i32 [[TMP138]] to i64 +// CHECK11-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i32* +// CHECK11-NEXT: store i32 [[TMP135]], i32* [[TMP141]], align 4 +// CHECK11-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32* +// CHECK11-NEXT: store i32 [[TMP135]], i32* [[TMP143]], align 4 +// CHECK11-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 0 +// CHECK11-NEXT: store i64 4, i64* [[TMP144]], align 4 +// CHECK11-NEXT: [[TMP145:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP145]], align 4 +// CHECK11-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* +// CHECK11-NEXT: store i32 [[TMP137]], i32* [[TMP147]], align 4 +// CHECK11-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* +// CHECK11-NEXT: store i32 [[TMP137]], i32* [[TMP149]], align 4 +// CHECK11-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP150]], align 4 +// CHECK11-NEXT: [[TMP151:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP151]], align 4 +// CHECK11-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP153]], align 4 +// CHECK11-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP155]], align 4 +// CHECK11-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP156]], align 4 +// CHECK11-NEXT: [[TMP157:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP157]], align 4 +// CHECK11-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP159]], align 4 +// CHECK11-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP161:%.*]] = bitcast i8** [[TMP160]] to i32** +// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP161]], align 4 +// CHECK11-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 3 +// CHECK11-NEXT: store i64 [[TMP139]], i64* [[TMP162]], align 4 +// CHECK11-NEXT: [[TMP163:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP163]], align 4 +// CHECK11-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP165:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP166:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP167:%.*]] = load i32, i32* [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP167]], i32* [[DOTCAPTURE_EXPR_52]], align 4 +// CHECK11-NEXT: [[TMP168:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_52]], align 4 +// CHECK11-NEXT: [[SUB54:%.*]] = sub nsw i32 [[TMP168]], 0 +// CHECK11-NEXT: [[DIV55:%.*]] = sdiv i32 [[SUB54]], 1 +// CHECK11-NEXT: [[SUB56:%.*]] = sub nsw i32 [[DIV55]], 1 +// CHECK11-NEXT: store i32 [[SUB56]], i32* [[DOTCAPTURE_EXPR_53]], align 4 +// CHECK11-NEXT: [[TMP169:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_53]], align 4 +// CHECK11-NEXT: [[ADD57:%.*]] = add nsw i32 [[TMP169]], 1 +// CHECK11-NEXT: [[TMP170:%.*]] = zext i32 [[ADD57]] to i64 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP170]]) +// CHECK11-NEXT: [[TMP171:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168.region_id, i32 4, i8** [[TMP164]], i8** [[TMP165]], i64* [[TMP166]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP172:%.*]] = icmp ne i32 [[TMP171]], 0 +// CHECK11-NEXT: br i1 [[TMP172]], label [[OMP_OFFLOAD_FAILED58:%.*]], label [[OMP_OFFLOAD_CONT59:%.*]] +// CHECK11: omp_offload.failed58: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i32 [[TMP135]], i32 [[TMP137]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT59]] +// CHECK11: omp_offload.cont59: +// CHECK11-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) +// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK11-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) +// CHECK11-NEXT: [[TMP175:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK11-NEXT: ret i32 [[TMP175]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I20:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3:%.*]] -// CHECK11: for.cond3: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK11-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK11: for.body5: -// CHECK11-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK11-NEXT: br label [[FOR_INC8:%.*]] -// CHECK11: for.inc8: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK11-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK11: for.end10: -// CHECK11-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK11-NEXT: br label [[FOR_COND12:%.*]] -// CHECK11: for.cond12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK11-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK11: for.body14: -// CHECK11-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK11-NEXT: br label [[FOR_INC17:%.*]] -// CHECK11: for.inc17: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK11-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK11-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end19: -// CHECK11-NEXT: store i32 0, i32* [[I20]], align 4 -// CHECK11-NEXT: br label [[FOR_COND21:%.*]] -// CHECK11: for.cond21: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[CMP22:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK11-NEXT: br i1 [[CMP22]], label [[FOR_BODY23:%.*]], label [[FOR_END28:%.*]] -// CHECK11: for.body23: -// CHECK11-NEXT: [[A24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A24]], i32 0, i32 [[TMP10]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX25]], align 4 -// CHECK11-NEXT: br label [[FOR_INC26:%.*]] -// CHECK11: for.inc26: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[INC27:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: store i32 [[INC27]], i32* [[I20]], align 4 -// CHECK11-NEXT: br label [[FOR_COND21]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK11: for.end28: -// CHECK11-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK11-NEXT: br label [[FOR_COND30:%.*]] -// CHECK11: for.cond30: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK11-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK11: for.body32: -// CHECK11-NEXT: [[A33:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A33]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK11-NEXT: br label [[FOR_INC35:%.*]] -// CHECK11: for.inc35: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK11-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end37: -// CHECK11-NEXT: [[A38:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A38]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX39]], align 4 -// CHECK11-NEXT: ret i32 [[TMP15]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]]) -// CHECK12-NEXT: ret i32 [[CALL]] +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 +// CHECK11-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK11-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] +// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] +// CHECK11-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK11: cond.true11: +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: br label [[COND_END13:%.*]] +// CHECK11: cond.false12: +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END13]] +// CHECK11: cond.end13: +// CHECK11-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE11]] ], [ [[TMP30]], [[COND_FALSE12]] ] +// CHECK11-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP20]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 +// CHECK11-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP19]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP21]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 4 +// CHECK11-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[M_CASTED19:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [2 x i8*], align 4 +// CHECK11-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK11-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11: omp_offload.failed: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK11: omp_offload.cont: +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK11-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK11: omp_offload.failed5: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK11: omp_offload.cont6: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[M_CASTED]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK11-NEXT: store i32 [[TMP19]], i32* [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK11-NEXT: store i32 [[TMP19]], i32* [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK11: omp_offload.failed11: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126(i32 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK11: omp_offload.cont12: +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP35]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP37]], align 4 +// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP38]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131.region_id, i32 1, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK11-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK11: omp_offload.failed17: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK11: omp_offload.cont18: +// CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 +// CHECK11-NEXT: store i32 [[TMP43]], i32* [[M_CASTED19]], align 4 +// CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[M_CASTED19]], align 4 +// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK11-NEXT: store i32 [[TMP44]], i32* [[TMP46]], align 4 +// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32* +// CHECK11-NEXT: store i32 [[TMP44]], i32* [[TMP48]], align 4 +// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP49]], align 4 +// CHECK11-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP51]], align 4 +// CHECK11-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to [10 x i32]** +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP53]], align 4 +// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK11-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 +// CHECK11-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED24:%.*]], label [[OMP_OFFLOAD_CONT25:%.*]] +// CHECK11: omp_offload.failed24: +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136(i32 [[TMP44]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT25]] +// CHECK11: omp_offload.cont25: +// CHECK11-NEXT: ret i32 0 +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 +// CHECK11-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..21 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..25 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK11-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 +// CHECK11-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK11-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK11: omp.dispatch.cond: +// CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK11: omp.dispatch.body: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK11-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK11: omp.dispatch.inc: +// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK11: omp.dispatch.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-LABEL: define {{[^@]+}}@main +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 +// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 +// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [4 x i64], align 4 +// CHECK12-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED31:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS32:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS33:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS34:%.*]] = alloca [3 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES35:%.*]] = alloca [3 x i64], align 4 +// CHECK12-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_37:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[M_CASTED45:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED46:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS47:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS48:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS49:%.*]] = alloca [4 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES50:%.*]] = alloca [4 x i64], align 4 +// CHECK12-NEXT: [[_TMP51:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_52:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_53:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 +// CHECK12-NEXT: store i32 100, i32* [[N]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK12-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 +// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) +// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 +// CHECK12-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK12-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 +// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 +// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 +// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 +// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 +// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 +// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 +// CHECK12-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 +// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK12-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 +// CHECK12-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 +// CHECK12-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK12-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 +// CHECK12-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK12-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 +// CHECK12-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 +// CHECK12-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) +// CHECK12-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 +// CHECK12-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK12: omp_offload.failed15: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK12: omp_offload.cont16: +// CHECK12-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 +// CHECK12-NEXT: store i32 [[TMP64]], i32* [[M_CASTED]], align 4 +// CHECK12-NEXT: [[TMP65:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK12-NEXT: [[TMP66:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP66]], i32* [[N_CASTED17]], align 4 +// CHECK12-NEXT: [[TMP67:%.*]] = load i32, i32* [[N_CASTED17]], align 4 +// CHECK12-NEXT: [[TMP68:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK12-NEXT: [[TMP69:%.*]] = sext i32 [[TMP68]] to i64 +// CHECK12-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* +// CHECK12-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 +// CHECK12-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32* +// CHECK12-NEXT: store i32 [[TMP65]], i32* [[TMP73]], align 4 +// CHECK12-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP74]], align 4 +// CHECK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP75]], align 4 +// CHECK12-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* +// CHECK12-NEXT: store i32 [[TMP67]], i32* [[TMP77]], align 4 +// CHECK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK12-NEXT: store i32 [[TMP67]], i32* [[TMP79]], align 4 +// CHECK12-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP80]], align 4 +// CHECK12-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP81]], align 4 +// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP83]], align 4 +// CHECK12-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP85]], align 4 +// CHECK12-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP86]], align 4 +// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP87]], align 4 +// CHECK12-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 4 +// CHECK12-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP91]], align 4 +// CHECK12-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 3 +// CHECK12-NEXT: store i64 [[TMP69]], i64* [[TMP92]], align 4 +// CHECK12-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP93]], align 4 +// CHECK12-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP97:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP97]], i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK12-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 +// CHECK12-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP98]], 0 +// CHECK12-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 +// CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 +// CHECK12-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK12-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 +// CHECK12-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP99]], 1 +// CHECK12-NEXT: [[TMP100:%.*]] = zext i32 [[ADD28]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP100]]) +// CHECK12-NEXT: [[TMP101:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158.region_id, i32 4, i8** [[TMP94]], i8** [[TMP95]], i64* [[TMP96]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP102:%.*]] = icmp ne i32 [[TMP101]], 0 +// CHECK12-NEXT: br i1 [[TMP102]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] +// CHECK12: omp_offload.failed29: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158(i32 [[TMP65]], i32 [[TMP67]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT30]] +// CHECK12: omp_offload.cont30: +// CHECK12-NEXT: [[TMP103:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP103]], i32* [[N_CASTED31]], align 4 +// CHECK12-NEXT: [[TMP104:%.*]] = load i32, i32* [[N_CASTED31]], align 4 +// CHECK12-NEXT: [[TMP105:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK12-NEXT: [[TMP106:%.*]] = sext i32 [[TMP105]] to i64 +// CHECK12-NEXT: [[TMP107:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* +// CHECK12-NEXT: store i32 [[TMP104]], i32* [[TMP108]], align 4 +// CHECK12-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* +// CHECK12-NEXT: store i32 [[TMP104]], i32* [[TMP110]], align 4 +// CHECK12-NEXT: [[TMP111:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP111]], align 4 +// CHECK12-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP112]], align 4 +// CHECK12-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP114]], align 4 +// CHECK12-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP116]], align 4 +// CHECK12-NEXT: [[TMP117:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP117]], align 4 +// CHECK12-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP118]], align 4 +// CHECK12-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP120]], align 4 +// CHECK12-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP122]], align 4 +// CHECK12-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 2 +// CHECK12-NEXT: store i64 [[TMP106]], i64* [[TMP123]], align 4 +// CHECK12-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP124]], align 4 +// CHECK12-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP126:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP127:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP128:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP128]], i32* [[DOTCAPTURE_EXPR_37]], align 4 +// CHECK12-NEXT: [[TMP129:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_37]], align 4 +// CHECK12-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP129]], 0 +// CHECK12-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 +// CHECK12-NEXT: [[SUB41:%.*]] = sub nsw i32 [[DIV40]], 1 +// CHECK12-NEXT: store i32 [[SUB41]], i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK12-NEXT: [[TMP130:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 +// CHECK12-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP130]], 1 +// CHECK12-NEXT: [[TMP131:%.*]] = zext i32 [[ADD42]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP131]]) +// CHECK12-NEXT: [[TMP132:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163.region_id, i32 3, i8** [[TMP125]], i8** [[TMP126]], i64* [[TMP127]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP133:%.*]] = icmp ne i32 [[TMP132]], 0 +// CHECK12-NEXT: br i1 [[TMP133]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] +// CHECK12: omp_offload.failed43: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163(i32 [[TMP104]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT44]] +// CHECK12: omp_offload.cont44: +// CHECK12-NEXT: [[TMP134:%.*]] = load i32, i32* [[M]], align 4 +// CHECK12-NEXT: store i32 [[TMP134]], i32* [[M_CASTED45]], align 4 +// CHECK12-NEXT: [[TMP135:%.*]] = load i32, i32* [[M_CASTED45]], align 4 +// CHECK12-NEXT: [[TMP136:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP136]], i32* [[N_CASTED46]], align 4 +// CHECK12-NEXT: [[TMP137:%.*]] = load i32, i32* [[N_CASTED46]], align 4 +// CHECK12-NEXT: [[TMP138:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK12-NEXT: [[TMP139:%.*]] = sext i32 [[TMP138]] to i64 +// CHECK12-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i32* +// CHECK12-NEXT: store i32 [[TMP135]], i32* [[TMP141]], align 4 +// CHECK12-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32* +// CHECK12-NEXT: store i32 [[TMP135]], i32* [[TMP143]], align 4 +// CHECK12-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 0 +// CHECK12-NEXT: store i64 4, i64* [[TMP144]], align 4 +// CHECK12-NEXT: [[TMP145:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP145]], align 4 +// CHECK12-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* +// CHECK12-NEXT: store i32 [[TMP137]], i32* [[TMP147]], align 4 +// CHECK12-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* +// CHECK12-NEXT: store i32 [[TMP137]], i32* [[TMP149]], align 4 +// CHECK12-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP150]], align 4 +// CHECK12-NEXT: [[TMP151:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP151]], align 4 +// CHECK12-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP153]], align 4 +// CHECK12-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP155]], align 4 +// CHECK12-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP156]], align 4 +// CHECK12-NEXT: [[TMP157:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP157]], align 4 +// CHECK12-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP159]], align 4 +// CHECK12-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP161:%.*]] = bitcast i8** [[TMP160]] to i32** +// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP161]], align 4 +// CHECK12-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 3 +// CHECK12-NEXT: store i64 [[TMP139]], i64* [[TMP162]], align 4 +// CHECK12-NEXT: [[TMP163:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP163]], align 4 +// CHECK12-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP165:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP166:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP167:%.*]] = load i32, i32* [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP167]], i32* [[DOTCAPTURE_EXPR_52]], align 4 +// CHECK12-NEXT: [[TMP168:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_52]], align 4 +// CHECK12-NEXT: [[SUB54:%.*]] = sub nsw i32 [[TMP168]], 0 +// CHECK12-NEXT: [[DIV55:%.*]] = sdiv i32 [[SUB54]], 1 +// CHECK12-NEXT: [[SUB56:%.*]] = sub nsw i32 [[DIV55]], 1 +// CHECK12-NEXT: store i32 [[SUB56]], i32* [[DOTCAPTURE_EXPR_53]], align 4 +// CHECK12-NEXT: [[TMP169:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_53]], align 4 +// CHECK12-NEXT: [[ADD57:%.*]] = add nsw i32 [[TMP169]], 1 +// CHECK12-NEXT: [[TMP170:%.*]] = zext i32 [[ADD57]] to i64 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP170]]) +// CHECK12-NEXT: [[TMP171:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168.region_id, i32 4, i8** [[TMP164]], i8** [[TMP165]], i64* [[TMP166]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP172:%.*]] = icmp ne i32 [[TMP171]], 0 +// CHECK12-NEXT: br i1 [[TMP172]], label [[OMP_OFFLOAD_FAILED58:%.*]], label [[OMP_OFFLOAD_CONT59:%.*]] +// CHECK12: omp_offload.failed58: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i32 [[TMP135]], i32 [[TMP137]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT59]] +// CHECK12: omp_offload.cont59: +// CHECK12-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) +// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK12-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) +// CHECK12-NEXT: [[TMP175:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK12-NEXT: ret i32 [[TMP175]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 +// CHECK12-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] +// CHECK12-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK12: cond.true11: +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: br label [[COND_END13:%.*]] +// CHECK12: cond.false12: +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END13]] +// CHECK12: cond.end13: +// CHECK12-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE11]] ], [ [[TMP30]], [[COND_FALSE12]] ] +// CHECK12-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP20]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 +// CHECK12-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I20:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP19]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 +// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP21]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 +// CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 4 +// CHECK12-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[M_CASTED19:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [2 x i8*], align 4 +// CHECK12-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK12-NEXT: store i32 10, i32* [[M]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12: omp_offload.failed: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK12: omp_offload.cont: +// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK12-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK12: omp_offload.failed5: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK12: omp_offload.cont6: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 +// CHECK12-NEXT: store i32 [[TMP18]], i32* [[M_CASTED]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK12-NEXT: store i32 [[TMP19]], i32* [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK12-NEXT: store i32 [[TMP19]], i32* [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK12-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] +// CHECK12: omp_offload.failed11: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126(i32 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT12]] +// CHECK12: omp_offload.cont12: +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP35]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP37]], align 4 +// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP38]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131.region_id, i32 1, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK12-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK12: omp_offload.failed17: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131([10 x i32]* [[A]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK12: omp_offload.cont18: +// CHECK12-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 +// CHECK12-NEXT: store i32 [[TMP43]], i32* [[M_CASTED19]], align 4 +// CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[M_CASTED19]], align 4 +// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK12-NEXT: store i32 [[TMP44]], i32* [[TMP46]], align 4 +// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32* +// CHECK12-NEXT: store i32 [[TMP44]], i32* [[TMP48]], align 4 +// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP49]], align 4 +// CHECK12-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP51]], align 4 +// CHECK12-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to [10 x i32]** +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP53]], align 4 +// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) +// CHECK12-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 +// CHECK12-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED24:%.*]], label [[OMP_OFFLOAD_CONT25:%.*]] +// CHECK12: omp_offload.failed24: +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136(i32 [[TMP44]], [10 x i32]* [[A]]) #[[ATTR3]] +// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT25]] +// CHECK12: omp_offload.cont25: +// CHECK12-NEXT: ret i32 0 +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..14 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 +// CHECK12-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..21 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..22 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP16]] // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3:%.*]] -// CHECK12: for.cond3: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK12-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK12: for.body5: -// CHECK12-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK12-NEXT: br label [[FOR_INC8:%.*]] -// CHECK12: for.inc8: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK12-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK12: for.end10: -// CHECK12-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK12-NEXT: br label [[FOR_COND12:%.*]] -// CHECK12: for.cond12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK12-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK12: for.body14: -// CHECK12-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK12-NEXT: br label [[FOR_INC17:%.*]] -// CHECK12: for.inc17: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK12-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK12-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end19: -// CHECK12-NEXT: store i32 0, i32* [[I20]], align 4 -// CHECK12-NEXT: br label [[FOR_COND21:%.*]] -// CHECK12: for.cond21: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[CMP22:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK12-NEXT: br i1 [[CMP22]], label [[FOR_BODY23:%.*]], label [[FOR_END28:%.*]] -// CHECK12: for.body23: -// CHECK12-NEXT: [[A24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A24]], i32 0, i32 [[TMP10]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX25]], align 4 -// CHECK12-NEXT: br label [[FOR_INC26:%.*]] -// CHECK12: for.inc26: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[INC27:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: store i32 [[INC27]], i32* [[I20]], align 4 -// CHECK12-NEXT: br label [[FOR_COND21]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK12: for.end28: -// CHECK12-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK12-NEXT: br label [[FOR_COND30:%.*]] -// CHECK12: for.cond30: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK12-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK12: for.body32: -// CHECK12-NEXT: [[A33:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A33]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK12-NEXT: br label [[FOR_INC35:%.*]] -// CHECK12: for.inc35: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK12-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end37: -// CHECK12-NEXT: [[A38:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A38]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX39]], align 4 -// CHECK12-NEXT: ret i32 [[TMP15]] +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..25 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK12-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 +// CHECK12-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..30 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK12-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK12-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK12-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@main @@ -9113,7 +18357,7 @@ // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) +// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13: omp.dispatch.cond: // CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -9344,7 +18588,7 @@ // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) +// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13: omp.dispatch.cond: // CHECK13-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -10138,7 +19382,7 @@ // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13: omp.dispatch.cond: // CHECK13-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -10309,7 +19553,7 @@ // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13: omp.dispatch.cond: // CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -11583,7 +20827,7 @@ // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) +// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14: omp.dispatch.cond: // CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -11814,7 +21058,7 @@ // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) +// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14: omp.dispatch.cond: // CHECK14-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -12608,7 +21852,7 @@ // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14: omp.dispatch.cond: // CHECK14-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -12779,7 +22023,7 @@ // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14: omp.dispatch.cond: // CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -14022,7 +23266,7 @@ // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) +// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15: omp.dispatch.cond: // CHECK15-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 @@ -14242,7 +23486,7 @@ // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) +// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15: omp.dispatch.cond: // CHECK15-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 @@ -15006,7 +24250,7 @@ // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15: omp.dispatch.cond: // CHECK15-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -15167,7 +24411,7 @@ // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15: omp.dispatch.cond: // CHECK15-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -16409,7 +25653,7 @@ // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) +// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16: omp.dispatch.cond: // CHECK16-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 @@ -16629,7 +25873,7 @@ // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) +// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16: omp.dispatch.cond: // CHECK16-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 @@ -17393,7 +26637,7 @@ // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 1073741859, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) +// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16: omp.dispatch.cond: // CHECK16-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -17554,7 +26798,7 @@ // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) +// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16: omp.dispatch.cond: // CHECK16-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) @@ -17599,10687 +26843,3 @@ // CHECK16-NEXT: call void @__tgt_register_requires(i64 1) // CHECK16-NEXT: ret void // -// -// CHECK17-LABEL: define {{[^@]+}}@main -// CHECK17-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK17-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK17-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES24:%.*]] = alloca [4 x i64], align 8 -// CHECK17-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[N_CASTED34:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS36:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS37:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS38:%.*]] = alloca [3 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES39:%.*]] = alloca [3 x i64], align 8 -// CHECK17-NEXT: [[_TMP40:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_41:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_42:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[M_CASTED49:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_CASTED51:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS53:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS54:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS55:%.*]] = alloca [4 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES56:%.*]] = alloca [4 x i64], align 8 -// CHECK17-NEXT: [[_TMP57:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_59:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK17-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK17-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK17-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK17-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK17-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK17-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK17-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK17-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK17-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK17-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK17-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK17-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK17-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK17-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK17-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK17-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK17-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK17-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK17-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK17-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) -// CHECK17-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK17-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK17: omp_offload.failed16: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK17: omp_offload.cont17: -// CHECK17-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 -// CHECK17-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP63]], i32* [[CONV18]], align 4 -// CHECK17-NEXT: [[TMP64:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK17-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* -// CHECK17-NEXT: store i32 [[TMP65]], i32* [[CONV20]], align 4 -// CHECK17-NEXT: [[TMP66:%.*]] = load i64, i64* [[N_CASTED19]], align 8 -// CHECK17-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* -// CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 -// CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* -// CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP71]], align 8 -// CHECK17-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP72]], align 8 -// CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP73]], align 8 -// CHECK17-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* -// CHECK17-NEXT: store i64 [[TMP66]], i64* [[TMP75]], align 8 -// CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* -// CHECK17-NEXT: store i64 [[TMP66]], i64* [[TMP77]], align 8 -// CHECK17-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 1 -// CHECK17-NEXT: store i64 4, i64* [[TMP78]], align 8 -// CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP79]], align 8 -// CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP81]], align 8 -// CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP83]], align 8 -// CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP84]], align 8 -// CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP85]], align 8 -// CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP87]], align 8 -// CHECK17-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 8 -// CHECK17-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 3 -// CHECK17-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 -// CHECK17-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP91]], align 8 -// CHECK17-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP95:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: store i32 [[TMP95]], i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK17-NEXT: [[TMP96:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK17-NEXT: [[SUB28:%.*]] = sub nsw i32 [[TMP96]], 0 -// CHECK17-NEXT: [[DIV29:%.*]] = sdiv i32 [[SUB28]], 1 -// CHECK17-NEXT: [[SUB30:%.*]] = sub nsw i32 [[DIV29]], 1 -// CHECK17-NEXT: store i32 [[SUB30]], i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK17-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK17-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP97]], 1 -// CHECK17-NEXT: [[TMP98:%.*]] = zext i32 [[ADD31]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP98]]) -// CHECK17-NEXT: [[TMP99:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158.region_id, i32 4, i8** [[TMP92]], i8** [[TMP93]], i64* [[TMP94]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP100:%.*]] = icmp ne i32 [[TMP99]], 0 -// CHECK17-NEXT: br i1 [[TMP100]], label [[OMP_OFFLOAD_FAILED32:%.*]], label [[OMP_OFFLOAD_CONT33:%.*]] -// CHECK17: omp_offload.failed32: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158(i64 [[TMP64]], i64 [[TMP66]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT33]] -// CHECK17: omp_offload.cont33: -// CHECK17-NEXT: [[TMP101:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CONV35:%.*]] = bitcast i64* [[N_CASTED34]] to i32* -// CHECK17-NEXT: store i32 [[TMP101]], i32* [[CONV35]], align 4 -// CHECK17-NEXT: [[TMP102:%.*]] = load i64, i64* [[N_CASTED34]], align 8 -// CHECK17-NEXT: [[TMP103:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK17-NEXT: [[TMP104:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64* -// CHECK17-NEXT: store i64 [[TMP102]], i64* [[TMP105]], align 8 -// CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* -// CHECK17-NEXT: store i64 [[TMP102]], i64* [[TMP107]], align 8 -// CHECK17-NEXT: [[TMP108:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP108]], align 8 -// CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP109]], align 8 -// CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP111]], align 8 -// CHECK17-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP113]], align 8 -// CHECK17-NEXT: [[TMP114:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 1 -// CHECK17-NEXT: store i64 8, i64* [[TMP114]], align 8 -// CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP115]], align 8 -// CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP117]], align 8 -// CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP119]], align 8 -// CHECK17-NEXT: [[TMP120:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 2 -// CHECK17-NEXT: store i64 [[TMP103]], i64* [[TMP120]], align 8 -// CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP121]], align 8 -// CHECK17-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP125:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: store i32 [[TMP125]], i32* [[DOTCAPTURE_EXPR_41]], align 4 -// CHECK17-NEXT: [[TMP126:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_41]], align 4 -// CHECK17-NEXT: [[SUB43:%.*]] = sub nsw i32 [[TMP126]], 0 -// CHECK17-NEXT: [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1 -// CHECK17-NEXT: [[SUB45:%.*]] = sub nsw i32 [[DIV44]], 1 -// CHECK17-NEXT: store i32 [[SUB45]], i32* [[DOTCAPTURE_EXPR_42]], align 4 -// CHECK17-NEXT: [[TMP127:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_42]], align 4 -// CHECK17-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP127]], 1 -// CHECK17-NEXT: [[TMP128:%.*]] = zext i32 [[ADD46]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP128]]) -// CHECK17-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163.region_id, i32 3, i8** [[TMP122]], i8** [[TMP123]], i64* [[TMP124]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0 -// CHECK17-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]] -// CHECK17: omp_offload.failed47: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163(i64 [[TMP102]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT48]] -// CHECK17: omp_offload.cont48: -// CHECK17-NEXT: [[TMP131:%.*]] = load i32, i32* [[M]], align 4 -// CHECK17-NEXT: [[CONV50:%.*]] = bitcast i64* [[M_CASTED49]] to i32* -// CHECK17-NEXT: store i32 [[TMP131]], i32* [[CONV50]], align 4 -// CHECK17-NEXT: [[TMP132:%.*]] = load i64, i64* [[M_CASTED49]], align 8 -// CHECK17-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CONV52:%.*]] = bitcast i64* [[N_CASTED51]] to i32* -// CHECK17-NEXT: store i32 [[TMP133]], i32* [[CONV52]], align 4 -// CHECK17-NEXT: [[TMP134:%.*]] = load i64, i64* [[N_CASTED51]], align 8 -// CHECK17-NEXT: [[TMP135:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64* -// CHECK17-NEXT: store i64 [[TMP132]], i64* [[TMP137]], align 8 -// CHECK17-NEXT: [[TMP138:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to i64* -// CHECK17-NEXT: store i64 [[TMP132]], i64* [[TMP139]], align 8 -// CHECK17-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 0 -// CHECK17-NEXT: store i64 4, i64* [[TMP140]], align 8 -// CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP141]], align 8 -// CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i64* -// CHECK17-NEXT: store i64 [[TMP134]], i64* [[TMP143]], align 8 -// CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i64* -// CHECK17-NEXT: store i64 [[TMP134]], i64* [[TMP145]], align 8 -// CHECK17-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 1 -// CHECK17-NEXT: store i64 4, i64* [[TMP146]], align 8 -// CHECK17-NEXT: [[TMP147:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP147]], align 8 -// CHECK17-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP149]], align 8 -// CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP151]], align 8 -// CHECK17-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP152]], align 8 -// CHECK17-NEXT: [[TMP153:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP153]], align 8 -// CHECK17-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP155]], align 8 -// CHECK17-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** -// CHECK17-NEXT: store i32* [[VLA]], i32** [[TMP157]], align 8 -// CHECK17-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 3 -// CHECK17-NEXT: store i64 [[TMP135]], i64* [[TMP158]], align 8 -// CHECK17-NEXT: [[TMP159:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP159]], align 8 -// CHECK17-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP161:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP163:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: store i32 [[TMP163]], i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK17-NEXT: [[TMP164:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK17-NEXT: [[SUB60:%.*]] = sub nsw i32 [[TMP164]], 0 -// CHECK17-NEXT: [[DIV61:%.*]] = sdiv i32 [[SUB60]], 1 -// CHECK17-NEXT: [[SUB62:%.*]] = sub nsw i32 [[DIV61]], 1 -// CHECK17-NEXT: store i32 [[SUB62]], i32* [[DOTCAPTURE_EXPR_59]], align 4 -// CHECK17-NEXT: [[TMP165:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_59]], align 4 -// CHECK17-NEXT: [[ADD63:%.*]] = add nsw i32 [[TMP165]], 1 -// CHECK17-NEXT: [[TMP166:%.*]] = zext i32 [[ADD63]] to i64 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP166]]) -// CHECK17-NEXT: [[TMP167:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168.region_id, i32 4, i8** [[TMP160]], i8** [[TMP161]], i64* [[TMP162]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP168:%.*]] = icmp ne i32 [[TMP167]], 0 -// CHECK17-NEXT: br i1 [[TMP168]], label [[OMP_OFFLOAD_FAILED64:%.*]], label [[OMP_OFFLOAD_CONT65:%.*]] -// CHECK17: omp_offload.failed64: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i64 [[TMP132]], i64 [[TMP134]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT65]] -// CHECK17: omp_offload.cont65: -// CHECK17-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) -// CHECK17-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK17-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) -// CHECK17-NEXT: [[TMP171:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK17-NEXT: ret i32 [[TMP171]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK17-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 -// CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK17-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] -// CHECK17-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] -// CHECK17: cond.true12: -// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: br label [[COND_END14:%.*]] -// CHECK17: cond.false13: -// CHECK17-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END14]] -// CHECK17: cond.end14: -// CHECK17-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE12]] ], [ [[TMP32]], [[COND_FALSE13]] ] -// CHECK17-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK17-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK17-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK17-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK17-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4 -// CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK17: omp.precond.then: -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK17-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: br label [[OMP_PRECOND_END]] -// CHECK17: omp.precond.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK17-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK17-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 8 -// CHECK17-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[M_CASTED19:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [2 x i8*], align 8 -// CHECK17-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK17-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK17-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK17-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK17: omp_offload.failed5: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK17: omp_offload.cont6: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP18]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK17-NEXT: store i64 [[TMP19]], i64* [[TMP21]], align 8 -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK17-NEXT: store i64 [[TMP19]], i64* [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 8 -// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK17-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK17: omp_offload.failed11: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126(i64 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK17: omp_offload.cont12: -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP35]], align 8 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP37]], align 8 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP38]], align 8 -// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131.region_id, i32 1, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 -// CHECK17-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK17: omp_offload.failed17: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK17: omp_offload.cont18: -// CHECK17-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 -// CHECK17-NEXT: [[CONV20:%.*]] = bitcast i64* [[M_CASTED19]] to i32* -// CHECK17-NEXT: store i32 [[TMP43]], i32* [[CONV20]], align 4 -// CHECK17-NEXT: [[TMP44:%.*]] = load i64, i64* [[M_CASTED19]], align 8 -// CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* -// CHECK17-NEXT: store i64 [[TMP44]], i64* [[TMP46]], align 8 -// CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* -// CHECK17-NEXT: store i64 [[TMP44]], i64* [[TMP48]], align 8 -// CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP49]], align 8 -// CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP51]], align 8 -// CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to [10 x i32]** -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP53]], align 8 -// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP54]], align 8 -// CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK17-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 -// CHECK17-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] -// CHECK17: omp_offload.failed25: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136(i64 [[TMP44]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT26]] -// CHECK17: omp_offload.cont26: -// CHECK17-NEXT: ret i32 0 -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK17-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[CONV3]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CONV4:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ] -// CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[COND]] to i32 -// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK17-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK17-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK17: omp.dispatch.cond: -// CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK17: omp.dispatch.body: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK17: omp.body.continue: -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK17: omp.dispatch.inc: -// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK17: omp.dispatch.end: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK18-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8 -// CHECK18-NEXT: [[_TMP9:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_CASTED19:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES24:%.*]] = alloca [4 x i64], align 8 -// CHECK18-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[N_CASTED34:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS36:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS37:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS38:%.*]] = alloca [3 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES39:%.*]] = alloca [3 x i64], align 8 -// CHECK18-NEXT: [[_TMP40:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_41:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_42:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[M_CASTED49:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_CASTED51:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS53:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS54:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS55:%.*]] = alloca [4 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES56:%.*]] = alloca [4 x i64], align 8 -// CHECK18-NEXT: [[_TMP57:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_59:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK18-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK18-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK18-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* -// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 -// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 8, i64* [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK18-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK18-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK18-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32* -// CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 -// CHECK18-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8 -// CHECK18-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK18-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK18-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP40]], align 8 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP41]], align 8 -// CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8 -// CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8 -// CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1 -// CHECK18-NEXT: store i64 8, i64* [[TMP46]], align 8 -// CHECK18-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP47]], align 8 -// CHECK18-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8 -// CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8 -// CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2 -// CHECK18-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8 -// CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP53]], align 8 -// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK18-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK18-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0 -// CHECK18-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 -// CHECK18-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1 -// CHECK18-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK18-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1 -// CHECK18-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP60]]) -// CHECK18-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 -// CHECK18-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] -// CHECK18: omp_offload.failed16: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT17]] -// CHECK18: omp_offload.cont17: -// CHECK18-NEXT: [[TMP63:%.*]] = load i32, i32* [[M]], align 4 -// CHECK18-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP63]], i32* [[CONV18]], align 4 -// CHECK18-NEXT: [[TMP64:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK18-NEXT: [[TMP65:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[CONV20:%.*]] = bitcast i64* [[N_CASTED19]] to i32* -// CHECK18-NEXT: store i32 [[TMP65]], i32* [[CONV20]], align 4 -// CHECK18-NEXT: [[TMP66:%.*]] = load i64, i64* [[N_CASTED19]], align 8 -// CHECK18-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK18-NEXT: [[TMP68:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* -// CHECK18-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8 -// CHECK18-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* -// CHECK18-NEXT: store i64 [[TMP64]], i64* [[TMP71]], align 8 -// CHECK18-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP72]], align 8 -// CHECK18-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP73]], align 8 -// CHECK18-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64* -// CHECK18-NEXT: store i64 [[TMP66]], i64* [[TMP75]], align 8 -// CHECK18-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* -// CHECK18-NEXT: store i64 [[TMP66]], i64* [[TMP77]], align 8 -// CHECK18-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 1 -// CHECK18-NEXT: store i64 4, i64* [[TMP78]], align 8 -// CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP79]], align 8 -// CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP81]], align 8 -// CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP83]], align 8 -// CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP84]], align 8 -// CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP85]], align 8 -// CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP87]], align 8 -// CHECK18-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 8 -// CHECK18-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 3 -// CHECK18-NEXT: store i64 [[TMP67]], i64* [[TMP90]], align 8 -// CHECK18-NEXT: [[TMP91:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP91]], align 8 -// CHECK18-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES24]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP95:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: store i32 [[TMP95]], i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK18-NEXT: [[TMP96:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4 -// CHECK18-NEXT: [[SUB28:%.*]] = sub nsw i32 [[TMP96]], 0 -// CHECK18-NEXT: [[DIV29:%.*]] = sdiv i32 [[SUB28]], 1 -// CHECK18-NEXT: [[SUB30:%.*]] = sub nsw i32 [[DIV29]], 1 -// CHECK18-NEXT: store i32 [[SUB30]], i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK18-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_27]], align 4 -// CHECK18-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP97]], 1 -// CHECK18-NEXT: [[TMP98:%.*]] = zext i32 [[ADD31]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP98]]) -// CHECK18-NEXT: [[TMP99:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158.region_id, i32 4, i8** [[TMP92]], i8** [[TMP93]], i64* [[TMP94]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP100:%.*]] = icmp ne i32 [[TMP99]], 0 -// CHECK18-NEXT: br i1 [[TMP100]], label [[OMP_OFFLOAD_FAILED32:%.*]], label [[OMP_OFFLOAD_CONT33:%.*]] -// CHECK18: omp_offload.failed32: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158(i64 [[TMP64]], i64 [[TMP66]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT33]] -// CHECK18: omp_offload.cont33: -// CHECK18-NEXT: [[TMP101:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[CONV35:%.*]] = bitcast i64* [[N_CASTED34]] to i32* -// CHECK18-NEXT: store i32 [[TMP101]], i32* [[CONV35]], align 4 -// CHECK18-NEXT: [[TMP102:%.*]] = load i64, i64* [[N_CASTED34]], align 8 -// CHECK18-NEXT: [[TMP103:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK18-NEXT: [[TMP104:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64* -// CHECK18-NEXT: store i64 [[TMP102]], i64* [[TMP105]], align 8 -// CHECK18-NEXT: [[TMP106:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* -// CHECK18-NEXT: store i64 [[TMP102]], i64* [[TMP107]], align 8 -// CHECK18-NEXT: [[TMP108:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP108]], align 8 -// CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP109]], align 8 -// CHECK18-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP111]], align 8 -// CHECK18-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP113]], align 8 -// CHECK18-NEXT: [[TMP114:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 1 -// CHECK18-NEXT: store i64 8, i64* [[TMP114]], align 8 -// CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP115]], align 8 -// CHECK18-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP117]], align 8 -// CHECK18-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP119]], align 8 -// CHECK18-NEXT: [[TMP120:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 2 -// CHECK18-NEXT: store i64 [[TMP103]], i64* [[TMP120]], align 8 -// CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP121]], align 8 -// CHECK18-NEXT: [[TMP122:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES39]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP125:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: store i32 [[TMP125]], i32* [[DOTCAPTURE_EXPR_41]], align 4 -// CHECK18-NEXT: [[TMP126:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_41]], align 4 -// CHECK18-NEXT: [[SUB43:%.*]] = sub nsw i32 [[TMP126]], 0 -// CHECK18-NEXT: [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1 -// CHECK18-NEXT: [[SUB45:%.*]] = sub nsw i32 [[DIV44]], 1 -// CHECK18-NEXT: store i32 [[SUB45]], i32* [[DOTCAPTURE_EXPR_42]], align 4 -// CHECK18-NEXT: [[TMP127:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_42]], align 4 -// CHECK18-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP127]], 1 -// CHECK18-NEXT: [[TMP128:%.*]] = zext i32 [[ADD46]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP128]]) -// CHECK18-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163.region_id, i32 3, i8** [[TMP122]], i8** [[TMP123]], i64* [[TMP124]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0 -// CHECK18-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]] -// CHECK18: omp_offload.failed47: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163(i64 [[TMP102]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT48]] -// CHECK18: omp_offload.cont48: -// CHECK18-NEXT: [[TMP131:%.*]] = load i32, i32* [[M]], align 4 -// CHECK18-NEXT: [[CONV50:%.*]] = bitcast i64* [[M_CASTED49]] to i32* -// CHECK18-NEXT: store i32 [[TMP131]], i32* [[CONV50]], align 4 -// CHECK18-NEXT: [[TMP132:%.*]] = load i64, i64* [[M_CASTED49]], align 8 -// CHECK18-NEXT: [[TMP133:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: [[CONV52:%.*]] = bitcast i64* [[N_CASTED51]] to i32* -// CHECK18-NEXT: store i32 [[TMP133]], i32* [[CONV52]], align 4 -// CHECK18-NEXT: [[TMP134:%.*]] = load i64, i64* [[N_CASTED51]], align 8 -// CHECK18-NEXT: [[TMP135:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64* -// CHECK18-NEXT: store i64 [[TMP132]], i64* [[TMP137]], align 8 -// CHECK18-NEXT: [[TMP138:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to i64* -// CHECK18-NEXT: store i64 [[TMP132]], i64* [[TMP139]], align 8 -// CHECK18-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 0 -// CHECK18-NEXT: store i64 4, i64* [[TMP140]], align 8 -// CHECK18-NEXT: [[TMP141:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP141]], align 8 -// CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i64* -// CHECK18-NEXT: store i64 [[TMP134]], i64* [[TMP143]], align 8 -// CHECK18-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to i64* -// CHECK18-NEXT: store i64 [[TMP134]], i64* [[TMP145]], align 8 -// CHECK18-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 1 -// CHECK18-NEXT: store i64 4, i64* [[TMP146]], align 8 -// CHECK18-NEXT: [[TMP147:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP147]], align 8 -// CHECK18-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP149]], align 8 -// CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP151]], align 8 -// CHECK18-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP152]], align 8 -// CHECK18-NEXT: [[TMP153:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP153]], align 8 -// CHECK18-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP155]], align 8 -// CHECK18-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32** -// CHECK18-NEXT: store i32* [[VLA]], i32** [[TMP157]], align 8 -// CHECK18-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 3 -// CHECK18-NEXT: store i64 [[TMP135]], i64* [[TMP158]], align 8 -// CHECK18-NEXT: [[TMP159:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS55]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP159]], align 8 -// CHECK18-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS53]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP161:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS54]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES56]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP163:%.*]] = load i32, i32* [[N]], align 4 -// CHECK18-NEXT: store i32 [[TMP163]], i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK18-NEXT: [[TMP164:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK18-NEXT: [[SUB60:%.*]] = sub nsw i32 [[TMP164]], 0 -// CHECK18-NEXT: [[DIV61:%.*]] = sdiv i32 [[SUB60]], 1 -// CHECK18-NEXT: [[SUB62:%.*]] = sub nsw i32 [[DIV61]], 1 -// CHECK18-NEXT: store i32 [[SUB62]], i32* [[DOTCAPTURE_EXPR_59]], align 4 -// CHECK18-NEXT: [[TMP165:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_59]], align 4 -// CHECK18-NEXT: [[ADD63:%.*]] = add nsw i32 [[TMP165]], 1 -// CHECK18-NEXT: [[TMP166:%.*]] = zext i32 [[ADD63]] to i64 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP166]]) -// CHECK18-NEXT: [[TMP167:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168.region_id, i32 4, i8** [[TMP160]], i8** [[TMP161]], i64* [[TMP162]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP168:%.*]] = icmp ne i32 [[TMP167]], 0 -// CHECK18-NEXT: br i1 [[TMP168]], label [[OMP_OFFLOAD_FAILED64:%.*]], label [[OMP_OFFLOAD_CONT65:%.*]] -// CHECK18: omp_offload.failed64: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i64 [[TMP132]], i64 [[TMP134]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT65]] -// CHECK18: omp_offload.cont65: -// CHECK18-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) -// CHECK18-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK18-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) -// CHECK18-NEXT: [[TMP171:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: ret i32 [[TMP171]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK18-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK18-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK18-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 -// CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK18-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] -// CHECK18-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] -// CHECK18: cond.true12: -// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: br label [[COND_END14:%.*]] -// CHECK18: cond.false13: -// CHECK18-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END14]] -// CHECK18: cond.end14: -// CHECK18-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE12]] ], [ [[TMP32]], [[COND_FALSE13]] ] -// CHECK18-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP34]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP35]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK18-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK18-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK18-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK18-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK18-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK18-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4 -// CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK18-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK18-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK18: omp.precond.then: -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK18-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: br label [[OMP_PRECOND_END]] -// CHECK18: omp.precond.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK18-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK18-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 8 -// CHECK18-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[M_CASTED19:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [2 x i8*], align 8 -// CHECK18-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK18-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK18-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK18-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK18: omp_offload.failed5: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK18: omp_offload.cont6: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP18]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = load i64, i64* [[M_CASTED]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK18-NEXT: store i64 [[TMP19]], i64* [[TMP21]], align 8 -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK18-NEXT: store i64 [[TMP19]], i64* [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 8 -// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK18-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK18: omp_offload.failed11: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126(i64 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK18: omp_offload.cont12: -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP35]], align 8 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP37]], align 8 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP38]], align 8 -// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131.region_id, i32 1, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 -// CHECK18-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK18: omp_offload.failed17: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK18: omp_offload.cont18: -// CHECK18-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 -// CHECK18-NEXT: [[CONV20:%.*]] = bitcast i64* [[M_CASTED19]] to i32* -// CHECK18-NEXT: store i32 [[TMP43]], i32* [[CONV20]], align 4 -// CHECK18-NEXT: [[TMP44:%.*]] = load i64, i64* [[M_CASTED19]], align 8 -// CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* -// CHECK18-NEXT: store i64 [[TMP44]], i64* [[TMP46]], align 8 -// CHECK18-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* -// CHECK18-NEXT: store i64 [[TMP44]], i64* [[TMP48]], align 8 -// CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP49]], align 8 -// CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP51]], align 8 -// CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to [10 x i32]** -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP53]], align 8 -// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP54]], align 8 -// CHECK18-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 -// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK18-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 -// CHECK18-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] -// CHECK18: omp_offload.failed25: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136(i64 [[TMP44]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT26]] -// CHECK18: omp_offload.cont26: -// CHECK18-NEXT: ret i32 0 -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK18-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[CONV3]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CONV4:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ] -// CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[COND]] to i32 -// CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK18-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK18-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK18: cond.true: -// CHECK18-NEXT: br label [[COND_END:%.*]] -// CHECK18: cond.false: -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: br label [[COND_END]] -// CHECK18: cond.end: -// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 -// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK18: omp.loop.exit: -// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK18: omp.dispatch.cond: -// CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK18: omp.dispatch.body: -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK18-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK18: omp.inner.for.cond: -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK18: omp.inner.for.body: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK18: omp.body.continue: -// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK18: omp.inner.for.inc: -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] -// CHECK18: omp.inner.for.end: -// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK18: omp.dispatch.inc: -// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK18: omp.dispatch.end: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK19-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK19-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [4 x i64], align 4 -// CHECK19-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED31:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS32:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS33:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS34:%.*]] = alloca [3 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES35:%.*]] = alloca [3 x i64], align 4 -// CHECK19-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_37:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[M_CASTED45:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED46:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS47:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS48:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS49:%.*]] = alloca [4 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES50:%.*]] = alloca [4 x i64], align 4 -// CHECK19-NEXT: [[_TMP51:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_52:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_53:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK19-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK19-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK19-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK19-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK19-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK19-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK19-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK19-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK19-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK19-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK19-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK19-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK19-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK19-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK19-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK19-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK19-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK19-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK19-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) -// CHECK19-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK19-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK19: omp_offload.failed15: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK19: omp_offload.cont16: -// CHECK19-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 -// CHECK19-NEXT: store i32 [[TMP64]], i32* [[M_CASTED]], align 4 -// CHECK19-NEXT: [[TMP65:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK19-NEXT: [[TMP66:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP66]], i32* [[N_CASTED17]], align 4 -// CHECK19-NEXT: [[TMP67:%.*]] = load i32, i32* [[N_CASTED17]], align 4 -// CHECK19-NEXT: [[TMP68:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK19-NEXT: [[TMP69:%.*]] = sext i32 [[TMP68]] to i64 -// CHECK19-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* -// CHECK19-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 -// CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32* -// CHECK19-NEXT: store i32 [[TMP65]], i32* [[TMP73]], align 4 -// CHECK19-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP74]], align 4 -// CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP75]], align 4 -// CHECK19-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* -// CHECK19-NEXT: store i32 [[TMP67]], i32* [[TMP77]], align 4 -// CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK19-NEXT: store i32 [[TMP67]], i32* [[TMP79]], align 4 -// CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP80]], align 4 -// CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP81]], align 4 -// CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP83]], align 4 -// CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP85]], align 4 -// CHECK19-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP86]], align 4 -// CHECK19-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP87]], align 4 -// CHECK19-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 4 -// CHECK19-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP91]], align 4 -// CHECK19-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 3 -// CHECK19-NEXT: store i64 [[TMP69]], i64* [[TMP92]], align 4 -// CHECK19-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP93]], align 4 -// CHECK19-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP97:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP97]], i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK19-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK19-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP98]], 0 -// CHECK19-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 -// CHECK19-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 -// CHECK19-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK19-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK19-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP99]], 1 -// CHECK19-NEXT: [[TMP100:%.*]] = zext i32 [[ADD28]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP100]]) -// CHECK19-NEXT: [[TMP101:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158.region_id, i32 4, i8** [[TMP94]], i8** [[TMP95]], i64* [[TMP96]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP102:%.*]] = icmp ne i32 [[TMP101]], 0 -// CHECK19-NEXT: br i1 [[TMP102]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] -// CHECK19: omp_offload.failed29: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158(i32 [[TMP65]], i32 [[TMP67]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT30]] -// CHECK19: omp_offload.cont30: -// CHECK19-NEXT: [[TMP103:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP103]], i32* [[N_CASTED31]], align 4 -// CHECK19-NEXT: [[TMP104:%.*]] = load i32, i32* [[N_CASTED31]], align 4 -// CHECK19-NEXT: [[TMP105:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK19-NEXT: [[TMP106:%.*]] = sext i32 [[TMP105]] to i64 -// CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* -// CHECK19-NEXT: store i32 [[TMP104]], i32* [[TMP108]], align 4 -// CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* -// CHECK19-NEXT: store i32 [[TMP104]], i32* [[TMP110]], align 4 -// CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP111]], align 4 -// CHECK19-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP112]], align 4 -// CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP114]], align 4 -// CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP116]], align 4 -// CHECK19-NEXT: [[TMP117:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP117]], align 4 -// CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP118]], align 4 -// CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP120]], align 4 -// CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP122]], align 4 -// CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 2 -// CHECK19-NEXT: store i64 [[TMP106]], i64* [[TMP123]], align 4 -// CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP124]], align 4 -// CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP128:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP128]], i32* [[DOTCAPTURE_EXPR_37]], align 4 -// CHECK19-NEXT: [[TMP129:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_37]], align 4 -// CHECK19-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP129]], 0 -// CHECK19-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 -// CHECK19-NEXT: [[SUB41:%.*]] = sub nsw i32 [[DIV40]], 1 -// CHECK19-NEXT: store i32 [[SUB41]], i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK19-NEXT: [[TMP130:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK19-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP130]], 1 -// CHECK19-NEXT: [[TMP131:%.*]] = zext i32 [[ADD42]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP131]]) -// CHECK19-NEXT: [[TMP132:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163.region_id, i32 3, i8** [[TMP125]], i8** [[TMP126]], i64* [[TMP127]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP133:%.*]] = icmp ne i32 [[TMP132]], 0 -// CHECK19-NEXT: br i1 [[TMP133]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] -// CHECK19: omp_offload.failed43: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163(i32 [[TMP104]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT44]] -// CHECK19: omp_offload.cont44: -// CHECK19-NEXT: [[TMP134:%.*]] = load i32, i32* [[M]], align 4 -// CHECK19-NEXT: store i32 [[TMP134]], i32* [[M_CASTED45]], align 4 -// CHECK19-NEXT: [[TMP135:%.*]] = load i32, i32* [[M_CASTED45]], align 4 -// CHECK19-NEXT: [[TMP136:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP136]], i32* [[N_CASTED46]], align 4 -// CHECK19-NEXT: [[TMP137:%.*]] = load i32, i32* [[N_CASTED46]], align 4 -// CHECK19-NEXT: [[TMP138:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK19-NEXT: [[TMP139:%.*]] = sext i32 [[TMP138]] to i64 -// CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i32* -// CHECK19-NEXT: store i32 [[TMP135]], i32* [[TMP141]], align 4 -// CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32* -// CHECK19-NEXT: store i32 [[TMP135]], i32* [[TMP143]], align 4 -// CHECK19-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 0 -// CHECK19-NEXT: store i64 4, i64* [[TMP144]], align 4 -// CHECK19-NEXT: [[TMP145:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP145]], align 4 -// CHECK19-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* -// CHECK19-NEXT: store i32 [[TMP137]], i32* [[TMP147]], align 4 -// CHECK19-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* -// CHECK19-NEXT: store i32 [[TMP137]], i32* [[TMP149]], align 4 -// CHECK19-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP150]], align 4 -// CHECK19-NEXT: [[TMP151:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP151]], align 4 -// CHECK19-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP153]], align 4 -// CHECK19-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP155]], align 4 -// CHECK19-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP156]], align 4 -// CHECK19-NEXT: [[TMP157:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP157]], align 4 -// CHECK19-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP159]], align 4 -// CHECK19-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP161:%.*]] = bitcast i8** [[TMP160]] to i32** -// CHECK19-NEXT: store i32* [[VLA]], i32** [[TMP161]], align 4 -// CHECK19-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 3 -// CHECK19-NEXT: store i64 [[TMP139]], i64* [[TMP162]], align 4 -// CHECK19-NEXT: [[TMP163:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP163]], align 4 -// CHECK19-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP165:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP166:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP167:%.*]] = load i32, i32* [[N]], align 4 -// CHECK19-NEXT: store i32 [[TMP167]], i32* [[DOTCAPTURE_EXPR_52]], align 4 -// CHECK19-NEXT: [[TMP168:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_52]], align 4 -// CHECK19-NEXT: [[SUB54:%.*]] = sub nsw i32 [[TMP168]], 0 -// CHECK19-NEXT: [[DIV55:%.*]] = sdiv i32 [[SUB54]], 1 -// CHECK19-NEXT: [[SUB56:%.*]] = sub nsw i32 [[DIV55]], 1 -// CHECK19-NEXT: store i32 [[SUB56]], i32* [[DOTCAPTURE_EXPR_53]], align 4 -// CHECK19-NEXT: [[TMP169:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_53]], align 4 -// CHECK19-NEXT: [[ADD57:%.*]] = add nsw i32 [[TMP169]], 1 -// CHECK19-NEXT: [[TMP170:%.*]] = zext i32 [[ADD57]] to i64 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP170]]) -// CHECK19-NEXT: [[TMP171:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168.region_id, i32 4, i8** [[TMP164]], i8** [[TMP165]], i64* [[TMP166]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP172:%.*]] = icmp ne i32 [[TMP171]], 0 -// CHECK19-NEXT: br i1 [[TMP172]], label [[OMP_OFFLOAD_FAILED58:%.*]], label [[OMP_OFFLOAD_CONT59:%.*]] -// CHECK19: omp_offload.failed58: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i32 [[TMP135]], i32 [[TMP137]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT59]] -// CHECK19: omp_offload.cont59: -// CHECK19-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) -// CHECK19-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK19-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) -// CHECK19-NEXT: [[TMP175:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: ret i32 [[TMP175]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK19-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK19-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] -// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] -// CHECK19-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK19: cond.true11: -// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: br label [[COND_END13:%.*]] -// CHECK19: cond.false12: -// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END13]] -// CHECK19: cond.end13: -// CHECK19-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE11]] ], [ [[TMP30]], [[COND_FALSE12]] ] -// CHECK19-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP20]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK19-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP19]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK19-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK19: omp.precond.then: -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP21]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: br label [[OMP_PRECOND_END]] -// CHECK19: omp.precond.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK19-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK19-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 4 -// CHECK19-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[M_CASTED19:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [2 x i8*], align 4 -// CHECK19-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK19-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK19-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK19-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK19: omp_offload.failed5: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK19: omp_offload.cont6: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK19-NEXT: store i32 [[TMP18]], i32* [[M_CASTED]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK19-NEXT: store i32 [[TMP19]], i32* [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK19-NEXT: store i32 [[TMP19]], i32* [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK19-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK19: omp_offload.failed11: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126(i32 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK19: omp_offload.cont12: -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP35]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP37]], align 4 -// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP38]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131.region_id, i32 1, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 -// CHECK19-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK19: omp_offload.failed17: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK19: omp_offload.cont18: -// CHECK19-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 -// CHECK19-NEXT: store i32 [[TMP43]], i32* [[M_CASTED19]], align 4 -// CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[M_CASTED19]], align 4 -// CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK19-NEXT: store i32 [[TMP44]], i32* [[TMP46]], align 4 -// CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32* -// CHECK19-NEXT: store i32 [[TMP44]], i32* [[TMP48]], align 4 -// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP49]], align 4 -// CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP51]], align 4 -// CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to [10 x i32]** -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP53]], align 4 -// CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK19-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 -// CHECK19-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED24:%.*]], label [[OMP_OFFLOAD_CONT25:%.*]] -// CHECK19: omp_offload.failed24: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136(i32 [[TMP44]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT25]] -// CHECK19: omp_offload.cont25: -// CHECK19-NEXT: ret i32 0 -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK19-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP16]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP12]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK19-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK19: omp.dispatch.cond: -// CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK19: omp.dispatch.body: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK19: omp.body.continue: -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK19: omp.dispatch.inc: -// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK19: omp.dispatch.end: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK20-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4 -// CHECK20-NEXT: [[_TMP8:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [4 x i64], align 4 -// CHECK20-NEXT: [[_TMP22:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED31:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS32:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS33:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS34:%.*]] = alloca [3 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES35:%.*]] = alloca [3 x i64], align 4 -// CHECK20-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_37:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_38:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[M_CASTED45:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED46:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS47:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS48:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS49:%.*]] = alloca [4 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES50:%.*]] = alloca [4 x i64], align 4 -// CHECK20-NEXT: [[_TMP51:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_52:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_53:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK20-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK20-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK20-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK20-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP30]]) -// CHECK20-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// CHECK20-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4 -// CHECK20-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK20-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64 -// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK20-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK20-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4 -// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK20-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4 -// CHECK20-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4 -// CHECK20-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4 -// CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4 -// CHECK20-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2 -// CHECK20-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4 -// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK20-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4 -// CHECK20-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0 -// CHECK20-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK20-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1 -// CHECK20-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK20-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4 -// CHECK20-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1 -// CHECK20-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP61]]) -// CHECK20-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 -// CHECK20-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] -// CHECK20: omp_offload.failed15: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT16]] -// CHECK20: omp_offload.cont16: -// CHECK20-NEXT: [[TMP64:%.*]] = load i32, i32* [[M]], align 4 -// CHECK20-NEXT: store i32 [[TMP64]], i32* [[M_CASTED]], align 4 -// CHECK20-NEXT: [[TMP65:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK20-NEXT: [[TMP66:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP66]], i32* [[N_CASTED17]], align 4 -// CHECK20-NEXT: [[TMP67:%.*]] = load i32, i32* [[N_CASTED17]], align 4 -// CHECK20-NEXT: [[TMP68:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK20-NEXT: [[TMP69:%.*]] = sext i32 [[TMP68]] to i64 -// CHECK20-NEXT: [[TMP70:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* -// CHECK20-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4 -// CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32* -// CHECK20-NEXT: store i32 [[TMP65]], i32* [[TMP73]], align 4 -// CHECK20-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP74]], align 4 -// CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP75]], align 4 -// CHECK20-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* -// CHECK20-NEXT: store i32 [[TMP67]], i32* [[TMP77]], align 4 -// CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* -// CHECK20-NEXT: store i32 [[TMP67]], i32* [[TMP79]], align 4 -// CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP80]], align 4 -// CHECK20-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP81]], align 4 -// CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP83]], align 4 -// CHECK20-NEXT: [[TMP84:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP85]], align 4 -// CHECK20-NEXT: [[TMP86:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP86]], align 4 -// CHECK20-NEXT: [[TMP87:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP87]], align 4 -// CHECK20-NEXT: [[TMP88:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP89]], align 4 -// CHECK20-NEXT: [[TMP90:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP91]], align 4 -// CHECK20-NEXT: [[TMP92:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 3 -// CHECK20-NEXT: store i64 [[TMP69]], i64* [[TMP92]], align 4 -// CHECK20-NEXT: [[TMP93:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP93]], align 4 -// CHECK20-NEXT: [[TMP94:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP96:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP97:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP97]], i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK20-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4 -// CHECK20-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP98]], 0 -// CHECK20-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 -// CHECK20-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1 -// CHECK20-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK20-NEXT: [[TMP99:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4 -// CHECK20-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP99]], 1 -// CHECK20-NEXT: [[TMP100:%.*]] = zext i32 [[ADD28]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP100]]) -// CHECK20-NEXT: [[TMP101:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158.region_id, i32 4, i8** [[TMP94]], i8** [[TMP95]], i64* [[TMP96]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP102:%.*]] = icmp ne i32 [[TMP101]], 0 -// CHECK20-NEXT: br i1 [[TMP102]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]] -// CHECK20: omp_offload.failed29: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158(i32 [[TMP65]], i32 [[TMP67]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT30]] -// CHECK20: omp_offload.cont30: -// CHECK20-NEXT: [[TMP103:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP103]], i32* [[N_CASTED31]], align 4 -// CHECK20-NEXT: [[TMP104:%.*]] = load i32, i32* [[N_CASTED31]], align 4 -// CHECK20-NEXT: [[TMP105:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK20-NEXT: [[TMP106:%.*]] = sext i32 [[TMP105]] to i64 -// CHECK20-NEXT: [[TMP107:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* -// CHECK20-NEXT: store i32 [[TMP104]], i32* [[TMP108]], align 4 -// CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* -// CHECK20-NEXT: store i32 [[TMP104]], i32* [[TMP110]], align 4 -// CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP111]], align 4 -// CHECK20-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP112]], align 4 -// CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP114]], align 4 -// CHECK20-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP116]], align 4 -// CHECK20-NEXT: [[TMP117:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP117]], align 4 -// CHECK20-NEXT: [[TMP118:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP118]], align 4 -// CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP120]], align 4 -// CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP122]], align 4 -// CHECK20-NEXT: [[TMP123:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 2 -// CHECK20-NEXT: store i64 [[TMP106]], i64* [[TMP123]], align 4 -// CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS34]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP124]], align 4 -// CHECK20-NEXT: [[TMP125:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS32]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP126:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS33]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES35]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP128:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP128]], i32* [[DOTCAPTURE_EXPR_37]], align 4 -// CHECK20-NEXT: [[TMP129:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_37]], align 4 -// CHECK20-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP129]], 0 -// CHECK20-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 -// CHECK20-NEXT: [[SUB41:%.*]] = sub nsw i32 [[DIV40]], 1 -// CHECK20-NEXT: store i32 [[SUB41]], i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK20-NEXT: [[TMP130:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_38]], align 4 -// CHECK20-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP130]], 1 -// CHECK20-NEXT: [[TMP131:%.*]] = zext i32 [[ADD42]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP131]]) -// CHECK20-NEXT: [[TMP132:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163.region_id, i32 3, i8** [[TMP125]], i8** [[TMP126]], i64* [[TMP127]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP133:%.*]] = icmp ne i32 [[TMP132]], 0 -// CHECK20-NEXT: br i1 [[TMP133]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] -// CHECK20: omp_offload.failed43: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163(i32 [[TMP104]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT44]] -// CHECK20: omp_offload.cont44: -// CHECK20-NEXT: [[TMP134:%.*]] = load i32, i32* [[M]], align 4 -// CHECK20-NEXT: store i32 [[TMP134]], i32* [[M_CASTED45]], align 4 -// CHECK20-NEXT: [[TMP135:%.*]] = load i32, i32* [[M_CASTED45]], align 4 -// CHECK20-NEXT: [[TMP136:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP136]], i32* [[N_CASTED46]], align 4 -// CHECK20-NEXT: [[TMP137:%.*]] = load i32, i32* [[N_CASTED46]], align 4 -// CHECK20-NEXT: [[TMP138:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK20-NEXT: [[TMP139:%.*]] = sext i32 [[TMP138]] to i64 -// CHECK20-NEXT: [[TMP140:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i32* -// CHECK20-NEXT: store i32 [[TMP135]], i32* [[TMP141]], align 4 -// CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32* -// CHECK20-NEXT: store i32 [[TMP135]], i32* [[TMP143]], align 4 -// CHECK20-NEXT: [[TMP144:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 0 -// CHECK20-NEXT: store i64 4, i64* [[TMP144]], align 4 -// CHECK20-NEXT: [[TMP145:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP145]], align 4 -// CHECK20-NEXT: [[TMP146:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* -// CHECK20-NEXT: store i32 [[TMP137]], i32* [[TMP147]], align 4 -// CHECK20-NEXT: [[TMP148:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* -// CHECK20-NEXT: store i32 [[TMP137]], i32* [[TMP149]], align 4 -// CHECK20-NEXT: [[TMP150:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP150]], align 4 -// CHECK20-NEXT: [[TMP151:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP151]], align 4 -// CHECK20-NEXT: [[TMP152:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP153]], align 4 -// CHECK20-NEXT: [[TMP154:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP155]], align 4 -// CHECK20-NEXT: [[TMP156:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP156]], align 4 -// CHECK20-NEXT: [[TMP157:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP157]], align 4 -// CHECK20-NEXT: [[TMP158:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP159]], align 4 -// CHECK20-NEXT: [[TMP160:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP161:%.*]] = bitcast i8** [[TMP160]] to i32** -// CHECK20-NEXT: store i32* [[VLA]], i32** [[TMP161]], align 4 -// CHECK20-NEXT: [[TMP162:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 3 -// CHECK20-NEXT: store i64 [[TMP139]], i64* [[TMP162]], align 4 -// CHECK20-NEXT: [[TMP163:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS49]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP163]], align 4 -// CHECK20-NEXT: [[TMP164:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS47]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP165:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS48]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP166:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* [[DOTOFFLOAD_SIZES50]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP167:%.*]] = load i32, i32* [[N]], align 4 -// CHECK20-NEXT: store i32 [[TMP167]], i32* [[DOTCAPTURE_EXPR_52]], align 4 -// CHECK20-NEXT: [[TMP168:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_52]], align 4 -// CHECK20-NEXT: [[SUB54:%.*]] = sub nsw i32 [[TMP168]], 0 -// CHECK20-NEXT: [[DIV55:%.*]] = sdiv i32 [[SUB54]], 1 -// CHECK20-NEXT: [[SUB56:%.*]] = sub nsw i32 [[DIV55]], 1 -// CHECK20-NEXT: store i32 [[SUB56]], i32* [[DOTCAPTURE_EXPR_53]], align 4 -// CHECK20-NEXT: [[TMP169:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_53]], align 4 -// CHECK20-NEXT: [[ADD57:%.*]] = add nsw i32 [[TMP169]], 1 -// CHECK20-NEXT: [[TMP170:%.*]] = zext i32 [[ADD57]] to i64 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP170]]) -// CHECK20-NEXT: [[TMP171:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168.region_id, i32 4, i8** [[TMP164]], i8** [[TMP165]], i64* [[TMP166]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP172:%.*]] = icmp ne i32 [[TMP171]], 0 -// CHECK20-NEXT: br i1 [[TMP172]], label [[OMP_OFFLOAD_FAILED58:%.*]], label [[OMP_OFFLOAD_CONT59:%.*]] -// CHECK20: omp_offload.failed58: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i32 [[TMP135]], i32 [[TMP137]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT59]] -// CHECK20: omp_offload.cont59: -// CHECK20-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) -// CHECK20-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK20-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) -// CHECK20-NEXT: [[TMP175:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: ret i32 [[TMP175]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK20-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK20-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] -// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] -// CHECK20-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK20: cond.true11: -// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: br label [[COND_END13:%.*]] -// CHECK20: cond.false12: -// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END13]] -// CHECK20: cond.end13: -// CHECK20-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE11]] ], [ [[TMP30]], [[COND_FALSE12]] ] -// CHECK20-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 1) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] -// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP20]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK20-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP19]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK20-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK20: omp.precond.then: -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] -// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP21]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: br label [[OMP_PRECOND_END]] -// CHECK20: omp.precond.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK20-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK20-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[_TMP10:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x i8*], align 4 -// CHECK20-NEXT: [[_TMP16:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[M_CASTED19:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [2 x i8*], align 4 -// CHECK20-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK20-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK20-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 -// CHECK20-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK20: omp_offload.failed5: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK20: omp_offload.cont6: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[M]], align 4 -// CHECK20-NEXT: store i32 [[TMP18]], i32* [[M_CASTED]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[M_CASTED]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK20-NEXT: store i32 [[TMP19]], i32* [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK20-NEXT: store i32 [[TMP19]], i32* [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP28]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126.region_id, i32 2, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.23, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.24, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK20-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] -// CHECK20: omp_offload.failed11: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126(i32 [[TMP19]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT12]] -// CHECK20: omp_offload.cont12: -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP35]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP37]], align 4 -// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP38]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131.region_id, i32 1, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 -// CHECK20-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] -// CHECK20: omp_offload.failed17: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131([10 x i32]* [[A]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT18]] -// CHECK20: omp_offload.cont18: -// CHECK20-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 -// CHECK20-NEXT: store i32 [[TMP43]], i32* [[M_CASTED19]], align 4 -// CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[M_CASTED19]], align 4 -// CHECK20-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK20-NEXT: store i32 [[TMP44]], i32* [[TMP46]], align 4 -// CHECK20-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32* -// CHECK20-NEXT: store i32 [[TMP44]], i32* [[TMP48]], align 4 -// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP49]], align 4 -// CHECK20-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP51]], align 4 -// CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to [10 x i32]** -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP53]], align 4 -// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 -// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 10) -// CHECK20-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.31, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.32, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 -// CHECK20-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED24:%.*]], label [[OMP_OFFLOAD_CONT25:%.*]] -// CHECK20: omp_offload.failed24: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136(i32 [[TMP44]], [10 x i32]* [[A]]) #[[ATTR3]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT25]] -// CHECK20: omp_offload.cont25: -// CHECK20-NEXT: ret i32 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK20-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] -// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP16]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..25 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32 35, i32 [[TMP3]], i32 [[TMP4]], i32 1, i32 1) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP12]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK20-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i32)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i32 [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 -// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK20: cond.true: -// CHECK20-NEXT: br label [[COND_END:%.*]] -// CHECK20: cond.false: -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: br label [[COND_END]] -// CHECK20: cond.end: -// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK20: omp.loop.exit: -// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 -// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] -// CHECK20: omp.dispatch.cond: -// CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) -// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] -// CHECK20: omp.dispatch.body: -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK20: omp.inner.for.cond: -// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK20: omp.inner.for.body: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK20: omp.body.continue: -// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK20: omp.inner.for.inc: -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] -// CHECK20: omp.inner.for.end: -// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] -// CHECK20: omp.dispatch.inc: -// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] -// CHECK20: omp.dispatch.end: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@main -// CHECK21-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK21-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK21-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2:%.*]] -// CHECK21: for.cond2: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK21-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK21: for.body4: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK21-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK21: for.end9: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11:%.*]] -// CHECK21: for.cond11: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK21-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK21: for.body13: -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK21-NEXT: br label [[FOR_INC16:%.*]] -// CHECK21: for.inc16: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK21-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end18: -// CHECK21-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20:%.*]] -// CHECK21: for.cond20: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], [[TMP17]] -// CHECK21-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK21: for.body22: -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM23]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK21-NEXT: br label [[FOR_INC25:%.*]] -// CHECK21: for.inc25: -// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK21-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK21: for.end27: -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30:%.*]] -// CHECK21: for.cond30: -// CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] -// CHECK21-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK21: for.body32: -// CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK21-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM33]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK21-NEXT: br label [[FOR_INC35:%.*]] -// CHECK21: for.inc35: -// CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK21-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK21: for.end37: -// CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP25]]) -// CHECK21-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK21-NEXT: [[TMP26:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP26]]) -// CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: ret i32 [[TMP27]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK21-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2:%.*]] -// CHECK21: for.cond2: -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK21-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK21: for.body4: -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK21-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK21: for.end9: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11:%.*]] -// CHECK21: for.cond11: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK21-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK21: for.body13: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK21-NEXT: br label [[FOR_INC16:%.*]] -// CHECK21: for.inc16: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK21: for.end18: -// CHECK21-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20:%.*]] -// CHECK21: for.cond20: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK21-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK21: for.body22: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM23]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK21-NEXT: br label [[FOR_INC25:%.*]] -// CHECK21: for.inc25: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK21: for.end27: -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30:%.*]] -// CHECK21: for.cond30: -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK21-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK21: for.body32: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK21-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM33]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK21-NEXT: br label [[FOR_INC35:%.*]] -// CHECK21: for.inc35: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK21-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK21: for.end37: -// CHECK21-NEXT: ret i32 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@main -// CHECK22-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK22-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK22-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2:%.*]] -// CHECK22: for.cond2: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK22-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK22: for.body4: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK22-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK22: for.end9: -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11:%.*]] -// CHECK22: for.cond11: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK22-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK22: for.body13: -// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK22-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK22-NEXT: br label [[FOR_INC16:%.*]] -// CHECK22: for.inc16: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK22-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK22: for.end18: -// CHECK22-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20:%.*]] -// CHECK22: for.cond20: -// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], [[TMP17]] -// CHECK22-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK22: for.body22: -// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK22-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM23]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK22-NEXT: br label [[FOR_INC25:%.*]] -// CHECK22: for.inc25: -// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK22-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK22: for.end27: -// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30:%.*]] -// CHECK22: for.cond30: -// CHECK22-NEXT: [[TMP21:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] -// CHECK22-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK22: for.body32: -// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK22-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM33]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK22-NEXT: br label [[FOR_INC35:%.*]] -// CHECK22: for.inc35: -// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK22-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK22: for.end37: -// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP25]]) -// CHECK22-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK22-NEXT: [[TMP26:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP26]]) -// CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: ret i32 [[TMP27]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK22-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2:%.*]] -// CHECK22: for.cond2: -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK22-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK22: for.body4: -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK22-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK22: for.end9: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11:%.*]] -// CHECK22: for.cond11: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK22-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK22: for.body13: -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK22-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK22-NEXT: br label [[FOR_INC16:%.*]] -// CHECK22: for.inc16: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK22-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK22: for.end18: -// CHECK22-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20:%.*]] -// CHECK22: for.cond20: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK22-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK22: for.body22: -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK22-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM23]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK22-NEXT: br label [[FOR_INC25:%.*]] -// CHECK22: for.inc25: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK22-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK22: for.end27: -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30:%.*]] -// CHECK22: for.cond30: -// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK22-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK22: for.body32: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK22-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM33]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK22-NEXT: br label [[FOR_INC35:%.*]] -// CHECK22: for.inc35: -// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK22-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK22: for.end37: -// CHECK22-NEXT: ret i32 0 -// -// -// CHECK23-LABEL: define {{[^@]+}}@main -// CHECK23-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK23-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK23-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK23-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2:%.*]] -// CHECK23: for.cond2: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK23-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK23: for.body4: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK23-NEXT: br label [[FOR_INC6:%.*]] -// CHECK23: for.inc6: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK23: for.end8: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10:%.*]] -// CHECK23: for.cond10: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK23-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK23: for.body12: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: br label [[FOR_INC14:%.*]] -// CHECK23: for.inc14: -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK23-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK23: for.end16: -// CHECK23-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18:%.*]] -// CHECK23: for.cond18: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP15]], [[TMP16]] -// CHECK23-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK23: for.body20: -// CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP17]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK23-NEXT: br label [[FOR_INC22:%.*]] -// CHECK23: for.inc22: -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK23-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK23: for.end24: -// CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27:%.*]] -// CHECK23: for.cond27: -// CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[TMP21:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]] -// CHECK23-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK23: for.body29: -// CHECK23-NEXT: [[TMP22:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP22]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK23-NEXT: br label [[FOR_INC31:%.*]] -// CHECK23: for.inc31: -// CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK23-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK23: for.end33: -// CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP24]]) -// CHECK23-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK23-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) -// CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK23-NEXT: ret i32 [[TMP26]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK23-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2:%.*]] -// CHECK23: for.cond2: -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK23-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK23: for.body4: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK23-NEXT: br label [[FOR_INC6:%.*]] -// CHECK23: for.inc6: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK23-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK23: for.end8: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10:%.*]] -// CHECK23: for.cond10: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK23-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK23: for.body12: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: br label [[FOR_INC14:%.*]] -// CHECK23: for.inc14: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK23: for.end16: -// CHECK23-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18:%.*]] -// CHECK23: for.cond18: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK23-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK23: for.body20: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK23-NEXT: br label [[FOR_INC22:%.*]] -// CHECK23: for.inc22: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK23-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK23: for.end24: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27:%.*]] -// CHECK23: for.cond27: -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK23-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK23: for.body29: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP15]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK23-NEXT: br label [[FOR_INC31:%.*]] -// CHECK23: for.inc31: -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK23-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK23: for.end33: -// CHECK23-NEXT: ret i32 0 -// -// -// CHECK24-LABEL: define {{[^@]+}}@main -// CHECK24-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK24-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK24-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK24-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2:%.*]] -// CHECK24: for.cond2: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK24-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK24: for.body4: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK24-NEXT: br label [[FOR_INC6:%.*]] -// CHECK24: for.inc6: -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK24-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK24: for.end8: -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10:%.*]] -// CHECK24: for.cond10: -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK24-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK24: for.body12: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: br label [[FOR_INC14:%.*]] -// CHECK24: for.inc14: -// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK24-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK24: for.end16: -// CHECK24-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18:%.*]] -// CHECK24: for.cond18: -// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP15]], [[TMP16]] -// CHECK24-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK24: for.body20: -// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP17]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK24-NEXT: br label [[FOR_INC22:%.*]] -// CHECK24: for.inc22: -// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK24-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK24: for.end24: -// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27:%.*]] -// CHECK24: for.cond27: -// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[TMP21:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]] -// CHECK24-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK24: for.body29: -// CHECK24-NEXT: [[TMP22:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP22]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK24-NEXT: br label [[FOR_INC31:%.*]] -// CHECK24: for.inc31: -// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK24-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK24: for.end33: -// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP24]]) -// CHECK24-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK24-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) -// CHECK24-NEXT: [[TMP26:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK24-NEXT: ret i32 [[TMP26]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK24-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2:%.*]] -// CHECK24: for.cond2: -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK24-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK24: for.body4: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK24-NEXT: br label [[FOR_INC6:%.*]] -// CHECK24: for.inc6: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK24-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK24: for.end8: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10:%.*]] -// CHECK24: for.cond10: -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK24-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK24: for.body12: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: br label [[FOR_INC14:%.*]] -// CHECK24: for.inc14: -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK24-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK24: for.end16: -// CHECK24-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18:%.*]] -// CHECK24: for.cond18: -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK24-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK24: for.body20: -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK24-NEXT: br label [[FOR_INC22:%.*]] -// CHECK24: for.inc22: -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK24-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK24: for.end24: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27:%.*]] -// CHECK24: for.cond27: -// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK24-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK24: for.body29: -// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP15]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK24-NEXT: br label [[FOR_INC31:%.*]] -// CHECK24: for.inc31: -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK24-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK24: for.end33: -// CHECK24-NEXT: ret i32 0 -// diff --git a/clang/test/OpenMP/teams_distribute_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_private_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_private_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2094,6 +2094,28 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: @@ -2132,191 +2154,6 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done8: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK5: arraydestroy.body10: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK5: arraydestroy.done14: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP11]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: @@ -2334,73 +2171,113 @@ // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 +// CHECK5-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* undef, i32** [[_TMP1]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK5-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[SIVAR]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK5-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK5-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK5-NEXT: ret void // // @@ -2413,6 +2290,13 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: @@ -2441,6 +2325,28 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: @@ -2479,191 +2385,6 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done8: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK6: arraydestroy.body10: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK6: arraydestroy.done14: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP11]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: @@ -2681,73 +2402,113 @@ // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 +// CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) +// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK6-NEXT: ret i32 0 // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 +// CHECK6-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* +// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* undef, i32** [[_TMP1]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK6-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[SIVAR]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK6-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 +// CHECK6-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK6-NEXT: ret void // // @@ -2760,1414 +2521,9 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK7-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK7-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done7: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK7: arraydestroy.body9: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK7: arraydestroy.done13: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP11]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK8-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done7: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK8: arraydestroy.body9: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK8: arraydestroy.done13: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP11]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 -// CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init() -// CHECK9-NEXT: call void @__cxx_global_var_init.1() -// CHECK9-NEXT: call void @__cxx_global_var_init.2() -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* -// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] -// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 -// CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(24) [[REF_TMP]]) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__cxx_global_var_init() -// CHECK10-NEXT: call void @__cxx_global_var_init.1() -// CHECK10-NEXT: call void @__cxx_global_var_init.2() -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp b/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1410,544 +1410,292 @@ // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 +// CHECK5-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: store i32 0, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP14:%.*]] = bitcast i32* [[SIVAR1]] to i8* +// CHECK5-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK5-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP15]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: switch i32 [[TMP16]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK5-NEXT: ] +// CHECK5: .omp.reduction.case1: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK5: .omp.reduction.case2: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP19]] monotonic, align 4 +// CHECK5-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK5: .omp.reduction.default: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK5-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK5-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@main // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK9-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK9: omp.body.continue: -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP14:%.*]] = bitcast i32* [[SIVAR1]] to i8* -// CHECK9-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP15]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: switch i32 [[TMP16]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK9-NEXT: ] -// CHECK9: .omp.reduction.case1: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.case2: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP19]] monotonic, align 4 -// CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.default: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK9-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK10-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK10-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 -// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK10: cond.true: -// CHECK10-NEXT: br label [[COND_END:%.*]] -// CHECK10: cond.false: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: br label [[COND_END]] -// CHECK10: cond.end: -// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) -// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK10: omp.body.continue: -// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK10: omp.inner.for.end: -// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK10: omp.loop.exit: -// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP14:%.*]] = bitcast i32* [[SIVAR1]] to i8* -// CHECK10-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP15]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: switch i32 [[TMP16]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK10-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK10-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK10-NEXT: ] -// CHECK10: .omp.reduction.case1: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 -// CHECK10-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK10: .omp.reduction.case2: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 -// CHECK10-NEXT: [[TMP20:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP19]] monotonic, align 4 -// CHECK10-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK10: .omp.reduction.default: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK10-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 +// CHECK6-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 +// CHECK6-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(8) [[REF_TMP]]) +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP14:%.*]] = bitcast i32* [[SIVAR1]] to i8* +// CHECK6-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK6-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP15]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: switch i32 [[TMP16]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.reduction.case1: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.case2: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP19]] monotonic, align 4 +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.default: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_firstprivate_codegen.cpp --- a/clang/test/OpenMP/teams_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_firstprivate_codegen.cpp @@ -7,40 +7,40 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -415,6154 +415,4846 @@ // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK5-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP8]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 8 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP26]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK5-NEXT: store i64 [[TMP4]], i64* [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK5-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK5-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* +// CHECK5-NEXT: store i32 [[TMP34]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP35:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 +// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK5-NEXT: store i64 [[TMP35]], i64* [[TMP37]], align 8 +// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK5-NEXT: store i64 [[TMP35]], i64* [[TMP39]], align 8 +// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP40]], align 8 +// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK5-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK5: omp_offload.failed7: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP35]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK5: omp_offload.cont8: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done9: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP46]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 +// CHECK5-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK5-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done4: +// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 +// CHECK5-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) +// CHECK5-NEXT: store i32 2, i32* [[CONV1]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done9: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK5-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) +// CHECK5-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK5-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK9-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP8]], align 8 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP26]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* -// CHECK9-NEXT: store i32 [[TMP34]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP35:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 -// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP37]], align 8 -// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP39]], align 8 -// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP40]], align 8 -// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK9-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK9: omp_offload.failed7: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP35]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK9: omp_offload.cont8: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done9: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP46]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 +// CHECK5-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 128 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP5]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK5-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 8 +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK5-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK5-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK5-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 8 +// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 8 +// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK5-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] +// CHECK5: omp_offload.failed4: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT5]] +// CHECK5: omp_offload.cont5: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done6: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP35]] +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float +// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] +// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK5-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK5-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK5-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 -// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) -// CHECK9-NEXT: ret void +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK9-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done4: -// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) -// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done9: -// CHECK9-NEXT: ret void +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) -// CHECK9-NEXT: ret void +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 +// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK5-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK5-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK5: omp.arraycpy.body: +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK5: omp.arraycpy.done4: +// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) +// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 +// CHECK5-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 +// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done9: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) -// CHECK9-NEXT: ret void +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK5-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK5-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK9-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK6-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK6-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK6-NEXT: store i64 [[TMP2]], i64* [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 8 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 8 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK6-NEXT: store i64 [[TMP4]], i64* [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK6-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK6-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* +// CHECK6-NEXT: store i32 [[TMP34]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP35:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 +// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK6-NEXT: store i64 [[TMP35]], i64* [[TMP37]], align 8 +// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* +// CHECK6-NEXT: store i64 [[TMP35]], i64* [[TMP39]], align 8 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP40]], align 8 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK6-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK6: omp_offload.failed7: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP35]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK6: omp_offload.cont8: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done9: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP46]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 +// CHECK6-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 +// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK6-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK6-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done4: +// CHECK6-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK6-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) +// CHECK6-NEXT: store i32 2, i32* [[CONV1]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done9: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK6-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK6-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP5]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK9-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK9-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 8 -// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] -// CHECK9: omp_offload.failed4: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT5]] -// CHECK9: omp_offload.cont5: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done6: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP35]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK6-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK6-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK9-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 +// CHECK6-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 128 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) +// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP5]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK6-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 8 +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK6-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 8 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK6-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK6-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 8 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK6-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] +// CHECK6: omp_offload.failed4: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT5]] +// CHECK6: omp_offload.cont5: +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done6: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP35]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float +// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] +// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK6-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK6-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK6-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK6-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK6-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 +// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK6-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK6-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK6-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done4: +// CHECK6-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) +// CHECK6-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 +// CHECK6-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 +// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done9: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK6-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) -// CHECK9-NEXT: ret void +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK6-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 -// CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK9: omp.arraycpy.body: -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK9: omp.arraycpy.done4: -// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) -// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK9-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done9: -// CHECK9-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@main +// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK7-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK7-NEXT: store i32 [[TMP2]], i32* [[TMP8]], align 4 +// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 4 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 4 +// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK7-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK7-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: store i32 [[TMP34]], i32* [[T_VAR_CASTED1]], align 4 +// CHECK7-NEXT: [[TMP35:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 +// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* +// CHECK7-NEXT: store i32 [[TMP35]], i32* [[TMP37]], align 4 +// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* +// CHECK7-NEXT: store i32 [[TMP35]], i32* [[TMP39]], align 4 +// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK7-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK7: omp_offload.failed5: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP35]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK7: omp_offload.cont6: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done7: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP46]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) -// CHECK9-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 +// CHECK7-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* +// CHECK7-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done3: +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) +// CHECK7-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done8: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK7-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK7-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) +// CHECK7-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK7-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK7-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) -// CHECK9-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 -// CHECK9-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 +// CHECK7-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 128 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) +// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP5]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK7-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK7-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK7-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 4 +// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK7-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 4 +// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK7-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK7-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 4 +// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 4 +// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK7-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] +// CHECK7: omp_offload.failed4: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT5]] +// CHECK7: omp_offload.cont5: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done6: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP35]] +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float +// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] +// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK7-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK7-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK7-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK7-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK7-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK7-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 +// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK7-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK7-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 +// CHECK7-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 +// CHECK7-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK7-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK7: omp.arraycpy.body: +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK7: omp.arraycpy.done4: +// CHECK7-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) +// CHECK7-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 +// CHECK7-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* +// CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done9: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK7-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 -// CHECK10-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* -// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* -// CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP8]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 -// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 8 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 8 -// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP26]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK10-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* -// CHECK10-NEXT: store i32 [[TMP34]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP35:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 -// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* -// CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP37]], align 8 -// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* -// CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP39]], align 8 -// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP40]], align 8 -// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK10-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] -// CHECK10: omp_offload.failed7: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP35]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT8]] -// CHECK10: omp_offload.cont8: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done9: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP46]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK7-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK7-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 -// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 -// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@main +// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK8-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[TMP8]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK8-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK8-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: store i32 [[TMP34]], i32* [[T_VAR_CASTED1]], align 4 +// CHECK8-NEXT: [[TMP35:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 +// CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* +// CHECK8-NEXT: store i32 [[TMP35]], i32* [[TMP37]], align 4 +// CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* +// CHECK8-NEXT: store i32 [[TMP35]], i32* [[TMP39]], align 4 +// CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP40]], align 4 +// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 +// CHECK8-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK8: omp_offload.failed5: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP35]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK8: omp_offload.cont6: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done7: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP46]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK10-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done4: -// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) -// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) -// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done9: -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 +// CHECK8-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* +// CHECK8-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done3: +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) +// CHECK8-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done8: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK8-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK8-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK8-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK8-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 +// CHECK8-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 128 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) +// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP5]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK8-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK8-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK8-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK8-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK8-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK8-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] +// CHECK8: omp_offload.failed4: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT5]] +// CHECK8: omp_offload.cont5: +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done6: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP35]] +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float +// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] +// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK8-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK8-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK8-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK8-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK8-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK8-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK10-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP5]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 8 -// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 -// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 8 -// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 8 -// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK10-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK10-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 8 -// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 8 -// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK10-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] -// CHECK10: omp_offload.failed4: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT5]] -// CHECK10: omp_offload.cont5: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done6: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP35]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 +// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK8-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK8-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* +// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done4: +// CHECK8-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) +// CHECK8-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 +// CHECK8-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 +// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* +// CHECK8-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done9: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK10-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK8-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg +// CHECK9-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 +// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK9-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] +// CHECK9-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] +// CHECK9-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** +// CHECK9-NEXT: store float* [[TMP8]], float** [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to float** +// CHECK9-NEXT: store float* [[TMP8]], float** [[TMP18]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 0, i64* [[TMP19]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** +// CHECK9-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** +// CHECK9-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP24]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 0, i64* [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP28]], align 8 +// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP30]], align 8 +// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 8, i64* [[TMP31]], align 8 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP32]], align 8 +// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to ppc_fp128** +// CHECK9-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP34]], align 8 +// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to ppc_fp128** +// CHECK9-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP36]], align 8 +// CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK9-NEXT: store i64 0, i64* [[TMP37]], align 8 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP38]], align 8 +// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP40]], align 8 +// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP42]], align 8 +// CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK9-NEXT: store i64 8, i64* [[TMP43]], align 8 +// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP44]], align 8 +// CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP46]], align 8 +// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP48]], align 8 +// CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK9-NEXT: store i64 8, i64* [[TMP49]], align 8 +// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 +// CHECK9-NEXT: store i8* null, i8** [[TMP50]], align 8 +// CHECK9-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** +// CHECK9-NEXT: store double* [[VLA]], double** [[TMP52]], align 8 +// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** +// CHECK9-NEXT: store double* [[VLA]], double** [[TMP54]], align 8 +// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP55]], align 8 +// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 +// CHECK9-NEXT: store i8* null, i8** [[TMP56]], align 8 +// CHECK9-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64* +// CHECK9-NEXT: store i64 [[TMP12]], i64* [[TMP58]], align 8 +// CHECK9-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i64* +// CHECK9-NEXT: store i64 [[TMP12]], i64* [[TMP60]], align 8 +// CHECK9-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK9-NEXT: store i64 4, i64* [[TMP61]], align 8 +// CHECK9-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 +// CHECK9-NEXT: store i8* null, i8** [[TMP62]], align 8 +// CHECK9-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP64:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP65:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, i32 8, i8** [[TMP63]], i8** [[TMP64]], i64* [[TMP65]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 +// CHECK9-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(float* [[TMP8]], %struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP68:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP68]]) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 +// CHECK9-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK9-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, ppc_fp128*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[CONV]], i64 [[TMP0]], ppc_fp128* [[TMP5]], float* [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]]) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK9-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK9-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK9-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 +// CHECK9-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) +// CHECK9-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 +// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 signext [[TMP13]], ppc_fp128* [[TMP14]]) +// CHECK9-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK10-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg +// CHECK9-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 8 +// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK9-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] +// CHECK9-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] +// CHECK9-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 +// CHECK9-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr i32, i32* [[B2]], i32 1 +// CHECK9-NEXT: [[TMP16:%.*]] = bitcast i32* [[A3]] to i8* +// CHECK9-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP15]] to i8* +// CHECK9-NEXT: [[TMP18:%.*]] = ptrtoint i8* [[TMP17]] to i64 +// CHECK9-NEXT: [[TMP19:%.*]] = ptrtoint i8* [[TMP16]] to i64 +// CHECK9-NEXT: [[TMP20:%.*]] = sub i64 [[TMP18]], [[TMP19]] +// CHECK9-NEXT: [[TMP21:%.*]] = sdiv exact i64 [[TMP20]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** +// CHECK9-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP23]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.St** +// CHECK9-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP25]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: store i64 0, i64* [[TMP26]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK9-NEXT: store i8* null, i8** [[TMP27]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP29]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP31]], align 8 +// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK9-NEXT: store i64 8, i64* [[TMP32]], align 8 +// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to ppc_fp128** +// CHECK9-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP35]], align 8 +// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to ppc_fp128** +// CHECK9-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP37]], align 8 +// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK9-NEXT: store i64 0, i64* [[TMP38]], align 8 +// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK9-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP41]], align 8 +// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP43]], align 8 +// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK9-NEXT: store i64 8, i64* [[TMP44]], align 8 +// CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK9-NEXT: store i8* null, i8** [[TMP45]], align 8 +// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP47]], align 8 +// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64* +// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP49]], align 8 +// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK9-NEXT: store i64 8, i64* [[TMP50]], align 8 +// CHECK9-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK9-NEXT: store i8* null, i8** [[TMP51]], align 8 +// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** +// CHECK9-NEXT: store double* [[VLA]], double** [[TMP53]], align 8 +// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double** +// CHECK9-NEXT: store double* [[VLA]], double** [[TMP55]], align 8 +// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK9-NEXT: store i64 [[TMP14]], i64* [[TMP56]], align 8 +// CHECK9-NEXT: [[TMP57:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 +// CHECK9-NEXT: store i8* null, i8** [[TMP57]], align 8 +// CHECK9-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to %struct.St** +// CHECK9-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP59]], align 8 +// CHECK9-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32** +// CHECK9-NEXT: store i32* [[A3]], i32** [[TMP61]], align 8 +// CHECK9-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK9-NEXT: store i64 [[TMP21]], i64* [[TMP62]], align 8 +// CHECK9-NEXT: [[TMP63:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 +// CHECK9-NEXT: store i8* null, i8** [[TMP63]], align 8 +// CHECK9-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to %struct.St** +// CHECK9-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP65]], align 8 +// CHECK9-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32** +// CHECK9-NEXT: store i32* [[B2]], i32** [[TMP67]], align 8 +// CHECK9-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK9-NEXT: store i64 4, i64* [[TMP68]], align 8 +// CHECK9-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 +// CHECK9-NEXT: store i8* null, i8** [[TMP69]], align 8 +// CHECK9-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to %struct.St** +// CHECK9-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP71]], align 8 +// CHECK9-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32** +// CHECK9-NEXT: store i32* [[A3]], i32** [[TMP73]], align 8 +// CHECK9-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK9-NEXT: store i64 4, i64* [[TMP74]], align 8 +// CHECK9-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 +// CHECK9-NEXT: store i8* null, i8** [[TMP75]], align 8 +// CHECK9-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* +// CHECK9-NEXT: store i64 [[TMP12]], i64* [[TMP77]], align 8 +// CHECK9-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* +// CHECK9-NEXT: store i64 [[TMP12]], i64* [[TMP79]], align 8 +// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK9-NEXT: store i64 4, i64* [[TMP80]], align 8 +// CHECK9-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 +// CHECK9-NEXT: store i8* null, i8** [[TMP81]], align 8 +// CHECK9-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, i32 10, i8** [[TMP82]], i8** [[TMP83]], i64* [[TMP84]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK9-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 +// CHECK9-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK9: omp_offload.failed: +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(%struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], %struct.St* [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] +// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK9: omp_offload.cont: +// CHECK9-NEXT: [[TMP87:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP87]]) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK10-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) -// CHECK10-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 +// CHECK9-SAME: (%struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK9-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK9-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, ppc_fp128*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP0]], ppc_fp128* [[TMP5]], %struct.St* [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]], i32* [[CONV]], %struct.St* [[TMP6]]) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 -// CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK10: omp.arraycpy.body: -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK10: omp.arraycpy.done4: -// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) -// CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) -// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK10-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done9: -// CHECK10-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 +// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() +// CHECK9-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK9-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 +// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK9-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 +// CHECK9-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* +// CHECK9-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 [[TMP9]], i1 false) +// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 +// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP3]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i64 [[TMP13]] +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 +// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] +// CHECK9-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 +// CHECK9-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 +// CHECK9-NEXT: [[TMP15:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK9-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 +// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP15]], i64 [[IDXPROM11]] +// CHECK9-NEXT: store ppc_fp128 [[CONV9]], ppc_fp128* [[ARRAYIDX12]], align 16 +// CHECK9-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) -// CHECK10-NEXT: ret void +// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK9-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg +// CHECK10-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 +// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK10-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK10-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] +// CHECK10-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] +// CHECK10-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** +// CHECK10-NEXT: store float* [[TMP8]], float** [[TMP16]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to float** +// CHECK10-NEXT: store float* [[TMP8]], float** [[TMP18]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 0, i64* [[TMP19]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** +// CHECK10-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP22]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** +// CHECK10-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP24]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 0, i64* [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP28]], align 8 +// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP30]], align 8 +// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 8, i64* [[TMP31]], align 8 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP32]], align 8 +// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to ppc_fp128** +// CHECK10-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP34]], align 8 +// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to ppc_fp128** +// CHECK10-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP36]], align 8 +// CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK10-NEXT: store i64 0, i64* [[TMP37]], align 8 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP38]], align 8 +// CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP40]], align 8 +// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP42]], align 8 +// CHECK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK10-NEXT: store i64 8, i64* [[TMP43]], align 8 +// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP44]], align 8 +// CHECK10-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP46]], align 8 +// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP48]], align 8 +// CHECK10-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK10-NEXT: store i64 8, i64* [[TMP49]], align 8 +// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 +// CHECK10-NEXT: store i8* null, i8** [[TMP50]], align 8 +// CHECK10-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** +// CHECK10-NEXT: store double* [[VLA]], double** [[TMP52]], align 8 +// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** +// CHECK10-NEXT: store double* [[VLA]], double** [[TMP54]], align 8 +// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP55]], align 8 +// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 +// CHECK10-NEXT: store i8* null, i8** [[TMP56]], align 8 +// CHECK10-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64* +// CHECK10-NEXT: store i64 [[TMP12]], i64* [[TMP58]], align 8 +// CHECK10-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i64* +// CHECK10-NEXT: store i64 [[TMP12]], i64* [[TMP60]], align 8 +// CHECK10-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK10-NEXT: store i64 4, i64* [[TMP61]], align 8 +// CHECK10-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 +// CHECK10-NEXT: store i8* null, i8** [[TMP62]], align 8 +// CHECK10-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP64:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP65:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, i32 8, i8** [[TMP63]], i8** [[TMP64]], i64* [[TMP65]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 +// CHECK10-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(float* [[TMP8]], %struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP68:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP68]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK10-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 +// CHECK10-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK10-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK10-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 +// CHECK10-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 +// CHECK10-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, ppc_fp128*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[CONV]], i64 [[TMP0]], ppc_fp128* [[TMP5]], float* [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK10-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 +// CHECK10-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 +// CHECK10-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK10-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK10-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 +// CHECK10-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) +// CHECK10-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 +// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 signext [[TMP13]], ppc_fp128* [[TMP14]]) +// CHECK10-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg +// CHECK10-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 8 +// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK10-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] +// CHECK10-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] +// CHECK10-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 +// CHECK10-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr i32, i32* [[B2]], i32 1 +// CHECK10-NEXT: [[TMP16:%.*]] = bitcast i32* [[A3]] to i8* +// CHECK10-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP15]] to i8* +// CHECK10-NEXT: [[TMP18:%.*]] = ptrtoint i8* [[TMP17]] to i64 +// CHECK10-NEXT: [[TMP19:%.*]] = ptrtoint i8* [[TMP16]] to i64 +// CHECK10-NEXT: [[TMP20:%.*]] = sub i64 [[TMP18]], [[TMP19]] +// CHECK10-NEXT: [[TMP21:%.*]] = sdiv exact i64 [[TMP20]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) +// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** +// CHECK10-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP23]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.St** +// CHECK10-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP25]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: store i64 0, i64* [[TMP26]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK10-NEXT: store i8* null, i8** [[TMP27]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP29]], align 8 +// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* +// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP31]], align 8 +// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK10-NEXT: store i64 8, i64* [[TMP32]], align 8 +// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to ppc_fp128** +// CHECK10-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP35]], align 8 +// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to ppc_fp128** +// CHECK10-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP37]], align 8 +// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK10-NEXT: store i64 0, i64* [[TMP38]], align 8 +// CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK10-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP41]], align 8 +// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP43]], align 8 +// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK10-NEXT: store i64 8, i64* [[TMP44]], align 8 +// CHECK10-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK10-NEXT: store i8* null, i8** [[TMP45]], align 8 +// CHECK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP47]], align 8 +// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64* +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP49]], align 8 +// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK10-NEXT: store i64 8, i64* [[TMP50]], align 8 +// CHECK10-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK10-NEXT: store i8* null, i8** [[TMP51]], align 8 +// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** +// CHECK10-NEXT: store double* [[VLA]], double** [[TMP53]], align 8 +// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 +// CHECK10-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double** +// CHECK10-NEXT: store double* [[VLA]], double** [[TMP55]], align 8 +// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK10-NEXT: store i64 [[TMP14]], i64* [[TMP56]], align 8 +// CHECK10-NEXT: [[TMP57:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 +// CHECK10-NEXT: store i8* null, i8** [[TMP57]], align 8 +// CHECK10-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to %struct.St** +// CHECK10-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP59]], align 8 +// CHECK10-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 +// CHECK10-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32** +// CHECK10-NEXT: store i32* [[A3]], i32** [[TMP61]], align 8 +// CHECK10-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK10-NEXT: store i64 [[TMP21]], i64* [[TMP62]], align 8 +// CHECK10-NEXT: [[TMP63:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 +// CHECK10-NEXT: store i8* null, i8** [[TMP63]], align 8 +// CHECK10-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to %struct.St** +// CHECK10-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP65]], align 8 +// CHECK10-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 +// CHECK10-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32** +// CHECK10-NEXT: store i32* [[B2]], i32** [[TMP67]], align 8 +// CHECK10-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK10-NEXT: store i64 4, i64* [[TMP68]], align 8 +// CHECK10-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 +// CHECK10-NEXT: store i8* null, i8** [[TMP69]], align 8 +// CHECK10-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 +// CHECK10-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to %struct.St** +// CHECK10-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP71]], align 8 +// CHECK10-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 +// CHECK10-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32** +// CHECK10-NEXT: store i32* [[A3]], i32** [[TMP73]], align 8 +// CHECK10-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK10-NEXT: store i64 4, i64* [[TMP74]], align 8 +// CHECK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 +// CHECK10-NEXT: store i8* null, i8** [[TMP75]], align 8 +// CHECK10-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 +// CHECK10-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* +// CHECK10-NEXT: store i64 [[TMP12]], i64* [[TMP77]], align 8 +// CHECK10-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 +// CHECK10-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* +// CHECK10-NEXT: store i64 [[TMP12]], i64* [[TMP79]], align 8 +// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK10-NEXT: store i64 4, i64* [[TMP80]], align 8 +// CHECK10-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 +// CHECK10-NEXT: store i8* null, i8** [[TMP81]], align 8 +// CHECK10-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, i32 10, i8** [[TMP82]], i8** [[TMP83]], i64* [[TMP84]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK10-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 +// CHECK10-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK10: omp_offload.failed: +// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(%struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], %struct.St* [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] +// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK10: omp_offload.cont: +// CHECK10-NEXT: [[TMP87:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP87]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 +// CHECK10-SAME: (%struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK10-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 +// CHECK10-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 +// CHECK10-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, ppc_fp128*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP0]], ppc_fp128* [[TMP5]], %struct.St* [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]], i32* [[CONV]], %struct.St* [[TMP6]]) // CHECK10-NEXT: ret void // // -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 +// CHECK10-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 +// CHECK10-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() +// CHECK10-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK10-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 +// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] +// CHECK10-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 +// CHECK10-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* +// CHECK10-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 [[TMP9]], i1 false) +// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 +// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK10-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP3]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i64 [[TMP13]] +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] +// CHECK10-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 +// CHECK10-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 +// CHECK10-NEXT: [[TMP15:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 +// CHECK10-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 +// CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP15]], i64 [[IDXPROM11]] +// CHECK10-NEXT: store ppc_fp128 [[CONV9]], ppc_fp128* [[ARRAYIDX12]], align 16 +// CHECK10-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK10-SAME: () #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK11-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe +// CHECK11-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK11-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP8]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 4 -// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 +// CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK11-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] +// CHECK11-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load float*, float** [[A_ADDR]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] +// CHECK11-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 +// CHECK11-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to float** +// CHECK11-NEXT: store float* [[TMP5]], float** [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** +// CHECK11-NEXT: store float* [[TMP5]], float** [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 0, i64* [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.St** +// CHECK11-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP20]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** +// CHECK11-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 0, i64* [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 // CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 // CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP28]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 4, i64* [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to x86_fp80** +// CHECK11-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP32]], align 4 +// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to x86_fp80** +// CHECK11-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP34]], align 4 +// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK11-NEXT: store i64 0, i64* [[TMP35]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP38]], align 4 +// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP40]], align 4 +// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK11-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP44]], align 4 +// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP46]], align 4 +// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK11-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 +// CHECK11-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to double** +// CHECK11-NEXT: store double* [[VLA]], double** [[TMP50]], align 4 +// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** +// CHECK11-NEXT: store double* [[VLA]], double** [[TMP52]], align 4 +// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK11-NEXT: store i64 [[TMP12]], i64* [[TMP53]], align 4 +// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 +// CHECK11-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* +// CHECK11-NEXT: store i32 [[TMP9]], i32* [[TMP56]], align 4 +// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* +// CHECK11-NEXT: store i32 [[TMP9]], i32* [[TMP58]], align 4 +// CHECK11-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK11-NEXT: store i64 4, i64* [[TMP59]], align 4 +// CHECK11-NEXT: [[TMP60:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 +// CHECK11-NEXT: store i8* null, i8** [[TMP60]], align 4 +// CHECK11-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, i32 8, i8** [[TMP61]], i8** [[TMP62]], i64* [[TMP63]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 +// CHECK11-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) #[[ATTR4:[0-9]+]] +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(float* [[TMP5]], %struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: store i32 [[TMP34]], i32* [[T_VAR_CASTED1]], align 4 -// CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 -// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* -// CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP37]], align 4 -// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* -// CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP39]], align 4 -// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK11-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK11: omp_offload.failed5: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP35]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK11: omp_offload.cont6: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done7: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP46]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK11-NEXT: [[TMP66:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP66]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 -// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 +// CHECK11-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK11-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK11-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 +// CHECK11-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 +// CHECK11-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i32, x86_fp80*, float*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[N_ADDR]], i32 [[TMP0]], x86_fp80* [[TMP5]], float* [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK11-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* -// CHECK11-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done3: -// CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) -// CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) -// CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) -// CHECK11-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done8: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK11-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK11-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 +// CHECK11-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 +// CHECK11-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] +// CHECK11-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] +// CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 +// CHECK11-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i32 [[TMP8]], i1 false) +// CHECK11-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i32 0 +// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) +// CHECK11-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK11-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe +// CHECK11-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 4 +// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK11-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP5]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK11-NEXT: store i8* null, i8** [[TMP10]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK11-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK11-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] +// CHECK11-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] +// CHECK11-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 +// CHECK11-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK11-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr i32, i32* [[B2]], i32 1 +// CHECK11-NEXT: [[TMP14:%.*]] = bitcast i32* [[A3]] to i8* +// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP13]] to i8* +// CHECK11-NEXT: [[TMP16:%.*]] = ptrtoint i8* [[TMP15]] to i64 +// CHECK11-NEXT: [[TMP17:%.*]] = ptrtoint i8* [[TMP14]] to i64 +// CHECK11-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] +// CHECK11-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) +// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.St** +// CHECK11-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP21]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** +// CHECK11-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP23]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: store i64 0, i64* [[TMP24]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK11-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP27]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP29]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK11-NEXT: store i64 4, i64* [[TMP30]], align 4 +// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK11-NEXT: store i8* null, i8** [[TMP31]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to x86_fp80** +// CHECK11-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP33]], align 4 +// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to x86_fp80** +// CHECK11-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP35]], align 4 +// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK11-NEXT: store i64 0, i64* [[TMP36]], align 4 +// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK11-NEXT: store i8* null, i8** [[TMP37]], align 4 +// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP39]], align 4 +// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP41]], align 4 +// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK11-NEXT: store i64 4, i64* [[TMP42]], align 4 +// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK11-NEXT: store i8* null, i8** [[TMP43]], align 4 +// CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP45]], align 4 +// CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP47]], align 4 +// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK11-NEXT: store i64 4, i64* [[TMP48]], align 4 +// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK11-NEXT: store i8* null, i8** [[TMP49]], align 4 +// CHECK11-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** +// CHECK11-NEXT: store double* [[VLA]], double** [[TMP51]], align 4 +// CHECK11-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** +// CHECK11-NEXT: store double* [[VLA]], double** [[TMP53]], align 4 +// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK11-NEXT: store i64 [[TMP12]], i64* [[TMP54]], align 4 +// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 +// CHECK11-NEXT: store i8* null, i8** [[TMP55]], align 4 +// CHECK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to %struct.St** +// CHECK11-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP57]], align 4 +// CHECK11-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i32** +// CHECK11-NEXT: store i32* [[A3]], i32** [[TMP59]], align 4 +// CHECK11-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK11-NEXT: store i64 [[TMP19]], i64* [[TMP60]], align 4 +// CHECK11-NEXT: [[TMP61:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 +// CHECK11-NEXT: store i8* null, i8** [[TMP61]], align 4 +// CHECK11-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to %struct.St** +// CHECK11-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP63]], align 4 +// CHECK11-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32** +// CHECK11-NEXT: store i32* [[B2]], i32** [[TMP65]], align 4 +// CHECK11-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK11-NEXT: store i64 4, i64* [[TMP66]], align 4 +// CHECK11-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 +// CHECK11-NEXT: store i8* null, i8** [[TMP67]], align 4 +// CHECK11-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to %struct.St** +// CHECK11-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP69]], align 4 +// CHECK11-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32** +// CHECK11-NEXT: store i32* [[A3]], i32** [[TMP71]], align 4 +// CHECK11-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK11-NEXT: store i64 4, i64* [[TMP72]], align 4 +// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 +// CHECK11-NEXT: store i8* null, i8** [[TMP73]], align 4 +// CHECK11-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* +// CHECK11-NEXT: store i32 [[TMP9]], i32* [[TMP75]], align 4 +// CHECK11-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* +// CHECK11-NEXT: store i32 [[TMP9]], i32* [[TMP77]], align 4 +// CHECK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK11-NEXT: store i64 4, i64* [[TMP78]], align 4 +// CHECK11-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 +// CHECK11-NEXT: store i8* null, i8** [[TMP79]], align 4 +// CHECK11-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, i32 10, i8** [[TMP80]], i8** [[TMP81]], i64* [[TMP82]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK11-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0 +// CHECK11-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(%struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], %struct.St* [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 4 -// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] -// CHECK11: omp_offload.failed4: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT5]] -// CHECK11: omp_offload.cont5: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done6: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP35]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK11-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK11-NEXT: [[TMP85:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP85]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK11-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 +// CHECK11-SAME: (%struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: +// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK11-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 +// CHECK11-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 +// CHECK11-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, x86_fp80*, %struct.St*, i32, i32, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP0]], x86_fp80* [[TMP5]], %struct.St* [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]], i32* [[N_ADDR]], %struct.St* [[TMP6]]) // CHECK11-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK11-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK11-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK11-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 -// CHECK11-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 -// CHECK11-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK11-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK11: omp.arraycpy.body: -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK11: omp.arraycpy.done4: -// CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) -// CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) -// CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 -// CHECK11-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* -// CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done9: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK11-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK11-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 +// CHECK11-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 +// CHECK11-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 +// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() +// CHECK11-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] +// CHECK11-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 +// CHECK11-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] +// CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 +// CHECK11-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* +// CHECK11-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 [[TMP9]], i1 false) +// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 +// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK11-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP3]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i32 [[TMP13]] +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] +// CHECK11-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 +// CHECK11-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 +// CHECK11-NEXT: [[TMP15:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK11-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 +// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP15]], i32 [[TMP16]] +// CHECK11-NEXT: store x86_fp80 [[CONV9]], x86_fp80* [[ARRAYIDX11]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) // CHECK11-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe +// CHECK12-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 -// CHECK12-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* -// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP8]], align 4 -// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 -// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 4 -// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 -// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 4 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 4 -// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 +// CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK12-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] +// CHECK12-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load float*, float** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] +// CHECK12-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 +// CHECK12-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to float** +// CHECK12-NEXT: store float* [[TMP5]], float** [[TMP14]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** +// CHECK12-NEXT: store float* [[TMP5]], float** [[TMP16]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 0, i64* [[TMP17]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.St** +// CHECK12-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP20]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** +// CHECK12-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP22]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 0, i64* [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 // CHECK12-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 // CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 // CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK12-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK12-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP28]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 4, i64* [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to x86_fp80** +// CHECK12-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP32]], align 4 +// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to x86_fp80** +// CHECK12-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP34]], align 4 +// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK12-NEXT: store i64 0, i64* [[TMP35]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP38]], align 4 +// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP40]], align 4 +// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK12-NEXT: store i64 4, i64* [[TMP41]], align 4 +// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP42]], align 4 +// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP44]], align 4 +// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP46]], align 4 +// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK12-NEXT: store i64 4, i64* [[TMP47]], align 4 +// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 +// CHECK12-NEXT: store i8* null, i8** [[TMP48]], align 4 +// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to double** +// CHECK12-NEXT: store double* [[VLA]], double** [[TMP50]], align 4 +// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** +// CHECK12-NEXT: store double* [[VLA]], double** [[TMP52]], align 4 +// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK12-NEXT: store i64 [[TMP12]], i64* [[TMP53]], align 4 +// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 +// CHECK12-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* +// CHECK12-NEXT: store i32 [[TMP9]], i32* [[TMP56]], align 4 +// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* +// CHECK12-NEXT: store i32 [[TMP9]], i32* [[TMP58]], align 4 +// CHECK12-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK12-NEXT: store i64 4, i64* [[TMP59]], align 4 +// CHECK12-NEXT: [[TMP60:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 +// CHECK12-NEXT: store i8* null, i8** [[TMP60]], align 4 +// CHECK12-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, i32 8, i8** [[TMP61]], i8** [[TMP62]], i64* [[TMP63]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 +// CHECK12-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) #[[ATTR4:[0-9]+]] +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(float* [[TMP5]], %struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: store i32 [[TMP34]], i32* [[T_VAR_CASTED1]], align 4 -// CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 -// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* -// CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP37]], align 4 -// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* -// CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP39]], align 4 -// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4 -// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK12-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] -// CHECK12: omp_offload.failed5: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP35]]) #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] -// CHECK12: omp_offload.cont6: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done7: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP46]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK12-NEXT: [[TMP66:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP66]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 -// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 +// CHECK12-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK12-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK12-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 +// CHECK12-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 +// CHECK12-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i32, x86_fp80*, float*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[N_ADDR]], i32 [[TMP0]], x86_fp80* [[TMP5]], float* [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK12-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* -// CHECK12-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK12-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done3: -// CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) -// CHECK12-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) -// CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) -// CHECK12-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done8: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK12-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) +// CHECK12-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 +// CHECK12-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 +// CHECK12-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] +// CHECK12-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] +// CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 +// CHECK12-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i32 [[TMP8]], i1 false) +// CHECK12-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i32 0 +// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) +// CHECK12-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK12-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe +// CHECK12-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 4 +// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 // CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK12-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP5]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 4 -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK12-NEXT: store i8* null, i8** [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 4 -// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 4 -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 4 -// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK12-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 -// CHECK12-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] +// CHECK12-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] +// CHECK12-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 +// CHECK12-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK12-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr i32, i32* [[B2]], i32 1 +// CHECK12-NEXT: [[TMP14:%.*]] = bitcast i32* [[A3]] to i8* +// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP13]] to i8* +// CHECK12-NEXT: [[TMP16:%.*]] = ptrtoint i8* [[TMP15]] to i64 +// CHECK12-NEXT: [[TMP17:%.*]] = ptrtoint i8* [[TMP14]] to i64 +// CHECK12-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] +// CHECK12-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) +// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.St** +// CHECK12-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP21]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** +// CHECK12-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP23]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: store i64 0, i64* [[TMP24]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK12-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP27]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP29]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 +// CHECK12-NEXT: store i64 4, i64* [[TMP30]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK12-NEXT: store i8* null, i8** [[TMP31]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to x86_fp80** +// CHECK12-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP33]], align 4 +// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to x86_fp80** +// CHECK12-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP35]], align 4 +// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 +// CHECK12-NEXT: store i64 0, i64* [[TMP36]], align 4 +// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK12-NEXT: store i8* null, i8** [[TMP37]], align 4 +// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP39]], align 4 +// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP41]], align 4 +// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK12-NEXT: store i64 4, i64* [[TMP42]], align 4 +// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK12-NEXT: store i8* null, i8** [[TMP43]], align 4 +// CHECK12-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP45]], align 4 +// CHECK12-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK12-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP47]], align 4 +// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK12-NEXT: store i64 4, i64* [[TMP48]], align 4 +// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK12-NEXT: store i8* null, i8** [[TMP49]], align 4 +// CHECK12-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** +// CHECK12-NEXT: store double* [[VLA]], double** [[TMP51]], align 4 +// CHECK12-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 +// CHECK12-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** +// CHECK12-NEXT: store double* [[VLA]], double** [[TMP53]], align 4 +// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 +// CHECK12-NEXT: store i64 [[TMP12]], i64* [[TMP54]], align 4 +// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 +// CHECK12-NEXT: store i8* null, i8** [[TMP55]], align 4 +// CHECK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to %struct.St** +// CHECK12-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP57]], align 4 +// CHECK12-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 +// CHECK12-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i32** +// CHECK12-NEXT: store i32* [[A3]], i32** [[TMP59]], align 4 +// CHECK12-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 +// CHECK12-NEXT: store i64 [[TMP19]], i64* [[TMP60]], align 4 +// CHECK12-NEXT: [[TMP61:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 +// CHECK12-NEXT: store i8* null, i8** [[TMP61]], align 4 +// CHECK12-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to %struct.St** +// CHECK12-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP63]], align 4 +// CHECK12-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 +// CHECK12-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32** +// CHECK12-NEXT: store i32* [[B2]], i32** [[TMP65]], align 4 +// CHECK12-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK12-NEXT: store i64 4, i64* [[TMP66]], align 4 +// CHECK12-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 +// CHECK12-NEXT: store i8* null, i8** [[TMP67]], align 4 +// CHECK12-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 +// CHECK12-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to %struct.St** +// CHECK12-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP69]], align 4 +// CHECK12-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 +// CHECK12-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32** +// CHECK12-NEXT: store i32* [[A3]], i32** [[TMP71]], align 4 +// CHECK12-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 +// CHECK12-NEXT: store i64 4, i64* [[TMP72]], align 4 +// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 +// CHECK12-NEXT: store i8* null, i8** [[TMP73]], align 4 +// CHECK12-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 +// CHECK12-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* +// CHECK12-NEXT: store i32 [[TMP9]], i32* [[TMP75]], align 4 +// CHECK12-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 +// CHECK12-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* +// CHECK12-NEXT: store i32 [[TMP9]], i32* [[TMP77]], align 4 +// CHECK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 +// CHECK12-NEXT: store i64 4, i64* [[TMP78]], align 4 +// CHECK12-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 +// CHECK12-NEXT: store i8* null, i8** [[TMP79]], align 4 +// CHECK12-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, i32 10, i8** [[TMP80]], i8** [[TMP81]], i64* [[TMP82]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK12-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0 +// CHECK12-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(%struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], %struct.St* [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 4 -// CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 4 -// CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// CHECK12-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] -// CHECK12: omp_offload.failed4: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT5]] -// CHECK12: omp_offload.cont5: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done6: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP35]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK12-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK12-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK12-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK12-NEXT: [[TMP85:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP85]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK12-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 +// CHECK12-SAME: (%struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: +// CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK12-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 +// CHECK12-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 +// CHECK12-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 // CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK12-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 -// CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK12-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK12-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK12-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 -// CHECK12-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 -// CHECK12-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* -// CHECK12-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* -// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK12: omp.arraycpy.body: -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) -// CHECK12-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) -// CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] -// CHECK12: omp.arraycpy.done4: -// CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) -// CHECK12-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) -// CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 -// CHECK12-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done9: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK12-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, x86_fp80*, %struct.St*, i32, i32, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP0]], x86_fp80* [[TMP5]], %struct.St* [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]], i32* [[N_ADDR]], %struct.St* [[TMP6]]) // CHECK12-NEXT: ret void // // -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK12-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK12-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 +// CHECK12-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 +// CHECK12-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() +// CHECK12-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] +// CHECK12-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] +// CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 +// CHECK12-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* +// CHECK12-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 [[TMP9]], i1 false) +// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 +// CHECK12-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK12-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP3]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i32 [[TMP13]] +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 +// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] +// CHECK12-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 +// CHECK12-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 +// CHECK12-NEXT: [[TMP15:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 +// CHECK12-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 +// CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP15]], i32 [[TMP16]] +// CHECK12-NEXT: store x86_fp80 [[CONV9]], x86_fp80* [[ARRAYIDX11]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK12-SAME: () #[[ATTR5:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done2: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done2: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK13-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK13-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done2: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done2: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK14-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK14-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK14-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK15-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done2: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP5]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done2: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP5]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK15-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK15-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK15-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK16-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done2: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP5]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done2: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP5]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK16-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK16-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK16-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg -// CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 -// CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** -// CHECK17-NEXT: store float* [[TMP8]], float** [[TMP16]], align 8 -// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to float** -// CHECK17-NEXT: store float* [[TMP8]], float** [[TMP18]], align 8 -// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 0, i64* [[TMP19]], align 8 -// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** -// CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP22]], align 8 -// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** -// CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP24]], align 8 -// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 0, i64* [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP28]], align 8 -// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP30]], align 8 -// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 8, i64* [[TMP31]], align 8 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP32]], align 8 -// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to ppc_fp128** -// CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP34]], align 8 -// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to ppc_fp128** -// CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP36]], align 8 -// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK17-NEXT: store i64 0, i64* [[TMP37]], align 8 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP38]], align 8 -// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP40]], align 8 -// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP42]], align 8 -// CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK17-NEXT: store i64 8, i64* [[TMP43]], align 8 -// CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP44]], align 8 -// CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP46]], align 8 -// CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP48]], align 8 -// CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK17-NEXT: store i64 8, i64* [[TMP49]], align 8 -// CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 -// CHECK17-NEXT: store i8* null, i8** [[TMP50]], align 8 -// CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** -// CHECK17-NEXT: store double* [[VLA]], double** [[TMP52]], align 8 -// CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** -// CHECK17-NEXT: store double* [[VLA]], double** [[TMP54]], align 8 -// CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP55]], align 8 -// CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 -// CHECK17-NEXT: store i8* null, i8** [[TMP56]], align 8 -// CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64* -// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP58]], align 8 -// CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i64* -// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP60]], align 8 -// CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK17-NEXT: store i64 4, i64* [[TMP61]], align 8 -// CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 -// CHECK17-NEXT: store i8* null, i8** [[TMP62]], align 8 -// CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP64:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, i32 8, i8** [[TMP63]], i8** [[TMP64]], i64* [[TMP65]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 -// CHECK17-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(float* [[TMP8]], %struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP68:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP68]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 -// CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, ppc_fp128*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[CONV]], i64 [[TMP0]], ppc_fp128* [[TMP5]], float* [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 -// CHECK17-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) -// CHECK17-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 -// CHECK17-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK17-NEXT: [[TMP14:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 signext [[TMP13]], ppc_fp128* [[TMP14]]) -// CHECK17-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg -// CHECK17-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 8 -// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 -// CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 -// CHECK17-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr i32, i32* [[B2]], i32 1 -// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i32* [[A3]] to i8* -// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP15]] to i8* -// CHECK17-NEXT: [[TMP18:%.*]] = ptrtoint i8* [[TMP17]] to i64 -// CHECK17-NEXT: [[TMP19:%.*]] = ptrtoint i8* [[TMP16]] to i64 -// CHECK17-NEXT: [[TMP20:%.*]] = sub i64 [[TMP18]], [[TMP19]] -// CHECK17-NEXT: [[TMP21:%.*]] = sdiv exact i64 [[TMP20]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) -// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** -// CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP23]], align 8 -// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.St** -// CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP25]], align 8 -// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: store i64 0, i64* [[TMP26]], align 8 -// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP29]], align 8 -// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP31]], align 8 -// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8 -// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to ppc_fp128** -// CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP35]], align 8 -// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to ppc_fp128** -// CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP37]], align 8 -// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK17-NEXT: store i64 0, i64* [[TMP38]], align 8 -// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP41]], align 8 -// CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK17-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP43]], align 8 -// CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK17-NEXT: store i64 8, i64* [[TMP44]], align 8 -// CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK17-NEXT: store i8* null, i8** [[TMP45]], align 8 -// CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP47]], align 8 -// CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64* -// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP49]], align 8 -// CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK17-NEXT: store i64 8, i64* [[TMP50]], align 8 -// CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK17-NEXT: store i8* null, i8** [[TMP51]], align 8 -// CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** -// CHECK17-NEXT: store double* [[VLA]], double** [[TMP53]], align 8 -// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 -// CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double** -// CHECK17-NEXT: store double* [[VLA]], double** [[TMP55]], align 8 -// CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP56]], align 8 -// CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 -// CHECK17-NEXT: store i8* null, i8** [[TMP57]], align 8 -// CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to %struct.St** -// CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP59]], align 8 -// CHECK17-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 -// CHECK17-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32** -// CHECK17-NEXT: store i32* [[A3]], i32** [[TMP61]], align 8 -// CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK17-NEXT: store i64 [[TMP21]], i64* [[TMP62]], align 8 -// CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 -// CHECK17-NEXT: store i8* null, i8** [[TMP63]], align 8 -// CHECK17-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to %struct.St** -// CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP65]], align 8 -// CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 -// CHECK17-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32** -// CHECK17-NEXT: store i32* [[B2]], i32** [[TMP67]], align 8 -// CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK17-NEXT: store i64 4, i64* [[TMP68]], align 8 -// CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 -// CHECK17-NEXT: store i8* null, i8** [[TMP69]], align 8 -// CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 -// CHECK17-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to %struct.St** -// CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP71]], align 8 -// CHECK17-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 -// CHECK17-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32** -// CHECK17-NEXT: store i32* [[A3]], i32** [[TMP73]], align 8 -// CHECK17-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK17-NEXT: store i64 4, i64* [[TMP74]], align 8 -// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 -// CHECK17-NEXT: store i8* null, i8** [[TMP75]], align 8 -// CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 -// CHECK17-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* -// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP77]], align 8 -// CHECK17-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 -// CHECK17-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* -// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP79]], align 8 -// CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK17-NEXT: store i64 4, i64* [[TMP80]], align 8 -// CHECK17-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 -// CHECK17-NEXT: store i8* null, i8** [[TMP81]], align 8 -// CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, i32 10, i8** [[TMP82]], i8** [[TMP83]], i64* [[TMP84]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK17-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 -// CHECK17-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(%struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], %struct.St* [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] -// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[TMP87:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP87]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 -// CHECK17-SAME: (%struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK17-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, ppc_fp128*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP0]], ppc_fp128* [[TMP5]], %struct.St* [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]], i32* [[CONV]], %struct.St* [[TMP6]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 -// CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* -// CHECK17-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* -// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 [[TMP9]], i1 false) -// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 -// CHECK17-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 -// CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK17-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP3]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i64 [[TMP13]] -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 -// CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] -// CHECK17-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 -// CHECK17-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 -// CHECK17-NEXT: [[TMP15:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK17-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 -// CHECK17-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP15]], i64 [[IDXPROM11]] -// CHECK17-NEXT: store ppc_fp128 [[CONV9]], ppc_fp128* [[ARRAYIDX12]], align 16 -// CHECK17-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg -// CHECK18-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 -// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK18-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK18-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** -// CHECK18-NEXT: store float* [[TMP8]], float** [[TMP16]], align 8 -// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to float** -// CHECK18-NEXT: store float* [[TMP8]], float** [[TMP18]], align 8 -// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 0, i64* [[TMP19]], align 8 -// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 -// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** -// CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP22]], align 8 -// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** -// CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP24]], align 8 -// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 0, i64* [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP28]], align 8 -// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP30]], align 8 -// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 8, i64* [[TMP31]], align 8 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP32]], align 8 -// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to ppc_fp128** -// CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP34]], align 8 -// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to ppc_fp128** -// CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP36]], align 8 -// CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK18-NEXT: store i64 0, i64* [[TMP37]], align 8 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP38]], align 8 -// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP40]], align 8 -// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP42]], align 8 -// CHECK18-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK18-NEXT: store i64 8, i64* [[TMP43]], align 8 -// CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP44]], align 8 -// CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP46]], align 8 -// CHECK18-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP48]], align 8 -// CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK18-NEXT: store i64 8, i64* [[TMP49]], align 8 -// CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 -// CHECK18-NEXT: store i8* null, i8** [[TMP50]], align 8 -// CHECK18-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** -// CHECK18-NEXT: store double* [[VLA]], double** [[TMP52]], align 8 -// CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** -// CHECK18-NEXT: store double* [[VLA]], double** [[TMP54]], align 8 -// CHECK18-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP55]], align 8 -// CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 -// CHECK18-NEXT: store i8* null, i8** [[TMP56]], align 8 -// CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64* -// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP58]], align 8 -// CHECK18-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i64* -// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP60]], align 8 -// CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK18-NEXT: store i64 4, i64* [[TMP61]], align 8 -// CHECK18-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 -// CHECK18-NEXT: store i8* null, i8** [[TMP62]], align 8 -// CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP64:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, i32 8, i8** [[TMP63]], i8** [[TMP64]], i64* [[TMP65]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 -// CHECK18-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(float* [[TMP8]], %struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP68:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP68]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 -// CHECK18-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 -// CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 -// CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, ppc_fp128*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[CONV]], i64 [[TMP0]], ppc_fp128* [[TMP5]], float* [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 -// CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 -// CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK18-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 -// CHECK18-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) -// CHECK18-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 -// CHECK18-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK18-NEXT: [[TMP14:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 signext [[TMP13]], ppc_fp128* [[TMP14]]) -// CHECK18-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg -// CHECK18-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 8 -// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 -// CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK18-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 -// CHECK18-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 -// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 -// CHECK18-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK18-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 -// CHECK18-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr i32, i32* [[B2]], i32 1 -// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i32* [[A3]] to i8* -// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP15]] to i8* -// CHECK18-NEXT: [[TMP18:%.*]] = ptrtoint i8* [[TMP17]] to i64 -// CHECK18-NEXT: [[TMP19:%.*]] = ptrtoint i8* [[TMP16]] to i64 -// CHECK18-NEXT: [[TMP20:%.*]] = sub i64 [[TMP18]], [[TMP19]] -// CHECK18-NEXT: [[TMP21:%.*]] = sdiv exact i64 [[TMP20]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) -// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** -// CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP23]], align 8 -// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.St** -// CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP25]], align 8 -// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: store i64 0, i64* [[TMP26]], align 8 -// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP29]], align 8 -// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* -// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP31]], align 8 -// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8 -// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 -// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to ppc_fp128** -// CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP35]], align 8 -// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to ppc_fp128** -// CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP37]], align 8 -// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK18-NEXT: store i64 0, i64* [[TMP38]], align 8 -// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 -// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP41]], align 8 -// CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK18-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP43]], align 8 -// CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK18-NEXT: store i64 8, i64* [[TMP44]], align 8 -// CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK18-NEXT: store i8* null, i8** [[TMP45]], align 8 -// CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP47]], align 8 -// CHECK18-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK18-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64* -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP49]], align 8 -// CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK18-NEXT: store i64 8, i64* [[TMP50]], align 8 -// CHECK18-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK18-NEXT: store i8* null, i8** [[TMP51]], align 8 -// CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** -// CHECK18-NEXT: store double* [[VLA]], double** [[TMP53]], align 8 -// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 -// CHECK18-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double** -// CHECK18-NEXT: store double* [[VLA]], double** [[TMP55]], align 8 -// CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP56]], align 8 -// CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 -// CHECK18-NEXT: store i8* null, i8** [[TMP57]], align 8 -// CHECK18-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to %struct.St** -// CHECK18-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP59]], align 8 -// CHECK18-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 -// CHECK18-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32** -// CHECK18-NEXT: store i32* [[A3]], i32** [[TMP61]], align 8 -// CHECK18-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK18-NEXT: store i64 [[TMP21]], i64* [[TMP62]], align 8 -// CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 -// CHECK18-NEXT: store i8* null, i8** [[TMP63]], align 8 -// CHECK18-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to %struct.St** -// CHECK18-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP65]], align 8 -// CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 -// CHECK18-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32** -// CHECK18-NEXT: store i32* [[B2]], i32** [[TMP67]], align 8 -// CHECK18-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK18-NEXT: store i64 4, i64* [[TMP68]], align 8 -// CHECK18-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 -// CHECK18-NEXT: store i8* null, i8** [[TMP69]], align 8 -// CHECK18-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 -// CHECK18-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to %struct.St** -// CHECK18-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP71]], align 8 -// CHECK18-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 -// CHECK18-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32** -// CHECK18-NEXT: store i32* [[A3]], i32** [[TMP73]], align 8 -// CHECK18-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK18-NEXT: store i64 4, i64* [[TMP74]], align 8 -// CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 -// CHECK18-NEXT: store i8* null, i8** [[TMP75]], align 8 -// CHECK18-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 -// CHECK18-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* -// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP77]], align 8 -// CHECK18-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 -// CHECK18-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* -// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP79]], align 8 -// CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK18-NEXT: store i64 4, i64* [[TMP80]], align 8 -// CHECK18-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 -// CHECK18-NEXT: store i8* null, i8** [[TMP81]], align 8 -// CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, i32 10, i8** [[TMP82]], i8** [[TMP83]], i64* [[TMP84]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK18-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 -// CHECK18-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK18: omp_offload.failed: -// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(%struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], %struct.St* [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] -// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[TMP87:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP87]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 -// CHECK18-SAME: (%struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 -// CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 -// CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* -// CHECK18-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, ppc_fp128*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP0]], ppc_fp128* [[TMP5]], %struct.St* [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]], i32* [[CONV]], %struct.St* [[TMP6]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 -// CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 -// CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 -// CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 -// CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 -// CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK18-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] -// CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 [[TMP9]], i1 false) -// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 -// CHECK18-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK18-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP3]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i64 [[TMP13]] -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 -// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] -// CHECK18-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 -// CHECK18-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 -// CHECK18-NEXT: [[TMP15:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 -// CHECK18-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP15]], i64 [[IDXPROM11]] -// CHECK18-NEXT: store ppc_fp128 [[CONV9]], ppc_fp128* [[ARRAYIDX12]], align 16 -// CHECK18-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK18-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe -// CHECK19-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 -// CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 -// CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to float** -// CHECK19-NEXT: store float* [[TMP5]], float** [[TMP14]], align 4 -// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** -// CHECK19-NEXT: store float* [[TMP5]], float** [[TMP16]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 0, i64* [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.St** -// CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP20]], align 4 -// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** -// CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP22]], align 4 -// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 0, i64* [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 -// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP28]], align 4 -// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 4, i64* [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to x86_fp80** -// CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP32]], align 4 -// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to x86_fp80** -// CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP34]], align 4 -// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK19-NEXT: store i64 0, i64* [[TMP35]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 -// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP38]], align 4 -// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP40]], align 4 -// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK19-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP44]], align 4 -// CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP46]], align 4 -// CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK19-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 -// CHECK19-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to double** -// CHECK19-NEXT: store double* [[VLA]], double** [[TMP50]], align 4 -// CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** -// CHECK19-NEXT: store double* [[VLA]], double** [[TMP52]], align 4 -// CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK19-NEXT: store i64 [[TMP12]], i64* [[TMP53]], align 4 -// CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 -// CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* -// CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP56]], align 4 -// CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* -// CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP58]], align 4 -// CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK19-NEXT: store i64 4, i64* [[TMP59]], align 4 -// CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 -// CHECK19-NEXT: store i8* null, i8** [[TMP60]], align 4 -// CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, i32 8, i8** [[TMP61]], i8** [[TMP62]], i64* [[TMP63]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 -// CHECK19-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(float* [[TMP5]], %struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP66:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP66]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 -// CHECK19-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 -// CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 -// CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i32, x86_fp80*, float*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[N_ADDR]], i32 [[TMP0]], x86_fp80* [[TMP5]], float* [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 -// CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 -// CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] -// CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] -// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 -// CHECK19-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i32 [[TMP8]], i1 false) -// CHECK19-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i32 0 -// CHECK19-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK19-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) -// CHECK19-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe -// CHECK19-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 4 -// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 -// CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK19-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr i32, i32* [[B2]], i32 1 -// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i32* [[A3]] to i8* -// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP13]] to i8* -// CHECK19-NEXT: [[TMP16:%.*]] = ptrtoint i8* [[TMP15]] to i64 -// CHECK19-NEXT: [[TMP17:%.*]] = ptrtoint i8* [[TMP14]] to i64 -// CHECK19-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] -// CHECK19-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) -// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.St** -// CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP21]], align 4 -// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** -// CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP23]], align 4 -// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: store i64 0, i64* [[TMP24]], align 4 -// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 -// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP27]], align 4 -// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP29]], align 4 -// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK19-NEXT: store i64 4, i64* [[TMP30]], align 4 -// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK19-NEXT: store i8* null, i8** [[TMP31]], align 4 -// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to x86_fp80** -// CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP33]], align 4 -// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to x86_fp80** -// CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP35]], align 4 -// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK19-NEXT: store i64 0, i64* [[TMP36]], align 4 -// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK19-NEXT: store i8* null, i8** [[TMP37]], align 4 -// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP39]], align 4 -// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK19-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP41]], align 4 -// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK19-NEXT: store i64 4, i64* [[TMP42]], align 4 -// CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK19-NEXT: store i8* null, i8** [[TMP43]], align 4 -// CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP45]], align 4 -// CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK19-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP47]], align 4 -// CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK19-NEXT: store i64 4, i64* [[TMP48]], align 4 -// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK19-NEXT: store i8* null, i8** [[TMP49]], align 4 -// CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** -// CHECK19-NEXT: store double* [[VLA]], double** [[TMP51]], align 4 -// CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 -// CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** -// CHECK19-NEXT: store double* [[VLA]], double** [[TMP53]], align 4 -// CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK19-NEXT: store i64 [[TMP12]], i64* [[TMP54]], align 4 -// CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 -// CHECK19-NEXT: store i8* null, i8** [[TMP55]], align 4 -// CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to %struct.St** -// CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP57]], align 4 -// CHECK19-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 -// CHECK19-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i32** -// CHECK19-NEXT: store i32* [[A3]], i32** [[TMP59]], align 4 -// CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK19-NEXT: store i64 [[TMP19]], i64* [[TMP60]], align 4 -// CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 -// CHECK19-NEXT: store i8* null, i8** [[TMP61]], align 4 -// CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to %struct.St** -// CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP63]], align 4 -// CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 -// CHECK19-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32** -// CHECK19-NEXT: store i32* [[B2]], i32** [[TMP65]], align 4 -// CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK19-NEXT: store i64 4, i64* [[TMP66]], align 4 -// CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 -// CHECK19-NEXT: store i8* null, i8** [[TMP67]], align 4 -// CHECK19-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 -// CHECK19-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to %struct.St** -// CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP69]], align 4 -// CHECK19-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 -// CHECK19-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32** -// CHECK19-NEXT: store i32* [[A3]], i32** [[TMP71]], align 4 -// CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK19-NEXT: store i64 4, i64* [[TMP72]], align 4 -// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 -// CHECK19-NEXT: store i8* null, i8** [[TMP73]], align 4 -// CHECK19-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 -// CHECK19-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* -// CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP75]], align 4 -// CHECK19-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 -// CHECK19-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* -// CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP77]], align 4 -// CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK19-NEXT: store i64 4, i64* [[TMP78]], align 4 -// CHECK19-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 -// CHECK19-NEXT: store i8* null, i8** [[TMP79]], align 4 -// CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, i32 10, i8** [[TMP80]], i8** [[TMP81]], i64* [[TMP82]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK19-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0 -// CHECK19-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(%struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], %struct.St* [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] -// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[TMP85:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP85]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 -// CHECK19-SAME: (%struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 -// CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 -// CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, x86_fp80*, %struct.St*, i32, i32, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP0]], x86_fp80* [[TMP5]], %struct.St* [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]], i32* [[N_ADDR]], %struct.St* [[TMP6]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 -// CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 -// CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 -// CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK19-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] -// CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] -// CHECK19-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 [[TMP9]], i1 false) -// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 -// CHECK19-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK19-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP3]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i32 [[TMP13]] -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 -// CHECK19-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] -// CHECK19-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 -// CHECK19-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 -// CHECK19-NEXT: [[TMP15:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK19-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 -// CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP15]], i32 [[TMP16]] -// CHECK19-NEXT: store x86_fp80 [[CONV9]], x86_fp80* [[ARRAYIDX11]], align 4 -// CHECK19-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe -// CHECK20-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 -// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK20-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK20-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 -// CHECK20-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to float** -// CHECK20-NEXT: store float* [[TMP5]], float** [[TMP14]], align 4 -// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** -// CHECK20-NEXT: store float* [[TMP5]], float** [[TMP16]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 0, i64* [[TMP17]], align 4 -// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.St** -// CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP20]], align 4 -// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** -// CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP22]], align 4 -// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 0, i64* [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 -// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP28]], align 4 -// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 4, i64* [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to x86_fp80** -// CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP32]], align 4 -// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to x86_fp80** -// CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP34]], align 4 -// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK20-NEXT: store i64 0, i64* [[TMP35]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 -// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP38]], align 4 -// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP40]], align 4 -// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK20-NEXT: store i64 4, i64* [[TMP41]], align 4 -// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP42]], align 4 -// CHECK20-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP44]], align 4 -// CHECK20-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP46]], align 4 -// CHECK20-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK20-NEXT: store i64 4, i64* [[TMP47]], align 4 -// CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 -// CHECK20-NEXT: store i8* null, i8** [[TMP48]], align 4 -// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to double** -// CHECK20-NEXT: store double* [[VLA]], double** [[TMP50]], align 4 -// CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** -// CHECK20-NEXT: store double* [[VLA]], double** [[TMP52]], align 4 -// CHECK20-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK20-NEXT: store i64 [[TMP12]], i64* [[TMP53]], align 4 -// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 -// CHECK20-NEXT: store i8* null, i8** [[TMP54]], align 4 -// CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* -// CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP56]], align 4 -// CHECK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* -// CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP58]], align 4 -// CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK20-NEXT: store i64 4, i64* [[TMP59]], align 4 -// CHECK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 -// CHECK20-NEXT: store i8* null, i8** [[TMP60]], align 4 -// CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, i32 8, i8** [[TMP61]], i8** [[TMP62]], i64* [[TMP63]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 -// CHECK20-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(float* [[TMP5]], %struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP66:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP66]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 -// CHECK20-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 -// CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 -// CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i32, x86_fp80*, float*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[N_ADDR]], i32 [[TMP0]], x86_fp80* [[TMP5]], float* [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 -// CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 -// CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] -// CHECK20-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] -// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 -// CHECK20-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i32 [[TMP8]], i1 false) -// CHECK20-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i32 0 -// CHECK20-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK20-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) -// CHECK20-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe -// CHECK20-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 4 -// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK20-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 -// CHECK20-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK20-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 -// CHECK20-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK20-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr i32, i32* [[B2]], i32 1 -// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i32* [[A3]] to i8* -// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP13]] to i8* -// CHECK20-NEXT: [[TMP16:%.*]] = ptrtoint i8* [[TMP15]] to i64 -// CHECK20-NEXT: [[TMP17:%.*]] = ptrtoint i8* [[TMP14]] to i64 -// CHECK20-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] -// CHECK20-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) -// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.St** -// CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP21]], align 4 -// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** -// CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP23]], align 4 -// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: store i64 0, i64* [[TMP24]], align 4 -// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 -// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP27]], align 4 -// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP29]], align 4 -// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 -// CHECK20-NEXT: store i64 4, i64* [[TMP30]], align 4 -// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK20-NEXT: store i8* null, i8** [[TMP31]], align 4 -// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to x86_fp80** -// CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP33]], align 4 -// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to x86_fp80** -// CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP35]], align 4 -// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 -// CHECK20-NEXT: store i64 0, i64* [[TMP36]], align 4 -// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK20-NEXT: store i8* null, i8** [[TMP37]], align 4 -// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP39]], align 4 -// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK20-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP41]], align 4 -// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK20-NEXT: store i64 4, i64* [[TMP42]], align 4 -// CHECK20-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK20-NEXT: store i8* null, i8** [[TMP43]], align 4 -// CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP45]], align 4 -// CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK20-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP47]], align 4 -// CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK20-NEXT: store i64 4, i64* [[TMP48]], align 4 -// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK20-NEXT: store i8* null, i8** [[TMP49]], align 4 -// CHECK20-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** -// CHECK20-NEXT: store double* [[VLA]], double** [[TMP51]], align 4 -// CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 -// CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** -// CHECK20-NEXT: store double* [[VLA]], double** [[TMP53]], align 4 -// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 -// CHECK20-NEXT: store i64 [[TMP12]], i64* [[TMP54]], align 4 -// CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 -// CHECK20-NEXT: store i8* null, i8** [[TMP55]], align 4 -// CHECK20-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to %struct.St** -// CHECK20-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP57]], align 4 -// CHECK20-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 -// CHECK20-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i32** -// CHECK20-NEXT: store i32* [[A3]], i32** [[TMP59]], align 4 -// CHECK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 -// CHECK20-NEXT: store i64 [[TMP19]], i64* [[TMP60]], align 4 -// CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 -// CHECK20-NEXT: store i8* null, i8** [[TMP61]], align 4 -// CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to %struct.St** -// CHECK20-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP63]], align 4 -// CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 -// CHECK20-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32** -// CHECK20-NEXT: store i32* [[B2]], i32** [[TMP65]], align 4 -// CHECK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK20-NEXT: store i64 4, i64* [[TMP66]], align 4 -// CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 -// CHECK20-NEXT: store i8* null, i8** [[TMP67]], align 4 -// CHECK20-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 -// CHECK20-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to %struct.St** -// CHECK20-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP69]], align 4 -// CHECK20-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 -// CHECK20-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32** -// CHECK20-NEXT: store i32* [[A3]], i32** [[TMP71]], align 4 -// CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 -// CHECK20-NEXT: store i64 4, i64* [[TMP72]], align 4 -// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 -// CHECK20-NEXT: store i8* null, i8** [[TMP73]], align 4 -// CHECK20-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 -// CHECK20-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* -// CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP75]], align 4 -// CHECK20-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 -// CHECK20-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* -// CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP77]], align 4 -// CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 -// CHECK20-NEXT: store i64 4, i64* [[TMP78]], align 4 -// CHECK20-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 -// CHECK20-NEXT: store i8* null, i8** [[TMP79]], align 4 -// CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, i32 10, i8** [[TMP80]], i8** [[TMP81]], i64* [[TMP82]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK20-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0 -// CHECK20-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK20: omp_offload.failed: -// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(%struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], %struct.St* [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] -// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[TMP85:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP85]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 -// CHECK20-SAME: (%struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 -// CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 -// CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, x86_fp80*, %struct.St*, i32, i32, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP0]], x86_fp80* [[TMP5]], %struct.St* [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]], i32* [[N_ADDR]], %struct.St* [[TMP6]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 -// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 -// CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 -// CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 -// CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 -// CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK20-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] -// CHECK20-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 -// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] -// CHECK20-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 [[TMP9]], i1 false) -// CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 -// CHECK20-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double -// CHECK20-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP3]] -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i32 [[TMP13]] -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 -// CHECK20-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] -// CHECK20-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 -// CHECK20-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 -// CHECK20-NEXT: [[TMP15:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK20-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 -// CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP15]], i32 [[TMP16]] -// CHECK20-NEXT: store x86_fp80 [[CONV9]], x86_fp80* [[ARRAYIDX11]], align 4 -// CHECK20-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK20-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg -// CHECK21-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK21-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK21-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK21-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP8]], i64 0 -// CHECK21-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP11:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK21-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP9]], i32 signext [[TMP10]], ppc_fp128* [[TMP11]]) -// CHECK21-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg -// CHECK21-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK21-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK21-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 -// CHECK21-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[B2]], align 4 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store i32 [[TMP9]], i32* [[A3]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double -// CHECK21-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i64 [[TMP10]] -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], 1 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 -// CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] -// CHECK21-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 -// CHECK21-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to ppc_fp128 -// CHECK21-NEXT: [[TMP12:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK21-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[B6]], align 4 -// CHECK21-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK21-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP12]], i64 [[IDXPROM7]] -// CHECK21-NEXT: store ppc_fp128 [[CONV5]], ppc_fp128* [[ARRAYIDX8]], align 16 -// CHECK21-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK21-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg -// CHECK22-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK22-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK22-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK22-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP8]], i64 0 -// CHECK22-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP11:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP9]], i32 signext [[TMP10]], ppc_fp128* [[TMP11]]) -// CHECK22-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg -// CHECK22-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK22-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK22-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK22-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 -// CHECK22-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[B2]], align 4 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store i32 [[TMP9]], i32* [[A3]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double -// CHECK22-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i64 [[TMP10]] -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], 1 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 -// CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] -// CHECK22-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 -// CHECK22-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to ppc_fp128 -// CHECK22-NEXT: [[TMP12:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK22-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[B6]], align 4 -// CHECK22-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK22-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP12]], i64 [[IDXPROM7]] -// CHECK22-NEXT: store ppc_fp128 [[CONV5]], ppc_fp128* [[ARRAYIDX8]], align 16 -// CHECK22-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK22-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe -// CHECK23-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK23-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP5]], i32 0 -// CHECK23-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK23-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP6]], i32 [[TMP7]], x86_fp80* [[TMP8]]) -// CHECK23-NEXT: [[TMP9:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP9]]) -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe -// CHECK23-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK23-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 -// CHECK23-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[B2]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store i32 [[TMP6]], i32* [[A3]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i32 [[TMP7]] -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 1 -// CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] -// CHECK23-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 -// CHECK23-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to x86_fp80 -// CHECK23-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK23-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[B6]], align 4 -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP9]], i32 [[TMP10]] -// CHECK23-NEXT: store x86_fp80 [[CONV5]], x86_fp80* [[ARRAYIDX7]], align 4 -// CHECK23-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK23-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe -// CHECK24-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK24-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP5]], i32 0 -// CHECK24-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK24-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP6]], i32 [[TMP7]], x86_fp80* [[TMP8]]) -// CHECK24-NEXT: [[TMP9:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP9]]) -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe -// CHECK24-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK24-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 -// CHECK24-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[B2]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store i32 [[TMP6]], i32* [[A3]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i32 [[TMP7]] -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 1 -// CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] -// CHECK24-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 -// CHECK24-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to x86_fp80 -// CHECK24-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK24-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[B6]], align 4 -// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP9]], i32 [[TMP10]] -// CHECK24-NEXT: store x86_fp80 [[CONV5]], x86_fp80* [[ARRAYIDX7]], align 4 -// CHECK24-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK24-NEXT: ret void -// diff --git a/clang/test/OpenMP/teams_private_codegen.cpp b/clang/test/OpenMP/teams_private_codegen.cpp --- a/clang/test/OpenMP/teams_private_codegen.cpp +++ b/clang/test/OpenMP/teams_private_codegen.cpp @@ -6,26 +6,26 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -836,11 +836,45 @@ // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK5-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done1: +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP4]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi @@ -856,17 +890,143 @@ // CHECK5-NEXT: ret void // // +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 +// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* +// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 4, i1 false) +// CHECK5-NEXT: store i32 3, i32* [[SIVAR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done3: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) +// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 128 +// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) +// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK5-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done1: +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK5-NEXT: ret i32 [[TMP4]] +// +// // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi // CHECK5-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 // CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 @@ -879,45 +1039,293 @@ // CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 // CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK5-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK5-NEXT: store i32* [[B3]], i32** [[TMP4]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK5-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK5-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(32) [[REF_TMP]]) +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** +// CHECK5-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** +// CHECK5-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP5]], align 8 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK5-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[C:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[TMP]], align 8 +// CHECK5-NEXT: store i32* [[C]], i32** [[_TMP1]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 +// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 +// CHECK5-NEXT: store i32 [[DEC]], i32* [[B]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 +// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev +// CHECK5-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 +// CHECK5-SAME: () #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK5: arrayctor.loop: +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK5: arrayctor.cont: +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 +// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* +// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i64 4, i1 false) +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK5: arraydestroy.body: +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK5: arraydestroy.done3: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev +// CHECK5-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** +// CHECK5-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** +// CHECK5-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK5-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK5-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK5-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK5: omp_offload.failed: +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK5: omp_offload.cont: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 +// CHECK5-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32* [[A]], i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK5-SAME: (%class.anon.0* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK5-SAME: () #[[ATTR6:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK5-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 +// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) // CHECK5-NEXT: ret void // // @@ -926,11 +1334,45 @@ // CHECK6-NEXT: entry: // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK6-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done1: +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP4]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi @@ -946,17 +1388,143 @@ // CHECK6-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 +// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* +// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 4, i1 false) +// CHECK6-NEXT: store i32 3, i32* [[SIVAR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done3: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK6-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) +// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 128 +// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) +// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) +// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK6-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done1: +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP4]] +// +// // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi // CHECK6-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 // CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 @@ -969,45 +1537,293 @@ // CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 // CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK6-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK6-NEXT: store i32* [[B3]], i32** [[TMP4]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK6-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK6-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(32) [[REF_TMP]]) +// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** +// CHECK6-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** +// CHECK6-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP5]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK6-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 +// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[C:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[TMP]], align 8 +// CHECK6-NEXT: store i32* [[C]], i32** [[_TMP1]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 +// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 +// CHECK6-NEXT: store i32 [[DEC]], i32* [[B]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 +// CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev +// CHECK6-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 +// CHECK6-SAME: () #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 +// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* +// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i64 4, i1 false) +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done3: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev +// CHECK6-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** +// CHECK6-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** +// CHECK6-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK6-NEXT: store i8* null, i8** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK6-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK6-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK6: omp_offload.failed: +// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK6: omp_offload.cont: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 +// CHECK6-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 +// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[A]], i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK6-SAME: (%class.anon.0* nonnull dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK6-SAME: () #[[ATTR6:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK6-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 +// CHECK6-NEXT: call void @__tgt_register_requires(i64 1) // CHECK6-NEXT: ret void // // @@ -1016,11 +1832,45 @@ // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK7-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done1: +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP4]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi @@ -1036,17 +1886,143 @@ // CHECK7-NEXT: ret void // // +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 +// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* +// CHECK7-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 4, i1 false) +// CHECK7-NEXT: store i32 3, i32* [[SIVAR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done3: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK7-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) +// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 128 +// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) +// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK7-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done1: +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK7-NEXT: ret i32 [[TMP4]] +// +// // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi // CHECK7-SAME: (%struct.SS* nonnull dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 // CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 @@ -1059,45 +2035,293 @@ // CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 // CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK7-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK7-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B3]], i32** [[TMP4]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP5]], align 4 -// CHECK7-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 4 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(16) [[REF_TMP]]) +// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** +// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** +// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP5]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK7-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[C:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[TMP]], align 4 +// CHECK7-NEXT: store i32* [[C]], i32** [[_TMP1]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 +// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 +// CHECK7-NEXT: store i32 [[DEC]], i32* [[B]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 +// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev +// CHECK7-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 +// CHECK7-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 +// CHECK7-SAME: () #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK7: arrayctor.loop: +// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK7: arrayctor.cont: +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* +// CHECK7-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i32 4, i1 false) +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i32 2 +// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK7: arraydestroy.body: +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK7: arraydestroy.done3: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev +// CHECK7-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK7-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** +// CHECK7-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** +// CHECK7-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK7-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK7-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK7-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK7: omp_offload.failed: +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK7: omp_offload.cont: +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 +// CHECK7-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 +// CHECK7-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 +// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 +// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK7-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32* [[A]], i32** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK7-NEXT: ret void +// +// +// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK7-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK7-SAME: () #[[ATTR6:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 4 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 +// CHECK7-NEXT: call void @__tgt_register_requires(i64 1) // CHECK7-NEXT: ret void // // @@ -1106,11 +2330,45 @@ // CHECK8-NEXT: entry: // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(1) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK8-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK8-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done1: +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP4]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi @@ -1126,17 +2384,143 @@ // CHECK8-NEXT: ret void // // +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 +// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* +// CHECK8-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 4, i1 false) +// CHECK8-NEXT: store i32 3, i32* [[SIVAR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done3: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) +// CHECK8-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) +// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 128 +// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) +// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) +// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) +// CHECK8-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +// CHECK8-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done1: +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK8-NEXT: ret i32 [[TMP4]] +// +// // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi // CHECK8-SAME: (%struct.SS* nonnull dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 // CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 @@ -1149,3464 +2533,292 @@ // CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 // CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 // CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK8-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK8-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK8-NEXT: store i32* [[B3]], i32** [[TMP4]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP5]], align 4 -// CHECK8-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 4 -// CHECK8-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull dereferenceable(16) [[REF_TMP]]) +// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** +// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** +// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP5]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK8-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 +// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[C:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[TMP]], align 4 +// CHECK8-NEXT: store i32* [[C]], i32** [[_TMP1]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 +// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 +// CHECK8-NEXT: store i32 [[DEC]], i32* [[B]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 +// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 +// CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev +// CHECK8-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 +// CHECK8-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 +// CHECK8-SAME: () #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 +// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK8: arrayctor.loop: +// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK8: arrayctor.cont: +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 +// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* +// CHECK8-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i32 4, i1 false) +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i32 2 +// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK8: arraydestroy.body: +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK8: arraydestroy.done3: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // -// CHECK8-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK8-SAME: (%class.anon.0* nonnull dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 -// CHECK8-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 4 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 // CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK9-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK9-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP4]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK9-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 4, i1 false) -// CHECK9-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK9-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK9-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP4]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK9-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK9-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK9-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK9-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** -// CHECK9-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** -// CHECK9-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP5]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK9-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK9-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[C:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32* [[C]], i32** [[_TMP1]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 -// CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK9-NEXT: store i32 [[DEC]], i32* [[B]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK9-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 -// CHECK9-SAME: () #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK9-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i64 4, i1 false) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK9-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** -// CHECK9-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** -// CHECK9-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] -// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK9: omp_offload.cont: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 -// CHECK9-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[A]], i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK10-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP4]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK10-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 4, i1 false) -// CHECK10-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK10-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP4]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK10-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK10-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK10-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK10-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK10-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** -// CHECK10-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** -// CHECK10-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP5]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK10-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK10-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[C:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32* [[C]], i32** [[_TMP1]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 -// CHECK10-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK10-NEXT: store i32 [[DEC]], i32* [[B]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK10-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK10-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 -// CHECK10-SAME: () #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK10-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i64 4, i1 false) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK10-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** -// CHECK10-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** -// CHECK10-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK10: omp_offload.failed: -// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] -// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK10: omp_offload.cont: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 -// CHECK10-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[A]], i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK10-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK11-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP4]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK11-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK11-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 4, i1 false) -// CHECK11-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done3: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK11-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK11-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK11-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP4]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK11-SAME: (%struct.SS* nonnull dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK11-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK11-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** -// CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** -// CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP5]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK11-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK11-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[TMP]], align 4 -// CHECK11-NEXT: store i32* [[C]], i32** [[_TMP1]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 -// CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK11-NEXT: store i32 [[DEC]], i32* [[B]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK11-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK11-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 -// CHECK11-SAME: () #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK11: arrayctor.loop: -// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK11-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i32 4, i1 false) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i32 2 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done3: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK11-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK11-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** -// CHECK11-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** -// CHECK11-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] -// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK11: omp_offload.cont: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 -// CHECK11-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK11-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32* [[A]], i32** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK12-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP4]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK12-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 4, i1 false) -// CHECK12-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done3: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK12-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP4]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK12-SAME: (%struct.SS* nonnull dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK12-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK12-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK12-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK12-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** -// CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** -// CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP5]], align 4 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK12-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK12-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[C:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[TMP]], align 4 -// CHECK12-NEXT: store i32* [[C]], i32** [[_TMP1]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 -// CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK12-NEXT: store i32 [[DEC]], i32* [[B]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK12-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK12-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 -// CHECK12-SAME: () #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK12: arrayctor.loop: -// CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 -// CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK12-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i32 4, i1 false) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i32 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done3: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK12-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 -// CHECK12-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** -// CHECK12-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** -// CHECK12-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) -// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] -// CHECK12: omp_offload.failed: -// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] -// CHECK12: omp_offload.cont: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 -// CHECK12-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK12-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 -// CHECK12-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32* [[A]], i32** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK12-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__tgt_register_requires(i64 1) -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done7: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK13: arraydestroy.body9: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK13: arraydestroy.done13: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK13-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done7: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK13: arraydestroy.body9: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK13: arraydestroy.done13: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK13-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK13-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK13-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK13-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK13-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK13-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK13-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK13-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK13-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK13-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done7: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK14: arraydestroy.body9: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK14: arraydestroy.done13: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK14-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done7: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK14: arraydestroy.body9: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK14: arraydestroy.done13: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK14-SAME: (%struct.SS* nonnull dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK14-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK14-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK14-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK14-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK14-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK14-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK14-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK14-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK14-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK14-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK15-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK15: arraydestroy.body9: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK15: arraydestroy.done13: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK15-SAME: (%struct.SS* nonnull dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK15: arraydestroy.body9: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK15: arraydestroy.done13: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK15-SAME: (%struct.SS* nonnull dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK15-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK15-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK15-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK15-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK15-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK15-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK15-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK15-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK15-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK15-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK15-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK15-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK16-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK16-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK16: arraydestroy.body9: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK16: arraydestroy.done13: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK16-SAME: (%struct.SS* nonnull dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull dereferenceable(4) [[SST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK16: arraydestroy.body9: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK16: arraydestroy.done13: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK16-SAME: (%struct.SS* nonnull dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK16-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK16-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK16-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK16-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK16-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK16-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK16-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK16-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK16-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK16-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK16-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK16-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK16-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void +// CHECK8-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev +// CHECK8-SAME: (%struct.SST* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** +// CHECK8-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** +// CHECK8-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK8-NEXT: store i8* null, i8** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK8-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK8-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK8: omp_offload.failed: +// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK8: omp_offload.cont: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 +// CHECK8-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 +// CHECK8-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 +// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[A]], i32** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK8-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK8-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK8-NEXT: ret void // diff --git a/clang/test/OpenMP/vla_crash.c b/clang/test/OpenMP/vla_crash.c --- a/clang/test/OpenMP/vla_crash.c +++ b/clang/test/OpenMP/vla_crash.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux-gnu -fopenmp -x c -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux-gnu -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux-gnu -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" int a; @@ -130,55 +130,3 @@ // CHECK1: if.end: // CHECK1-NEXT: ret void // -// -// CHECK2-LABEL: define {{[^@]+}}@foo -// CHECK2-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[B:%.*]] = alloca i32*, align 8 -// CHECK2-NEXT: [[C:%.*]] = alloca i32***, align 8 -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @a, align 4 -// CHECK2-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32***, i32**** [[C]], align 8 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32**, i32*** [[TMP4]], i64 0 -// CHECK2-NEXT: [[TMP5:%.*]] = load i32**, i32*** [[ARRAYIDX]], align 8 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* @a, align 4 -// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK2-NEXT: [[TMP7:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32*, i32** [[TMP5]], i64 [[TMP7]] -// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32*, i32** [[ARRAYIDX1]], i64 0 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[ARRAYIDX2]], align 8 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* @a, align 4 -// CHECK2-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i64 [[IDXPROM3]] -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK2-NEXT: [[TMP12:%.*]] = mul nsw i64 0, [[TMP1]] -// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[TMP11]], i64 [[TMP12]] -// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX5]], i64 0 -// CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX6]], align 4 -// CHECK2-NEXT: ret void -// -// -// CHECK2-LABEL: define {{[^@]+}}@bar -// CHECK2-SAME: (i32 signext [[N:%.*]], i32* [[A:%.*]]) #[[ATTR0]] { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK2-NEXT: [[P:%.*]] = alloca i32*, align 8 -// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK2-NEXT: [[TMP2:%.*]] = bitcast i32** [[A_ADDR]] to i32* -// CHECK2-NEXT: store i32* [[TMP2]], i32** [[P]], align 8 -// CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[P]], align 8 -// CHECK2-NEXT: [[TMP4:%.*]] = bitcast i32** [[A_ADDR]] to i32* -// CHECK2-NEXT: [[CMP:%.*]] = icmp eq i32* [[TMP3]], [[TMP4]] -// CHECK2-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] -// CHECK2: if.then: -// CHECK2-NEXT: br label [[IF_END]] -// CHECK2: if.end: -// CHECK2-NEXT: ret void -//